Memory module, apparatus, and server

Abstract

The present application relates to the technical field of chip packaging, and provides a memory module, an apparatus, and a server. The memory module comprises at least one memory chip set; the memory chip set comprises at least one subset; different subsets are connected to different memory channels; each subset is formed by stacking a plurality of memory chips; the bit widths of the memory chips in each subset include a first bit width and a second bit width; the first bit width is N times the second bit width, and the second bit width is greater than or equal to 8 bits, wherein N is a positive integer greater than 1. Compared with the related art, because memory chips having larger bit widths are adopted, the number of memory chips carried by a memory channel is smaller, thereby reducing the number of CA lines in the memory channel, and lowering the CA signal load of a CPU; the CPU can directly drive clock and CA signals so as to access the memory module, eliminating the need for relay driving via an RCD, reducing product costs; and moreover, the memory module is more miniaturized and can be mounted closer to the CPU, improving the signal quality.

Description

Memory module, device and server

[0001] The present application claims priority to the Chinese patent application No. 202410586003.1, filed on May 11, 2024, and entitled "Memory module, device and server", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the chip packaging technical field, and particularly relates to a memory module, a device and a server. BACKGROUND

[0003] The memory in the server usually adopts a registered dual inline memory module (RDIMM) form, that is, a plurality of memory particles are mounted on a printed circuit board (PCB), and the PCB is inserted into the mainboard through a gold finger connector. In some product forms, the memory in the server adopts a surface mount form, that is, the memory particles are directly pasted on the mainboard without using the PCB and the gold finger connector. The central processing unit (CPU) accesses the memory through a memory channel, and the bit width of the memory channel is usually 64 bits. In the above two product forms, memory particles with a bit width of 4 bits or a bit width of 8 bits are usually used. Considering data redundancy, the CPU can simultaneously access 20 memory particles (in the case of a memory particle bit width of 4 bits) or 10 memory particles (in the case of a memory particle bit width of 8 bits) through one memory channel. The number of memory particles corresponding to one memory channel is large, which leads to a large number of command address (CA) lines of one memory channel. The CPU is difficult to drive too many CA signals at the same time, which leads to low integrity and poor quality of the CA signal.

[0004] In the related art, a registered clock driver (RCD) is configured in the memory product. The RCD is used to drive the clock and the CA signal between the CPU and the memory particle to ensure the quality of the CA signal and realize the access of the CPU to the memory particle.

[0005] However, the configuration of the RCD will increase the cost of the memory product, and the RCD will occupy the area on the PCB or the mainboard, which will increase the size of the memory product and further increase the cost of the memory product. SUMMARY

[0006] The embodiment of the present application provides a memory module, device and server, which can guarantee the quality of the CA signal without configuring RCD to drive the clock and CA signal, thereby reducing the product cost. The technical scheme is as follows.

[0007] In a first aspect, a memory module is provided, which includes at least one memory chip set, the memory chip set including at least one sub-group, different sub-groups being connected with different memory channels, each sub-group being stacked by a plurality of memory chips, and the bit width of the memory chips in each sub-group including a first bit width and a second bit width, the first bit width being N times of the second bit width, the second bit width being greater than or equal to 8 bits, and N being a positive integer greater than 1.

[0008] The memory module is a device providing data storage function packaged by a plurality of memory chips. The memory module can be installed on a mainboard, one memory module being connected with at least one memory channel, and a processor being able to access the memory module through the at least one memory channel, thereby storing data to the memory module or reading data from the memory module.

[0009] In the above memory module, compared with the related art, the memory chips connected with one memory channel are reduced due to the use of memory chips with larger bit width, thereby reducing the number of CA lines of the memory channel and reducing the CA signal load of the processor. According to the relationship between the first bit width and the second bit width, the minimum value of the first bit width is 16, and the minimum value of the second bit width is 8. In this bit width combination, one sub-group includes 4 data chips with a bit width of 16 and 2 ECC chips with a bit width of 8. The sub-group includes a total of 6 memory chips, that is, the number of memory chips connected with one memory channel in the present application is at most 6, which is reduced by 40% compared with the related art. According to the simulation results shown in FIG. 4, in the case of 6 memory chips, the processor can directly drive the clock signal and the CA signal to access the memory module without relaying the driving through the RCD. Moreover, the signal quality is better. In summary, the embodiment of the present application can reduce the number of memory chips connected with one memory channel by at least 40% compared with the related art, thereby not needing to configure RCD and reducing the product cost. Moreover, the stacked memory chips are used to package the memory module. Compared with the related art in which each memory chip is flatly pasted on the PCB to form a memory stick or directly flatly pasted on the mainboard, the size of the memory module is obviously reduced. The memory module can be installed at a position closer to the processor, the memory channel connecting the processor and the memory module is shorter, the efficiency of the processor accessing the memory module is higher, and the signal quality is better.

[0010] It should be noted that, compared with the related art, the number of memory chips connected with one memory channel in the memory module is reduced, and thus the capacity of memory accessed by one memory channel is reduced compared with the related art; since the size of the memory module is significantly reduced compared with the related art, in a scenario where a large memory capacity is required, a plurality of memory modules provided by the embodiments of the present application can be selected to provide a large memory capacity.

[0011] In a possible implementation, when the memory module includes a plurality of memory chip groups, each memory chip group includes the same number of memory chips.

[0012] In a possible implementation, when the memory module includes a plurality of memory chip groups, there are at least two first memory chip groups in the memory module, and the at least two first memory chip groups include different numbers of memory chips.

[0013] In a possible implementation, the sub-group includes at least one data chip and at least one error correction code (ECC) chip.

[0014] In the memory module, since the sub-group connected with one memory channel includes a data chip and an ECC chip, the ECC chip is used to store the error correction code of the data in the data chip, that is, to store the redundant data of the data chip, and thus when the data in the data chip is erroneous and the number of erroneous bits is within the error correction capability of the ECC technology, data recovery can be performed, so that the processor can continue to normally access the sub-group, avoiding the interruption of the processor accessing the sub-group due to a small amount of data errors, and the reliability of the data in the sub-group and the stability of data reading and writing can be improved.

[0015] In a possible implementation, the memory chip group includes at least one first sub-group, the bit width ratio of a single data chip to a single ECC chip in the first sub-group is 2:1, and the number ratio of the data chip to the ECC chip in the first sub-group is 2:1.

[0016] In the memory module, the bit width ratio of the data chip to the ECC chip is 2:1, and the number ratio of the data chip to the ECC chip is also 2:1, which can meet the requirement that the total bit width of the data chip and the total bit width of the ECC chip in the ECC technology are in a ratio of 4:1, and thus the error correction capability of the ECC technology can be ensured when data errors occur.

[0017] In a possible implementation, the memory chip group includes at least one second sub-group, the bit width ratio of a single data chip to a single ECC chip in the second sub-group is 4:1, and the number ratio of the data chip to the ECC chip in the second sub-group is 1:1.

[0018] In the memory module, the bit width ratio of the data chip and the ECC chip is 4:1, the quantity ratio of the data chip and the ECC chip is 1:1, the total bit width ratio of the data chip and the ECC chip in the ECC technology is 4:1, and the error correction capability of the ECC technology can be ensured when data error occurs.

[0019] In a possible implementation, the memory chip set includes a plurality of sub-sets, the plurality of sub-sets include at least one first sub-set and at least one second sub-set, the bit width ratio of a single data chip and a single ECC chip in the first sub-set is 2:1, the quantity ratio of the data chip and the ECC chip in the first sub-set is 2:1, the bit width ratio of a single data chip and a single ECC chip in the second sub-set is 4:1, and the quantity ratio of the data chip and the ECC chip in the second sub-set is 1:1.

[0020] In a possible implementation, the capacity ratio of a single data chip and a single ECC chip in the first sub-set is 2:1.

[0021] In the memory module, the bit width ratio of the data chip and the ECC chip is 2:1, that is, the quantity ratio of the data pins of the data chip and the data pins of the ECC chip is 2:1, the capacity ratio of the data chip and the ECC chip is also set to 2:1, the quantity of the data pins can be ensured to correspond to the capacity of the memory chip, that is, the quantity of the data pins of the memory chip with larger capacity is more, and the number of data bits written or read from the memory chip at a time is more, so that the waste of the capacity of the memory chip is avoided.

[0022] In a possible implementation, when the memory chip set includes a plurality of first sub-sets, the stacking sequence of the data chip and the ECC chip in each first sub-set is the same.

[0023] In the memory module, the plurality of chips in each first sub-set adopt the same stacking sequence, the order of the memory module package can be ensured, the processing error of the memory module is reduced, the yield of the memory module is improved, and the processor can identify the data chip and the ECC chip.

[0024] In a possible implementation, the capacity ratio of a single data chip and a single ECC chip in the second sub-set is 4:1.

[0025] In the memory module, the bit width ratio of the data chip and the ECC chip is 4:1, that is, the number of data pins of the data chip and the number of data pins of the ECC chip are in a ratio of 4:1, and the capacity ratio of the data chip and the ECC chip is also set to 4:1, so as to ensure the correspondence between the number of data pins and the capacity of the memory chip, that is, the more the capacity of the memory chip, the more the number of data pins, and the more the number of data bits written or read from the memory chip at a time, thereby avoiding the waste of the capacity of the memory chip.

[0026] In a possible implementation, when the memory chip group includes a plurality of second subgroups, the stacking order of the data chip and the ECC chip in each second subgroup is the same.

[0027] In the memory module, since the plurality of chips in each second subgroup adopts the same stacking order, the order of the memory module packaging can be ensured, thereby facilitating the reduction of processing errors of the memory module, improving the yield of the memory module, and facilitating the CPU to identify the data chip and the ECC chip.

[0028] In a possible implementation, the memory chip group includes at least one third subgroup, each third subgroup is stacked by 3 data chips and 1 ECC chip, wherein the bit width of 1 data chip is 32 bits, the bit width of 2 data chips is 16 bits, and the bit width of 1 ECC chip is 16 bits.

[0029] In a possible implementation, the plurality of memory chips in each memory chip group are stacked based on the rewiring layer (RDL) technology and wire bonding.

[0030] In the memory module, the pads in the center of the plurality of memory chips are rewired to the edges of the memory chips by the RDL technology, and then the pads of the plurality of memory chips are connected with the leads of the substrate by wire bonding to form the memory module.

[0031] In the memory module, the pads are rewired to the edges of the memory chips by the RDL technology, thereby facilitating the shortening of the length of the wire bonding wire for connecting the pads and the leads of the substrate, and the shorter the length of the wire bonding wire, the higher the signal quality transmitted through the wire bonding wire.

[0032] In a possible implementation, the plurality of memory chips in each memory chip group are stacked based on wire bonding.

[0033] In the memory module, the plurality of memory chips in the memory chip group are packaged directly by wire bonding without using the RDL technology which has a high process difficulty, thereby reducing the process difficulty of packaging and saving costs.

[0034] In a possible implementation, the memory module does not include a register clock driver (RCD).

[0035] Compared with the RDIMM in the related art, the memory module can save product cost, and can save about 10 dollars of cost per memory module; and the position of the RCD does not need to be considered when packaging the memory module, the packaging size of the memory module is smaller, and the memory module can be installed closer to the processor, so that the efficiency of the processor accessing the memory module is improved and the signal quality is improved.

[0036] In a second aspect, an apparatus is provided, which includes a plurality of memory modules, a processor and a mainboard;

[0037] The plurality of memory modules and the processor are installed on the mainboard.

[0038] The processor directly drives clock and command address signals to access the plurality of memory modules.

[0039] Each memory module includes at least one memory chip set, the memory chip set includes at least one sub-group, different sub-groups are connected with different memory channels, each sub-group is stacked by a plurality of memory chips, the bit width of the memory chips in each sub-group includes a first bit width and a second bit width, the first bit width is N times of the second bit width, the second bit width is greater than or equal to 8 bits, and N is a positive integer greater than 1.

[0040] The clock signal is used to provide synchronization and timing reference for various operations in the processor, to ensure that each component in the processor executes instructions, processes and transmits data, and performs other operations in accordance with accurate rhythm and time sequence, and to ensure the coordination and accuracy of the processor operation. The command address signal includes a command signal and an address signal, the command signal is used to instruct the specific operation of the processor, such as reading data, writing data, performing operation, etc., which determines the specific action of the processor. The address signal is used to specify the position of data or instructions in the memory, and the processor can accurately find the required data or instructions through the address signal to perform reading or writing operation, so as to realize accurate access and control of the memory and other storage resources.

[0041] In the device, the memory chips connected to one memory channel are reduced in number compared with the related art due to the use of memory chips with a larger bit width, thereby reducing the number of CA lines of the memory channel and reducing the CA signal load of the processor. The number of memory chips connected to one memory channel is reduced by at least 40% compared with the related art. The processor can directly drive the clock signal and the CA signal to access the memory module without the need for driving through the RCD relay. The number of memory chips connected to one memory channel is significantly reduced, and the RCD does not need to be configured, thereby reducing the product cost. In addition, the memory module is packaged by stacking memory chips. Compared with the related art in which each memory chip is flatly attached to the PCB to form a memory bank or is directly attached to the motherboard, the size of the memory module is significantly reduced. The memory module can be installed closer to the processor. The memory channel connecting the processor and the memory module is shorter, and the efficiency of the processor accessing the memory module is higher, and the signal quality is better.

[0042] In a third aspect, a server is provided, which includes a plurality of memory modules, a processor, and a motherboard;

[0043] The plurality of memory modules and the processor are installed on the motherboard;

[0044] The processor directly drives the clock and command address signals to access the plurality of memory modules;

[0045] Each memory module includes at least one memory chip group, the memory chip group includes at least one sub-group, different sub-groups are connected to different memory channels, each sub-group is stacked by a plurality of memory chips, and the bit width of the memory chips in each sub-group includes a first bit width and a second bit width, the first bit width is N times the second bit width, the second bit width is greater than or equal to 8 bits, and N is a positive integer greater than 1.

[0046] On the basis of the implementation manners of the above aspects provided by the present application, further combinations can be made to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0047] FIG. 1 is a schematic diagram of a memory module 1A provided by an embodiment of the present application;

[0048] FIG. 2 is a schematic diagram of a memory module 2A provided by an embodiment of the present application;

[0049] FIG. 3 is a schematic diagram of a memory module 3A provided by an embodiment of the present application;

[0050] FIG. 4 is a CA eye-mask simulation result diagram provided by an embodiment of the present application;

[0051] FIG. 5 is a schematic diagram of a device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0052] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0053] In order to facilitate the understanding of the technical solutions of the embodiments of the present application, the following will first explain and describe several technical terms involved in the embodiments of the present application.

[0054] Memory channel: refers to a physical path connecting between a processor and a memory module, a memory channel includes a plurality of physical lines, one physical line is connected with one data pin of a memory chip, and 1 bit is transmitted each time. The bit width of a memory channel indicates the number of bits transmitted simultaneously through the memory channel. For example, the bit width of a memory channel is 64 bits, indicating that the memory channel includes 64 physical lines, and 64 bits are transmitted simultaneously each time. Data transmission can be performed in parallel between a plurality of memory channels, the more the number of memory channels, the more the number of bits that can be transmitted in parallel, and the higher the efficiency of the processor accessing the memory. The total bit width of the data chip connected with one memory channel is equal to the bit width of the memory channel.

[0055] Bit width of a memory chip: refers to the number of data pins included in the memory chip, indicating the number of bits that can be written or read to the memory chip at a time. For example, the bit width of a memory chip is 8, indicating that the memory chip includes 8 data pins, and 8 bits can be transmitted simultaneously at a time, that is, the memory chip can write or read 8 bits simultaneously at a time.

[0056] Processor bit width: refers to the amount of data read or written by the processor to the memory at a time through one memory channel. For example, the processor bit width is 64, indicating that the processor can write or read 64 bits from the memory at a time.

[0057] The embodiment of the present application provides a memory module, which comprises at least one memory chip set, each memory chip set comprises at least one sub-group, different sub-groups are connected with different memory channels, wherein each sub-group is stacked by memory chips with a bit width greater than or equal to 8 bits, and at least one memory chip with a bit width greater than 8 bits exists in each sub-group. Wherein, one memory chip set is a plurality of memory chips stacked together, which can be understood as "a pile". Compared with the related art, the number of memory chips connected with one memory channel is reduced by using the memory chip with a larger bit width, and the number of CA lines of the memory channel is reduced, the CA signal load of the processor is reduced, the number of memory chips connected with one memory channel is reduced by at least 40% compared with the related art, and the processor can directly drive the clock signal and the CA signal to access the memory module without driving through the RCD relay, since the number of memory chips connected with one memory channel is significantly reduced and the RCD does not need to be configured, the product cost can be reduced; and the stacked memory chip is used to package the memory module, compared with the related art that each memory chip is flatly attached on the PCB to form a memory bank or is directly flatly attached on the mainboard, the size of the memory module is obviously reduced, the memory module can be installed in a position closer to the processor, the memory channel connecting the processor and the memory module is shorter, the efficiency of the processor accessing the memory module is higher, and the signal quality is better.

[0058] It should be noted that the plurality of memory chips in the memory module are dies, and the specifications of the plurality of memory chips can be the same or different. Exemplarily, the plurality of memory chips can all be dynamic random access memory (DRAM) chips. In some embodiments, the DRAM chip can be a DDR SDRAM (double data rate synchronous dynamic random access memory) chip, referred to as DDR for short; for example, DDR4, DDR5 or DDR6, etc.

[0059] As is understood by those skilled in the art, as the bit area is continuously reduced, the margin of the memory cell is also continuously reduced, and the probability of bit flip in the memory chip is increased. In order to ensure the reliability of data storage of the memory module, a plurality of memory chips in the memory module include a data chip and an error correcting code (ECC) chip. It should be understood that the ECC is an error correction technology that detects and corrects errors in data operations by adding additional bits to the data. The ECC technology can tolerate errors in memory operation. Even if there is an error in the data, the memory controller will automatically correct the error based on the ECC, so that the system can continue to work normally and will not be interrupted due to the error. When data is written to the ECC chip, the error correcting code corresponding to the written data is stored in the ECC chip. When reading data, the memory controller compares the stored error correcting code with the error correcting code generated when reading the data. If the read error correcting code does not match the stored error correcting code, the error correcting code can be used to determine which bit is wrong, and then the bit is immediately corrected.

[0060] In addition, when the ECC technology is used, the ratio of the total bit width of the data chip to the total bit width of the ECC chip in the plurality of memory chips connected to one memory channel is usually 4:1. In the case of a CPU bit width of 64 bits, the total bit width of the data chip is 64 bits, and the total bit width of the ECC chip is 16 bits. The error correction capability of the ECC technology is to correct bit errors of any 4 data queues (DQs). If the on-die error correction engine (ODECC) is included on the memory chip, the error correction capability can be improved to correct bit errors in 8 DQs by using on-die ECC and multi-level system ECC joint error correction. That is, if the bit width of the data chip is 16 bits, the half chipkill of the data chip can be achieved.

[0061] The memory module provided by the embodiments of the present application is further described below through specific embodiments.

[0062] Figure 1 is a schematic diagram of a memory module 1A according to an embodiment of the present application. As shown in Figure 1, the memory module 1A includes a memory chip group 11 and a memory chip group 12. The memory chip group 11 includes a first sub-group 110 and the memory chip group 12 includes a first sub-group 120. The first sub-group 110 and the first sub-group 120 are each stacked by six memory chips, four of which are data chips (shown by white fill in Figure 1) and two of which are ECC chips (shown by black fill in Figure 1). Each data chip has a bit width of 16 bits and each ECC chip has a bit width of 8 bits. The ratio of the number of data chips to the number of ECC chips is 2:1 and the ratio of the bit width of a single data chip to the bit width of a single ECC chip is 2:1. The first sub-group 110 is connected to one memory channel and the first sub-group 120 is connected to another memory channel. That is, one memory module 1A can be connected to two memory channels at the same time and different sub-groups in the memory module group are connected to different memory channels. Understandably, the total bit width of the four data chips in one first sub-group shown in Figure 1 is 64, which is aligned with the CPU bit width, and the total bit width of the two ECC chips in one first sub-group shown in Figure 1 is 16. The ratio of the total bit width of the data chips to the total bit width of the ECC chips is 4:1.

[0063] In some embodiments, the plurality of memory chips in the memory module 1A are stacked and packaged based on a redistribution layer (RDL) technology and wire bonding. Illustratively, the pads in the center of the plurality of memory chips are rewired to the edges of the plurality of memory chips by the RDL technology, and the pads of the plurality of memory chips are connected to the substrate leads by wire bonding to form the memory module. In some embodiments, when the number of stacked layers of the memory chips in the memory module is greater than a preset value, the above-described packaging method is used, where the preset value can be determined according to actual needs. Illustratively, the preset value can be 3.

[0064] In some embodiments, the capacity of the data chips and the capacity of the ECC chips in the memory chip group are equal. For example, the capacity of the data chips and the capacity of the ECC chips are each 4 gigabytes (GB), 8 GB, or 16 GB. It should be noted that the above examples of the capacity of the memory chips are merely illustrative and the embodiments of the present application do not limit the capacity of the memory chips.

[0065] In some embodiments, the capacity ratio of the data chip to the ECC chip in the memory chip set is 2:1. For example, the capacity of the data chip is 16 GB and the capacity of the ECC chip is 8 GB; or for example, the capacity of the data chip is 8 GB and the capacity of the ECC chip is 4 GB. In the above optional manner, the bit width ratio of the data chip to the ECC chip is 2:1, that is, the number of data pins of the data chip to the number of data pins of the ECC chip is 2:1. By setting the capacity ratio of the data chip to the ECC chip to 2:1, the correspondence between the number of data pins and the capacity of the memory chip can be ensured, that is, the more the capacity of the memory chip, the more the number of data pins of the memory chip, and the more the number of data bits written or read from the memory chip at a time, thereby avoiding the waste of the capacity of the memory chip.

[0066] It should be noted that FIG. 1 is an example of the up-down positional relationship and the number of stacked layers of the plurality of memory chips in a memory chip set, and is not a front view, a side view or a top view of the memory module 1A, and does not limit the actual product form of the memory module 1A.

[0067] It should be noted that the sizes of the plurality of memory chips in the first sub-group can be the same or different. In some embodiments, the sizes of the plurality of memory chips in the first sub-group are the same, thereby shortening the length of the bonding wire and improving the signal quality. The embodiments of the present application do not limit the size of the memory chip in the same memory chip set.

[0068] It should be noted that the memory module 1A shown in FIG. 1 is described by taking an example of a memory module including two memory chip sets. In some embodiments, the memory module includes one memory chip set. In other embodiments, the memory module includes more than two memory chip sets. The embodiments of the present application do not limit the number of memory chip sets included in the memory module. More than two memory chip sets can be stacked in a single column or multiple columns, which is not limited by the embodiments of the present application. Among them, a single column means that in a top view, more than two memory chip sets are arranged in a single column; and multiple columns means that in a top view, more than two memory chip sets are arranged in multiple columns.

[0069] It should be noted that the memory module 1A shown in FIG. 1 is described by taking an example of a memory chip set including a first sub-group, and in some embodiments, the memory chip set includes a plurality of first sub-groups. In the plurality of first sub-groups, the stacking order of the data chips and the memory chips can be the same or different. For example, in some embodiments, the stacking order of the data chips and the ECC chips in the plurality of first sub-groups is the same, for example, each first sub-group is stacked in the order of data chip, data chip, ECC chip, data chip, data chip, ECC chip from bottom to top. In the above embodiment, since the plurality of chips in the plurality of sub-groups with the same composition adopt the same stacking order, the order of the memory module package can be ensured, thereby facilitating reduction of processing errors of the memory module, thereby improving the yield of the memory module, and facilitating identification of the data chips and the ECC chips by the CPU. It should be noted that the stacking order of the memory chips shown in FIG. 1 is exemplary only, and the embodiments of the present application do not limit the stacking order. For another example, in another embodiment, the stacking order of the data chips and the ECC chips in at least two first sub-groups of the plurality of first sub-groups of the memory chip set is different.

[0070] The memory module 1A shown in FIG. 1 is described by taking an example of a first sub-group including a data chip with a bit width of 16 bits and an ECC chip with a bit width of 8 bits, and in some embodiments, the first sub-group includes a data chip with a bit width of 32 bits and an ECC chip with a bit width of 16. For example, FIG. 2 is a schematic diagram of a memory module 2A provided by an embodiment of the present application. As shown in FIG. 2, the memory module 2A includes a memory chip set 21, which includes a first sub-group 211 and a first sub-group 212, each of which is stacked by 3 memory chips, wherein 2 memory chips are data chips (exemplarily shown by white filling in FIG. 2), and 1 memory chip is an ECC chip (exemplarily shown by black filling in FIG. 2), each data chip has a bit width of 32 bits, and each ECC chip has a bit width of 16 bits. The number ratio of the data chips to the ECC chips is 2:1, and the bit width ratio of a single data chip to a single ECC chip is 2:1. The first sub-group 211 is connected to a memory channel, and the first sub-group 212 is connected to another memory channel, that is, one memory module 2A can be connected to two memory channels at the same time, and different sub-groups in the first memory module 2A are connected to different memory channels. Understandably, the total bit width of 2 data chips in one first sub-group shown in FIG. 2 is 64, which is aligned with the bit width of the CPU, and the total bit width of 1 ECC chip in one first sub-group shown in FIG. 2 is 16, and the total bit width ratio of the data chips to the ECC chips is 4:1.

[0071] Compared with the memory module 1A, the memory module 2A shown in FIG. 2 uses a memory chip with a larger bit width, the number of memory chips included in a first subgroup is reduced, and the number of stacked layers formed by stacking the memory chips in a first subgroup is also reduced. Therefore, with the same number of stacked layers, the memory module 2A can stack more first subgroups, and since a first subgroup is connected to a memory channel, the memory module 2A can be connected to more memory channels with the same number of stacked layers, that is, the same number of memory chips stacked in the same area can be connected to more memory channels, thereby increasing the number of memory channels per unit area, that is, increasing the memory channel density. In addition, since the number of memory channels connected to a memory module is increased, the efficiency of the processor accessing the memory module can be improved.

[0072] In some embodiments, the memory module 2A is packaged by wire bonding. In some embodiments, when the number of stacked layers of memory chips in the memory module is less than or equal to a preset value, the memory module is packaged by wire bonding. The value of the preset value can be determined according to actual needs. For example, the preset value can be 3. In the above embodiment, when the number of stacked layers of memory chips is small, wire bonding is directly used for packaging without using RDL technology, which can reduce the process difficulty of packaging and save costs.

[0073] In some embodiments, the capacity of the data chip and the capacity of the ECC chip in the memory chip group are equal. For example, the capacity of the data chip and the capacity of the ECC chip are both 2GB, 4GB, 8GB, or 16GB. It should be noted that the above examples of the capacity of the memory chip are only exemplary, and the embodiments of the present application do not limit the capacity of the memory chip.

[0074] In some embodiments, the capacity ratio of the data chip to the ECC chip in the memory chip group is 2:1. For example, the capacity of the data chip is 16GB and the capacity of the ECC chip is 8GB. For another example, the capacity of the data chip is 8GB and the capacity of the ECC chip is 4GB. For another example, the capacity of the data chip is 4GB and the capacity of the ECC chip is 2GB. In the above optional manner, the bit width ratio of the data chip to the ECC chip is 2:1, that is, the number of data pins of the data chip to the number of data pins of the ECC chip is 2:1. By setting the capacity ratio of the data chip to the ECC chip to 2:1, the correspondence between the number of data pins and the capacity of the memory chip can be ensured, that is, the more the data pins of the memory chip, the more the number of data bits written or read from the memory chip at a time, thereby avoiding waste of the capacity of the memory chip.

[0075] It should be noted that FIG. 2 is an example of the up-down positional relationship and the number of stacked layers of the plurality of memory chips in a memory chip set, and is not a front view, a side view or a top view of the memory module 2A, and does not limit the actual product form of the memory module 2A.

[0076] The memory module shown in FIGS. 1 and 2 is described by taking the ratio of the bit width of a single data chip to the bit width of a single ECC grain as 2:1 as an example. In some embodiments, the ratio of the bit width of a single data chip to the bit width of a single ECC grain is 4:1. For example, FIG. 3 is a schematic diagram of a memory module according to an embodiment of the present application. As shown in FIG. 3, the memory module 3A includes a memory chip set 31 and a memory chip set 32. The memory chip set 31 includes a second sub-set 310, and the memory chip set 32 includes a second sub-set 320. The second sub-set 310 and the second sub-set 320 are stacked by 4 memory chips, of which 2 memory chips are data chips (shown by white filling in FIG. 3 as an example) and 2 memory chips are ECC chips (shown by black filling in FIG. 3 as an example). The bit width of each data chip is 32 bits, and the bit width of each ECC chip is 8 bits. The number ratio of the data chips to the ECC chips is 1:1, and the bit width ratio of a single data chip to a single ECC chip is 4:1. The second sub-set in the memory chip set 31 is connected to one memory channel, and the second sub-set in the memory chip set 32 is connected to another memory channel. That is, one memory module 3A can be connected to two memory channels at the same time, and different sub-sets in one memory module 3A are connected to different memory channels. Understandably, the total bit width of the 2 data chips in one second sub-set shown in FIG. 3 is 64, which is aligned with the CPU bit width, and the total bit width of the 2 ECC chips in one second sub-set shown in FIG. 3 is 16. The total bit width ratio of the data chips to the ECC chips is 4:1.

[0077] In the above embodiment, compared with the memory module 1A shown in FIG. 3, the memory module 3A uses memory chips with a bit width of 32 bits, and the number of memory chips connected to one memory channel is smaller, that is, the number of memory chips included in one sub-set is reduced. Therefore, the number of stacked layers of the memory chips in the memory module is smaller, the packaging engineering difficulty is reduced under the same packaging size, the length of the bonding wire is shortened, the signal quality is better, and the capacity of the memory module is flexible and configurable.

[0078] In some embodiments, the plurality of memory chips in the memory module 3A are packaged based on the re-distribution layer (RDL) technology and the wire bonding method.

[0079] In some embodiments, the capacity of the data chip and the capacity of the ECC chip in the memory chip set are equal. For example, the capacity of the data chip and the capacity of the ECC chip are 4GB, 8GB or 16GB. It should be noted that the above examples of the capacity of the memory chip are exemplary only, and the embodiments of the present application do not limit the capacity of the memory chip.

[0080] In some embodiments, the capacity ratio of the data chip and the ECC chip in the memory chip set is 4:1. For example, the capacity of the data chip is 16GB, and the capacity of the ECC chip is 4GB. In the above optional manner, the bit width ratio of the data chip and the ECC chip is 4:1, that is, the number of data pins of the data chip and the number of data pins of the ECC chip are in a ratio of 4:1. By setting the capacity ratio of the data chip and the ECC chip to 4:1, the correspondence between the number of data pins and the capacity of the memory chip can be ensured, that is, the more the data pins of the memory chip, the more the number of data bits written or read from the memory chip at a time, thereby avoiding the waste of the capacity of the memory chip.

[0081] It should be noted that FIG. 3 is an example of the up-down positional relationship and the number of stacked layers of the plurality of memory chips in a memory chip set, and is not a front view, a side view or a top view of the memory module 2A, and does not limit the actual product form of the memory module 2A.

[0082] It should be noted that the memory module 3A shown in FIG. 3 is described by taking an example of a memory module including two memory chip sets. In some embodiments, the memory module includes one memory chip set. In other embodiments, the memory module includes two or more memory chip sets, and the embodiments of the present application do not limit the number of memory chip sets included in the memory module. Two or more memory chip sets can be stacked in a single column or multiple columns, and the embodiments of the present application do not limit this. Among them, a single column means that two or more memory chip sets are arranged in a single column in a top view; and multiple columns means that two or more memory chip sets are arranged in multiple columns in a top view.

[0083] It should be noted that the memory module 3A shown in FIG. 3 is described by taking an example of the memory chip group including one second sub-group, and in some embodiments, the memory chip group includes a plurality of second sub-groups. In the plurality of second sub-groups, the stacking order of the data chip and the memory chip can be the same or different. For example, in some embodiments, the stacking order of the data chip and the ECC chip in the plurality of second sub-groups is the same, for example, each second sub-group is stacked in the order of data chip, ECC chip, data chip, ECC chip from bottom to top. In the above embodiment, since the plurality of chips in the plurality of sub-groups with the same composition adopt the same stacking order, the order of the memory module package can be ensured, thereby facilitating the reduction of processing errors of the memory module, thereby improving the yield of the memory module, and facilitating the CPU to identify the data chip and the ECC chip. It should be noted that the stacking order of the memory chip shown in FIG. 3 is exemplary, and the embodiments of the present application do not limit the stacking order. For another example, in another embodiment, the stacking order of the data chip and the ECC chip in at least two second sub-groups of the plurality of second sub-groups of the memory chip group is different.

[0084] It should be noted that the memory modules 1A, 2A and 3A are described by taking an example of the same memory module in which the different memory chip groups include the same number of sub-groups, and in some embodiments, the different memory chip groups in the same memory module can include different numbers of sub-groups.

[0085] It should be noted that the memory modules 1A, 2A and 3A are described by taking an example of the same memory module in which the different memory chip groups include the same number of sub-groups, and in some embodiments, the different memory chip groups in the same memory module can include different numbers of sub-groups.

[0086] It should be noted that the memory modules 1A, 2A and 3A are described by taking an example of the memory module in which one memory chip group includes only the first sub-group or only the second sub-group, and in some embodiments, in the case where the memory chip group includes a plurality of sub-groups, one memory chip group includes both the first sub-group and the second sub-group.

[0087] It should be noted that the memory modules 1A, 2A and 3A described above are described by taking an example in which the bit widths of the plurality of data chips in one sub-group and the plurality of ECC chips are equal, in some embodiments, the bit widths of the plurality of data chips in one sub-group can not be equal, and the bit widths of the plurality of ECC chips in one sub-group can not be equal, for example, in some embodiments, the memory chip set includes at least one third sub-group, each third sub-group is stacked by 3 data chips and 1 ECC chip, wherein the bit width of 1 data chip is 32 bits, the bit width of 2 data chips is 16 bits, and the bit width of 1 ECC chip is 16 bits.

[0088] In the above plurality of embodiments, compared with the related art, the use of a memory chip with a larger bit width reduces the number of memory chips connected to one memory channel, thereby reducing the number of CA lines of the memory channel, reducing the CA signal load of the processor, the number of memory chips connected to one memory channel is reduced by at least 40% compared with the related art, and the processor can directly drive the clock signal and the CA signal to access the memory module without the need for driving through the RCD relay, since the number of memory chips connected to one memory channel is significantly reduced and does not need to be configured with an RCD, the product cost can be reduced; and the stacked memory chip is used to package the memory module, compared with the related art in which each memory chip is flatly attached to the PCB to form a memory bank or is directly flatly attached to the motherboard, the size of the memory module is significantly reduced, the memory module can be installed closer to the processor, the memory channel connecting the processor and the memory module is shorter, the efficiency of the processor accessing the memory module is higher, and the signal quality is better. In addition, the memory module provided by the embodiments of the present application can be installed on the motherboard in a flat manner without the need for using a PCB and a connector (socket) for installation, which can improve the signal link environment and further reduce the cost.

[0089] The base area of the memory module provided in the embodiments of the present application is greater than 10 mm*10 mm and less than 20 mm*20 mm, compared with the related art, the size of the memory module is greatly reduced, and the number of memory channels is more under the same area, for example, taking the memory module accessed through two memory channels in the present application as an example, under the area occupied by 8 memory channels of the RDIMM in the related art, there are more than 100 memory channels in the embodiments of the present application, and the bandwidth capacity density per unit area is significantly improved. Moreover, as shown in FIG. 4, which is a CA eye-mask simulation result diagram provided by the embodiments of the present application, the upper diagram in FIG. 4 is a simulation result of the RDIMM memory module in the related art, wherein the eye height is 164 mV, and the eye width is 272 ps; the lower diagram in FIG. 4 is a simulation result of the memory module provided by the embodiments of the present application, wherein the eye height is 195 mV, and the eye width is 288 ps. It can be seen that the two indexes of eye height and eye width in the simulation result of the memory module provided by the embodiments of the present application are higher than those in the simulation result of the related art, which indicates that the CA signal can be directly driven by the CPU without relying on the RCD, and the CA signal quality is better. Since it is not necessary to rely on the RCD, at least 10 dollars of cost is saved for each memory module.

[0090] FIG. 5 is a schematic diagram of an apparatus provided by the embodiments of the present application, as shown in FIG. 5, the apparatus includes a processor, a mainboard and a plurality of memory modules provided by the above embodiments; the mainboard is installed with the plurality of memory modules and the processor; and the processor directly drives clock and command address signals to access the plurality of memory modules.

[0091] It should be noted that the apparatus includes 4 memory modules in FIG. 5, in actual application, the apparatus can include more or less memory modules; and it is only exemplary that each memory module is connected with two memory channels in FIG. 5, referring to the above embodiments, the number of memory channels connected with each memory module is determined by the number of subgroups encapsulated by the memory module; and the 4 memory modules shown in FIG. 5 can be the same encapsulation or different encapsulation, which is not limited in the embodiments of the present application.

[0092] The processor can be a general central processing unit (CPU), a graphics processing unit (GPU), a processor unit of a switching module (SMPU), a network processor unit (NPU) or a microprocessor, etc., and the type of the processor is not limited in the embodiments of the present application.

[0093] The embodiment of the application further provides a server, comprising a processor, a mainboard and a plurality of memory modules provided by the above embodiment; the plurality of memory modules and the processor are installed on the mainboard; the processor directly drives clock and command address signals to access the plurality of memory modules.

[0094] The terms "first", "second", and the like in the present application are used to distinguish between identical or similar items having substantially the same function and should be understood not to have a logical or chronological dependency between "first", "second", "n-th", and to not limit the number and execution order. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first sub-group can be referred to as a second sub-group, and similarly, a second sub-group can be referred to as a first sub-group. The first sub-group and the second sub-group can both be node sub-groups, and in some cases, can be separate and distinct sub-groups.

[0095] In the present application, the term "at least one" means one or more, and the term "a plurality of" means two or more. The terms "system" and "network" are often used interchangeably.

[0096] It should also be understood that the term "if" can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]".

[0097] The above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0098] The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory module, comprising: The memory module comprises at least one memory chip set, and the memory chip set comprises at least one sub-group, different sub-groups are connected with different memory channels, and each sub-group is stacked by a plurality of memory chips. The bit width of the memory chips in each sub-group comprises a first bit width and a second bit width, the first bit width is N times of the second bit width, the second bit width is greater than or equal to 8 bits, and N is a positive integer greater than 1.

2. The memory module of claim 1, wherein, The memory module comprises a plurality of memory chip sets, and each memory chip set comprises the same number of memory chips.

3. The memory module of claim 1, wherein, The memory module comprises a plurality of memory chip sets, and there are at least two first memory chip sets in the memory module, and the at least two first memory chip sets comprise different numbers of memory chips.

4. The memory module of claim 1, wherein, Each sub-group comprises at least one data chip and at least one error correction code (ECC) chip.

5. The memory module of claim 4, wherein, The memory chip set comprises at least one first sub-group, the bit width ratio of a single data chip to a single ECC chip in the first sub-group is 2:1, and the number ratio of data chips to ECC chips in the first sub-group is 2:

1.

6. The memory module of claim 4, wherein, The memory chip set comprises at least one second sub-group, the bit width ratio of a single data chip to a single ECC chip in the second sub-group is 4:1, and the number ratio of data chips to ECC chips in the second sub-group is 1:

1.

7. The memory module of claim 4, wherein, The memory chip set comprises a plurality of sub-groups, the plurality of sub-groups comprise at least one first sub-group and at least one second sub-group, the bit width ratio of a single data chip to a single ECC chip in the first sub-group is 2:1, the number ratio of data chips to ECC chips in the first sub-group is 2:1, the bit width ratio of a single data chip to a single ECC chip in the second sub-group is 4:1, and the number ratio of data chips to ECC chips in the second sub-group is 1:

1.

8. The memory module of claim 5 or 7, wherein, The capacity ratio of a single data chip to a single ECC chip in the first sub-group is 2:

1.

9. The memory module of claim 5 or 7, wherein, The number of the first sub-groups is greater than or equal to 2, and the stacking order of data chips and ECC chips in each first sub-group is the same.

10. The memory module of any of claims 6 to 9, wherein, The capacity ratio of a single data chip to a single ECC chip in the second sub-group is 4:

1.

11. The memory module of any of claims 6-9, wherein, The number of the second sub-groups is greater than or equal to 2, and the stacking order of data chips and ECC chips in each second sub-group is the same.

12. The memory module of any one of claims 1 to 11, wherein, The plurality of memory chips in each memory chip set are stacked based on a re-distribution layer (RDL) technology and a wire bonding manner.

13. The memory module of any of claims 1-11, wherein, The plurality of memory chips in each memory chip set are stacked based on a wire bonding manner.

14. The memory module of any one of claims 1 to 13, wherein, The memory module does not comprise a register clock driver (RCD).

15. An apparatus, comprising: The device comprises a plurality of memory modules, a processor and a mainboard. The mainboard is installed with the plurality of memory modules and the processor. The processor directly drives clock and command address signals to access the plurality of memory modules. Each of the memory modules comprises at least one memory chip set, the memory chip set comprises at least one sub-group, different sub-groups are connected with different memory channels, each of the sub-groups is stacked by a plurality of memory chips, the bit width of the memory chips in each of the sub-groups comprises a first bit width and a second bit width, the first bit width is N times of the second bit width, the second bit width is greater than or equal to 8 bits, and N is a positive integer greater than 1.

16. A server, characterized by The server comprises a plurality of memory modules, a processor and a mainboard. The mainboard is installed with the plurality of memory modules and the processor. The processor directly drives clock and command address signals to access the plurality of memory modules. Each of the memory modules comprises at least one memory chip set, the memory chip set comprises at least one sub-group, different sub-groups are connected with different memory channels, each of the sub-groups is stacked by a plurality of memory chips, the bit width of the memory chips in each of the sub-groups comprises a first bit width and a second bit width, the first bit width is N times of the second bit width, the second bit width is greater than or equal to 8 bits, and N is a positive integer greater than 1.

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