Capacitor-less dynamic random access memory and manufacturing method therefor

Abstract

The present disclosure relates to the technical field of microelectronics, and in particular to a capacitor-less dynamic random access memory structure and a manufacturing method therefor. The structure comprises: a low-leakage transistor and a vertical complementary field effect transistor, wherein a drain of the low-leakage transistor is connected to a common gate of the vertical complementary field effect transistor; and drains of P-type and N-type transistors of the vertical complementary field effect transistor are connected to each other, a source of the P-type transistor is connected to a power supply end, and a source of the N-type transistor is connected to a ground wire.

Description

Capacitorless dynamic random access memory and method of making the same

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410581940.8, filed on May 11, 2024, entitled “Capacitorless dynamic random access memory and method of making the same” to Tsinghua University. TECHNICAL FIELD

[0003] The present disclosure relates to the field of microelectronics, and particularly relates to a capacitorless dynamic random access memory and a method of making the same. BACKGROUND

[0004] Dynamic random access memory (DRAM) is the core of modern computer hierarchical memory system, which plays a role of buffering and speed matching between high-speed low-density static random access memory (SRAM) and low-speed high-density external memory. Current DRAM faces great challenges in capacity and speed, especially for data-centric high-performance computing, artificial intelligence and big data applications. For capacity, DRAM has been difficult to size down in the planar direction to increase the capacity of a single DRAM chip. This is because DRAM technology is complex and Moore's law has limited prospects. For speed, the refresh time, output bandwidth and parasitic effects of DRAM are difficult to improve enough under size reduction, and even many parameters will worsen. Therefore, DRAM technology has reached a turning point, and it is difficult to effectively improve the performance of DRAM by continuing to use traditional technology, and new process technology is urgently needed.

[0005] Two transistor one capacitor (2T0C) structure is a capacitorless DRAM technology based on oxide semiconductor devices, which is composed of two transistors without a separate capacitor. Unlike the traditional 1T1C structure DRAM (shown in FIG. 1(a)), the 2T0C structure (shown in FIG. 1(b)) uses the parasitic capacitance of the transistor to achieve storage, thereby greatly simplifying the DRAM process, saving costs, and improving storage density. In order to save the capacitor, it is necessary to reduce the leakage of the transistor as much as possible, so the transistor is usually made of oxide semiconductor, which makes the 2T0C DRAM have a longer retention time compared to the traditional 1T1C structure, thereby having a long refresh interval, fast working speed and low power consumption. In addition, 2T0C adopts a read-write separation design scheme, that is, through the transconductance of a transistor, the read port and the storage node are isolated, thereby effectively weakening the influence of charge sharing effect on stored data.

[0006] But the 2T0C structure is a combination of two field effect transistors (NFET / NFET, NFET / PFET), for the 2T0C structure with NFET as the read tube, the read 1 is slow because of only pull-down function; similarly, for the 2T0C structure with PFET as the read tube, the read 0 is slow because of only pull-up function. In addition, the output of the 2T0C structure is current, if it is applied to a digital circuit, an additional current-voltage conversion module needs to be added, which increases the circuit complexity, area and cost. SUMMARY

[0007] The present disclosure provides a capacitorless dynamic random access memory and a preparation method thereof to solve the problems of slow readout speed of the existing capacitorless dynamic random access memory, and the need to add an additional current-voltage conversion module when applied to a digital circuit, which increases the circuit complexity, area and cost, etc.

[0008] The first aspect of the present disclosure provides a capacitorless dynamic random access memory, comprising a low-leakage transistor and a vertical complementary field effect transistor (CFET), wherein the low-leakage transistor serves as a write tube, the drain of the low-leakage transistor is connected with the common gate of the vertical complementary field effect transistor, so as to write target data into a preset data source; the vertical complementary field effect transistor serves as a read tube, the drain of the P-type transistor and the drain of the N-type transistor in the vertical complementary field effect transistor are connected with each other, the source of the P-type transistor is connected with a power supply end, and the source of the N-type transistor is connected with a ground wire, so as to read the target data from the preset data source.

[0009] In some embodiments, the P-type channel material of the low-leakage transistor adopts any one of P-type doped silicon, P-type nanomaterial and P-type oxide.

[0010] In some embodiments, the N-type channel material of the low-leakage transistor adopts any one of N-type doped silicon, N-type oxide and N-type nanomaterial.

[0011] In some embodiments, the P-type channel material of the vertical complementary field effect transistor adopts any one of P-type doped silicon, P-type nanomaterial and P-type oxide.

[0012] In some embodiments, the N-type channel material of the vertical complementary field effect transistor adopts any one of N-type doped silicon, N-type oxide and N-type nanomaterial.

[0013] In some embodiments, the low-leakage transistor is an IGZO transistor, and the vertical complementary field effect transistor is a CFET transistor composed of a CNT transistor and an IGZO transistor.

[0014] The second aspect of the present disclosure provides a preparation method of a capacitorless dynamic random access memory structure, comprising: depositing a layer of carbon nanotubes on a first preset semiconductor substrate, and performing photolithography definition and evaporating a preset metal material on the carbon nanotubes to obtain a source electrode and a drain electrode of a CNT transistor; based on the source electrode and the drain electrode of the CNT transistor, performing photolithography definition on a channel region of the CNT transistor and etching carbon tubes outside the channel region to deposit a yttrium oxide layer; depositing hafnium oxide on the yttrium oxide layer to take the hafnium oxide as a gate oxide layer of the CNT transistor, and etching and removing the hafnium oxide of an interconnection region of the CNT transistor to expose a first metal; based on the first metal, performing photolithography definition and evaporating the preset metal material to obtain a common gate of the CNT transistor and a first IGZO transistor; depositing first aluminum oxide on the common gate to take the first aluminum oxide as a gate oxide layer of the first IGZO transistor, depositing second aluminum oxide on a second preset semiconductor substrate by using an atomic layer deposition device to take the second aluminum oxide as a gate oxide layer of a second IGZO transistor, and removing the aluminum oxide of the interconnection region of the first IGZO transistor to expose a second metal; growing an indium gallium zinc oxide thin film on the gate oxide layer of the first IGZO transistor and the gate oxide layer of the second IGZO transistor, and performing photolithography definition and evaporating a preset metal material on the indium gallium zinc oxide thin film to obtain a source electrode and a drain electrode of the first IGZO transistor and a source electrode and a drain electrode of the second IGZO transistor; performing photolithography definition on a channel region of the first IGZO transistor on the source electrode and the drain electrode of the first IGZO transistor, performing photolithography definition on a channel region of the second IGZO transistor on the source electrode and the drain electrode of the second IGZO transistor, and etching the first IGZO transistor and the second IGZO transistor outside the channel regions to obtain the capacitorless dynamic random access memory structure.

[0015] The third aspect of the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the preparation method of the capacitorless dynamic random access memory as described in the above embodiments.

[0016] The fourth aspect of the present disclosure provides a computer program product, wherein the computer program / instruction is executed by a processor to implement the preparation method of the capacitorless dynamic random access memory as described above.

[0017] The fifth aspect of the present disclosure provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the preparation method of the capacitorless dynamic random access memory as described above.

[0018] The capacitorless dynamic random access memory and the preparation method thereof provided by the embodiments of the present disclosure replace the traditional N / P FET with a vertical complementary field effect transistor as a read tube, have an up-pull tube and a down-pull tube at the same time without increasing the unit area, and are faster in readout speed; the vertical complementary field effect transistor can achieve better isolation effect, thereby isolating the influence of bias stress on output; the output of the structure is voltage, and the structure can be directly applied to a digital circuit.

[0019] Additional aspects and advantages of the present disclosure will be made apparent from the following description, which, taken in conjunction with the accompanying drawings, which are shown by way of illustration. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and / or additional aspects and advantages of the present disclosure will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0021] FIG. 1 is a structural schematic diagram of a dynamic random access memory different from a traditional dynamic random access memory, wherein (a) is a dynamic random access memory of a 1T1C structure, and (b) is a dynamic random access memory of a 2T0C structure;

[0022] FIG. 2 is a structural schematic diagram of a capacitorless dynamic random access memory provided by the embodiments of the present disclosure, wherein (a) is a capacitorless dynamic random access memory, (b) is a device cross-sectional schematic diagram of a low-leakage transistor, and (c) is a device cross-sectional schematic diagram of a vertical complementary field effect transistor;

[0023] FIG. 3 is a comparison schematic diagram of test results of an existing 2T0C capacitorless dynamic random access memory and a capacitorless dynamic random access memory based on a vertical complementary field effect transistor provided by the embodiments of the present disclosure, wherein (a) is a speed test of reading 0 or 1, and (b) is a stability test;

[0024] FIG. 4 is a flowchart of a preparation method of a capacitorless dynamic random access memory provided by the embodiments of the present disclosure;

[0025] FIG. 5 is a specific manufacturing schematic diagram of a CFET 2T0C provided by the embodiments of the present disclosure;

[0026] FIG. 6 is a structural schematic diagram of an electronic device provided by the embodiments of the present disclosure.

[0027] Legend of reference signs: 201-low-leakage transistor and 202-vertical complementary field effect transistor. DETAILED DESCRIPTION

[0028] The capacitorless dynamic random access memory structure and the preparation method thereof according to the embodiments of the present disclosure are described below with reference to the accompanying drawings. In order to solve the problem that the oxide semiconductor device-based capacitorless dynamic random access memory mentioned in the above background can greatly simplify the DRAM process, save the cost, and improve the storage density, but the readout speed is slow and it cannot be directly applied to the digital circuit, the present disclosure provides a capacitorless dynamic random access memory and a preparation method thereof. In the capacitorless dynamic random access memory, a low-leakage transistor and a vertical complementary field effect transistor are used, and the capacitorless dynamic random access memory has a pull-up transistor and a pull-down transistor at the same time without increasing the cell area, and the output is a voltage. Thus, the problem that the readout speed of the existing capacitorless dynamic random access memory is slow, and when the capacitorless dynamic random access memory is applied to the digital circuit, an additional current-voltage conversion module needs to be added, which increases the circuit complexity, area, and cost is solved.

[0029] FIG. 2 is a structural schematic diagram of a capacitorless dynamic random access memory provided by an embodiment of the present disclosure.

[0030] As shown in FIG. 2, the capacitorless dynamic random access memory CFET 2T0C includes a low-leakage transistor 201 and a vertical complementary field effect transistor 202.

[0031] The low-leakage transistor 201 is used as a write transistor, and the drain of the low-leakage transistor 201 is connected to the common gate of the vertical complementary field effect transistor 202 to write target data into a preset data source. The vertical complementary field effect transistor 202 is used as a read transistor, and the drain of the P-type transistor and the drain of the N-type transistor in the vertical complementary field effect transistor 202 are connected to each other, the source of the P-type transistor is connected to a power supply terminal, and the source of the N-type transistor is connected to a ground terminal to read target data from the preset data source.

[0032] In the actual execution process, as shown in FIG. 2, in the CFET 2T0C structure, the low-leakage transistor 201 such as IGZO-NFET can be used as a write transistor, and the CFET composed of a P-type transistor (PFET) and an N-type transistor (NFET) stacked in the vertical direction can be used as a read transistor, for example, a CFET composed of a CNT transistor and an IGZO transistor. The drain of the write transistor is connected to the common gate of the read transistor as a storage node, the drain of the N-type transistor and the drain of the P-type transistor in the CFET read transistor are connected as a signal output terminal, the source of the N-type transistor is connected to the ground terminal, and the source of the P-type transistor is connected to the power supply terminal. Thus, the capacitorless dynamic random access memory has a pull-up transistor and a pull-down transistor at the same time, and the readout speed is faster. At the same time, the output of the capacitorless dynamic random access memory is a voltage, and the capacitorless dynamic random access memory can be directly applied to the digital circuit.

[0033] In some embodiments, the P-type channel material of the low-leakage transistor 201 adopts any one of P-type doped silicon, P-type nanomaterial and P-type oxide, and the N-type channel material of the low-leakage transistor 201 adopts any one of N-type doped silicon, N-type oxide and N-type nanomaterial.

[0034] Specifically, the P-type channel material of the low-leakage transistor 201 can be selected from P-type nanomaterials such as CNT and WSe2, or P-type oxide materials such as SnO, and the N-type channel material of the low-leakage transistor 201 can be selected from N-type oxides such as IGZO and ITO, or N-type nanomaterials such as MoS2 and WS2. Those skilled in the art can select according to actual conditions, which are not specifically limited here.

[0035] In some embodiments, the P-type channel material of the vertical complementary field effect transistor 202 adopts any one of P-type doped silicon, P-type nanomaterial and P-type oxide, and the N-type channel material of the vertical complementary field effect transistor 202 adopts any one of N-type doped silicon, N-type oxide and N-type nanomaterial.

[0036] Specifically, the size of the P-type transistor and the N-type transistor in the vertical complementary field effect transistor 202 can be flexibly adjusted according to different performance requirements, and the vertically stacked structure is conducive to further reducing the size of the device and improving the integration of the chip; the channels of the P-type transistor and the N-type transistor can adopt different kinds of semiconductor materials, for example, the P-type channel material can be selected from P-type nanomaterials such as CNT and WSe2, or P-type oxide materials such as SnO, and the N-type channel material can be selected from N-type oxides such as IGZO and ITO, or N-type nanomaterials such as MoS2 and WS2, so as to match the carrier mobility of NFET and PFET, further increase the driving current of the device, and thus the turn-on capability and stability of the capacitorless dynamic random access memory can be enhanced.

[0037] The capacitorless dynamic random access memory proposed by the application is further described below through a specific embodiment.

[0038] As shown in FIG. 4, the readout data speed and stability of the existing 2T0C capacitorless dynamic random access memory structure with two field effect transistor combinations NFET / NFET, NFET / PFET and the capacitorless dynamic random access memory CFET 2T0C proposed by the embodiment of the present disclosure are compared, in FIG. (a), the black line is the speed of reading out "0", and the gray line is the speed of reading out "1", it can be seen that the CFET 2T0C has a faster readout speed, and from FIG. (b), it can be seen that the CFET 2T0C has stronger stability.

[0039] In summary, the capacitorless dynamic random access memory proposed by the embodiment of the present disclosure has the following beneficial effects:

[0040] (1) The capacitorless dynamic random access memory CFET 2T0C proposed in the embodiments of the present disclosure has both pull-up and pull-down tubes at the same time, has faster readout speed, and solves the problem of slow readout speed of the existing oxide semiconductor device-based capacitorless dynamic random access memory 2T0C which has only pull-up or pull-down tube during readout;

[0041] (2) The capacitorless dynamic random access memory CFET 2T0C proposed in the embodiments of the present disclosure uses complementary logic read tubes, can better isolate the influence of bias stress on the output, thereby having better stability, and solves the problem of the existing oxide semiconductor device-based capacitorless dynamic random access memory 2T0C which uses a single read tube and the readout result is easily affected by bias stress;

[0042] (3) The CFET 2T0C proposed in the embodiments of the present disclosure has output as voltage without increasing the unit area, and can be directly applied to circuits, solving the problem of the existing oxide semiconductor device-based capacitorless dynamic random access memory 2T0C which has output as current and is difficult to be directly applied to digital circuits.

[0043] Secondly, the preparation method of the capacitorless dynamic random access memory according to the embodiments of the present disclosure is described with reference to the accompanying drawings.

[0044] FIG. 4 is a flowchart of the preparation method of the capacitorless dynamic random access memory provided by the embodiments of the present disclosure.

[0045] As shown in FIG. 4, the preparation method of the capacitorless dynamic random access memory is for preparing the aforementioned capacitorless dynamic random access memory, and includes the following steps:

[0046] In step S401, a layer of carbon nanotube is deposited on a first predetermined semiconductor substrate, and a pre-determined metal material is defined by photolithography and evaporated on the carbon nanotube to obtain the source and drain of the CNT transistor.

[0047] In the actual execution process, as shown in FIG. 5, taking the CNT transistor as a P-type transistor and the IGZO transistor as an N-type transistor as an example, a layer of carbon nanotube is deposited on a negative film by using a wet transfer method, the source and drain of the CNT transistor are defined by photolithography, and metal palladium (Pd) is evaporated by using an electron beam evaporation method, and then the pattern is stripped to form the source and drain of the carbon nanotube transistor.

[0048] It should be noted that in addition to Pd, other materials such as Pt can also be used. In addition, in addition to the above-mentioned photolithography-stripping process, a growth-etching process can also be used, that is, the source and drain metal is first grown, then photolithography is performed, and then etching (including plasma etching, etc.) is used to form the source and drain metal.

[0049] In step S402, based on the source and drain of the CNT transistor, a photoetching defines a channel region of the CNT transistor, and carbon tubes outside the channel region are etched to deposit a yttrium oxide layer.

[0050] In actual implementation, as shown in FIG. 5, a CNT channel region is defined by photoetching, carbon tubes outside the channel region are etched by oxygen plasma, and a yttrium oxide (Y2O3) layer is deposited.

[0051] In step S403, hafnium oxide is deposited on the yttrium oxide layer to take the hafnium oxide as a gate oxide layer of the CNT transistor, and the hafnium oxide and the yttrium oxide layer in the interconnection region are etched and removed to expose the first metal.

[0052] In actual implementation, as shown in FIG. 5, hafnium oxide (HfO2) is deposited by an atomic layer deposition (ALD) device to take the hafnium oxide as a gate oxide layer of a top-gate CNT transistor, and the HfO2 in the interconnection region is etched and removed by inductively coupled plasma (ICP) etching, and then the Y2O3 is etched by wet etching to expose the metal for subsequent interconnection.

[0053] It should be noted that the HfO2 can be replaced by other materials such as Al2O3 or a combination thereof, for example, Al2O+HfO2, and the growth method can be ALD, PECVD, PEALD, etc.

[0054] In step S404, based on the first metal, a photoetching defines and evaporates a preset metal material to obtain a common gate of the CNT transistor and the first IGZO transistor.

[0055] In actual implementation, as shown in FIG. 5, a gate region is defined by photoetching, Pd is evaporated as a common gate of the CNT and IGZO transistors, and the gate metal is stripped; in addition to Pd, other materials such as Pt can also be used.

[0056] It should be noted that in addition to the above photoetching-stripping process, the common gate metal can also be formed by a growth-etching process, that is, the gate metal is first grown in the form of a body as described above, then photoetched, and then etched (including plasma etching, etc.) to form the common gate metal.

[0057] In step S405, first aluminum oxide is deposited on the common gate to take the first aluminum oxide as a gate oxide layer of the first IGZO transistor, second aluminum oxide is deposited on the second preset semiconductor substrate by an atomic layer deposition device to take the second aluminum oxide as a gate oxide layer of the second IGZO transistor, and the aluminum oxide in the interconnection region of the first IGZO transistor is removed to expose the second metal.

[0058] In actual implementation, as shown in FIG. 5, aluminum oxide (Al2O3) is deposited on the common gate metal by ALD as the gate oxide layer of the IGZO back-gate transistor, and the Al2O3 in the interconnection area is removed by ICP etching again to expose the metal for subsequent interconnection. It should be noted that the IGZO transistor in the low-leakage transistor and the vertical complementary field effect transistor will be prepared at the same time in this process, and the preparation process is the same. Al2O3 can also be replaced by other materials such as HfO2, or a combination thereof, for example, Al2O+HfO2, and the growth method can be ALD, PECVD, PEALD, etc.

[0059] In step S406, an indium gallium zinc oxide film is grown on the gate oxide layer of the first IGZO transistor and the gate oxide layer of the second IGZO transistor, and a pre-set metal material is defined and evaporated on the indium gallium zinc oxide film by photolithography to obtain the source and drain of the first IGZO transistor and the source and drain of the second IGZO transistor.

[0060] In actual implementation, as shown in FIG. 5, the IGZO film is grown by ALD, and the source and drain area of the IGZO transistor can be defined by photolithography, and titanium / palladium (Ti / Pd) is evaporated as the source and drain metal of the IGZO transistor. It should be noted that the IGZO transistor in the low-leakage transistor and the vertical complementary field effect transistor is prepared at the same time in this process. Ti as the source and drain contact metal of IGZO can also be replaced by Mo, TiN, ITO, etc.; Pd as the protective metal can be replaced by Pt, etc. In addition, the patterning of the source and drain metal can also use the growth-etching process, that is, the source and drain metal is first grown, then photolithography is performed, and then etching (including plasma etching, etc.) is used to form the source and drain metal.

[0061] In step S407, the channel region of the first IGZO transistor is defined by photolithography on the source and drain of the first IGZO transistor, the channel region of the second IGZO transistor is defined by photolithography on the source and drain of the second IGZO transistor, and the first IGZO transistor and the second IGZO transistor outside the channel region are etched to obtain a capacitorless dynamic random access memory structure.

[0062] In actual implementation, as shown in FIG. 5, the IGZO channel region is defined by photolithography, and the IGZO outside the channel region is etched by wet or dry etching to realize channel isolation, thereby forming a capacitorless dynamic random access memory composed of a CNT transistor and two IGZO transistors.

[0063] It should be noted that the preparation process of the above capacitorless dynamic random access memory can be adjusted according to actual conditions, so that the free selection of the top gate / back gate transistor channel material can be realized, for example, the top gate IGZO transistor can be prepared first, and then the back gate CNT transistor with a common gate can be prepared. In addition, the CFET channel material can be selected according to actual needs, and different types of CFET 2T0C structures can be prepared.

[0064] It should be noted that the above explanation of the capacitorless dynamic random access memory embodiment is also applicable to the preparation method of the capacitorless dynamic random access memory of the embodiment, which will not be repeated here.

[0065] The preparation method of the capacitorless dynamic random access memory according to the embodiments of the present disclosure has the following beneficial effects:

[0066] (1) The capacitorless dynamic random access memory CFET 2T0C proposed in the embodiments of the present disclosure has both pull-up and pull-down tubes, and the readout speed is faster, solving the problem that the existing oxide semiconductor device-based capacitorless dynamic random access memory 2T0C has only pull-up or pull-down tubes when reading, and the readout speed is slow.

[0067] (2) The capacitorless dynamic random access memory CFET 2T0C proposed in the embodiments of the present disclosure uses a complementary logic read tube, which can better isolate the influence of bias stress on the output, thereby having better stability, solving the problem that the existing oxide semiconductor device-based capacitorless dynamic random access memory 2T0C uses a single read tube, and the readout result is easily affected by bias stress.

[0068] (3) The CFET 2T0C proposed in the embodiments of the present disclosure outputs a voltage without increasing the cell area, which can be directly applied to a circuit, solving the problem that the existing oxide semiconductor device-based capacitorless dynamic random access memory 2T0C outputs a current, which is difficult to be directly applied to a digital circuit.

[0069] FIG. 6 is a structural schematic diagram of an electronic device provided by the embodiments of the present disclosure. The electronic device can include:

[0070] The memory 601, the processor 602, and the computer program stored on the memory 601 and executable on the processor 602.

[0071] The processor 602 implements the preparation method of the capacitorless dynamic random access memory provided in the above embodiments when executing the program.

[0072] Further, the electronic device further includes:

[0073] The communication interface 603 is used for communication between the memory 601 and the processor 602.

[0074] a memory 601 for storing a computer program executable on the processor 602.

[0075] The memory 601 can include a high-speed RAM memory, and can also include a non-volatile memory, for example at least one disk memory.

[0076] If the memory 601, the processor 602 and the communication interface 603 are implemented independently, the communication interface 603, the memory 601 and the processor 602 can be connected to each other through a bus and complete communication between each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, only one thick line is used in FIG. 6, but it does not mean that there is only one bus or only one type of bus.

[0077] Optionally, in a specific implementation, if the memory 601, the processor 602 and the communication interface 603 are integrated on a chip, the memory 601, the processor 602 and the communication interface 603 can complete communication between each other through an internal interface.

[0078] The processor 602 can be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure.

[0079] The embodiments of the present disclosure further provide a computer program product, and the computer program / instruction is executed by the processor to implement the preparation method of the capacitorless dynamic random memory as above.

[0080] The embodiments of the present disclosure further provide a computer readable storage medium, and the computer program is stored on the computer readable storage medium, and the program is executed by the processor to implement the preparation method of the capacitorless dynamic random memory as above.

[0081] In the description of the disclosure, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the disclosure. In the description of the disclosure, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or N embodiments or examples. In addition, the skilled person in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples, without contradiction.

[0082] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the disclosure, the meaning of "N" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0083] Any process or method descriptions in flow charts or otherwise described herein represent embodiments that can be understood as a module, segment, or portion of code that includes one or N executable instructions for implementing the specified logical function or process, and the scope of the preferred embodiments of the disclosure includes additional implementation in which the functions described are performed in a different order, including substantially simultaneously, or in reverse order, as appropriate, depending on the functionality involved, which should be understood by those skilled in the art of the embodiments of the disclosure.

[0084] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0085] It should be understood that the various parts of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0086] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0087] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing module, or each unit can exist physically separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module. When the integrated module is realized in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0088] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A capacitorless dynamic random access memory, wherein, The application relates to a capacitorless dynamic random access memory, comprising: a low-leakage transistor and a vertical complementary field effect transistor, the low-leakage transistor is used as a write transistor, the drain of the low-leakage transistor is connected with the common gate of the vertical complementary field effect transistor, so as to write target data into a preset data source; the vertical complementary field effect transistor is used as a read transistor, the drain of a P-type transistor and the drain of an N-type transistor in the vertical complementary field effect transistor are connected with each other, the source of the P-type transistor is connected with a power supply end, and the source of the N-type transistor is connected with a ground wire, so as to read the target data from the preset data source.

2. The capacitorless dynamic random access memory of claim 1, wherein, The P-type channel material of the low-leakage transistor adopts any one of a P-type doped silicon, a P-type nanomaterial and a P-type oxide.

3. The capacitorless dynamic random access memory of claim 1, wherein, The N-type channel material of the low-leakage transistor adopts any one of an N-type doped silicon, an N-type oxide and an N-type nanomaterial.

4. The capacitorless dynamic random access memory of claim 1, wherein, The P-type channel material of the vertical complementary field effect transistor adopts any one of a P-type doped silicon, a P-type nanomaterial and a P-type oxide.

5. The capacitorless dynamic random access memory of claim 1, wherein, The N-type channel material of the vertical complementary field effect transistor adopts any one of an N-type doped silicon, an N-type oxide and an N-type nanomaterial.

6. The capacitorless dynamic random access memory of claim 1, wherein, The low-leakage transistor is an IGZO transistor, and the vertical complementary field effect transistor is a CFET transistor composed of a CNT transistor and an IGZO transistor.

7. A method for fabricating a capacitorless dynamic random access memory, wherein, The application further relates to a preparation method of the capacitorless dynamic random access memory, comprising the following steps: deposition of a layer of carbon nanotubes on a first preset semiconductor substrate, photolithography definition on the carbon nanotubes and evaporation of preset metal materials to obtain the source and drain of a CNT transistor; based on the source and drain of the CNT transistor, photolithography definition of the channel region of the CNT transistor and etching of the carbon tubes outside the channel region to deposit a yttrium oxide layer; deposition of hafnium oxide on the yttrium oxide layer to take the hafnium oxide as the gate oxide layer of the CNT transistor, and etching removal of the hafnium oxide of the interconnection region and the yttrium oxide layer to expose a first metal; based on the first metal, photolithography definition and evaporation of the preset metal materials to obtain the common gate of the CNT transistor and a first IGZO transistor; deposition of first aluminum oxide on the common gate to take the first aluminum oxide as the gate oxide layer of the first IGZO transistor, deposition of second aluminum oxide on a second preset semiconductor substrate by using an atomic layer deposition device to take the second aluminum oxide as the gate oxide layer of a second IGZO transistor, and removal of the aluminum oxide of the interconnection region of the first IGZO transistor to expose a second metal; growth of an indium gallium zinc oxide thin film on the gate oxide layer of the first IGZO transistor and the gate oxide layer of the second IGZO transistor, and photolithography definition and evaporation of preset metal materials on the indium gallium zinc oxide thin film to obtain the source and drain of the first IGZO transistor and the source and drain of the second IGZO transistor; Photoetching the channel region of the first IGZO transistor on the source and drain of the first IGZO transistor, photoetching the channel region of the second IGZO transistor on the source and drain of the second IGZO transistor, and etching the first IGZO transistor and the second IGZO transistor outside the channel region, to obtain a capacitorless dynamic random access memory structure.

8. An electronic device, comprising: The computer program / instructions, when executed by a processor, implement the preparation method of the capacitorless dynamic random access memory of claim 7. The computer program / instructions, when executed by a processor, implement the preparation method of the capacitorless dynamic random access memory of claim 7.

9. A computer program product, wherein, The program is executed by a processor for implementing the preparation method of the capacitorless dynamic random access memory of claim 7.

10. A computer readable storage medium having stored thereon a computer program, wherein, ​

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