Amplification device and balun

Abstract

The present invention makes it possible to obtain low noise and low distortion in both of transistors to which a push-pull operation using a balun is applied.　This amplification device comprises: a first field effect transistor in which an input voltage is applied to the gate; a second field effect transistor connected in series to the first field effect transistor; a first inductor connected to the gate of the second field effect transistor; a second inductor connected in series to the source of the first field effect transistor and step-down inductively coupled to the first inductor; and a third inductor connected in series to the source of the second field effect transistor and step-down inductively coupled to the first inductor.

Description

Amplifiers and baluns

[0001] The present technology relates to an amplifier device and a balun. More particularly, the present technology relates to an amplifier device and a balun that are applicable to push-pull operation.

[0002] A low noise amplifier (LNA) used for amplifying radio frequency bands includes an amplifying device coupled in a triple-coupled arrangement of inductors. For example, a technique is disclosed in which a second inductor is inductively coupled to a first inductor and couples the amplifying device to a first node, and a third inductor is inductively coupled to the first inductor and the second inductor and couples the amplifying device to a second node (see, for example, Patent Document 1).

[0003] Special table 2017-536779 publication

[0004] However, with the above-mentioned conventional technology, it is difficult to reduce noise and distortion in both transistors to which push-pull operation using a balun is applied.

[0005] This technology was developed in light of these circumstances, and aims to enable low noise and low distortion in both transistors to which push-pull operation using a balun is applied.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an amplifier device including: a first field-effect transistor having a gate to which an input voltage is applied, a second field-effect transistor connected in series with the first field-effect transistor, a first inductor connected to a gate of the second field-effect transistor, a second inductor connected in series with a source of the first field-effect transistor and step-down inductively coupled to the first inductor, and a third inductor connected in series with the source of the second field-effect transistor and step-down inductively coupled to the first inductor, thereby providing an effect of canceling noise generated in the first field-effect transistor and the second field-effect transistor via a balun.

[0007] In the first aspect, an equivalent turns ratio between the first inductor, the second inductor, and the third inductor may be 1:n:n (0<n<1), thereby providing an effect that the second inductor and the third inductor are step-down inductively coupled to the first inductor.

[0008] In the first aspect, the first inductor, the second inductor, and the third inductor may form an on-chip balun, thereby providing an effect that the first inductor, the second inductor, and the third inductor are integrated on a chip on which the first field-effect transistor and the second field-effect transistor are formed.

[0009] In the first aspect, the gate of the first field-effect transistor may be connected to a center tap of the first inductor, thereby achieving low noise in both field-effect transistors to which push-pull operation using a balun is applied.

[0010] In the first aspect, the first field effect transistor may be an N-channel field effect transistor, and the second field effect transistor may be a P-channel field effect transistor, thereby providing an effect that an input voltage is converted into an output current based on a push-pull operation of the first field effect transistor and the second field effect transistor.

[0011] In the first aspect, the first field-effect transistor and the second field-effect transistor may convert the input voltage into an output current based on a push-pull operation, thereby producing an effect that the output current is generated based on a current flowing into the first field-effect transistor and a current flowing out of the second field-effect transistor.

[0012] In the first aspect, the amplifier circuit may further include a cascode transistor connected between the first field effect transistor and the second field effect transistor, thereby increasing the conversion gain of the amplifier circuit.

[0013] In addition, in the first aspect, the power supply may further include a CMFB (Common Mode Feedback) circuit connected to the gate of the second field effect transistor, thereby providing an effect of adjusting the operating point of the second field effect transistor.

[0014] In addition, in the first aspect, the amplifier circuit may further include a matching circuit connected to the gate of the first field effect transistor and matching input impedance, thereby improving the conversion efficiency of the amplifier circuit.

[0015] In the first aspect, the power supply may further include a capacitor connected to the gate of the first field-effect transistor to cut DC components, thereby providing an effect that only AC components are applied to the gate of the first field-effect transistor.

[0016] In the first aspect, the power supply may further include a bias circuit connected to the first inductor, thereby providing an effect of adjusting the gate voltage of the first field effect transistor.

[0017] The second aspect may also include a first field-effect transistor having a gate to which an input voltage is applied, a second field-effect transistor connected in series with the first field-effect transistor, a first inductor having an intermediate tap connected to the gate of the first field-effect transistor and one end connected to the gate of the second field-effect transistor, a second inductor connected in series with the source of the first field-effect transistor and step-down inductively coupled to the first inductor, and a third inductor connected in series with the source of the second field-effect transistor and step-down inductively coupled to the first inductor, thereby providing an effect of canceling noise generated in the first field-effect transistor and the second field-effect transistor via the balun.

[0018] A third aspect of the present invention is a balun including a first inductor having a first winding formed on a first layer and a second layer connected through a via, a terminal provided on the first layer, and a center tap provided on the second layer, a second inductor having a second winding provided on a third layer, and a third inductor having a third winding provided on the third layer adjacent to the second winding, thereby providing an effect of stacking the balun with a center tap.

[0019] In addition, in the third aspect, the second inductor and the third inductor may be arranged to overlap the first inductor, thereby providing an effect that the second inductor and the third inductor are inductively coupled to the first inductor while the balun is laminated.

[0020] In the third aspect, the second inductor and the third inductor may be formed alternately on the third layer, thereby providing an effect that the second inductor and the third inductor are inductively coupled to each other while the balun is laminated.

[0021] In the third aspect, the balun may further include a wiring layer in which the first inductor, the second inductor, and the third inductor are formed, and a semiconductor substrate in which the wiring layer is formed, thereby achieving the effect of integrating a device using the balun.

[0022] FIG. 1 is a diagram showing a configuration example of an amplifier device according to a first embodiment; FIG. 2 is a diagram showing a noise cancellation method for the amplifier device according to the first embodiment; FIG. 3 is a perspective view showing a configuration example of an on-chip balun applied to the amplifier device according to the first embodiment; FIG. 4 is a plan view showing a configuration example of an on-chip balun applied to the amplifier device according to the first embodiment; FIG. 5 is a plan view showing a configuration example of a first inductor of the on-chip balun applied to the amplifier device according to the first embodiment; FIG. 6 is a plan view showing a configuration example of second and third inductors of the on-chip balun applied to the amplifier device according to the first embodiment; FIG. 7 is a diagram showing a configuration example of an amplifier device according to a second embodiment; FIG. 8 is a diagram showing a configuration example of an amplifier device according to a third embodiment; and FIG. 9 is a block diagram showing a configuration example of a communication device to which an amplifier device according to a fourth embodiment is applied.

[0023] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which a step-down inductively coupled balun is applied to an amplifier device to which push-pull operation is applied) 2. Second embodiment (an example in which a cascode transistor, a CMFB circuit, a matching circuit, a bias circuit, and a DC cut capacitor are applied to an amplifier device with a push-pull configuration using a step-down inductively coupled balun) 3. Third embodiment (an example in which an amplifier device with a push-pull configuration using a step-down inductively coupled balun is used as a voltage output) 4. Fourth embodiment (an example in which an amplifier device with a push-pull configuration using a step-down inductively coupled balun is applied to a communication circuit)

[0024] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an amplifier device according to a first embodiment.

[0025] In the figure, the amplifier device amplifies an input voltage Vin and converts it into an output current Io. In this case, the amplifier device can operate as an LNTA (Low Noise Transconductance Amplifier). The amplifier device includes field-effect transistors M1 and M2 and a balun BA.

[0026] The field-effect transistors M1 and M2 are connected in series. The field-effect transistor M1 can be an N-channel field-effect transistor, and the field-effect transistor M2 can be a P-channel field-effect transistor. In this case, the field-effect transistors M1 and M2 can convert the input voltage Vin into an output current Io based on a push-pull operation. In the push-pull operation, the field-effect transistor M1 can cause the output current Io to flow in, and the field-effect transistor M2 can cause the output current Io to flow out.

[0027] The balun BA has a step-down inductively coupled primary side and secondary side. The balun BA may be an on-chip balun. In this case, the amplifier can cancel noise from the field-effect transistors M1 and M2 based on a push-pull operation using the step-down inductively coupled balun BA. The balun BA includes inductors L1 to L3.

[0028] Inductor L1 is placed on the primary side of balun BA. Inductors L2 and L3 are placed on the secondary side of balun BA. In this case, the equivalent winding ratio of inductors L1 to L3 can be set to 1:n:n (0<n<1).

[0029] One end of inductor L1 is connected to the gate of field-effect transistor M2. A center tap of inductor L1 is connected to the gate of field-effect transistor M1. Inductor L2 is connected in series with the source of field-effect transistor M1 and is step-down inductively coupled to inductor L1. Inductor L3 is connected in series with the source of field-effect transistor M2 and is step-down inductively coupled to inductor L1.

[0030] 2 is a diagram showing a noise cancellation method for the amplifier device according to the first embodiment. Note that although the diagram shows a noise cancellation method for the field-effect transistor M1, the noise cancellation method for the field-effect transistor M2 is similar.

[0031] In the figure, the current Ino flowing into the field-effect transistor M1 includes a noise current In. The noise current In flows through the field-effect transistor M1 to the inductor L2. At this time, the source voltages of the field-effect transistors M1 and M2 are raised by ΔVn, and a voltage of -AΔVn is generated across the inductor L1. Here, A is a conversion coefficient. At this time, the inductor L2 is step-down inductively coupled to the inductor L1, so A > 1, and can be given by A = 1 / n. When a voltage of -AΔVn is generated across the inductor L1, this voltage controls the gate potentials of the field-effect transistors M1 and M2, generating cancellation currents Ic and Ic' in the field-effect transistors M1 and M2. The cancellation currents Ic and Ic' cancel out the noise current In, thereby canceling the noise current In contained in the current Ino. In this case, by setting A>1, the amplifier device can stably generate cancellation currents Ic and Ic' that cancel the noise current In, and can stably cancel the noise current In contained in the current Ino.

[0032] Fig. 3 is a perspective view showing a configuration example of an on-chip balun applied to the amplifier device according to the first embodiment, Fig. 4 is a plan view showing a configuration example of an on-chip balun applied to the amplifier device according to the first embodiment, Fig. 5 is a plan view showing a configuration example of a first inductor of the on-chip balun applied to the amplifier device according to the first embodiment, and Fig. 6 is a plan view showing configuration examples of second and third inductors of the on-chip balun applied to the amplifier device according to the first embodiment.

[0033] 3 to 6, the balun BA can be formed in a multi-layer wiring layer. The multi-layer wiring layer on which the balun BA is formed can be disposed on a semiconductor substrate on which the field-effect transistors M1 and M2 are formed. The semiconductor substrate can be made of, for example, Si, GaAs, InGaAs, SiC, or GaN.

[0034] The multilayer wiring layer in which the balun BA is formed includes wiring layers LH1 to LH4 and via layers LV1 and LV2. The via layer LV1 is disposed between the wiring layers LH1 and LH2, and the via layer LV2 is disposed between the wiring layers LH3 and LH4. The wiring layers LH1 and LH2 can be disposed above the wiring layer LH3. The conductors formed in the wiring layers LH1 and LH2 can have higher conductivity than the conductors formed in the wiring layer LH3. The conductivity of the conductors used for the inductor L1 is preferably higher than that of the conductors used for the inductors L2 and L3.

[0035] An inductor L1 is formed in the wiring layers LH1 and LH2. A via VA1 is formed in the via layer LV1. The inductors L1 formed in each wiring layer LH1 and LH2 can be arranged overlapping each other. The inductors L1 formed in each wiring layer LH1 and LH2 are connected to each other via the via VA1. Terminals P1 and Q1 of the inductor L1 are arranged in the wiring layer LH1. Note that, since the terminals P1 and Q1 of the inductor L1 are connected to the wiring layers LH1 and LH2 via the via, they can be arranged in either the wiring layer LH1 or the wiring layer LH2. An intermediate tap T1 of the inductor L1 is arranged in the wiring layer LH2.

[0036] Inductors L2 and L3 are formed on the wiring layer LH3. The inductors L2 and L3 are arranged adjacent to each other. In this case, the inductors L2 and L3 can be formed alternately on the wiring layer LH3. The inductors L2 and L3 can also be arranged so as to overlap the inductor L1. Terminals P2 and P3 of the inductors L2 and L3 are arranged on the wiring layer LH3.

[0037] Wiring H1 and H2 are formed in the wiring layer LH4. Vias VA2 and VA3 are formed in the via layer LV2. Wiring H1 is connected to inductor L3 via via VA3. Wiring H2 is connected to inductor L2 via via VA2. Terminals Q2 and Q3 of each inductor L2 and L3 are arranged in the wiring layer LH4. Terminal Q2 of inductor L2 is connected to the source of field-effect transistor M1, and terminal Q3 of inductor L3 is connected to the source of field-effect transistor M2. Note that FIGS. 4 to 6 show the planar shapes of vias VA1 to VA3 and their positions on the plane, and omit the interlayer connections via vias VA1 to VA3.

[0038] In this way, in the first embodiment described above, the step-down inductively coupled balun BA is applied to an amplifier that employs push-pull operation, thereby achieving low noise in both field-effect transistors M1 and M2 that employ push-pull operation using the balun BA.

[0039] Furthermore, inductor L1 is formed in wiring layers LH1 and LH2, and inductors L2 and L3 are formed in wiring layer LH3, with inductors L2 and L3 arranged to overlap inductor L1. This allows the balun BA to be integrated while improving the Q value and coupling coefficient of the balun BA, and reduces noise in the amplifier device while suppressing an increase in the size of the amplifier device applicable to push-pull operation.

[0040] 2. Second Embodiment In the first embodiment described above, a step-down inductively coupled balun BA is applied to an amplifier device employing a push-pull operation. In this second embodiment, a cascode transistor, a CMFB circuit, a matching circuit, a bias circuit, and a DC-cut capacitor are applied to an amplifier device having a push-pull configuration in which a step-down inductively coupled balun BA is used.

[0041] FIG. 7 is a diagram illustrating an example of the configuration of an amplifier according to the second embodiment.

[0042] 1, this amplifier device is configured by adding a cascode transistor 204, a CMFB circuit 201, a matching circuit 202, a bias circuit 203, and a DC blocking capacitor C5 to the amplifier device of the first embodiment described above. The other configurations of the amplifier device of the second embodiment are the same as those of the amplifier device of the first embodiment described above.

[0043] A first potential VSS is applied to one end of the inductor L2, and a second potential VDD is applied to one end of the inductor L3. The first potential VSS may be a ground potential, and the second potential VDD may be a power supply potential.

[0044] The cascode transistor 204 increases the conversion gain of the amplifier circuit. The cascode transistor 204 is connected between the field-effect transistors M1 and M2. The cascode transistor 204 includes the field-effect transistors M3 and M4. The field-effect transistors M3 and M4 are connected in series with each other. In this case, the output current Io of this amplifier device is output from the connection point of the field-effect transistors M3 and M4. The source of the field-effect transistor M3 is connected to the drain of the field-effect transistor M1, and the source of the field-effect transistor M4 is connected to the drain of the field-effect transistor M2. A bias voltage Va1 is applied to the gate of the field-effect transistor M3, and a bias voltage Va2 is applied to the gate of the field-effect transistor M4. The bias voltages Va1 and Va2 can be set to fixed potentials. The field-effect transistor M3 can be an N-channel field-effect transistor, and the field-effect transistor M4 can be a P-channel field-effect transistor.

[0045] The CMFB circuit 201 adjusts the operating point of the field-effect transistor M2. The CMFB circuit 201 is connected to the gate of the field-effect transistor M2. The CMFB circuit 201 includes an operational amplifier P, resistors R2 and R3, and a capacitor C4. The resistor R2 and the capacitor C4 are connected in series. The series circuit of the resistor R2 and the capacitor C4 is connected between the output terminal and the inverting input terminal of the operational amplifier P. A reference signal Vref is input to the inverting input terminal of the operational amplifier P. The non-inverting input terminal of the operational amplifier P is connected to the connection point of the field-effect transistors M3 and M4. The output terminal of the operational amplifier P is connected to the gate of the field-effect transistor M2 via the resistor R3. At this time, the operational amplifier P compares the potential of the connection point of the field-effect transistors M3 and M4 with the reference signal Vref. The gate potential of the field-effect transistor M2 is controlled so that the potential of the connection point of the field-effect transistors M3 and M4 matches the reference signal Vref.

[0046] The matching circuit 202 matches the input impedance of the amplifier circuit. The matching circuit 202 is connected to the gate of the field-effect transistor M1. The matching circuit 202 includes capacitors C1 and C2. The capacitor C1 cuts out the DC component contained in the input voltage Vin and applies it to the gate of the field-effect transistor M1. The capacitor C1 is connected in series to the gate of the field-effect transistor M1. The capacitor C2 is connected between the gate of the field-effect transistor M1 and a first potential VSS.

[0047] The bias circuit 203 adjusts the gate voltage of the field-effect transistor M1. The bias circuit 203 is connected to an inductor L1. The bias circuit 203 includes a field-effect transistor M5, a resistor R1, and a capacitor C3. The field-effect transistor M5 may be an N-channel field-effect transistor. The capacitor C3 is connected between the inductor L1 and a first potential VSS. A reference current Iref is input to the drain of the field-effect transistor M5. The gate of the field-effect transistor M5 is connected to the drain of the field-effect transistor M5. The source of the field-effect transistor M5 is connected to the first potential VSS. The resistor R1 is connected between the connection point of the inductor L1 and the capacitor C3 and the drain of the field-effect transistor M5. The reference current Iref flows to the capacitor C3 via the resistor R1, and a voltage is generated according to the charge stored in the capacitor C3. The gate potential of the field effect transistor M5 is controlled in accordance with the voltage generated across the capacitor C3, and the reference current Iref flows through the field effect transistor M5, thereby controlling the voltage generated across the capacitor C3.

[0048] The DC blocking capacitor C5 blocks the DC component superimposed on the inductor L1 and applies it to the gate of the field effect transistor M2. The DC blocking capacitor C5 is connected between one end of the inductor L1 and the gate of the field effect transistor M2.

[0049] In this way, in the second embodiment described above, the cascode transistor 204, the CMFB circuit 201, the matching circuit 202, the bias circuit 203, and the DC blocking capacitor C5 are applied to an amplifier having a push-pull configuration in which a step-down inductively coupled balun BA is used, thereby improving the accessibility of the amplifier having a push-pull configuration in which a step-down inductively coupled balun BA is used.

[0050] 3. Third Embodiment In the first embodiment described above, a push-pull configuration amplifier using a step-down inductively coupled balun BA is used to output a current. In this third embodiment, a push-pull configuration amplifier using a step-down inductively coupled balun BA is used to output a voltage. Note that, although the third embodiment shows an example in which a voltage is extracted as a voltage output based on conversion using a transformer, a voltage can also be extracted as a voltage output in the first and second embodiments described above.

[0051] FIG. 8 is a diagram illustrating an example of the configuration of an amplifier according to the third embodiment.

[0052] In the figure, this amplifier device is the same as the amplifier device of the first embodiment except that a transformer TR and a DC blocking capacitor C6 are added. Other configurations of the amplifier device of the third embodiment are the same as those of the amplifier device of the first embodiment.

[0053] A bias voltage Vb1 is applied to one end of the inductor L1, a first potential VSS is applied to one end of the inductor L2, and a second potential VDD is applied to one end of the inductor L3. The bias voltage Vb1 may be a fixed potential.

[0054] The transformer TR converts the output current Io of the amplifier device into an output voltage Vo and outputs the output voltage Vo. The transformer TR includes inductors L4 and L5. The inductor L4 is provided on the primary side of the transformer TR, and the inductor L5 is provided on the secondary side of the transformer TR. A bias voltage Vb2 is applied to one end of the inductor L4, and a bias voltage Vb3 is applied to one end of the inductor L5. The bias voltages Vb2 and Vb3 may be fixed potentials.

[0055] The drains of the field-effect transistors M1 and M2 are connected to the primary side of a transformer TR via a DC blocking capacitor C6. The output current Io is converted into an output voltage Vo based on the inductive coupling of the inductors L4 and L5, and the output voltage Vo is output from the secondary side of the transformer TR.

[0056] In this way, in the third embodiment described above, the current output of the push-pull amplifier using the step-down inductively coupled balun BA is input to the transformer TR, which allows the current output of the push-pull amplifier using the step-down inductively coupled balun BA to be converted into a voltage output and output.

[0057] 4. Fourth Embodiment In the first embodiment described above, a step-down inductively coupled balun BA is applied to an amplifier device employing a push-pull operation. In this fourth embodiment, an amplifier device with a push-pull configuration employing a step-down inductively coupled balun BA is applied to a receiver circuit.

[0058] FIG. 9 is a block diagram showing an example of the configuration of a communication device to which an amplifier device according to the fourth embodiment is applied.

[0059] In the figure, the communication device performs wireless communication. The communication device can support quadrature modulation. The communication device may be mounted on a mobile terminal such as a smartphone, or on a mobile object such as a drone or vehicle. The communication device may support near field communication (NFC), Wi-Fi, Bluetooth, cellular communication, satellite communication, etc. The communication device includes an antenna 401, a switch 402, a receiving circuit 403, a digital circuit 404, a phase locked loop (PLL) circuit 405, and a transmitting circuit 406.

[0060] The antenna 401 converts electromagnetic waves into RF (Radio Frequency) signals and outputs them, or converts RF signals into electromagnetic waves and radiates them into space.

[0061] The switch 402 switches the connection of the antenna 401 between the receiving circuit 403 and the transmitting circuit 406. The switch 402 may be configured using a field effect transistor.

[0062] The receiving circuit 403 receives the RF signal output from the antenna 401. The receiving circuit 403 includes an amplifier circuit 411, mixers 412A and 412B, TIAs (Transmission Impedance Amplifiers) 413A and 413B, PGAs (Programmable Gain Amplifiers) 414A and 414B, LPFs (Low Pass Filters) 415A and 415B, and ADCs (Analog to Digital Converters) 416A and 416B. Mixers 412A and 412B are connected to the downstream of the amplifier circuit 411, TIAs 413A and 413B are connected to the downstream of each mixer 412A and 412B, PGAs 414A and 414B are connected to the downstream of each TIA 413A and 413B, LPFs 415A and 415B are connected to the downstream of each PGA 414A and 414B, and ADCs 416A and 416B are connected to the downstream of each LPF 415A and 415B.

[0063] The amplifier circuit 411 amplifies the RF signal output from the antenna 401 and outputs the amplified signal to the mixers 412A and 412B. The amplifier circuit 411 may be an LNTA. In this case, the amplifier circuit 411 may use the amplifier device according to the first or second embodiment.

[0064] Each of the mixers 412A and 412B down-converts the RF signal output from the amplifier circuit 411 based on the clock signal output from the PLL circuit 405, and outputs the down-converted signal to the TIAs 413A and 413B, respectively.

[0065] Each of the TIAs 413A and 413B converts the baseband signals output from the mixers 412A and 412B into voltages and outputs them to the PGAs 414A and 414B, respectively.

[0066] Each PGA 414A, 414B amplifies the output from each TIA 413A, 413B and outputs the amplified output to each LPF 415A, 415B.

[0067] Each of the LPFs 415A and 415B attenuates the high frequency components of the output from each of the PGAs 414A and 414B, and outputs the attenuated components to the ADCs 416A and 416B, respectively.

[0068] Each ADC 416A, 416B converts the output from each LPF 415A, 415B into a digital value and outputs it to the digital circuit 404.

[0069] The digital circuit 404 digitally processes the baseband signal output from the receiving circuit 403 and controls the PLL circuit 405 .

[0070] The PLL circuit 405 generates a clock signal based on a PLL loop and outputs it to the mixers 412A and 412B and the transmission circuit 406. In this case, the PLL circuit 405 can support In-Phase (in-phase) and Quadrature-Phase (quadrature phase). The PLL circuit 405 may be an ADPLL (all digital PLL) circuit.

[0071] The transmitting circuit 406 amplifies the RF signal output via the PLL circuit 405 and outputs the amplified signal to the antenna 401 .

[0072] In this way, in the fourth embodiment described above, a push-pull amplifier using a step-down inductively coupled balun BA is applied to a communication device, thereby improving the signal-to-noise ratio of the communication device and improving the receiving performance of the communication device.

[0073] In the fourth embodiment, a push-pull amplifier using a step-down inductively coupled balun BA is applied to a communication device. In this case, amplifiers with different matching frequency bands may be applied to the communication device to enable multi-band compatibility.

[0074] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0075] The present technology may also be configured as follows: (1) An amplifier device comprising: a first field-effect transistor having a gate to which an input voltage is applied; a second field-effect transistor connected in series to the first field-effect transistor; a first inductor connected to a gate of the second field-effect transistor; a second inductor connected in series to a source of the first field-effect transistor and step-down inductively coupled to the first inductor; and a third inductor connected in series to the source of the second field-effect transistor and step-down inductively coupled to the first inductor. (2) The amplifier device according to (1), wherein an equivalent winding ratio of the first inductor, the second inductor, and the third inductor is 1:n:n (0<n<1). (3) The amplifier device according to (1) or (2), wherein the first inductor, the second inductor, and the third inductor form an on-chip balun. (4) The amplifier device according to any of (1) to (3), wherein the gate of the first field-effect transistor is connected to a center tap of the first inductor. (5) The amplifier device according to any one of (1) to (4), wherein the first field effect transistor is an N-channel field effect transistor and the second field effect transistor is a P-channel field effect transistor. (6) The amplifier device according to any one of (1) to (5), wherein the first field effect transistor and the second field effect transistor convert the input voltage to an output current based on a push-pull operation. (7) The amplifier device according to any one of (1) to (6), further comprising: a cascode transistor connected between the first field effect transistor and the second field effect transistor. (8) The amplifier device according to any one of (1) to (7), further comprising: a CMFB (Common Mode Feedback) circuit connected to the gate of the second field effect transistor. (9) The amplifier device according to any one of (1) to (8), further comprising: a matching circuit connected to the gate of the first field effect transistor and matching input impedance. (10) The amplifier device according to any one of (1) to (9), further comprising: a capacitor connected to the gate of the first field effect transistor and cutting DC components.(11) The amplifier device according to any one of (1) to (10), further comprising: a bias circuit connected to the first inductor. (12) An amplifier device comprising: a first field-effect transistor having a gate to which an input voltage is applied, a second field-effect transistor connected in series with the first field-effect transistor, a first inductor having a center tap connected to the gate of the first field-effect transistor and one end connected to the gate of the second field-effect transistor, a second inductor connected in series with a source of the first field-effect transistor and step-down inductively coupled to the first inductor, and a third inductor connected in series with the source of the second field-effect transistor and step-down inductively coupled to the first inductor. (13) A balun comprising: a first inductor, in which first windings formed on a first layer and a second layer are connected via a via, a terminal is provided on the first layer, and a center tap is provided on the second layer; a second inductor, in which a second winding is provided on a third layer; and a third inductor, in which a third winding is provided on the third layer adjacent to the second winding. (14) The balun according to (13), in which the second inductor and the third inductor are arranged to overlap the first inductor. (15) The balun according to (13) or (14), in which the second inductor and the third inductor are formed alternately on the third layer. (16) The balun according to any of (13) to (15), further comprising: a wiring layer in which the first inductor, the second inductor, and the third inductor are formed; and a semiconductor substrate in which the wiring layer is formed.

[0076] M1, M2 Field effect transistors L1 to L3 Inductors BA Balun

Claims

1. An amplifier comprising: a first field effect transistor to whose gate an input voltage is applied; a second field effect transistor connected in series with the first field effect transistor; a first inductor connected to the gate of the second field effect transistor; a second inductor connected in series with the source of the first field effect transistor and step-down inductively coupled to the first inductor; and a third inductor connected in series with the source of the second field effect transistor and step-down inductively coupled to the first inductor.

2. The amplifier device according to claim 1, wherein the equivalent winding ratio of the first inductor, the second inductor, and the third inductor is 1:n:n (0<n<1).

3. The amplifying device according to claim 1, wherein the first inductor, the second inductor, and the third inductor form an on-chip balun.

4. The amplifier device according to claim 1, wherein the gate of the first field effect transistor is connected to the center tap of the first inductor.

5. The amplifier device according to claim 1, wherein the first field effect transistor is an N-channel field effect transistor, and the second field effect transistor is a P-channel field effect transistor.

6. The amplifier device according to claim 1, wherein the first field-effect transistor and the second field-effect transistor convert the input voltage into an output current based on a push-pull operation.

7. The amplifier device according to claim 1, further comprising a cascode transistor connected between said first field effect transistor and said second field effect transistor.

8. The amplifier device according to claim 1, further comprising a CMFB (Common Mode Feedback) circuit connected to the gate of the second field effect transistor.

9. The amplifier device according to claim 1, further comprising a matching circuit connected to the gate of said first field effect transistor for matching input impedance.

10. The amplifier device according to claim 1, further comprising a capacitor connected to the gate of said first field effect transistor for cutting DC components.

11. The amplifier device of claim 1, further comprising: a bias circuit connected to the first inductor.

12. An amplifier device comprising: a first field effect transistor to whose gate an input voltage is applied; a second field effect transistor connected in series with the first field effect transistor; a first inductor having an intermediate tap connected to the gate of the first field effect transistor and one end connected to the gate of the second field effect transistor; a second inductor connected in series with the source of the first field effect transistor and inductively coupled to the first inductor in a step-down manner; and a third inductor connected in series with the source of the second field effect transistor and inductively coupled to the first inductor in a step-down manner.

13. A balun comprising: a first inductor, in which a first winding formed on a first layer and a second layer is connected through a via, a terminal is provided on the first layer, and a center tap is provided on the second layer; a second inductor, in which a second winding is provided on a third layer; and a third inductor, in which a third winding is provided on the third layer adjacent to the second winding.

14. The balun according to claim 13, wherein the second inductor and the third inductor are arranged to overlap the first inductor.

15. The balun according to claim 13, wherein the second inductor and the third inductor are formed alternately on the third layer.

16. The balun according to claim 13, further comprising: a wiring layer in which the first inductor, the second inductor, and the third inductor are formed; and a semiconductor substrate in which the wiring layer is formed.

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