Memory circuit, processing-in-memory apparatus, and electronic device

Abstract

Disclosed are a memory circuit, a processing-in-memory apparatus, and an electronic device. The memory circuit comprises a memory cell group, which comprises a plurality of memory cells. Each memory cell comprises a first transistor, a second transistor, and a capacitor. A first terminal of the first transistor and a second driving terminal of the second transistor are connected to the capacitor. In each memory cell in the memory cell group, a first driving terminal of the first transistor is connected to a first control terminal, a second terminal is connected to a second control terminal, and the first control terminal and the second control terminal are configured to control weight data stored in the memory cell. Among the plurality of memory cells in the memory cell group, third terminals of the second transistors are respectively connected to a plurality of input terminals, and fourth terminals are connected to an output terminal. The memory cell group receives a plurality of input signals by means of the plurality of input terminals, converts the plurality of input signals into an output signal on the basis of the weight data stored in the plurality of memory cells, and outputs the output signal at the output terminal. The memory circuit can be used in processing-in-memory architectures, and has higher reliability and processing efficiency.

Description

Storage circuit, storage-computing device and electronic equipment TECHNICAL FIELD

[0001] The present disclosure relates to data processing technology, and particularly relates to a storage circuit, a storage-computing device and an electronic equipment. BACKGROUND

[0002] In a traditional computing mode (for example, in a Von Neumann architecture), storage and computing are physically separated. When data processing is performed by using the computing mode, data is frequently transmitted between a storage device and a computing device, which causes transmission delay and energy consumption. With the development of big data and artificial intelligence technologies, the amount of data processing rapidly increases, and the demand for data transmission also rapidly increases. The transmission delay and energy consumption caused thereby are increasingly prominent, which restricts the development of data processing capability, and makes it difficult for the traditional computing mode to meet the demand for processing capability.

[0003] A storage-computing integrated architecture can physically fuse storage and computing, and perform computing by using a storage device or store data in a computing device, so as to reduce the demand for data transmission, reduce transmission delay and energy consumption, and greatly improve the efficiency of data processing. However, the storage-computing integrated architecture still faces challenges, for example, how to improve the reliability of the storage-computing integrated architecture in data processing. SUMMARY

[0004] Embodiments of the present disclosure provide a storage circuit, a storage-computing device and an electronic equipment, so as to perform data processing by using the storage circuit, and improve the reliability and efficiency of data processing.

[0005] In a first aspect, a storage circuit is provided. The storage circuit includes a group of storage units. Each storage unit in the group of storage units includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first terminal, a second terminal, and a first driving terminal. The second transistor includes a third terminal, a fourth terminal, and a second driving terminal. The first transistor includes a first oxide semiconductor structure, and a channel is formed in the first oxide semiconductor structure between the first terminal and the second terminal and controlled by the first driving terminal. The first terminal of the first transistor, the second driving terminal of the second transistor, and the capacitor are connected. In each storage unit in the group of storage units, the first driving terminal of the first transistor is connected to a first control terminal, and the second terminal of the first transistor is connected to a second control terminal. The first control terminal and the second control terminal are configured to control weight data stored in the storage units in the group of storage units. The third terminal of the second transistor in each storage unit in the group of storage units is connected to a plurality of input terminals, respectively, and the fourth terminal of the second transistor in each storage unit in the group of storage units is connected to an output terminal. The group of storage units is configured to receive a plurality of input signals through the plurality of input terminals, convert the plurality of input signals into an output signal based on the weight data stored in the storage units in the group of storage units, and output the output signal at the output terminal.

[0006] The storage circuit can use the group of storage units to perform operations, thereby achieving data processing inside the storage circuit, reducing the overhead of data transmission, and improving the efficiency and accuracy of data processing. The third terminal of the second transistor in each storage unit in the group of storage units can be connected to a plurality of input signals, respectively, and the fourth terminal can be connected to an output terminal. The weight data of the plurality of storage units in the group of storage units can be used to output the multiplication and accumulation result in the group of storage units. The storage circuit can perform operations, reduce the overhead of data transmission, and improve the efficiency of data processing. The first transistor with an oxide semiconductor structure has a smaller leakage current, and the capacitor can keep the charge at the storage node for a longer time, so that the weight data stored in the storage unit has a longer stability, thereby improving the accuracy of the multiplication and accumulation result in the group of storage units, and further improving the reliability of the storage circuit for data processing.

[0007] Optionally, the first oxide semiconductor structure has a band gap greater than or equal to 1.65 eV.

[0008] Optionally, the first oxide semiconductor structure includes an indium gallium zinc oxide structure, a germanium-doped indium germanium oxide structure, or an indium tin oxide structure.

[0009] Optionally, the first driving terminal of the first transistor in each storage unit in the group of storage units is connected to the same first control terminal, and the second terminal of the first transistor in each storage unit in the group of storage units is connected to different second control terminals.

[0010] Optionally, the first driving terminal of the first transistor in the plurality of memory cells in the memory cell group is connected to different first control terminals, and the second terminal of the first transistor in the plurality of memory cells in the memory cell group is connected to the same second control terminal.

[0011] Optionally, the memory circuit comprises a memory cell array, and the memory cells in the memory cell group are located in a row or a column of the memory cell array.

[0012] Optionally, in the memory cell array, the first driving terminals of the first transistors in the memory cells in the same row are connected in common to the same first control terminal, and the second terminals of the first transistors in the memory cells in the same column are connected in common to the same second control terminal; or, the first driving terminals of the first transistors in the memory cells in the same column are connected in common to the same first control terminal, and the second terminals of the first transistors in the memory cells in the same row are connected in common to the same second control terminal. Optionally, the third terminals of the second transistors in the memory cells in the same column are connected in common to the same input terminal of the plurality of input terminals, and the third terminals of the second transistors in the memory cells in different columns are connected to different input terminals of the plurality of input terminals; the fourth terminals of the second transistors in the memory cells in the same row are connected in common to the same output terminal.

[0013] Optionally, in the memory cell array, the first driving terminals of the first transistors in the memory cells in the same row are connected in common to the same first control terminal, and the second terminals of the first transistors in the memory cells in the same column are connected in common to the same second control terminal; or, the first driving terminals of the first transistors in the memory cells in the same column are connected in common to the same first control terminal, and the second terminals of the first transistors in the memory cells in the same row are connected in common to the same second control terminal. Optionally, the third terminals of the second transistors in the memory cells in the same row are connected in common to the same input terminal of the plurality of input terminals, and the third terminals of the second transistors in the memory cells in different rows are connected to different input terminals of the plurality of input terminals; the fourth terminals of the second transistors in the memory cells in the same column are connected in common to the same output terminal.

[0014] Optionally, the memory circuit comprises a plurality of memory cell groups, and the plurality of memory cell groups comprises a first memory cell group and a second memory cell group, the first memory cell group comprises a first memory cell, and the second memory cell group comprises a second memory cell. The third terminal of the second transistor in the first memory cell and the third terminal of the second transistor in the second memory cell are connected in common to the same input line connected to one of the plurality of input terminals.

[0015] Optionally, the plurality of storage cell groups further comprises a third storage cell group and a fourth storage cell group, the third storage cell group comprises a third storage cell, and the fourth storage cell group comprises a fourth storage cell; the third terminal of the second transistor in the third storage cell and the third terminal of the second transistor in the fourth storage cell are connected in common to the same input line.

[0016] Optionally, the first storage cell group comprises a first column of storage cells, and the second storage cell group comprises a second column of storage cells, the first column of storage cells and the second column of storage cells being adjacent; or the first storage cell group comprises a first row of storage cells, and the second storage cell group comprises a second row of storage cells, the first row of storage cells and the second row of storage cells being adjacent.

[0017] Optionally, the storage cell group comprises a first storage cell sub-group and a second storage cell sub-group, the first storage cell sub-group comprises a first storage cell, and the second storage cell sub-group comprises a second storage cell; the third terminal of the second transistor in the first storage cell and the third terminal of the second transistor in the second storage cell are connected to different input terminals of the plurality of input terminals, and the fourth terminal of the second transistor in the first storage cell and the fourth terminal of the second transistor in the second storage cell are connected in common to the same output terminal.

[0018] Optionally, the first driving terminal of the first transistor in the first storage cell and the first driving terminal of the first transistor in the second storage cell are connected to the same first control terminal, and the second terminal of the first transistor in the first storage cell and the second terminal of the first transistor in the second storage cell are connected to different second control terminals.

[0019] Optionally, the first driving terminal of the first transistor in the first storage cell and the first driving terminal of the first transistor in the second storage cell are connected to different first control terminals, and the second terminal of the first transistor in the first storage cell and the second terminal of the first transistor in the second storage cell are connected to the same second control terminal.

[0020] Optionally, the first storage cell sub-group comprises a first column of storage cells, and the second storage cell sub-group comprises a second column of storage cells; or the first storage cell sub-group comprises a first row of storage cells, and the second storage cell sub-group comprises a second row of storage cells.

[0021] Optionally, the first column of storage cells and the second column of storage cells are adjacent; or the first row of storage cells and the second row of storage cells are adjacent.

[0022] Optionally, the first driving terminal of the first transistor comprises a gate; the first terminal of the first transistor comprises a source, and the second terminal of the first transistor comprises a drain; or the first terminal of the first transistor comprises a drain, and the second terminal of the first transistor comprises a source.

[0023] Optionally, the second driving terminal of the second transistor comprises a gate; the third terminal of the second transistor comprises a source, and the fourth terminal of the second transistor comprises a drain; or the third terminal of the second transistor comprises a drain, and the fourth terminal of the second transistor comprises a source.

[0024] Optionally, the second transistor comprises a second oxide semiconductor structure, and a channel controlled by the second driving terminal is formed in the second oxide semiconductor structure between the third terminal and the fourth terminal.

[0025] In a second aspect, a memory and computing device is provided, comprising the memory circuit and the control circuit of any one of the first aspect; the control circuit is configured to control the working state of the memory circuit.

[0026] In a third aspect, an electronic device is provided, comprising any one of the memory and computing device of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0027] The embodiments shown in the drawings are for illustrative purposes only and do not limit the scope of the claims. In the drawings, the same reference signs refer to similar but not necessarily identical elements.

[0028] FIG. 1 shows a schematic diagram of a memory and computing device according to an exemplary embodiment of the present disclosure;

[0029] FIG. 2 shows a schematic diagram of a memory and computing device according to an exemplary embodiment of the present disclosure;

[0030] FIG. 3 shows a schematic diagram of a memory circuit according to an exemplary embodiment of the present disclosure;

[0031] FIG. 4 shows a schematic diagram of another memory circuit according to an exemplary embodiment of the present disclosure;

[0032] FIG. 5 shows a schematic diagram of yet another memory circuit according to an exemplary embodiment of the present disclosure;

[0033] FIG. 6 shows a schematic diagram of yet another memory circuit according to an exemplary embodiment of the present disclosure;

[0034] FIG. 7 shows a schematic diagram of yet another memory circuit according to an exemplary embodiment of the present disclosure;

[0035] FIG. 8 shows a schematic diagram of yet another memory circuit according to an exemplary embodiment of the present disclosure;

[0036] FIG. 9 shows a schematic diagram of yet another memory circuit according to an exemplary embodiment of the present disclosure;

[0037] FIG. 10 shows a schematic diagram of an electronic device according to an exemplary embodiment of the present disclosure;

[0038] FIG. 11 illustrates a schematic diagram of a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0039] FIGS. 12A-12F illustrate schematic diagrams of memory cells, according to example embodiments of the present disclosure;

[0040] FIGS. 13A-13D illustrate schematic diagrams of memory arrays in a compute-in-memory circuit, according to example embodiments of the present disclosure;

[0041] FIG. 14 illustrates a schematic diagram of a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0042] FIG. 15 illustrates a schematic diagram of a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0043] FIG. 16 illustrates a schematic diagram of a converter in a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0044] FIG. 17 illustrates a schematic diagram of a process for forward computation by a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0045] FIG. 18 illustrates a schematic diagram of a process for backward computation by a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0046] FIG. 19 illustrates a flowchart of a method for controlling a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0047] FIG. 20 illustrates a schematic diagram of a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0048] FIG. 21 illustrates a circuit schematic for controlling a write, according to an example embodiment of the present disclosure;

[0049] FIG. 22 illustrates a schematic diagram of a write control circuit, according to an example embodiment of the present disclosure;

[0050] FIG. 23 illustrates a circuit schematic for controlling a write, according to an example embodiment of the present disclosure;

[0051] FIG. 24 illustrates a schematic diagram of a write control circuit, according to an example embodiment of the present disclosure;

[0052] FIG. 25 illustrates a flowchart of a method for controlling a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0053] FIG. 26 illustrates a schematic diagram of a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0054] FIG. 27 illustrates a schematic diagram of a compute-in-memory circuit, according to an example embodiment of the present disclosure;

[0055] FIG. 28 illustrates a circuit schematic for controlling a write, according to an example embodiment of the present disclosure;

[0056] FIG. 29 shows a schematic diagram of a write control circuit according to an example embodiment of the present disclosure;

[0057] FIG. 30 shows a flowchart of a method for controlling a memory and compute circuit according to an example embodiment of the present disclosure;

[0058] FIG. 31 shows a schematic diagram of a memory and compute circuit according to an example embodiment of the present disclosure;

[0059] FIG. 32 shows a schematic diagram of a write control circuit according to an example embodiment of the present disclosure;

[0060] FIG. 33 shows a schematic diagram of a write control circuit according to an example embodiment of the present disclosure;

[0061] FIG. 34 shows a flowchart of a method for controlling a memory and compute circuit according to an example embodiment of the present disclosure;

[0062] FIG. 35 shows a schematic diagram of a memory and compute circuit according to an example embodiment of the present disclosure;

[0063] FIGS. 36A-36B show a schematic diagram of a memory and compute circuit according to an example embodiment of the present disclosure;

[0064] FIGS. 37A-37B show a schematic diagram of a memory and compute circuit according to an example embodiment of the present disclosure;

[0065] FIGS. 38A-38B show a schematic diagram of a memory and compute circuit according to an example embodiment of the present disclosure;

[0066] FIG. 39 shows a flowchart of a method for controlling a memory and compute circuit according to an example embodiment of the present disclosure;

[0067] FIG. 40 shows a schematic diagram of a chip according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] For the purpose of making the drawings simple, only the parts related to the corresponding embodiments are shown in the drawings in the embodiments of the present disclosure, which do not represent the actual structure of the products. In addition, in order to make the drawings simple and easy to understand, only some structures or components are shown in some drawings, and there can be more or less the same or similar structures or components.

[0069] In the present disclosure, unless specifically stated and limited otherwise, ordinal terms such as "first", "second", etc. are used merely to distinguish descriptions of objects, and cannot be understood as indicating or implying relative importance or sequence between the described objects. In addition, ordinal terms also do not represent the number of the described objects. "Plural" includes two or more, and other quantifiers are similar. "Or", "and / or" are used to describe the relationship between objects, which means non-exclusive inclusion. For example, "A and / or B", "A or B" can include: "A alone", "B alone", or "A and B". For another example, "A, B and / or C", "A, B or C" can include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C". In addition, " / " in the present disclosure is used to represent the relationship between the front and rear objects "or". In the present disclosure, "one or more of A and B" or "at least one of A and B" has the same meaning as "A and / or B", "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C", "A, B or C" above.

[0070] In the present disclosure, unless specifically stated and limited otherwise, "connection" includes direct connection or indirect connection between objects: the connection between objects can be directly connected through a medium (such as a wire, a trace, etc.), or can be indirectly connected through other elements, or can be internal communication. "Coupling" includes signal connection between objects, which can be directly connected through a medium (such as a wire, a trace, etc.), or can be connected through other elements, etc. "Grounding" includes direct grounding or indirect grounding, and indirect grounding includes grounding through other elements, for example. In the storage-computing integrated technology, the storage-computing device can realize in-memory computing (or operation) by taking the memory as the carrier. The memory can include: non-volatile memory (NVM) or volatile memory (VM). The volatile memory may, for example, include but not limited to: static random access memory (SRAM); the non-volatile memory may, for example, include but not limited to: flash, resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or phase change memory (PCM), etc.

[0071] For ease of understanding, FIG. 1 shows a schematic diagram of a storage-computing device according to an exemplary embodiment of the present disclosure.

[0072] As shown in FIG. 1, the storage and computing device 100 can include a storage circuit 110 and a control circuit 120. The storage circuit 110 can be configured to store weight data (may also be referred to as weights); the control circuit 120 can be configured to control the working state of the storage circuit 110. The working state of the storage circuit 110 includes, for example, a programming state and a computing state. In the programming state, the weight data is written into the storage circuit. In the computing state, the storage circuit 110 receives an input signal Sin, and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store a plurality of weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store the weight data in units of storage cells, which can also be referred to as storage units or storage structures. For example, the storage circuit 110 can include a storage cell array including a plurality of storage cells arranged in an array.

[0073] The storage cell can utilize the on-state capability of a semiconductor device, such as conductance or transconductance, to store weight data. For example, the storage cell can include a resistive storage device or a transistor storage device. For example, the storage of weight data can be achieved by controlling the conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device.

[0074] The storage circuit 110 can perform computation in groups. For example, the storage cell array can include at least one storage cell group including a plurality of storage cells, which can store a plurality of weight data, which can be equivalent to a first data vector (or a first data matrix). In the programming state, the weight data is written into the storage cell, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In the computing state, the storage circuit 110 receives an input signal, and the on-state capability of the storage cell can change the input signal to obtain an output signal. The cumulative output of the output signal in the storage cell group can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array or a two-dimensional array, and the storage cell group can include a plurality of storage cells in the same row or the same column in the storage cell array, or a plurality of storage cells in multiple rows or multiple columns, and the like, which can output their output signals in a collinear manner.

[0075] According to some embodiments, the storage and computing device 100 can further comprise an input circuit 130 and an output circuit 140. The input circuit 130 can convert the input data D1 into at least one input signal Sin provided to the storage circuit 110; the storage circuit 110 can convert the received input signal Sin into an output signal Sout based on the weight data; and the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of the first data vector (or the first data matrix) and the second data vector (or the second data matrix).

[0076] As an example, FIG. 2 shows a schematic diagram of a storage and computing device according to an example embodiment of the present disclosure.

[0077] As shown in FIG. 2, the storage and computing device 200 comprises a storage cell array 210, which comprises a plurality of storage cells S ij , where i ∈ [1, m], j ∈ [1, n], m is the number of rows of the storage cell array, and n is the number of columns of the storage cell array. The storage cell S ij may store weight data W ij . The control circuit 220 is configured to control the working state of the storage cell array 210, for example, including a programming state and a computing state. When the storage cell array 210 is in the programming state, the on-state capability of the storage cell S ij may be controlled based on the weight data to achieve a target state, thereby achieving storage of the weight data. When the storage cell array 210 is in the computing state, an input signal, for example, an input voltage V ij may be provided to the storage cell S i through the input end IN of the storage cell S ij , and the storage cell S 1j outputs its output signal, for example, an output current, through the output end OUT. The output ends of a plurality of storage cells (for example, S mj -S j ) can be output in parallel, and according to Kirchhoff's law, the output signals of the plurality of storage cells are accumulated, and the obtained output signal I 2k satisfies the following formula:

[0078] According to some embodiments, the input data can include digital input signals, and the input signals Vi of the memory cell array 210 can include analog signals. The input circuit 230 may, for example, include a digital to analog converter (DAC) to convert the digital signals to analog signals to provide to the memory cell array 210. According to some embodiments, the input signals of the memory cell array 210 can include digital signals, which can be represented by waveform characteristics of the signals, such as pulse width, amplitude, or area, etc. of the signals. The input circuit 230 can adjust the waveforms of the signals based on the input data to obtain the input signals to provide to the memory cell array.

[0079] According to some embodiments, the output circuit 240 can include an analog to digital converter (ADC) to convert the output signals of the memory cell array 210 to digital signals to provide to a subsequent circuit. In some embodiments of the present disclosure, the input signals can include voltage signals, and the output signals can include current signals. The computing and storage device 200 can further include a conversion circuit 250 to convert the current signals to voltage signals to provide to the output circuit 240 for analog to digital conversion. Illustratively, the conversion circuit 250 may, for example, include a transimpedance amplifier (TIA).

[0080] The accurate and stable storage of the weight data by the storage circuit is related to the reliability of the calculation result of the storage and calculation circuit. The storage circuit provided in the embodiments of the present disclosure can not only be used for calculation, so as to realize the processing of data by the storage circuit, reduce the bus overhead and power consumption overhead of data transmission, but also can improve the accuracy and stability of the storage of the weight data by the storage circuit, thereby improving the reliability of the storage and calculation integrated architecture. For example, the storage circuit includes a storage unit group, and the storage unit group includes a plurality of storage units. The storage unit includes a first transistor, a second transistor and a capacitor. The first terminal of the first transistor, the driving terminal of the second transistor and the capacitor are connected, and the storage of the weight data is realized by using the charge (for example, voltage) at the driving terminal of the second transistor. The driving terminal of the second transistor or any voltage node connected thereto can be understood as the storage node (SN) of the storage unit. The first transistor with an oxide semiconductor structure has smaller leakage current, and the capacitor can make the charge at the storage node remain for a longer time, so that the weight data stored by the storage unit has longer stability. One non-driving terminal of the plurality of second transistors in the storage unit group is coupled to a plurality of input signals, and the other non-driving terminal is connected to the same output terminal, so that the output of the multiplication and accumulation result in the storage unit group can be realized, the calculation in the storage circuit can be realized, the overhead of data transmission is reduced, and the efficiency of data processing is improved. The storage circuit provided in the embodiments of the present disclosure can realize more stable storage of weight data in the storage circuit, improve the reliability of data processing, and can reduce the overhead and time delay of data transmission, so that the data processing is more efficient.

[0081] In some embodiments of the present disclosure, the band gap of the oxide semiconductor structure is greater than or equal to 1.65eV. For example, the oxide semiconductor structure includes an indium gallium zinc oxide (IGZO) structure, a germanium (Ge) doped indium germanium oxide (InGeO) structure, or an indium tin oxide (ITO) structure, etc. The selection of the oxide semiconductor structure can make the leakage performance of the first transistor better, can reduce the leakage at the storage node, so that the weight data stored by the storage unit has longer stability, so that the storage circuit has higher reliability when calculating.

[0082] The following will be described with reference to the accompanying drawings.

[0083] FIG. 3 illustrates a schematic diagram of a storage circuit according to an example embodiment of the present disclosure. As shown in FIG. 3, the storage circuit 300 includes a storage cell group 310, which includes a plurality of storage cells 311-31N, where N is a positive integer greater than 1. The storage cell 31k includes a first transistor T1, a second transistor T2, and a capacitor C; where k e [1, N]. For ease of description, the non-driving terminals of the first transistor T1 are described as a first terminal and a second terminal, and the non-driving terminals of the second transistor T2 are described as a third terminal and a fourth terminal; the driving terminals of the first transistor T1 are described as a first driving terminal, and the driving terminals of the second transistor T2 are described as a second driving terminal. Then the first transistor T1 includes the first terminal, the second terminal, and the first driving terminal; the second transistor T2 includes the third terminal, the fourth terminal, and the second driving terminal. The first terminal of the first transistor T1, the second driving terminal of the second transistor T2, and the capacitor C are connected; for example, the first terminal of the first transistor T1, the second driving terminal of the second transistor T2, and one end of the capacitor C are connected, and the other end of the capacitor C is coupled to a voltage signal V0. The voltage signal V0 can include a positive voltage signal, a negative voltage signal, or a ground signal. For example, the other end of the capacitor C can be grounded. According to some embodiments, the capacitors within the storage cell group 310 can be coupled to the same voltage signal in a common line, for example, connected to the same ground terminal in a common line.

[0084] Please continue to refer to FIG. 3. According to some embodiments, in the storage cell 31k within the storage cell group 310, the first driving terminal of the first transistor T1 is connected to a first control terminal C1, and the second terminal of the first transistor T1 is connected to a second control terminal C2. 2k The first control terminal C1 and the second control terminal C 2k may be used to control the weight data W 1,k of the storage cell 31k. For example, a first control signal can be applied on the first driving terminal of the first transistor T1 through the first control terminal C1, which is used to control the conduction of the first transistor T1; a second control signal, which can also be referred to as a programming signal, can be applied on the second terminal of the first transistor T1 through the second control terminal C 2k , which is used to control the charge at the storage node of the storage cell 31k, i.e., to control the weight data stored by the storage cell 31k. The first control signal and the second control signal input through the above first control terminal and the second control terminal can realize the programming of the storage cell, write the target weight data of the storage cell, and obtain a storage cell group with a target vector. According to some embodiments, the first control signal can include a voltage signal, and the second control signal can include a voltage signal or a current signal.

[0085] Please continue to refer to FIG. 3, according to some embodiments, the third terminal of the second transistor T2 in the storage unit 311-31N in the storage unit group 310 is connected to the plurality of input terminals IN1-IN N respectively, and the fourth terminal is connected to the output terminal OUT. The writing of the weight data can make the second transistor T2 have a voltage corresponding to the target weight data at the second driving terminal, so that the channel between the third terminal and the fourth terminal has a corresponding conduction capability. The second transistor T2 outputs an output signal adjusted by the conduction capability of the channel in response to the input signal received by the third terminal. The fourth terminals of the second transistors T2 in the storage units 311-31N are connected together, and the output signals commonly output through the same output terminal equivalently implement the multiplication operation between vectors (or matrices).

[0086] According to some embodiments, the voltage at the storage node controlled by the first driving terminal and the second terminal of the first transistor T1 can realize different charge amounts (Q=C*V, where Q is the charge amount of the capacitive storage, C is the capacitance value of the capacitor, and V is the voltage at the storage node) of the capacitive storage, forming the channel conduction capability of the second transistor T2 in the storage unit group corresponding to the weight data; thereby realizing the programming of the weight data stored by the storage unit. The voltages at the storage nodes of different storage units can be the same, different, or partially different, thereby forming a voltage combination configuration of the storage nodes in the storage unit group.

[0087] Although the storage units 311-31N in the storage unit group 310 in FIG. 3 are located in the same row, the distribution of the storage units in the storage unit group 310 is not limited thereto, for example, the plurality of storage units in the storage unit group 310 can be located in the same column, or can be located in the storage unit array of multiple rows and / or columns. For another example, the plurality of storage units in the storage unit group 310 can adopt a three-dimensional array arrangement or a non-array arrangement.

[0088] According to some embodiments, the first control terminal and the second control terminal can select the storage unit 31k in the storage unit group 310, and write the weight data to the storage unit 31k. One control terminal can be used to select the storage unit group 310, and the other control terminal can be independently controlled to select the storage unit 31k in the storage unit group 310. For example, as shown in FIG. 3, the first driving terminal of the first transistor T1 in the storage units 311-31N in the storage unit group 310 is connected to the same first control terminal C1, and the second terminal is connected to different second control terminals C 21 -C 2N. When writing the weight data of the memory cells 311-31N in the memory cell group 310, a first control signal is input at the first control end C1, the memory cells 311-311N in the memory cell group 310 are enabled, and a second control signal is input at the second control end C2 to control the charge at the storage node in the memory cell 31k, so as to realize the writing of the weight data of the memory cell 31k. In this way, the wiring of the storage circuit can be simplified, the complexity of the storage circuit can be reduced, and the area or volume of the storage circuit can be reduced. 2k . When writing the weight data of the memory cells 311-31N in the memory cell group 310, a first control signal is input at the first control end C1, the memory cells 311-311N in the memory cell group 310 are enabled, and a second control signal is input at the second control end C2 to control the charge at the storage node in the memory cell 31k, so as to realize the writing of the weight data of the memory cell 31k. In this way, the wiring of the storage circuit can be simplified, the complexity of the storage circuit can be reduced, and the area or volume of the storage circuit can be reduced.

[0089] For another example, FIG. 4 shows a schematic diagram of another storage circuit according to an example embodiment of the present disclosure. As shown in FIG. 4, the storage circuit 400 includes a memory cell group 410, the first driving terminal of the first transistor T1 in the memory cells 411-41N in the memory cell group 410 is connected to different first control ends C 11 -C 1N , and the second terminal is connected to the same second control end C2. When writing the weight data of the memory cells 411-41N in the memory cell group 410, a first control signal is input at the first control end C 1k to enable or enable the memory cell 41k, and a second control signal is input at the second control end C2 to control the charge at the storage node in the memory cell 41k, so as to realize the writing of the weight data of the memory cell 41k. In this way, the wiring of the storage circuit can be simplified, the complexity of the storage circuit can be reduced, and the area or volume of the storage circuit can be reduced.

[0090] The above writing process of the weight data of the memory cells can be understood as the programming process of the storage circuit, and the above process of converting the input signal into the output signal for output can be understood as the calculation process of the storage circuit. The working state of the storage circuit can include a programming state or a calculation state. The present disclosure does not limit the writing order of the weight data of the memory cells in the memory cell group in the programming process. The present disclosure also does not limit the relationship between the plurality of input signals, for example, the plurality of input signals can all be different, all be the same, or part of them be the same, etc.

[0091] Any one of the storage circuits provided in the above examples can write the weights of a model for processing data in the form of the weight data of the memory cells in the storage circuit when processing data. The input data is converted into a plurality of input signals and input into the storage circuit, and the storage circuit can convert the plurality of input signals into output signals using the written weight data, so as to realize the processing of the data by the model using the hardware circuit, and improve the efficiency and accuracy of data processing.

[0092] For example, it is assumed that the weight data of the memory cell 31k / 41k in the memory cell group 310 / 410 is W 1,k , and the input signal is SINk , the output signal of the storage unit 31k / 41k can be represented as S OUTk , the output signal of the storage unit 31k / 41k can be represented as S OUTk = S INk W 1,K According to Kirchhoff's law, the output signal of the storage unit group 310 / 410 can be represented as According to some embodiments, the input signal can comprise a voltage signal or a current signal, and the output signal can comprise a current signal.

[0093] According to some embodiments, the storage units in the storage circuit can be arranged in an array, for example, the storage circuit comprises a storage unit array, and the storage unit array can comprise one or more storage unit groups. For example, the storage unit groups shown in FIG. 3 or FIG. 4 can be extended in any direction, such as up, down, left, right, etc., to obtain a storage unit array comprising more storage unit groups.

[0094] The operation between vectors (or matrices), such as the multiplication operation between vectors (or matrices), can be implemented by the storage array. For example, the input signal received by the storage unit group corresponds to a first vector in a vector operation, the weight data stored by the storage unit group corresponds to a second vector in the vector operation, and the output signal of the storage unit group corresponds to the result of the multiplication operation of the first vector and the second vector. The output signals of the plurality of storage unit groups in the storage unit array correspond to the result of the multiplication operation between a vector and a matrix, or the result of the multiplication operation between two matrices.

[0095] For example, assume that the weight data stored by the storage unit located at the i-th row and the j-th column is W i,j , the input signal is S INi,j , and the output signal is SOUTi，j , where 1≤i≤M and 1≤j≤N, where M represents the number of rows of the storage unit array, and N represents the number of columns of the storage unit array. The output signal of the storage unit located at the i-th row and the j-th column can be represented as S OUTi,j = S INi,j W i,j . Assume that the storage units in the same row are connected to the same output terminal. According to Kirchhoff's law, for the storage units in the i-th row, the output signal current S OUTi of the i-th row output terminal can be represented as The weight data matrix of the storage unit array is Assume that the storage unit array inputs the same input signal for the same column, and the input signals for multiple columns can be represented as a vector Then the output signals of multiple rows of the storage unit array can be represented as a vector

[0096] Several storage unit arrays are described below in conjunction with the accompanying drawings.

[0097] Figure 5 shows a schematic diagram of yet another storage circuit according to an example embodiment of the present disclosure. As shown in Figure 5, according to some embodiments, the storage circuit 500 comprises a storage cell array, the storage cells in a group of storage cells 510 are located in a row in the storage cell array. In the storage cell array: the first driving terminals of the first transistors T1 in the storage cells located in the same row are connected in common to the same first control terminal; the second terminals of the first transistors T1 in the storage cells located in the same column are connected in common to the same second control terminal; the third terminals of the second transistors T2 in the storage cells located in the same column are connected in common to the same input terminal in the plurality of input terminals, and the third terminals of the second transistors T2 in the storage cells located in different columns are connected to different input terminals in the plurality of input terminals; the fourth terminals of the second transistors T2 in the storage cells located in the same row are connected in common to the same output terminal. Taking an example where the storage cell array comprises M rows and N columns, the first driving terminals of the first transistors T1 in the storage cells in the i-th row are connected in common to the first control terminal C 1i , where i ∈ [1, M]. The second terminals of the first transistors T1 in the storage cells in the j-th column are connected in common to the same second control terminal C 2j , where j ∈ [1, N]. The third terminals of the second transistors T2 in the storage cells in the j-th column are connected in common to the input terminal IN j ; the fourth terminals of the second transistors T2 in the storage cells in the i-th row are connected in common to the output terminal OUT i .

[0098] Figure 6 shows a schematic diagram of yet another storage circuit according to an example embodiment of the present disclosure. As shown in Figure 6, according to some embodiments, the storage circuit 600 comprises a storage cell array, the storage cells in a group of storage cells 610 are located in a column in the storage cell array. It differs from the embodiment shown in Figure 5 in that: the third terminals of the second transistors T2 in the storage cells located in the same row are connected in common to the same input terminal in the plurality of input terminals, and the third terminals of the second transistors T2 in the storage cells located in different rows are connected to different input terminals in the plurality of input terminals; the fourth terminals of the second transistors T2 in the storage cells located in the same column are connected in common to the same output terminal. For example, the third terminals of the second transistors T2 in the storage cells in the i-th row are connected in common to the input terminal IN i ; the fourth terminals of the second transistors T2 in the storage cells in the j-th column are connected in common to the output terminal OUT j .

[0099] In the above embodiments, the first driving terminals of the first transistors T1 in the memory cells in the same row are connected in common to the same first control terminal, and the second terminals of the first transistors T1 in the memory cells in the same column are connected in common to the same second control terminal. In some other embodiments, the first driving terminals of the first transistors T1 in the memory cells in the same column are connected in common to the same first control terminal, and the second terminals of the first transistors T1 in the memory cells in the same row are connected in common to the same second control terminal. For example, FIG. 7 shows a schematic diagram of yet another memory circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 7, according to some embodiments, the memory circuit 700 includes a memory cell array, and the memory cells in the memory cell group 710 are in a row in the memory cell array. The first driving terminals of the first transistors T1 in the memory cells in the jthcolumn are connected in common to the first control terminal C 1j , and the second terminals of the first transistors T1 in the memory cells in the ithrow are connected in common to the same second control terminal C 2i .

[0100] According to some embodiments, the wires for connecting the input terminals can be referred to as input lines, the wires for connecting the output terminals can be referred to as output lines, the wires for connecting the first control terminals can be referred to as first control lines, and the wires for connecting the second control terminals can be referred to as second control lines.

[0101] According to some embodiments, the third terminals of the second transistors T2 in the memory cells in the same column are connected to the same input line, and the fourth terminals of the second transistors T2 in the memory cells in the same row are connected to the same output line. Alternatively, the third terminals of the second transistors T2 in the memory cells in the same row are connected to the same input line, and the fourth terminals of the second transistors T2 in the memory cells in the same column are connected to the same output line.

[0102] According to some embodiments, the first driving terminals of the first transistors T1 in the memory cells in the same row are connected to the same first control line, and the second terminals of the first transistors T1 in the memory cells in the same column are connected to the same second control line. Alternatively, the first driving terminals of the first transistors T1 in the memory cells in the same column are connected to the same first control line, and the second terminals of the first transistors T1 in the memory cells in the same row are connected to the same second control line.

[0103] By the above co-linear connection manner, the storage units in the storage circuit can multiplex the wires by rows or by columns, reducing the complexity of the wires in the storage circuit, which is conducive to simplifying the manufacturing process of the storage circuit. Moreover, the storage units multiplex the input lines and output lines in different directions such as rows and columns, which not only reduces the complexity of the wires in the storage circuit, but also facilitates the control of the input signals and output signals when the storage circuit is used for calculation in the compute-in-memory architecture, improves the control accuracy of the calculation, and improves the calculation efficiency. In addition, it can reduce the signal interference between the input lines and the output lines, such as the interference caused by parasitic capacitance, further improving the reliability of the storage circuit and the calculation performance of the storage circuit.

[0104] The present disclosure does not limit the directions of "rows" and "columns" in the array of storage units, which can have different directions based on different product space positions.

[0105] In the array of storage units, one or more storage units in the array of storage units can be opened by inputting control signals to the plurality of first control terminals and the plurality of second control terminals, to control the weight data of the opened storage units in the array of storage units. The present disclosure does not limit the writing order of the weight data of the storage units in the array of storage units, for example, one or more rows in the array of storage units can be selected by the first control terminals, and then one or more storage units in the row can be opened by the second control terminals, to program the opened storage units. For another example, one or more columns in the array of storage units can be selected by the first control terminals, and then one or more storage units in the column can be opened by the second control terminals, to program the opened storage units.

[0106] According to some embodiments, the storage circuit can include a plurality of storage unit groups, and the terminals for coupling the input signals between different storage unit groups can be further shared or co-linear. This makes the layout of the storage circuit more compact, further reduces the complexity, further reduces the size of the storage circuit, and further simplifies the manufacturing process of the storage circuit. For example, FIG. 8 shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 8, the plurality of storage unit groups includes a first storage unit group 810 and a second storage unit group 820, the first storage unit group 810 includes a first storage unit 811, and the second storage unit group includes a second storage unit 821. The third terminal of the second transistor T2 in the first storage unit 811 and the third terminal of the second transistor T2 in the second storage unit 821 are co-terminal or co-linearly connected to the same input line, which is connected to one of the input terminals IN1-IN M For example, the input terminal IN1 is taken as an example, and the other input terminals are similar.

[0107] According to some embodiments, the third terminal of the second transistor T2 in the first storage unit 811 and the third terminal of the second transistor T2 in the second storage unit 821 can be shared, further saving the size of the storage circuit, simplifying the manufacturing process of the storage circuit. Taking the third terminal as the source terminal as an example, the active regions of the second transistor T2 in the first storage unit 811 and the second transistor T2 in the second storage unit 821 are shared, so that the number of transistor active regions is reduced, further reducing the size of the storage circuit, and more dense storage units can be integrated in the same area, or more space can be provided for other circuits in the chip.

[0108] The above embodiments simplify the manufacturing process of the storage circuit, save costs, and due to the increase in storage unit density, the size of the storage circuit can be reduced. In addition, additional parasitic interference caused by vias or wires can be reduced, further improving the reliability of the storage circuit.

[0109] According to some embodiments, the common line can save the electrical connection structure, for example, the electrical connection structure of the common line can include a via between the third terminal of the transistor and the wire. The sharing of the via can save the size of the storage circuit, simplify the manufacturing process of the storage circuit.

[0110] According to some embodiments, the common line or common terminal of the storage unit group can be further connected to the same input terminal with other similar storage unit groups. For example, please continue to refer to FIG. 8, the plurality of storage unit groups can further include a third storage unit group 830 and a fourth storage unit group 840, the third storage unit group 830 includes a third storage unit 831, and the fourth storage unit group 840 includes a fourth storage unit 841. The third terminal of the second transistor T2 in the third storage unit 831 and the third terminal of the second transistor T2 in the fourth storage unit 841 are connected to the same input line in common line or common terminal.

[0111] According to some embodiments, similar to the above, the third terminal of the second transistor T2 in the third storage unit 831 and the third terminal of the second transistor T2 in the fourth storage unit 841 can be shared, further saving the size of the storage circuit, simplifying the manufacturing process of the storage circuit. According to some embodiments, the common line can save the electrical connection structure, for example, the electrical connection structure of the common line can include a via between the third terminal of the transistor and the wire. The sharing of the via can save the size of the storage circuit, simplify the manufacturing process of the storage circuit.

[0112] According to some embodiments, a storage unit group can include a column or a row of storage units in a storage unit array, and the storage units in adjacent columns or rows can be connected in common line or common terminal. For example, a first storage unit group includes a first column of storage units, and a second storage unit group includes a second column of storage units, and the first column of storage units and the second column of storage units are adjacent. Alternatively, a first storage unit group includes a first row of storage units, and a second storage unit group includes a second row of storage units, and the first row of storage units and the second row of storage units are adjacent. The storage units in adjacent rows or columns share an input line connected to an input terminal, which can reduce the area occupied by the storage units and internal connections of the storage unit array, reduce the size of the storage circuit, and simplify the manufacturing process of the storage circuit.

[0113] Other connection relationships of the storage units in the storage unit groups can refer to the above embodiments. For example, the fourth terminal of the second transistor T2 in the storage unit in the first storage unit group 810 is connected in common line to the output terminal OUT1; the fourth terminal of the second transistor T2 in the storage unit in the second storage unit group 820 is connected in common line to the output terminal OUT2. The fourth terminal of the second transistor T2 in the storage unit in the third storage unit group 830 is connected in common line to the output terminal OUT3; the fourth terminal of the second transistor T2 in the storage unit in the fourth storage unit group 840 is connected in common line to the output terminal OUT4. For another example, the first driving terminal of the first transistor T1 in the storage unit in the i-th row is connected in common line to the first control terminal C 1i , and the second terminal of the first transistor T1 in the storage unit in the j-th column is connected in common line to the second control terminal C 2j . The connection relationship is only an example, and any connection mode in the above embodiments can be used.

[0114] According to some embodiments, the storage units in a storage unit group can be further grouped to realize a ping-pong structure to perform group-in-group calculation to reduce the calculation difference between two storage unit subgroups and improve the calculation accuracy. Alternatively, the storage units in different subgroups can be coupled to independent input signals, and the calculation results of the storage units in different subgroups can be combined, so that the number of storage units in the output line direction can be reduced, and thus the RC delay of the signals in this direction can be effectively reduced, and the calculation speed can be improved.

[0115] For example, FIG. 9 shows a schematic diagram of yet another storage circuit according to an example embodiment of the present disclosure. As shown in FIG. 9, the storage unit group 910 includes a first storage unit subgroup 911 including a first storage unit 9111 and a second storage unit subgroup 912 including a second storage unit 9121. The fourth terminal of the second transistor T2 in the first storage unit 9111 and the fourth terminal of the second transistor T2 in the second storage unit 9121 are connected to the same output terminal in a common line or a common terminal. In this way, not only the technical effects of the embodiment shown in FIG. 8, such as reducing the size of the storage circuit and reducing the process complexity, are achieved, but also a ping-pong structure can be formed to perform grouped calculation within the group (for example, first calculate the odd-numbered subgroup and then calculate the even-numbered subgroup) to reduce the calculation difference between the two storage unit subgroups and improve the calculation accuracy.

[0116] Alternatively, the storage units of different subgroups can be connected to different input terminals to couple independent input signals, and the storage units of different subgroups can combine the calculation results. In this way, the number of storage units in the output line direction can be reduced, and thus the RC delay of the signals in this direction can be effectively reduced and the calculation speed can be improved. For example, please continue to refer to FIG. 9, the first storage unit 9111 and the second storage unit 9121 in the ith row can be connected to different input terminals IN i1 and IN i2 .

[0117] For example, the storage unit subgroups are divided by column, and the odd and even columns receive independent input signals. Two adjacent storage units in each column can be combined to perform multiplication and addition calculation. The number of storage units in the column is about 1 / 2 of the single column in the non-subgroup scheme under the same number of storage units. In this way, the RC delay of the signals in the column can be effectively reduced and the calculation speed can be improved. The row division is similar.

[0118] According to some embodiments, the first driving terminal of the first transistor T1 in the first storage unit 9111 and the first driving terminal of the first transistor T1 in the second storage unit 9121 are connected to the same first control terminal C 11 , and the second terminal of the first transistor T1 in the first storage unit 9111 and the second terminal of the first transistor T1 in the second storage unit 9112 are connected to different second control terminals. For example, please continue to refer to FIG. 9, the first driving terminals of the first transistors T1 in the storage units in the same row are connected in a common line to the same first control terminal, for example, the first driving terminals of the first transistors T1 in the storage units in the ith row are connected in a common line to the first control terminal C 1i . The second terminals of the first transistors T1 in the storage units in the same column are connected to the same second control terminal, for example, the second terminals of the first transistors T1 in the storage units in the jth column are connected to the same second control terminal C 2j .

[0119] According to some embodiments, the first driving terminal of the first transistor in the first storage unit and the first driving terminal of the first transistor in the second storage unit are connected to different first control terminals, and the second terminal of the first transistor in the first storage unit and the second terminal of the first transistor in the second storage unit are connected to the same second control terminal.

[0120] According to some embodiments, the first storage unit sub-group comprises a first column of storage units, and the second storage unit sub-group comprises a second column of storage units; or, the first storage unit sub-group comprises a first row of storage units, and the second storage unit sub-group comprises a second row of storage units. In this way, simple storage unit sub-group division can be realized in rows or in columns, the wiring within the storage unit array is simplified, and the size and process complexity of the storage circuit are reduced.

[0121] According to some embodiments, the first column of storage units and the second column of storage units are adjacent; or, the first row of storage units and the second row of storage units are adjacent. In this way, the adjacent storage units realize a common terminal or common line structure, the process is simple, the wiring design of the storage circuit can be further simplified, the area occupied by the storage circuit is reduced, and the size of the storage circuit is reduced; at the same time, the storage circuit has the ability to optimize the calculation speed.

[0122] The present disclosure does not limit the type of transistor, for example, can include a bipolar junction transistor (BJT), or a field-effect transistor (FET), etc. The transistor is, for example, a semiconductor device including a non-driving terminal and a driving terminal, and the signal of the driving terminal, for example, current / voltage, can control the on-state capability between the non-driving terminals, thereby changing the current flowing between the non-driving terminals. According to some embodiments, the first driving terminal of the first transistor includes a gate; the first terminal of the first transistor includes a source, and the second terminal of the first transistor includes a drain; or, the first terminal of the first transistor includes a drain, and the second terminal of the first transistor includes a source. Alternatively, the first driving terminal of the first transistor includes a base; the first terminal of the first transistor can include a collector, and the second terminal of the first transistor can include an emitter; or, the first terminal of the first transistor includes an emitter, and the second terminal of the first transistor includes a collector. Similarly, the second driving terminal of the second transistor includes a gate; the third terminal of the second transistor includes a source, and the fourth terminal of the second transistor includes a drain; or, the third terminal of the second transistor includes a drain, and the fourth terminal of the second transistor includes a source. Alternatively, the second driving terminal of the second transistor includes a base; the third terminal of the second transistor can include a collector, and the fourth terminal of the second transistor can include an emitter; or, the third terminal of the second transistor includes an emitter, and the fourth terminal of the second transistor includes a collector.

[0123] Some embodiments of the present disclosure can also provide a storage and calculation device (or processing device) including a storage circuit and a control circuit as any one of the above embodiments, and the control circuit is configured to control the working state of the storage circuit.

[0124] Some embodiments of the present disclosure can also provide an electronic device, for example, FIG. 10 shows a schematic diagram of an electronic device according to an exemplary embodiment of the present disclosure. The electronic device 1000 can include a storage and calculation device 1010 for processing data of the electronic device 1000. The electronic device 1000 can also include an input / output device 1020 for receiving user input or outputting processing results, and the present disclosure does not limit the input type and output type, for example, the input can include voice input, text input, image input, or video input, etc. The output can include text output, voice output, image output, or video output, etc. The electronic device 1000 can also include a processor 1030, which can process the data provided to the storage and calculation device 1010, or can process the output data of the storage and calculation device 1010. The output of the input / output device 1020 above can be based on the output of the processor 1030 or based on the output of the storage and calculation device 1010.

[0125] The present disclosure does not limit the type of electronic device. For example, according to some embodiments, the electronic device 1000 can include a wearable device. The wearable device includes, for example, but is not limited to, a head-mounted device (e.g., a helmet or a hat, etc.), a device wearable on an ear (e.g., an earphone), a device wearable on a wrist (e.g., a watch), a device wearable on other parts of a body (e.g., an electronic necklace, a medical monitoring device, or glasses, etc.), etc. According to some embodiments, the electronic device 1000 can include a portable terminal. For example, the electronic device 1000 can include, but is not limited to, a mobile phone, a general computing device (e.g., a laptop computer, or a tablet computer, etc.), a personal digital assistant, etc. According to some embodiments, the electronic device 1000 can include other types of terminal devices, such as a personal computer, an in-vehicle computer or in-vehicle computing platform, or a smart home electronic product, etc. According to some embodiments, the electronic device 1000 can also include a server or the like.

[0126] The present disclosure provides a memory and compute circuit, comprising: at least two memory arrays including a first memory array and a second memory array, wherein for each of the at least two memory arrays, each memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell comprises a first transistor and a second transistor, in each memory cell, a gate terminal of the first transistor is connected to one of a source terminal and a drain terminal of the second transistor, and each memory cell is configured to store a weight corresponding to the memory cell, and for each memory array, one of a drain terminal and a source terminal of the first transistor in the memory cells in a same row is connected to a row input-output terminal corresponding to the row, and the other of the drain terminal and the source terminal of the first transistor in the memory cells in a same column is connected to a column input-output terminal corresponding to the column; and at least one converter, each converter connected to two memory arrays of the at least two memory arrays, the at least one converter comprising a first converter connected to the row input-output terminals of the plurality of rows of the first memory array and the input-output terminals of the plurality of rows of the second memory array, and configured to, in response to the first memory array outputting to the second memory array, for any row of the first memory array, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the second memory array, and input the input signal of the corresponding row of the second memory array to the row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is a row of the second memory array corresponding to the any row of the first memory array.

[0127] According to embodiments as described in the disclosure, by using a memory array with different row input / output configurations, i.e., coupling a memory array with row outputs with a memory array with row inputs through a transducer, components separately used for performing matrix transposition are omitted, operation efficiency is improved, and thus circuit structure is further simplified.

[0128] In embodiments described in the disclosure, a row in a memory array is a set of memory cells in the memory array in a same vertical position in a horizontal direction, a column in the memory array is a set of memory cells in the memory array in a same horizontal position in a vertical direction, or a column in the memory array is a set of memory cells in the memory array in a same vertical position in a horizontal direction, and a row in the memory array is a set of memory cells in the memory array in a same horizontal position in a vertical direction.

[0129] FIG. 11 shows a schematic diagram of a memory-computing circuit 1100 according to an exemplary embodiment of the disclosure.

[0130] According to some embodiments, as shown in FIG. 11, the memory-computing circuit 1100 includes at least two memory arrays 1101-1102 and at least one transducer 1111, wherein each transducer is connected to two memory arrays to perform signal conversion (e.g., analog-digital conversion, digital-analog conversion) between the two memory arrays. It should be understood that although two memory arrays 1101-1102 and one transducer 1111 are shown in FIG. 11, FIG. 11 is merely schematic, and the memory-computing circuit 1100 can include more than two memory arrays and / or more than one transducer.

[0131] It should be understood that, in order to clearly show the circuit structure of the entire memory-computing circuit, the internal structure of each memory cell is not drawn in FIG. 11, and the internal structure of the memory cell will be described in detail below in conjunction with FIGS. 12A-12B and 13A-13D.

[0132] FIGS. 12A-12F show a schematic diagram of a memory cell 1200 according to an exemplary embodiment of the disclosure. According to some embodiments, the structure of each of the memory cells 1101-1102 in the memory arrays 1101-1102 in FIG. 11 can be the same as or similar to the memory cell 1200 described with reference to FIGS. 12A-12B. 1,1 -1101 M,N 、1102 1,1 -1102 M,N FIGS. 12A-12F show a schematic diagram of a memory cell 1200 according to an exemplary embodiment of the disclosure. According to some embodiments, the structure of each of the memory cells 1101-1102 in the memory arrays 1101-1102 in FIG. 11 can be the same as or similar to the memory cell 1200 described with reference to FIGS. 12A-12B.

[0133] According to some embodiments, as shown in FIGS. 12A-12B, for each of the at least two memory arrays 1101-1102, each memory array includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a first transistor and a second transistor, in each memory cell, a gate terminal of the first transistor is connected to one of a source terminal and a drain terminal of the second transistor 1202a, and the memory cell is configured to store a weight corresponding to the memory cell.

[0134] According to some embodiments, as shown in FIG. 12A, in the memory cell 1200, there is a parasitic capacitance 1203 between the gate terminal 1201g of the first transistor 1201 and the ground, and the weight stored by the memory cell 1200 is determined based on the charge stored in the parasitic capacitance 1203 in the memory cell 1200. The first transistor 1201 includes terminals 1201a and 1201b.

[0135] According to some embodiments, as shown in FIG. 12B, the memory cell 1200 further includes a storage capacitance 1203, a first terminal of the storage capacitance 1203 is connected to the gate terminal 1201g of the first transistor 1201 of the memory cell 1200, and a second terminal of the storage capacitance 1203 is connected to the ground, wherein the weight stored by the memory cell 1200 is determined based on the charge stored in the storage capacitance 1203 in the memory cell 1200.

[0136] According to some embodiments, in the memory cell 1200 as shown in FIGS. 12A-12B, the charge stored in the storage capacitance 1203 or the parasitic capacitance 1203 in the memory cell 1200 can be controlled by applying a conductive signal (e.g., a conductive voltage) on the gate terminal 1202g of the second transistor 1202, and applying a write signal (e.g., a write voltage) on the other terminal 1202b of the source terminal and the drain terminal of the second transistor 1202, thereby controlling the weight value stored by the memory cell.

[0137] Similarities between the memory cell 1200 in FIGS. 12C-12F and the memory cell 1200 in FIGS. 12A-12B will not be repeated here, and the differences will be mainly described. The memory cell 1200 in FIGS. 12C-12F further includes a write control switch 1204.

[0138] According to some embodiments, in any of the memory arrays 1101-1102, one of the drain terminal and the source terminal of the first transistor in the memory cells in the same row is connected to a row input-output terminal corresponding to the row, and the other of the drain terminal and the source terminal of the first transistor in the memory cells in the same column is connected to a column input-output terminal corresponding to the column.

[0139] FIGS. 13A-13D show schematic diagrams of a memory array 1300 in a compute- in-memory circuit, according to exemplary embodiments of the disclosure.

[0140] According to some embodiments, as shown in FIGS. 13A-13B, the source terminal of the first transistor in the memory cells in the same row in the memory array 1300 is connected to a row input-output terminal corresponding to the row (e.g., as shown in FIG. 13A, the row input-output terminal as a row output terminal, or, as shown in FIG. 13B, the row input-output terminal as a row input terminal), and the drain terminal of the first transistor in the memory cells in the same column is connected to a column input-output terminal corresponding to the column (e.g., as shown in FIG. 13A, the column input-output terminal as a column input terminal, or, as shown in FIG. 13B, the column input-output terminal as a column output terminal).

[0141] According to some embodiments, the first memory array 1101 in the compute-in- memory circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13A, e.g., when the first memory array 1101 is outputting to the second memory array 1102. According to other embodiments, the first memory array 1101 in the compute-in-memory circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13B, e.g., when the second memory array 1102 is outputting to the memory array 1101.

[0142] According to some embodiments, the second memory array 1102 in the compute-in- memory circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13B, e.g., when the first memory array 1101 is outputting to the second memory array 1102. According to other embodiments, the second memory array 1102 in the compute-in-memory circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13A, e.g., when the second memory array 1102 is outputting to the memory array 1101.

[0143] It should be appreciated that the circuit structures of the memory array 1300 in FIG. 13A and FIG. 13B are the same, with the only difference being that in the memory array 1300 of FIG. 13A, the column input-output terminals are column input terminals and the row input-output terminals are row output terminals, while in the memory array 1300 of FIG. 13B, the column input-output terminals are column output terminals and the row input-output terminals are row input terminals.

[0144] According to some embodiments, as shown in FIGS. 13C-13D, the source terminal of the first transistor in the memory cells in the same column in the memory array 1300 is connected to a column input-output terminal corresponding to the column (e.g., as shown in FIG. 13C, the column input-output terminal as a column output terminal, or, as shown in FIG. 13D, the column input-output terminal as a column input terminal), and the drain terminal of the first transistor in the memory cells in the same row is connected to a row input-output terminal corresponding to the row (e.g., as shown in FIG. 13C, the row input-output terminal as a row input terminal, or, as shown in FIG. 13D, the row input-output terminal as a row output terminal).

[0145] According to some embodiments, the first memory array 1101 in the in-memory computing circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13C, e.g., when the first memory array 1101 outputs to the second memory array 1102. According to other embodiments, the first memory array 1101 in the in-memory computing circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13D, e.g., when the second memory array 1102 outputs to the memory array 1101.

[0146] According to some embodiments, the second memory array 1102 in the in-memory computing circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13D, e.g., when the first memory array 1101 outputs to the second memory array 1102. According to other embodiments, the second memory array 1102 in the in-memory computing circuit 1100 in FIG. 11 is the memory array 1300 as shown in FIG. 13C, e.g., when the second memory array 1102 outputs to the memory array 1101.

[0147] It should be appreciated that the circuit structures of the memory array 1300 in FIG. 13C and FIG. 13D are the same, with the only difference being that in the memory array 1300 of FIG. 13C, the column input-output terminals are column input terminals and the row input-output terminals are row output terminals, while in the memory array 1300 of FIG. 13D, the column input-output terminals are column output terminals and the row input-output terminals are row input terminals.

[0148] According to some embodiments, in each memory cell, the second transistor is connected to the first transistor to change the weight stored in the memory cell. According to some embodiments, as shown in FIGS. 13A-13D, the gate terminals of the second transistors in the memory cells in the same row in the memory array 1300 are connected, while the other one of the source terminal and the drain terminal of the second transistors in the memory cells in the same column in the memory array 1300 is connected (i.e., the terminal that is not connected to the gate terminal of the first transistor). According to other embodiments, the gate terminals of the second transistors in the memory cells in the same column in the memory array 1300 are connected, while the other one of the source terminal and the drain terminal of the second transistors in the memory cells in the same row in the memory array 1300 is connected (i.e., the terminal that is not connected to the gate terminal of the first transistor).

[0149] According to some embodiments, vector-matrix multiplication can be implemented by the memory array 1300, for example, in FIG. 13A or FIG. 13C, the input signals received by each column of the memory array 1300 correspond to each component of the input vector of the vector-matrix multiplication, the weights of each memory cell of the memory array 1300 correspond to each weight value of the matrix of the vector-matrix multiplication, and the output signals of each row of the memory array 1300 correspond to each component of the output vector of the vector-matrix multiplication, and for example, in FIG. 13B or FIG. 13D, the input signals received by each row of the memory array 1300 correspond to each component of the input vector of the vector-matrix multiplication, the weights of each memory cell of the memory array 1300 correspond to each weight value of the matrix of the vector-matrix multiplication, and the output signals of each column of the memory array 1300 correspond to each component of the output vector of the vector-matrix multiplication.

[0150] According to some embodiments, in FIG. 13A or FIG. 13C, for any row of memory cells in the memory array 1300, the output currents of the first transistors of the memory cells in the row are summed up due to the connection of the second terminals of the first transistors of the memory cells in the row, forming the output current of the row.

[0151] According to some embodiments, in FIG. 13B or FIG. 13D, for any column of memory cells in the memory array 1300, the output currents of the first transistors of the memory cells in the column are summed up due to the connection of the second terminals of the first transistors of the memory cells in the column, forming the output current of the column.

[0152] According to embodiments as described in the present disclosure, by using a memory array with different row input / output configurations, i.e., coupling a memory array with row outputs to a memory array with row inputs through a converter, the operation efficiency is improved and the circuit design is simplified without separately setting components for performing matrix transposition.

[0153] According to some embodiments, the first converter 1111 is connected to the row input-output terminals of a plurality of rows of the first memory array 1101 and to the input-output terminals of a plurality of rows of the second memory array 1102, and is configured to, in response to the first memory array 1101 outputting to the second memory array 1102, for any row of the first memory array 1101, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the second memory array 1102, and input the input signal of the corresponding row of the second memory array 1102 to the row input-output terminal of the corresponding row of the second memory array 1102, wherein the corresponding row of the second memory array 1102 is a row of the second memory array 1102 that corresponds to the row of the first memory array 1101.

[0154] According to some embodiments, the corresponding row of the second memory array 1102 is a row of the second memory array 1102 that has the same row number as the row of the first memory array 1101, e.g., the i-th row of the first memory array 1101 corresponds to the i-th row of the second memory array 1102.

[0155] According to some embodiments, as will be described in further detail below, the first converter 1111 comprises an analog-to-digital converter, a digital-to-analog converter, and a multiplexer, wherein the analog-to-digital converter receives an analog output signal from the first memory array 1101 and converts it to a digital intermediate signal, and the digital-to-analog converter converts the digital intermediate signal to an analog input signal provided to the second memory array 1102. According to some embodiments, the first converter 1111 can also comprise other components, e.g., a current-to-voltage converter that converts an output current of the first memory array to a voltage, and / or a voltage-to-current converter that converts an output voltage of the first memory array to a current.

[0156] According to some embodiments, the first converter 1111 is further configured to, in response to the second memory array 1102 outputting to the first memory array 1101, for any row of the second memory array 1102, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the first memory array 1101, and input the input signal of the corresponding row of the first memory array 1101 to the row input-output terminal of the corresponding row of the first memory array 1101, wherein the corresponding row of the first memory array 1101 is a row of the first memory array 1101 that corresponds to the row of the second memory array 1102.

[0157] According to some embodiments, whether the first memory array 1101 outputs to the second memory array 1102 is determined according to the operation mode of the memory-compute circuit 1100, for example, when the memory-compute circuit 1100 is in a forward operation mode, the first memory array 1101 outputs to the second memory array 1102, for example, the calculation result of the calculation performed by the first memory array 1101 as the input data of the second memory array 1102, for another example, when the memory-compute circuit 1100 is in a reverse operation mode, the second memory array 1102 outputs to the first memory array 1101, for example, the calculation result of the calculation performed by the second memory array 1102 as the input data of the first memory array 1101.

[0158] According to embodiments as described in the present disclosure, in the utilization of the memory-compute circuit 1100 in different modes of computation, for example, forward computation of the memory-compute circuit from the first memory array 1101 to the second memory array 1102, and reverse computation from the second memory array 1102 to the first memory array 1101, without changing the circuit structure of the first memory array 1101 and the second memory array 1102 for performing computation, only the control of the converter 1111 to change the signal flow direction is needed, thereby improving the utilization of the memory-compute circuit.

[0159] FIG. 14 shows a schematic diagram of a memory-compute circuit 1400 according to an exemplary embodiment of the present disclosure. According to some embodiments, the first memory array 1401, the second memory array 1402, and the first converter 1411 in the memory-compute circuit 1400 can be the same as or similar to the first memory array 1101, the second memory array 1102, and the first converter 1111 in the memory-compute circuit 1100 described with reference to FIG. 11, respectively.

[0160] According to some embodiments, at least two memory arrays in the memory-compute circuit 1400 further include a third memory array 1403. For simplicity, the specific structure of the memory arrays 1401-1403 is not shown in FIG. 14, and it should be understood that the structure of the third memory array 1403 can be the same as or similar to the memory array 1300 described with reference to FIG. 13A or the memory array 1300 described with reference to FIG. 13C.

[0161] According to some embodiments, the at least one converter further comprises a second converter 1412 connected to the column input-output terminals of the plurality of columns of the second memory array 1402 and the input-output terminals of the plurality of columns of the third memory array 1403, and configured to, in response to the first memory array 1401 outputting to the second memory array 1402, for any column of the second memory array 1402, convert an output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the third memory array 1403, and input the input signal of the corresponding column of the third memory array 1403 to the column input-output terminal of the corresponding column of the third memory array 1403, wherein the corresponding column of the third memory array 1403 is a column of the third memory array 1403 corresponding to the any column of the second memory array 1402. According to embodiments as described in the present disclosure, the second converter 1412 controls the second memory array 1402 to further output to the third memory array 1403 for forward calculation.

[0162] According to embodiments as described in the present disclosure, by using memory arrays with different column input / output configurations, i.e., by coupling memory arrays with column outputs with memory arrays with column inputs through converters, the operation efficiency is improved and the circuit design is simplified without separately setting components for performing matrix transposition.

[0163] According to some embodiments, the second converter 1412 is further configured to, in response to the second memory array 1402 outputting to the first memory array 1401, for any column of the third memory array 1403, convert an output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the second memory array 1402, and input the input signal of the corresponding column of the second memory array 1402 to the column input-output terminal of the corresponding column of the second memory array 1402, wherein the corresponding column of the second memory array 1402 is a column of the second memory array 1402 corresponding to the any column of the third memory array 1403. According to embodiments as described in the present disclosure, the second converter 1412 controls the third memory array 1403 to output to the second memory array 1402 for reverse calculation.

[0164] According to embodiments as described in the present disclosure, in different modes of calculation using the compute-in-memory circuit 1400, e.g., forward calculation from the first memory array 1401 to the third memory array 1403 and reverse calculation from the third memory array 1403 to the first memory array 1401, without changing the circuit structure of the first memory array 1401, the second memory array 1402, and the third memory array 1403 for performing calculation, only the signal flow direction needs to be changed by controlling the converters 1411, 1412, thereby improving the utilization rate of the compute-in-memory circuit.

[0165] FIG. 15 shows a schematic diagram of a storage-computing circuit 1500 according to an example embodiment of the present disclosure. According to some embodiments, the first memory array 1501, the second memory array 1502, and the first converter 1511 in the storage-computing circuit 1500 can be the same as or similar to the first memory array 1101, the second memory array 1102, and the first converter 1111 in the storage-computing circuit 1100 described with reference to FIG. 11, respectively, and the third memory array 1503 and the second converter 1512 in the storage-computing circuit 1500 can be the same as or similar to the third memory array 1403 and the second converter 1412 in the storage-computing circuit 1400 described with reference to FIG. 14, respectively.

[0166] According to some embodiments, at least two of the memory arrays in the storage-computing circuit 1500 further include a fourth memory array 1504. For simplicity, the specific structures of the memory arrays 1501-1503 are not shown in FIG. 15, and it should be understood that the structure of the fourth memory array 1504 can be the same as or similar to the memory array 1300 described with reference to FIG. 13A or the memory array 1300 described with reference to FIG. 13C.

[0167] According to some embodiments, the at least one converter further includes a third converter 1513 and a fourth converter 1514. According to some embodiments, the third converter 1513 is connected to the row input-output terminals of a plurality of rows of the third memory array 1503 and the input-output terminals of a plurality of rows of the fourth memory array 1504, and is configured to, in response to the first memory array 1501 outputting to the second memory array 1502, for any row of the third memory array 1503, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the fourth memory array 1504, and input the input signal of the corresponding row of the fourth memory array 1504 to the row input-output terminal of the corresponding row of the fourth memory array 1504, where the corresponding row of the fourth memory array 1504 is a row of the fourth memory array 1504 corresponding to the any row of the third memory array 1503.

[0168] According to some embodiments, the fourth converter 1514 is connected to column input-output terminals of a plurality of columns of the fourth memory array 1504 and input-output terminals of a plurality of columns of the first memory array 1501, and is configured to, in response to the first memory array 1501 outputting to the second memory array 1502, for any column of the fourth memory array 1504, convert an output signal of a column input-output terminal of the any column to an input signal of a corresponding column of the first memory array 1501, and input the input signal of the corresponding column of the first memory array 1501 to the column input-output terminal of the corresponding column of the first memory array 1501, wherein the corresponding column of the first memory array 1501 is a column of the first memory array 1501 corresponding to the any column of the fourth memory array 1504.

[0169] According to embodiments as in the present disclosure, the third converter 1513 controls the third memory array 1503 to further output to the fourth memory array 1504, and the fourth converter 1514 controls the fourth memory array 1504 to further output to the first memory array 1501, for forward calculation.

[0170] According to some embodiments, the third converter 1513 is further configured to, in response to the second memory array 1502 outputting to the first memory array 1501, for any row of the fourth memory array 1504, convert an output signal of a row input-output terminal of the any row to an input signal of a corresponding row of the third memory array 1503, and input the input signal of the corresponding row of the third memory array 1503 to the row input-output terminal of the corresponding row of the third memory array 1503, wherein the corresponding row of the third memory array 1503 is a row of the third memory array 1503 corresponding to the any row of the fourth memory array 1504.

[0171] According to some embodiments, the fourth converter is further configured to, in response to the second memory array 1502 outputting to the first memory array 1501, for any column of the first memory array 1501, convert an output signal of a column input-output terminal of the any column to an input signal of a corresponding column of the fourth memory array 1504, and input the input signal of the corresponding column of the fourth memory array 1504 to the column input-output terminal of the corresponding column of the fourth memory array 1504, wherein the corresponding column of the fourth memory array 1504 is a column of the fourth memory array 1504 corresponding to the any column of the first memory array 1501.

[0172] According to embodiments as in the present disclosure, the third converter 1513 controls the fourth memory array 1504 to output to the third memory array 1503, and the fourth converter 1514 controls the first memory array 1501 to output to the fourth memory array 1504, for backward calculation.

[0173] According to embodiments as described in the disclosure, by using memory arrays with different row input / output configurations and different column input / output configurations, i.e., by coupling the memory array with column outputs with the memory array with column inputs through the transducer, the operation efficiency is improved and the circuit design is simplified without separately setting components for performing matrix transposition.

[0174] According to embodiments as described in the disclosure, in different modes of calculation using the memory-computing circuit 1500, for example, forward calculation of the memory-computing circuit from the first memory array 1501 to the fourth memory array 1504 and reverse calculation of the memory-computing circuit from the fourth memory array 1504 to the first memory array 1501, without changing the circuit structure of the first memory array 1501, the second memory array 1502, the third memory array 1503, and the fourth memory array 1504 for performing calculation, only the control of the transducers 1511-1514 to change the signal flow direction is needed, thereby improving the utilization rate of the memory-computing circuit.

[0175] FIG. 16 shows a schematic diagram of a transducer 1600 in a memory-computing circuit according to an exemplary embodiment of the disclosure. According to some embodiments, the transducer 1600 can be the same as or similar to the transducer 1111 described with reference to FIG. 11, the transducers 1411-1412 described with reference to FIG. 14, and the transducers 1511-1514 described with reference to FIG. 15.

[0176] According to some embodiments, the transducer 1600 includes an analog-to-digital transducer 1601 configured to generate a digital output signal of the analog-to-digital transducer 1601 based on an output signal of one of two memory arrays connected with the transducer 1600, a digital-to-analog transducer 1602 configured to generate an analog output signal of the transducer 1600 and output the analog output signal to the other of the two memory arrays connected with the transducer 1600, and a multiplexer 1603 configured to control the analog-to-digital transducer 1601 to receive the output signal of one of the two memory arrays connected with the transducer 1600 and control the digital-to-analog transducer 1602 to output the analog output signal of the transducer 1600 to the other of the two memory arrays connected with the transducer.

[0177] According to some embodiments, the converter 1600 can further include other components, for example, a current-to-voltage converter for converting the received output current of the memory array into a voltage. According to some embodiments, the converter 1600 further includes an intermediate circuit between the analog-to-digital converter 1601 and the digital-to-analog converter 1602, and the analog-to-digital converter 1601 outputs the generated digital output signal to the intermediate circuit, the intermediate circuit generates an intermediate signal based on the digital output signal from the analog-to-digital converter 1601, and the digital-to-analog converter 1602 generates the analog output signal of the converter 1600 based on the received intermediate signal from the intermediate circuit.

[0178] According to embodiments as described in the present disclosure, by including multiplexers in the converters, the signal flow direction in the compute-in-memory circuit can be controlled.

[0179] FIG. 17 shows a schematic diagram of the compute-in-memory circuit 1500 performing forward computation according to an exemplary embodiment of the present disclosure. According to some embodiments, the compute-in-memory circuit 1500 in FIG. 17 can be the same as or similar to the compute-in-memory circuit described with reference to FIG. 15, with the only difference being that FIG. 17 depicts the internal structure of the converters 1511-1514. It should be understood that for simplicity, only the analog-to-digital converters and the digital-to-analog converters of the converters 1511-1514 are depicted in FIG. 17, and the multiplexers are omitted, but in fact, the converters 1511-1514 include multiplexers to control the signal flow direction.

[0180] According to some embodiments, the first analog-to-digital converter 15111 in the first converter 1511 receives the output signal from the first memory array 1501, and the first digital-to-analog converter 15112 generates an analog output signal and outputs the generated analog output signal to the second memory array 1502.

[0181] According to some embodiments, the second analog-to-digital converter 15121 in the second converter 1512 receives the output signal from the second memory array 1502, and the second digital-to-analog converter 15122 generates an analog output signal and outputs the generated analog output signal to the third memory array 1503.

[0182] According to some embodiments, the third analog-to-digital converter 15131 in the third converter 1513 receives the output signal from the third memory array 1503, and the third digital-to-analog converter 15132 generates an analog output signal and outputs the generated analog output signal to the fourth memory array 1504.

[0183] According to some embodiments, a fourth analog-to-digital converter 15141 in the fourth converter 1514 receives the output signal from the fourth memory array 1504 and a fourth digital-to-analog converter 15142 generates an analog output signal and outputs the generated analog output signal to the first memory array 1501.

[0184] FIG. 17 shows a schematic diagram of the forward calculation of the memory-compute circuit 1500 according to an exemplary embodiment of the present disclosure. According to some embodiments, the memory-compute circuit 1500 in FIG. 17 can be the same as or similar to the memory-compute circuit described with reference to FIG. 15, with the only difference being that FIG. 17 depicts the internal structure of the converters 1511-1514. It should be understood that for simplicity, only the analog-to-digital converters and digital-to-analog converters of the converters 1511-1514 are depicted in FIG. 17, and the multiplexers are omitted, but in practice, the converters 1511-1514 can include multiplexers to control the signal flow direction.

[0185] According to some embodiments, a first analog-to-digital converter 15111 in the first converter 1511 receives the output signal from the second memory array 1502 and a first digital-to-analog converter 15112 generates an analog output signal and outputs the generated analog output signal to the first memory array 1501.

[0186] According to some embodiments, a second analog-to-digital converter 15121 in the second converter 1512 receives the output signal from the third memory array 1503 and a second digital-to-analog converter 15122 generates an analog output signal and outputs the generated analog output signal to the second memory array 1502.

[0187] According to some embodiments, a third analog-to-digital converter 15131 in the third converter 1513 receives the output signal from the fourth memory array 1504 and a third digital-to-analog converter 15132 generates an analog output signal and outputs the generated analog output signal to the third memory array 1503.

[0188] According to some embodiments, a fourth analog-to-digital converter 15141 in the fourth converter 1514 receives the output signal from the first memory array 1501 and a fourth digital-to-analog converter 15142 generates an analog output signal and outputs the generated analog output signal to the fourth memory array 1504.

[0189] According to some embodiments, the first transistor is a silicon transistor (e.g., a Complementary Metal-Oxide-Semiconductor (CMOS) transistor), and the second transistor is an Indium Gallium Zinc Oxide (IGZO) transistor. According to embodiments as described in the present disclosure, since the leakage performance of the IGZO transistor is better, using the IGZO transistor as the write transistor can better prevent the leakage of the memory cell (e.g., the leakage of the storage capacitor or the parasitic capacitor connected to the source terminal or the drain terminal of the IGZO transistor), and since the gate of the silicon transistor is usually oxide, there is not much leakage, and using the silicon transistor as the read transistor also does not cause much leakage of the memory cell (e.g., the leakage of the storage capacitor or the parasitic capacitor) IGZO.

[0190] According to other embodiments, the first transistor can also be set as an IGZO transistor to improve the write speed.

[0191] According to some embodiments, the storage and calculation circuit can further include a programming circuit to control the process of writing to the memory array in the storage and calculation circuit.

[0192] FIG. 19 shows a flowchart of a method 1900 for controlling a storage and calculation circuit (e.g., the storage and calculation circuit 1100 described with reference to FIG. 11, the storage and calculation circuit 1400 described with reference to FIG. 14, and the storage and calculation circuit 1500 described with reference to FIG. 15) according to exemplary embodiments of the present disclosure. According to some embodiments, the features and / or technical effects of the storage and calculation circuits described above with reference to FIGS. 11-18 and the components therein can be correspondingly applied to the method 1900, and thus are omitted here. As shown in FIG. 19, the method 1900 includes:

[0193] Step S1901: in response to the first memory array outputting to the second memory array, inputting an input signal corresponding to each column of the first memory array to the column input-output terminal of each column;

[0194] Step S1902: for any row of the first memory array, converting the output signal of the row input-output terminal of any row to an input signal of the corresponding row of the second memory array; and

[0195] Step S1903: inputting the input signal of the corresponding row of the second memory array to the row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is the row of the second memory array corresponding to any row of the first memory array.

[0196] According to some embodiments, the method as described in the present disclosure further comprises: in response to the second memory array outputting to the first memory array, inputting to the column input-output terminals of each column of the second memory array an input signal corresponding to the column; for any row of the second memory array, converting the output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the first memory array; and inputting to the row input-output terminal of the corresponding row of the first memory array the input signal of the corresponding row of the first memory array, wherein the corresponding row of the first memory array is a row of the first memory array corresponding to the any row of the second memory array.

[0197] According to some embodiments, the at least two memory arrays further comprise a third memory array, and the at least one converter further comprises a second converter connected to the column input-output terminals of the plurality of columns of the second memory array and the input-output terminals of a plurality of columns of the third memory array, and the method as described in the present disclosure further comprises: in response to the first memory array outputting to the second memory array, for any column of the second memory array, converting the output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the third memory array; and inputting to the column input-output terminal of the corresponding column of the third memory array the input signal of the corresponding column of the third memory array, wherein the corresponding column of the third memory array is a column of the third memory array corresponding to the any column of the second memory array.

[0198] According to some embodiments, the method as described in the present disclosure further comprises: in response to the second memory array outputting to the first memory array, inputting to the row input-output terminals of each row of the third memory array an input signal corresponding to the row; for any column of the third memory array, converting the output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the second memory array; and inputting to the column input-output terminal of the corresponding column of the second memory array the input signal of the corresponding column of the second memory array, wherein the corresponding column of the second memory array is a column of the second memory array corresponding to the any column of the third memory array.

[0199] According to some embodiments, the at least two memory arrays further comprise a fourth memory array, the at least one translator further comprises a third translator and a fourth translator, the third translator is connected to row input-output terminals of a plurality of rows of the third memory array and input-output terminals of a plurality of rows of the fourth memory array, the fourth translator is connected to column input-output terminals of a plurality of columns of the fourth memory array and input-output terminals of a plurality of columns of the first memory array, and the method as described in the disclosure further comprises: in response to the second memory array outputting to the first memory array, for any row of the third memory array, translating output signals of row input-output terminals of the any row into input signals of a corresponding row of the fourth memory array; and inputting the input signals of the corresponding row of the fourth memory array to row input-output terminals of the corresponding row of the fourth memory array, wherein the corresponding row of the fourth memory array is a row of the fourth memory array corresponding to the any row of the third memory array, and in response to the first memory array being in the output mode, inputting the input signals corresponding to each column of the first memory array to column input-output terminals of the column comprises: in response to the second memory array outputting to the first memory array, for any column of the fourth memory array, translating output signals of column input-output terminals of the any column into input signals of a corresponding column of the first memory array; and inputting the input signals of the corresponding column of the first memory array to column input-output terminals of the corresponding column of the first memory array, wherein the corresponding column of the first memory array is a column of the first memory array corresponding to the any column of the fourth memory array.

[0200] According to some embodiments, the method as described in the disclosure further comprises: in response to the second memory array outputting to the first memory array, for any column of the first memory array, translating output signals of column input-output terminals of the any column into input signals of a corresponding column of the fourth memory array, and inputting the input signals of the corresponding column of the fourth memory array to column input-output terminals of the corresponding column of the fourth memory array, wherein the corresponding column of the fourth memory array is a column of the fourth memory array corresponding to the any column of the first memory array, and in response to the second memory array outputting to the first memory array, for any column of the second memory array, translating output signals of column input-output terminals of the any column into input signals of a corresponding column of the third memory array comprises: in response to the second memory array outputting to the first memory array, for any row of the fourth memory array, translating output signals of row input-output terminals of the any row into input signals of a corresponding row of the third memory array; and inputting the input signals of the corresponding row of the third memory array to row input-output terminals of the corresponding row of the third memory array, wherein the corresponding row of the third memory array is a row of the third memory array corresponding to the any row of the fourth memory array.

[0201] The present disclosure provides a memory-compute circuit, comprising: a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell comprises a first transistor and a second transistor, a gate terminal of the first transistor in each memory cell is connected to a first terminal of the second transistor, an output current of each memory cell is an output current of a first terminal of the first transistor in the memory cell, and each memory cell is configured to store a weight corresponding to the memory cell, wherein the first terminals of the first transistors in the memory cells in a same row are connected to a row output terminal corresponding to the row, and the second terminals of the first transistors in the memory cells in a same column are connected to a column input terminal corresponding to the column; and one or more write control circuits, wherein each write control circuit is configured to control one or more memory cells in the memory array, and each write control circuit is configured to, for any memory cell controlled by the write control circuit, in response to that any memory cell is in a write state and an output current of that any memory cell satisfies a threshold condition, control to stop applying a write signal to a second terminal of the second transistor in that any memory cell, wherein the threshold condition is determined based on a to-be-written value of that any memory cell, wherein the first terminal of the first transistor is a source terminal and the second terminal of the first transistor is a drain terminal, or the first terminal of the first transistor is a drain terminal and the second terminal of the first transistor is a source terminal, and the first terminal of the second transistor is a source terminal and the second terminal of the second transistor is a drain terminal, or the first terminal of the second transistor is a drain terminal and the second terminal of the second transistor is a source terminal.

[0202] According to embodiments as described in the present disclosure, via the write control circuit, by controlling to stop the write of the memory cell according to the output current of the memory cell when the memory cell is in the write state, the accuracy of the value written into the memory cell is ensured.

[0203] FIG. 20 shows a schematic diagram of a memory-compute circuit 2000 according to an exemplary embodiment of the present disclosure.

[0204] According to some embodiments, as shown in FIG. 20, the memory-compute circuit 2000 comprises a memory array 2010 and one or more write control circuits 2021-202N, wherein each write control circuit is configured to control one or more memory cells in the memory array 2010. It should be understood that although multiple write control circuits 2021-202N are shown in FIG. 20, FIG. 20 is merely schematic, and the memory-compute circuit 2000 can comprise only one write control circuit.

[0205] According to some embodiments, for each write control circuit, each write control circuit is configured to control one or more memory cells in the memory array, for example, as shown in FIG. 20, write control circuit 2021 is configured to control memory cells in a first column and a second column in the memory array.

[0206] According to some embodiments, as shown in FIG. 20, each of write control circuits 2021-202N can implement control of write to multiple memory cells in a multiplexed manner, wherein for each write control circuit, when any of the memory cells under its control is in a write state, the output current of the memory cell in the write state is detected to determine whether the write signal applied to the second terminal of the second transistor in the memory cell needs to be stopped to end the write to the memory cell. It should be understood that, as described above, the compute-in-memory circuit 2000 can only include one write control circuit, at this time, the write control circuit can implement write control to the memory cells in the compute-in-memory circuit 2000 through multiplexing, in this implementation, the circuit structure for write control is simplified, the area of the write control circuit on the chip is saved, but the efficiency of write to the compute-in-memory circuit is reduced compared to the embodiment of using multiple write control circuits.

[0207] According to some embodiments, each write control circuit includes a write detection circuit configured to, for any memory cell under the control of the write control circuit, in response to any memory cell being in a write state and the output current of any memory cell satisfying a threshold condition, generate a stop write signal corresponding to any memory cell, and each memory cell further includes a write control switch, one end of the write control switch being connected to the second terminal of the second transistor in the memory cell, the other end of the write control switch receiving the write signal corresponding to the memory cell, and the write control switch in each memory cell is configured to, in response to receiving the stop write signal corresponding to the memory cell at the control end of the write control switch, open the write control switch.

[0208] According to some embodiments, the write control switch in each memory cell is further configured to, in response to the memory cell being in a write state and not receiving the stop write signal corresponding to the memory cell at the control end of the write control switch, close the write control switch.

[0209] It should be understood that the transmission of signals in the figures is only schematically shown, but the actual circuit connection can be adjusted according to actual needs, for example, in FIG. 20, the memory cells in the same column can share a bus for transmitting the write control signal, and each memory cell in the same column has a signal sub-line respectively connected to the bus to transmit the write control signal to the memory cell.

[0210] FIG. 21 shows a circuit schematic diagram of a write control according to an example embodiment of the present disclosure. For simplicity, in FIG. 21, only one write control circuit and one memory cell controlled thereby in a write state are drawn out to illustrate the write control of the write control circuit to the memory cell, while other parts of the memory array are omitted.

[0211] According to some embodiments, the memory cell 2100 shown in FIG. 21 can be the same as or similar to the memory cell in the memory array 2010 described with reference to FIG. 20 and the memory cell 1200 described with reference to FIG. 12C or 12D, and thus the characteristics and technical effects of the memory cell in the memory array 2010 described with reference to FIG. 20 and the memory cell 1200 described with reference to FIG. 12C or 12D above can also be applied to the memory cell 2100 in FIG. 21, and are omitted here.

[0212] According to some embodiments, the write control circuit 2110 shown in FIG. 21 can be the same as or similar to the write control circuits 2021-202N described with reference to FIG. 20, and thus the characteristics and technical effects of the write control circuits 2021-202N in the memory array 2000 described with reference to FIG. 20 above can also be applied to the write control circuit 2110 in FIG. 21, and are omitted here.

[0213] According to some embodiments, the write control circuit 2110 includes a write detection circuit 2111 configured to, for any memory cell (e.g., the memory cell 2100 shown in FIG. 21) controlled by the write control circuit, generate a stop write signal corresponding to the any memory cell (e.g., the memory cell 2100 shown in FIG. 21) in response to the any memory cell (e.g., the memory cell 2100 shown in FIG. 21) being in a write state and an output current of the any memory cell (e.g., the memory cell 2100 shown in FIG. 21) satisfying a threshold condition.

[0214] According to some embodiments, the memory cell 2100 further includes a write control switch 2104 having one end connected to the second terminal 2102b of the second transistor 2102 in the memory cell 2100 and the other end receiving a write signal corresponding to the memory cell 2100, and the write control switch 2104 in each memory cell is configured to, in response to receiving the stop write signal corresponding to the memory cell at the control end of the write control switch 2104, open the write control switch. The gate terminal 2101g of the first transistor 2101 can be connected to the capacitor 2103 and the first terminal 2102a of the second transistor.

[0215] According to some embodiments, although the write control circuit 2110 is shown in FIG. 21 to directly receive the output current of the memory cell 2100, as will be described in further detail below with reference to FIGS. 22-23, the write control circuit 2110 can also be connected through a multiplexer to the plurality of memory cells whose write it controls to implement its multiplexing, in particular, when the write control circuit 2110 is used to control any memory cell that is in a write state, the write control circuit 2110 is connected through the multiplexer to the memory cell that is in the write state to receive its output current.

[0216] According to some embodiments, the write control switch in the memory cell 2100 is connected to a write bit line (WBL) 2120 corresponding to the memory cell 2100 to receive a write signal. According to some embodiments, as shown in FIG. 20, the second terminal of the second transistor in the memory cell in the same column in the memory array is connected (e.g., connected to a write bit line corresponding to the column), and the gate terminal 2102g of the second transistor in the memory cell in the same row in the memory array is connected (e.g., connected to a write word line corresponding to the row). According to other embodiments, the second terminal of the second transistor in the memory cell in the same row in the memory array is connected (e.g., connected to a write bit line corresponding to the column), and the gate terminal 2102g of the second transistor in the memory cell in the same column in the memory array is connected (e.g., connected to a write word line corresponding to the row).

[0217] According to some embodiments, when performing a write operation on the memory cell 2100, an input voltage is applied to the second terminal 2101a of the first transistor 2101 in the memory cell 2100, where the input voltage can be a preset value in order to determine a threshold condition for judging the output current. According to some embodiments, as analyzed above, since the output current of the first terminal 2101b of the first transistor 2101 in the memory cell 2100 is the product of the weight stored by the memory cell 2100 and the input voltage on the second terminal 2101a of the first transistor 2101 of the memory cell 2100, the threshold condition for the output current can be set to be that the output current is greater than or equal to an upper limit value of the current, where the upper limit value of the current is set based on the weight value written to the memory cell 2100 and the input voltage of the memory cell 2100 (e.g., equal to the product of the weight value written to the memory cell 2100 and the input voltage of the memory cell 2100).

[0218] According to some embodiments, although the write control circuit 2110 is shown in FIG. 21 to send the stop write signal directly to the memory cell 2100, as will be described in further detail below with reference to FIGS. 22-23, the write control circuit 2110 can also be connected through a multiplexer to a plurality of memory cells whose write it controls, to multiplex it, in particular, when the write control circuit 2110 is used to control any memory cell in a write state, the write control circuit 2110 is connected through the multiplexer to the memory cell in the write state to send the stop write signal to the write control switch therein.

[0219] According to some embodiments, the write control switch 2104 in the memory cell 2100 is further configured to close the write control switch 2104 in response to the memory cell 2100 being in the write state and not receiving the stop write signal corresponding to the memory cell at the control terminal of the write control switch 2104. According to some embodiments, the write detection circuit 2111 is further configured to generate the open write signal corresponding to any memory cell (e.g., the memory cell 2100 shown in FIG. 21) in response to any memory cell (e.g., the memory cell 2100 shown in FIG. 21) being in the write state and the output current of any memory cell (e.g., the memory cell 2100 shown in FIG. 21) not satisfying the threshold condition, and the write control switch 2104 in the memory cell 2100 is further configured to close the write control switch 2104 in response to the memory cell 2100 being in the write state and receiving the open write signal corresponding to the memory cell at the control terminal of the write control switch 2104.

[0220] According to some embodiments, each write control circuit includes a first multiplexer, and the first multiplexer in each write control circuit is configured to connect the write control circuit to which the first multiplexer corresponds to the second terminal of the first transistor in any memory cell in the write state in response to any memory cell controlled by the write control circuit to which the first multiplexer corresponds being in the write state, to receive the output current of any memory cell in the write state.

[0221] According to some embodiments, each write control circuit comprises a second multiplexer, and the second multiplexer in each write control circuit is configured to, in response to any memory cell controlled by the write control circuit to which the second multiplexer corresponds being in a write state, connect the write control circuit to which the second multiplexer corresponds to the write control circuit in any memory cell in the write state to provide a stop write signal corresponding to any memory cell to any memory cell when the write control circuit to which the second multiplexer corresponds generates the stop write signal corresponding to any memory cell.

[0222] FIG. 22 shows a schematic diagram of a write control circuit 2200 according to an exemplary embodiment of the present disclosure. According to some embodiments, the write control circuit 2200 can be the same as or similar to the write control circuits 2021-202N described with reference to FIG. 20, the write control circuit 2110 in FIG. 21, and thus the features and / or technical effects of the write control circuits 2021-202N described with reference to FIG. 20, the write control circuit 2110 in FIG. 21 can be applied to the write control circuit 2200 and thus are omitted.

[0223] According to some embodiments, the write control circuit 2200 comprises a first multiplexer 2201 configured to, in response to any memory cell controlled by the write control circuit 2200 being in a write state, connect the write control circuit 2200 to which the first multiplexer 2201 corresponds to the second terminal of the first transistor in any memory cell in the write state to receive an output current of any memory cell in the write state.

[0224] According to some embodiments, the write control circuit 2200 comprises a write detection circuit 2203, where the write detection circuit 2203 can be the same as or similar to the write detection circuit 2111 described with reference to FIG. 21, and the first multiplexer 2201 can optionally connect any memory cell in the write state to the write detection circuit 2203 for write control of the any memory cell.

[0225] According to some embodiments, the write control circuit 2200 comprises a second multiplexer 2202, and the second multiplexer 2202 is configured to, in response to any memory cell controlled by the write control circuit 2200 being in a write state, connect the write control circuit 2200 to the write control switch in any memory cell in the write state to provide a stop write signal corresponding to any memory cell to the write control unit in any memory cell when the write control circuit 2200 generates the stop write signal corresponding to any memory cell.

[0226] According to some embodiments, the second multiplexer 2202 can optionally connect the write control switch in any memory cell in the write state to the write detection circuit 2210 for write control of the any memory cell.

[0227] FIG. 23 shows a circuit schematic diagram of a write control circuit according to an exemplary embodiment of the present disclosure. For simplicity, in FIG. 23, only one write control circuit 2300 and memory cells 2311-231N in a memory cell controlled thereby located in a row are drawn out to illustrate the write control of the memory cells by the write control circuit, while other parts of the memory cell are omitted.

[0228] According to some embodiments, when performing a write operation on a memory cell in a memory array, the memory cells are written row by row, thus, only the memory cells in a row can be equivalently connected to the write control circuit 2300 at the same write time. According to some embodiments, the memory cells 2311-231N are connected to the same write word line 2320.

[0229] According to some embodiments, the write control circuit 2300 is optionally connected to the memory cells 2311-231N through a first multiplexer 2301 and a second multiplexer 2302, where the first multiplexer 2301 optionally connects the memory cells 2311-231N in the write state to the write control circuit 2300 (e.g., a write detection circuit 2303 in the write control circuit 2300) to receive the output current from the memory cells in the write state, and the second multiplexer 2302 optionally connects the memory cells 2311-231N in the write state to the write control circuit 2300 (e.g., the write detection circuit 2303 in the write control circuit 2300) to transmit a stop write signal to the memory cells in the write state when the output current of the memory cells in the write state meets a threshold condition.

[0230] According to some embodiments, each of the one or more write control circuits comprises: a conversion circuit configured to receive an output current of any memory cell controlled by the write control circuit, and convert the received output current of the any memory cell into a detection voltage; and a comparison circuit configured to, in response to the detection voltage being greater than or equal to a threshold voltage, control to stop applying a write signal to a second terminal of a second transistor in the any memory cell, where the threshold voltage is determined based on a to-be-written value of the any memory cell.

[0231] FIG. 24 shows a schematic diagram of a write control circuit 2400 according to an example embodiment of the present disclosure. It should be appreciated that, for simplicity, only one write control circuit 2400 and signals received from and sent to memory cells in a write state are drawn, while other components and connections in the memory array are omitted.

[0232] According to some embodiments, as shown in FIG. 24, the write control circuit 2400 includes a conversion circuit 2401 configured to: receive an output current I out of any memory cell controlled by the write control circuit 2400, and convert the received output current I out of any memory cell into a detection voltage V dec ; and a comparison circuit 2402 configured to: in response to the detection voltage V dec being greater than or equal to a threshold voltage V ref , control to stop applying a write signal to a second terminal of a second transistor in any memory cell, wherein the threshold voltage V ref is determined based on a to-be-written value of any memory cell.

[0233] According to some embodiments, in response to the detection voltage Vdec being greater than or equal to the threshold voltage V ref , the comparison circuit 2402 outputs a stop write signal.

[0234] According to some embodiments, the write control circuit 2400 can further include the first multiplexer and / or the second multiplexer as shown in FIG. 22 or FIG. 23 to optionally connect the write control circuit 2400 to a memory cell in a write state among the memory cells controlled thereby.

[0235] According to some embodiments, one or more write control circuits include a write control circuit corresponding to each column group of the memory array, wherein each column group of the memory array includes memory cells in one or more columns of the memory array. According to some embodiments, each column group of the memory array can include memory cells in four columns of the memory array.

[0236] FIG. 25 shows a flowchart of a method 2500 for controlling a compute-and-memory circuit (e.g., the compute-and-memory circuit 2000 described with reference to FIG. 20) according to an example embodiment of the present disclosure. According to some embodiments, the features and / or technical effects of the compute-and-memory circuit and components therein described above with reference to FIGs. 20-24 can be correspondingly applied to the method 2500, and thus are omitted here. As shown in FIG. 25, the method 2500 includes:

[0237] Step S2501 : in response to any memory cell in the memory array being in a write state, applying a write signal corresponding to the any memory cell to a second terminal of the second transistor of the any memory cell, and applying an on control signal to a gate terminal of the second transistor of the any memory cell; and

[0238] Step S2502: in response to an output current of the any memory cell in the write state satisfying a threshold condition, controlling to stop applying the write signal corresponding to the any memory cell to the second terminal of the second transistor in the any memory cell, wherein the threshold condition is determined based on a value to be written into the any memory cell.

[0239] According to some embodiments, each memory cell further comprises a write control switch, one end of the write control switch being connected to the second terminal of the second transistor in the memory cell, the other end of the write control switch receiving the write signal corresponding to the memory cell, wherein the controlling to stop applying the write signal corresponding to the any memory cell to the second terminal of the second transistor in the any memory cell in response to the output current of the any memory cell in the write state satisfying the threshold condition comprises: in response to the output current of the any memory cell in the write state satisfying the threshold condition, opening the write control switch in the any memory cell.

[0240] According to some embodiments, the method as described in the present disclosure further comprises: in response to the output current of the any memory cell in the write state not satisfying the threshold condition, closing the write control switch in the any memory cell.

[0241] According to some embodiments, each write control circuit comprises a first multiplexer, and the method as described in the present disclosure further comprises: for each first multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the first multiplexer being in a write state, connecting the write control circuit corresponding to the first multiplexer to the second terminal of the first transistor in the any memory cell in the write state to receive the output current of the any memory cell in the write state.

[0242] According to some embodiments, each write control circuit comprises a second multiplexer, and the method as described in the present disclosure further comprises: for each second multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the second multiplexer being in a write state, connecting the write control circuit corresponding to the second multiplexer to the any memory cell in the write state to provide a stop write signal corresponding to the any memory cell to the any memory cell when the write control circuit corresponding to the second multiplexer generates the stop write signal corresponding to the any memory cell.

[0243] According to some embodiments, each of the one or more write control circuits comprises a conversion circuit and a comparison circuit, and in response to the output current of any memory cell in the write state satisfying a threshold condition, the control of stopping applying the write signal corresponding to the any memory cell to the second terminal of the second transistor in the any memory cell comprises: receiving, via the conversion circuit in the write control circuit corresponding to the any memory cell, the output current of the any memory cell, and converting the received output current of the any memory cell into a detection voltage; and in response to the detection voltage being greater than or equal to a threshold voltage, via the comparison circuit in the write control circuit corresponding to the any memory cell, controlling stopping applying the write signal to the second terminal of the second transistor in the any memory cell, wherein the threshold voltage is determined based on the to-be-written value of the any memory cell.

[0244] The present disclosure provides a memory and computing circuit, comprising: a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell comprises a first transistor and a second transistor, a gate terminal of the first transistor in each memory cell is connected to a first terminal of the second transistor, an output current of each memory cell is an output current of a first terminal of the first transistor in the memory cell, and each memory cell is configured to store a weight corresponding to the memory cell, wherein the first terminals of the first transistors in the memory cells in a same row are connected to a row output terminal corresponding to the row, and the second terminals of the first transistors in the memory cells in a same column are connected to a column input terminal corresponding to the column; and one or more write control circuits, wherein each write control circuit is used to control one or more memory cells in the memory array, and each write control circuit is configured to, for any memory cell controlled by the write control circuit, in response to the any memory cell being in a write state and the output current of the any memory cell satisfying a threshold condition, control stopping applying a write signal to a second terminal of the second transistor in the any memory cell, wherein the threshold condition is determined based on a to-be-written value of the any memory cell, wherein for each write control circuit, gate terminals of the second transistors in different memory cells controlled by the write control circuit are connected to different write word lines, and wherein the first terminal of the first transistor is a source terminal, the second terminal of the first transistor is a drain terminal, or the first terminal of the first transistor is a drain terminal, the second terminal of the first transistor is a source terminal, the first terminal of the second transistor is a source terminal, the second terminal of the second transistor is a drain terminal, or the first terminal of the second transistor is a drain terminal, the second terminal of the second transistor is a source terminal.

[0245] According to embodiments as disclosed herein, via the write control circuit, the accuracy of the value written into the memory cell is ensured by controlling the stop of the write of the memory cell according to the output current of the memory cell when the memory cell is in the write state; and since the gate terminal of the second write transistor (i.e., the transistor performing the write control) in the different memory cell controlled by each write control circuit is connected to a different write word line, independent control of the write process of the different memory cells controlled by each write control circuit can be achieved, ensuring that the memory cell in the write state controlled by each write control circuit does not interfere with the memory cell not in the write state.

[0246] FIG. 26 shows a schematic diagram of a compute circuit 2600 according to an exemplary embodiment of the present disclosure. Similarities between the compute circuit 2600 of FIG. 26 and the compute circuit 2000 of FIG. 20 can not be repeated here, and the differences therebetween will be mainly described.

[0247] According to some embodiments, for each write control circuit, the gate terminal of the second transistor in the different memory cell controlled by the write control circuit is connected to a different write word line, thereby allowing independent write control of the different memory cells controlled by the write control circuit, for example, when one of the memory cells controlled by the write control circuit is in the write state, the on control signal is applied to the write word line to which the memory cell in the write state is connected, and the off control signal is applied to the write word lines to which the other memory cells controlled by the write control circuit are connected, so that the other memory cells make the second transistor in the other memory cells off and not in the write state, wherein since the off control signal is applied to the write word line to which the other memory cells are connected, the second transistor in the other memory cells is off, thereby avoiding the interference caused by the floating voltage that can still exist on the second terminal of the second transistor when the stop of the application of the write signal to the second terminal of the second transistor in the memory cell is controlled as described above, and the interference between the memory cell in the write state and the memory cell not in the write state is minimized.

[0248] According to some embodiments, for each write control circuit of the one or more write control circuits, the gate terminal of the second transistor in any memory cell controlled by the write control circuit and the gate terminal of the second transistor in the corresponding memory cell controlled by the other write control circuit are connected to the same write word line. According to some embodiments, any memory cell controlled by the write control circuit and the corresponding memory cell controlled by the other write control circuit are located in the same row of the memory array and are not adjacent.

[0249] For example, the gate terminals of the second transistors in the memory cells of the same row number and the same column number in the memory cells controlled by the write control circuits 2621-262N as shown in FIG. 26 are connected to the same write word line, for example, the memory cells in the first row, the first column in the memory cells controlled by the write control circuit 2621, the memory cells in the first row, the first column in the memory cells controlled by the write control circuit 2622, …, the memory cells in the first row, the first column in the memory cells controlled by the write control circuit 262N are connected to the same write word line.

[0250] According to embodiments of the present disclosure, by connecting the gate terminals of the second transistors in the corresponding memory cells controlled by different write control circuits to the same write word line, parallel writing of the corresponding memory cells controlled by different write control circuits can be achieved, and since the corresponding memory cells controlled by different write control circuits are usually spaced apart by a certain distance (for example, at least not adjacent memory cells), the possibility of mutual interference between them is extremely small.

[0251] According to some embodiments, for each of the one or more write control circuits, the memory cells controlled by the write control circuit are memory cells in a corresponding column group of the memory array, wherein the corresponding column group of the memory array includes memory cells in a plurality of consecutive columns of the memory array, for example, the write control circuit 2621 controls memory cells in the first column and the second column as shown in FIG. 26. FIG. 27 shows a schematic diagram of a compute-in-memory circuit 2700 according to an exemplary embodiment of the present disclosure. According to some embodiments, the memory array 2710 and the write control circuits 2721-272N in FIG. 27 can be similar to the memory array 2610 and the write control circuits 2621-262N in FIG. 26, respectively, and thus the features and / or effects of the memory array 2610 and the write control circuits 2621-262N described above with reference to FIG. 26 can also be applied to the memory array 2710 and the write control circuits 2721-272N in FIG. 27, and are omitted here.

[0252] According to some embodiments, the compute-in-memory circuit 2700 further includes a first encoding circuit 2731, wherein the first encoding circuit 2731 is configured to generate a signal corresponding to the write word line of the memory array 2710 in the compute-in-memory circuit 2700. According to some embodiments, the first encoding circuit 2700 is configured to, in response to any memory cell in the memory array 2710 being in a write state, apply a turn-on control signal to the write word line connected to the any memory cell; and, in response to any memory cell in the memory array ending the write state, apply a turn-off control signal to the write word line connected to the any memory cell.

[0253] It should be understood that although FIG. 27 shows multiple write control circuits, the storage and compute circuit 2700 can include only one write control circuit, in which case the write control circuit can implement write control of memory cells in the storage and compute circuit 2700 by multiplexing.

[0254] FIG. 28 shows a circuit schematic diagram of controlling write according to an example embodiment of the present disclosure. For simplicity, in FIG. 28, only one write control circuit and one memory cell controlled thereby in a write state are drawn out to illustrate write control of the memory cell by the write control circuit and the write word line, while other parts of the storage and compute circuit are omitted. Similarities of FIG. 28 to FIG. 21 can not be repeated here, and mainly differences are described. For example, the write control circuit 2810 and the write detection circuit 2811 can refer to the write control circuit 2110 and the write detection circuit 2111 of FIG. 21.

[0255] According to some embodiments, the memory cell 2800 includes a first transistor 2801 including terminals 2801a and 2801b and a gate terminal 2801g, a second transistor 2802 including terminals 2802a and 2802b and a gate terminal 2802g, and a capacitor 2803. A write control switch 2804 in the memory cell 2800 is connected to a write bit line (WBL) 2830 corresponding to the memory cell 2800 to receive a write signal.

[0256] According to some embodiments, the gate terminal 2802g of the second transistor 2802 in the memory cell 2800 is connected to a write word line (WWL) 2820 corresponding to the memory cell 2800 to control the second transistor 2802 to turn on or turn off.

[0257] The write control circuit can refer to the write control circuit 2200 of FIG. 22.

[0258] FIG. 29 shows a circuit schematic diagram of controlling write according to an example embodiment of the present disclosure. For simplicity, in FIG. 29, only two write control circuits 2921-2922 and memory cells controlled thereby in a row of memory cells 29111-2911N, 29121-2912N are drawn out to illustrate write control of the memory cells by the write control circuits, while other parts of the storage and compute circuit are omitted.

[0259] According to some embodiments, when performing write operations on memory cells in a memory array, the write operations are performed on the memory cells row by row, so that only memory cells within a same row are connected to write control circuits 2921 and 2922 at a same write time.

[0260] According to some embodiments, for each write control circuit, each memory cell controlled by the write control circuit corresponds to a same write word line as a memory cell controlled by another write control circuit that corresponds to the memory cell. For example, a memory cell 29111 in a first column of memory cells 29111-2911N controlled by a first write control circuit 2921 and a memory cell 29121 in a first column of memory cells 29121-29112N in a same row controlled by a second write control circuit 2922 are connected to a same write word line 2941, a memory cell 29112 in a second column of memory cells 29111-2911N controlled by the first write control circuit 2921 and a memory cell 29122 in a second column of memory cells 29121-29112N in the same row controlled by the second write control circuit 2922 are connected to a same write word line 2942, …, a memory cell 2911N in an Nth column of memory cells 29111-2911N controlled by the first write control circuit 2921 and a memory cell 2912N in the Nth column of memory cells 29121-29112N in the same row controlled by the second write control circuit 2922 are connected to a same write word line 294N.

[0261] According to some embodiments, the write control circuit 2921 is optionally connected to the memory cells 29111-2911N through a first multiplexer 29211 and a second multiplexer 29213, where the first multiplexer 29211 optionally connects memory cells 29111-2911N in a write state to the write control circuit 2921 (e.g., a write detection circuit 29212 in the write control circuit 2921) to receive an output current from the memory cells in the write state, and the second multiplexer 29213 optionally connects the memory cells 29111-2911N in the write state to the write control circuit 2921 (e.g., the write detection circuit 29212 in the write control circuit 2921) to transmit a stop write signal to the memory cells in the write state when the output current from the memory cells in the write state satisfies a threshold condition.

[0262] According to some embodiments, the write control circuit 2922 is optionally connected to the memory cells 29121-2912N through a first multiplexer 29221 and a second multiplexer 29223, wherein the first multiplexer 29221 optionally connects the memory cells 29121-2912N in the write state to the write control circuit 2922 (e.g., the write detection circuit 29222 in the write control circuit 2922) to receive the output current from the memory cells in the write state, and the second multiplexer 29223 optionally connects the memory cells 29121-2912N in the write state to the write control circuit 2922 (e.g., the write detection circuit 29222 in the write control circuit 2922) to transmit the stop write signal to the memory cells in the write state when the output current of the memory cells in the write state meets the threshold condition.

[0263] According to some embodiments, the first encoding circuit 2931 is connected to the write word lines 2941-294N corresponding to the memory cells 29111-2911N, 29121-2912N to generate the respective signals of the write word lines 2941-294N.

[0264] The write control circuit can refer to the write control circuit 2400 of FIG. 24.

[0265] FIG. 30 shows a flowchart of a method 3000 for controlling a memory-computing circuit (e.g., the memory-computing circuit 2600 described with reference to FIG. 26, the memory-computing circuit 2700 described with reference to FIG. 27) according to an exemplary embodiment of the present disclosure. According to some embodiments, the features and / or technical effects of the memory-computing circuits described above with reference to FIGS. 26-29 and the components therein can be correspondingly applied to the method 3000, and thus are omitted here. As shown in FIG. 30, the method 3000 includes:

[0266] Step S3001: in response to any memory cell in the memory array being in the write state, applying a write signal corresponding to the any memory cell to a second terminal of the second transistor of the any memory cell, and applying an on-off control signal to the write word line connected to the any memory cell;

[0267] Step S3002: in response to the output current of the any memory cell in the write state meeting a threshold condition, controlling to stop applying the write signal corresponding to the any memory cell to the second terminal of the second transistor in the any memory cell, wherein the threshold condition is determined based on the to-be-written value of the any memory cell; and

[0268] Step S3003: in response to any memory cell in the memory array ending a write state, applying an off control signal to a write word line connected to any memory cell.

[0269] The present disclosure provides a memory-compute circuit, comprising: a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell comprises a first transistor, a second transistor and a write control switch, in each memory cell, a gate terminal of the first transistor is connected to a first terminal of the second transistor, a first terminal of the write control switch is connected to a gate terminal of the second transistor, a second terminal of the write control switch is connected to a write word line corresponding to the memory cell, an output current of each memory cell is an output current of a first terminal of the first transistor in the memory cell, and each memory cell is configured to store a weight corresponding to the memory cell, wherein the first terminals of the first transistors in the memory cells in a same row are connected to a row output terminal corresponding to the row, and the second terminals of the first transistors in the memory cells in a same column are connected to a column input terminal corresponding to the column; and one or more write control circuits, wherein each write control circuit is used to control one or more memory cells in the memory array, and each write control circuit is configured to, for any memory cell controlled by the write control circuit, in response to any memory cell being in a write state and an output current of any memory cell satisfying a threshold condition, control the write control switch in any memory cell to be off, the threshold condition being determined based on a to-be-written value of any memory cell, wherein the first terminal of the first transistor is a source terminal and the second terminal of the first transistor is a drain terminal, or the first terminal of the first transistor is a drain terminal and the second terminal of the first transistor is a source terminal, and the first terminal of the second transistor is a source terminal and the second terminal of the second transistor is a drain terminal, or the first terminal of the second transistor is a drain terminal and the second terminal of the second transistor is a source terminal.

[0270] FIG. 31 shows a schematic diagram of a memory-compute circuit 3100 according to an example embodiment of the present disclosure. Hereinafter, the similarities between the memory-compute circuit 3100 of FIG. 31 and the memory-compute circuits 2000 and 2600 of FIGS. 20 and 26 will not be described again, and the differences therebetween will be mainly described. For example, the memory array 3110 can refer to the memory arrays 2010 and 2610 of FIGS. 20 and 26.

[0271] According to some embodiments, each memory cell comprises a first transistor, a second transistor, and a write control switch, in each memory cell, a gate terminal of the first transistor is connected to a first terminal of the second transistor, a first terminal of the write control switch is connected to a gate terminal of the second transistor, a second terminal of the write control switch is connected to a write word line (WWL) corresponding to the memory cell, and the memory cell is configured to store a weight corresponding to the memory cell. According to some embodiments, an output current of each memory cell is an output current of a first terminal of the first transistor in the memory cell.

[0272] According to some embodiments, each write control circuit is configured to, for any memory cell controlled by the write control circuit, in response to the any memory cell being in a write state and an output current of the any memory cell satisfying a threshold condition, control a write control switch in the any memory cell to open, the threshold condition being determined based on a value to be written into the any memory cell.

[0273] According to some embodiments, as shown in FIG. 31, each of the write control circuits 3121-312N can control the writing of multiple memory cells in a multiplexed manner, wherein for each write control circuit, when any of the memory cells controlled by the write control circuit is in a write state, the output current of the memory cell in the write state is detected to determine whether the write control switch in the any memory cell needs to be controlled to open to end the writing into the memory cell.

[0274] According to some embodiments, each write control circuit is further configured to, for any memory cell controlled by the write control circuit, in response to the any memory cell being in a write state and an output current of the any memory cell not satisfying a threshold condition, control a write control switch in the any memory cell to close.

[0275] According to some embodiments, in each memory cell, the write control switch is a transistor, a gate terminal of the write control switch is connected to a write control circuit that controls the memory cell, wherein a first terminal of the write control switch is a source terminal and a second terminal of the write control switch is a drain terminal, or a first terminal of the write control switch is a drain terminal and a second terminal of the write control switch is a source terminal.

[0276] FIG. 32 shows a circuit schematic diagram of control of writing according to an example embodiment of this disclosure. For simplicity, in FIG. 32, only one write control circuit and one memory cell controlled thereby in a writing state are drawn out to illustrate the write control of the write control circuit to the memory cell, while other parts of the memory array are omitted. Similarities of FIG. 32 to FIGS. 21 and 28 can not be repeated here, and mainly differences are described.

[0277] The memory cell 3200 includes a first transistor 3201 including terminals 3201a and 3201b and a gate terminal 3201g, a second transistor 3202 including terminals 3202a and 3202b and a gate terminal 3202g, and a capacitor 3203.

[0278] According to some embodiments, the memory cell 3200 can be the same as or similar to the memory cell 1200 described with reference to FIG. 12E or 12F.

[0279] According to some embodiments, the write control circuit 3210 is configured to, for any memory cell (e.g., the memory cell 3200 shown in FIG. 32) controlled thereby, generate a stop writing signal corresponding to the any memory cell (e.g., the memory cell 3200 shown in FIG. 32) in response to the any memory cell (e.g., the memory cell 3200 shown in FIG. 32) being in a writing state and an output current of the any memory cell (e.g., the memory cell 3200 shown in FIG. 32) satisfying a threshold condition.

[0280] According to some embodiments, the memory cell 3200 further includes a write control switch 3204 having one end connected to the gate terminal 3202g of the second transistor 3202 in the memory cell 3200 and the other end receiving a write control signal corresponding to the memory cell 3200, and the write control switch 3204 in each memory cell is configured to, in response to receiving the stop writing signal corresponding to the memory cell at a control terminal of the write control switch 3204, open the write control switch 3204.

[0281] According to some embodiments, the write control switch 3204 is a transistor, and the control terminal of the write control switch 3204 is a gate terminal, wherein the write control switch is turned off in response to receiving the stop writing signal corresponding to the memory cell at the control terminal of the write control switch 3204.

[0282] According to some embodiments, when the write control switch 3204 is open in response to the stop write signal, the second transistor 3202 is disconnected from the word line WWL 3220, and the second transistor 3202 is turned off accordingly, so that the write process to the memory cell 3200 is stopped.

[0283] According to some embodiments, in response to that the memory cell 3200 is in the write state and the output current of the memory cell 3200 does not satisfy the threshold condition, the write control circuit 3210 controls the write control switch 3204 in the memory cell 3200 to be closed, for example, sends the turn-on write signal to the control terminal of the write control switch 3204 in the memory cell 3200, so that the second transistor 3202 can accept the write control signal from the word line WWL 3220 to turn on, and further accept the write signal from the write bit line (WBL) 3230 from the second terminal 3202b of the second transistor 3202 to perform the write operation on the memory cell 3200.

[0284] According to some embodiments, the second terminal of the write control switch in the memory cell in the same row is connected to the write word line corresponding to the row.

[0285] According to some embodiments, each write control circuit includes a second multiplexer, and the second multiplexer in each write control circuit is configured to: in response to that any memory cell controlled by the write control circuit to which the second multiplexer corresponds is in the write state, connect the write control circuit to which the second multiplexer corresponds to the write control switch in any memory cell in the write state.

[0286] FIG. 33 shows a schematic diagram of a write control circuit 3300 according to an exemplary embodiment of the present disclosure. According to some embodiments, the write control circuit 3300 can be the same as or similar to the write control circuits 3121-312N described with reference to FIG. 31 and the write control circuit 3210 in FIG. 32, and thus the features and / or technical effects of the write control circuits 3121-312N described with reference to FIG. 31 and the write control circuit 3210 in FIG. 32 can be applied to the write control circuit 3300 and thus are omitted.

[0287] According to some embodiments, the write control circuit 3300 includes a first multiplexer 3301 configured to: in response to that any memory cell controlled by the write control circuit 3300 to which the first multiplexer 3301 corresponds is in the write state, connect the write control circuit 3300 to which the first multiplexer 3301 corresponds to the second terminal of the first transistor in any memory cell in the write state to receive the output current of any memory cell in the write state.

[0288] According to some embodiments, the write control circuit 3300 comprises a write detection circuit 3303, wherein the write detection circuit 3303 is configured to determine whether to generate a stop write signal based on an output current of the first transistor in any memory cell in a write state received by the first multiplexer 3301, and the first multiplexer 3301 can optionally connect any memory cell in a write state to the write detection circuit 3303 for write control of the any memory cell.

[0289] According to some embodiments, the write control circuit 3300 comprises a second multiplexer 3302, and the second multiplexer 3302 is configured to connect the write control circuit 3300 to the write control switch in any memory cell in a write state in response to any memory cell controlled by the write control circuit 3300 being in a write state.

[0290] According to some embodiments, the write detection circuit 3303 determines whether to generate a stop write signal based on an output current of the first transistor in any memory cell in a write state received by the first multiplexer 3301, and the second multiplexer 3302 can optionally connect the write control switch in any memory cell in a write state to the write detection circuit 3310 for write control of the any memory cell, for example, the write control signal is optionally transmitted by the second multiplexer 3302 to the write control switch in any memory cell in a write state when the write detection circuit 3303 generates the write control signal.

[0291] The circuit schematic diagram for controlling write can refer to the circuit schematic diagram for controlling write of FIG. 23, and the write control circuit can refer to the write control circuit of FIG. 24.

[0292] According to some embodiments, each of the one or more write control circuits comprises: a conversion circuit configured to receive an output current of any memory cell controlled by the write control circuit, and convert the received output current of any memory cell into a detection voltage; and a comparison circuit configured to control a write control switch in any memory cell to be turned off in response to the detection voltage being greater than or equal to a threshold voltage, wherein the threshold voltage is determined based on a to-be-written value of any memory cell.

[0293] FIG. 34 shows a flowchart of a method 3400 for controlling a memory-computing circuit (e.g., the memory-computing circuit 3100 described with reference to FIG. 31) according to an example embodiment of the present disclosure. According to some embodiments, the features and / or technical effects of the memory-computing circuit and components therein described above with reference to FIGS. 31-6 can be correspondingly applied to the method 3400, and thus are omitted here. As shown in FIG. 34, the method 3400 comprises:

[0294] Step S3401: in response to any memory cell in the memory array being in the write state, applying a write signal corresponding to any memory cell to a write word line corresponding to any memory cell, and applying an on control signal to a gate terminal of the second transistor of any memory cell; and

[0295] Step S3402: in response to an output current of any memory cell in the write state satisfying a threshold condition, controlling the write control switch in any memory cell to be off, wherein the threshold condition is determined based on a to-be-written value of any memory cell.

[0296] According to some embodiments, the method as described in the present disclosure further comprises: in response to an output current of the any memory cell in the write state not satisfying a threshold condition, controlling the write control switch in the any memory cell to be on.

[0297] According to some embodiments, in each memory cell, the write control switch is a transistor, a gate terminal of the write control switch is connected to a write control circuit controlling the memory cell, and in response to an output current of any memory cell in the write state satisfying a threshold condition, controlling the write control switch in any memory cell to be off comprises: in response to an output current of any memory cell in the write state satisfying a threshold condition, generating a stop write signal corresponding to any memory cell; and applying the stop write signal corresponding to any memory cell to a gate terminal of the write control switch in any memory cell to control the write control switch in any memory cell to be off.

[0298] According to some embodiments, each write control circuit comprises a second multiplexer, and the method as described in the present disclosure further comprises: for each second multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the second multiplexer being in the write state, connecting the write control circuit corresponding to the second multiplexer to the write control switch in any memory cell in the write state.

[0299] According to some embodiments, each of the one or more write control circuits comprises a conversion circuit and a comparison circuit, and in response to the output current of any memory cell in the write state satisfying a threshold condition, controlling the write control switch in the any memory cell to open comprises: receiving, via the conversion circuit in the write control circuit corresponding to the any memory cell, the output current of the any memory cell, and converting the received output current of the any memory cell into a detection voltage; and in response to the detection voltage being greater than or equal to a threshold voltage, controlling, via the comparison circuit in the write control circuit corresponding to the any memory cell, the write control switch in the any memory cell to open, wherein the threshold voltage is determined based on the to-be-written value of the any memory cell.

[0300] The present disclosure provides a memory-computing circuit, comprising: a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell comprises a first transistor and a second transistor, a gate terminal of the first transistor is connected to a first terminal of the second transistor, and each memory cell is configured to store a weight corresponding to the memory cell, wherein the first terminals of the memory cells in a same row are connected to a row output terminal corresponding to the row, and the second terminals of the memory cells in a same column are connected to a column input terminal corresponding to the column; and a plurality of conversion circuits comprising a plurality of input conversion circuits corresponding to the plurality of columns, wherein each input conversion circuit is configured to: convert an input current corresponding to the input conversion circuit into an input voltage corresponding to the input conversion circuit, and output the input voltage corresponding to the input conversion circuit to the column input terminal of the column corresponding to the input conversion circuit, wherein the first terminal of the first transistor is a source terminal, the second terminal of the first transistor is a drain terminal, or the first terminal of the first transistor is a drain terminal, the second terminal of the first transistor is a source terminal, and the first terminal of the second transistor is a source terminal, the second terminal of the second transistor is a drain terminal, or the first terminal of the second transistor is a drain terminal, the second terminal of the second transistor is a source terminal.

[0301] According to embodiments as described in the present disclosure, by storing the computation-related weights in the memory array in the memory-computing circuit, and by applying the input voltage to the first terminal of the first transistor (i.e., the source terminal or the drain terminal of the first transistor) of the memory cell in the memory array, the computation (e.g., multiplication computation) between the input and the stored weights can be implemented, thereby reducing the overhead brought by analog-to-digital conversion, digital-to-analog conversion, data transmission, etc., improving the processing performance, simplifying the circuit structure, improving the response speed, and reducing the power consumption.

[0302] FIG. 35 shows a schematic diagram of a memory-computing circuit 3500 according to an exemplary embodiment of the present disclosure.

[0303] According to some embodiments, as shown in FIG. 35, the compute-in-memory circuit 3500 includes a memory array 3510 and a plurality of input conversion circuits 3521-352N, where the memory array 3510 includes a plurality of memory cells arranged in a plurality of rows (e.g., M rows as shown in FIG. 35) and a plurality of columns (e.g., N columns as shown in FIG. 35), and the plurality of input conversion circuits 3521-352N are configured to provide input voltages V IN0 ~ V INN to the plurality of memory cells in the memory array 3510, and the memory array 3510 outputs output currents I OUT0 ~ V OUTM。 Similarities between the compute-in-memory circuit 3500 of FIG. 35 and the compute-in-memory circuits 2000, 2600, and 3100 of FIGS. 20, 26, and 31 can not be repeated here, and the differences between them will be mainly described.

[0304] According to some embodiments, the plurality of input conversion circuits includes an input conversion circuit corresponding to each column of the memory array 3510, where each input conversion circuit is configured to: convert an input current corresponding to the input conversion circuit into an input voltage corresponding to the input conversion circuit, and output the input voltage corresponding to the input conversion circuit to a column input of the column corresponding to the input conversion circuit, e.g., for the input conversion circuit 3521 connected to the first column, it receives an input current I IN0 corresponding to the first column, converts the input current I IN0 into an input voltage V IN0 corresponding to the first column, and applies the input voltage V IN0 corresponding to the first column to the column input of the first column, i.e., also to the second terminal of the first transistor of all memory cells in the first column. According to some embodiments, the plurality of input currents input to the plurality of input converters correspond to input signals that are to participate in a computation (e.g., a vector-matrix multiplication computation) to be performed by the compute-in-memory circuit.

[0305] According to some embodiments, the compute-in-memory circuit further includes a digital-to-analog converter for converting a digital format input signal into an analog signal to be input to the plurality of input conversion circuits 3521-352N of the compute-in-memory circuit. According to some embodiments, the compute-in-memory circuit further includes an analog-to-digital converter for converting an analog output signal of the memory array into a digital signal output.

[0306] FIGS. 36A-36B show a schematic diagram of a compute-in-memory circuit 3600 including a programming circuit 3620, according to an example embodiment of the present disclosure. According to some embodiments, the memory array 3610 and the plurality of input conversion circuits 3621-362N in FIGS. 36A-36B can be similar to the memory 3510 and the plurality of input conversion circuits 3521-352N in FIG. 35, respectively, and thus the features and / or effects described above with reference to the memory 3510 and the plurality of input conversion circuits 3521-352N in FIG. 35 can also apply to the memory array 3610 and the plurality of input conversion circuits 3621-362N in FIGS. 36A-36B.

[0307] According to some embodiments, as shown in FIG. 36A, the gate terminal of the second transistor in the memory cells in the same row is connected to the control input corresponding to the row, and the second terminal of the second transistor in the memory cells in the same column is connected to the write input corresponding to the column.

[0308] According to some embodiments, the compute-in-memory circuit 3600 further includes a programming circuit configured to, for each row in the memory array, generate a program control voltage corresponding to the row, and output the program control voltage corresponding to the row to the control input of the row to control turning on or turning off of the second transistor of the memory cells in the row; and for each column in the memory array, generate a program write voltage corresponding to the column, and output the program write voltage corresponding to the column to the write input of the column to control the voltage between the gate terminal of the first transistor of the memory cells in the column and the ground.

[0309] According to embodiments as described in the present disclosure, the write operation control of each memory cell in the memory array can be implemented, and the write processes of each memory cell are prevented from interfering with each other.

[0310] According to some embodiments, as shown in FIG. 36A, the programming circuit includes a first programming portion 3631 for controlling the second terminal of the second transistor of the memory cells in the memory array and a second programming portion 3632 for controlling the gate terminal of the second transistor of the memory cells in the memory array, wherein the first programming portion 3631 is configured to, for each column in the memory array, generate a program write voltage corresponding to the column, and output the program write voltage corresponding to the column to the write input of the column to control the voltage between the gate terminal of the first transistor of the memory cells in the column and the ground, and the second programming portion 3632 is configured to, for each row in the memory array, generate a program control voltage corresponding to the row, and output the program control voltage corresponding to the row to the control input of the row to control turning on or turning off of the second transistor of the memory cells in the row.

[0311] According to some embodiments, the first programming portion 3631 includes a plurality of column programming portions 36311~3631N corresponding to respective columns in the memory array 3610, wherein each column programming portion is configured to generate a program write voltage corresponding to the column of the column programming portion, and output the program write voltage corresponding to the column to a write input terminal of the column, i.e., apply the program write voltage corresponding to the column to the second terminal of the second transistor of all memory cells in the column, for example, the column programming portion 36311 generates a program write voltage corresponding to the first column, and applies the program write voltage corresponding to the first column to the second terminal of the second transistor of the memory cells in the first column.

[0312] According to some embodiments, the second programming portion 3632 includes a plurality of row programming portions 36321~3632M corresponding to respective rows in the memory array 3610, wherein each row programming portion is configured to generate a program control voltage corresponding to the row of the row programming portion, and output the program control voltage corresponding to the row to a control input terminal of the row, i.e., apply the program write voltage corresponding to the row to the gate terminal of the second transistor of all memory cells in the row, for example, the row programming portion 36321 generates a program control voltage corresponding to the first row, and applies the program control voltage corresponding to the first row to the gate terminal of the second transistor of the memory cells in the first row.

[0313] According to some embodiments, as shown in FIG. 36B, the gate terminals of the second transistors in the memory cells in the same column are connected to the control input terminal corresponding to the column, and the second terminals of the second transistors in the memory cells in the same row are connected to the write input terminal corresponding to the row.

[0314] According to some embodiments, the programming circuit is configured to, for each column in the memory array, generate a program control voltage corresponding to the column, and output the program control voltage corresponding to the column to a control input terminal of the column to control turning on or turning off of the second transistors of the memory cells in the column; and for each row in the memory array, generate a program write voltage corresponding to the row, and output the program write voltage corresponding to the row to a write input terminal of the row to control the voltage between the gate terminal of the first transistor of the memory cells in the row and the ground.

[0315] According to embodiments as described in the present disclosure, the write operation control of the respective memory cells in the memory array can be implemented, and the write processes of the respective memory cells are avoided from interfering with each other.

[0316] According to some embodiments, as shown in FIG. 36B, the programming circuit includes a first programming portion 3631 for controlling the gate terminal of the second transistor of the memory cells in the memory array and a second programming portion 3632 for controlling the second terminal of the second transistor of the memory cells in the memory array, wherein the first programming portion 3631 is configured to, for each column in the memory array, generate a program control voltage corresponding to the column and output the program control voltage corresponding to the column to the control input of the column to control the turn-on or turn-off of the second transistor of the memory cells in the column, and the second programming portion 3632 is configured to, for each row in the memory array, generate a program write voltage corresponding to the row and output the program write voltage corresponding to the row to the write input of the row to control the voltage between the gate terminal of the first transistor of the memory cells in the row and the ground.

[0317] According to some embodiments, the first programming portion 3631 includes a plurality of column programming portions 36311-3631N corresponding to respective columns in the memory array 3610, wherein each column programming portion is configured to generate a program control voltage corresponding to the column of the column programming portion and output the program control voltage corresponding to the column to the control input of the column, i.e., apply the program write voltage corresponding to the column to the gate terminal of the second transistor of all the memory cells in the column, for example, the column programming portion 36311 generates a program control voltage corresponding to the first column and applies the program control voltage corresponding to the first column to the gate terminal of the second transistor of the memory cells in the first column.

[0318] According to some embodiments, the second programming portion 3632 includes a plurality of row programming portions 36321-3632M corresponding to respective rows in the memory array 3610, wherein each row programming portion is configured to generate a program write voltage corresponding to the row of the row programming portion and output the program write voltage corresponding to the row to the write input of the row, i.e., apply the program write voltage corresponding to the row to the second terminal of the second transistor of all the memory cells in the row, for example, the row programming portion 36321 generates a program write voltage corresponding to the first row and applies the program write voltage corresponding to the first row to the second terminal of the second transistor of the memory cells in the first row.

[0319] FIG. 37A shows a schematic diagram of a memory and computing circuit 3700 according to an example embodiment of the present disclosure. According to some embodiments, the features and / or effects of the memory 3510 and the plurality of input conversion circuits 3521-352N described above with reference to FIG. 35, and the memory array 3610 and the plurality of input conversion circuits 3621-362N in FIGS. 36A-36B can also be applied to the memory array 3710 and the plurality of input conversion circuits 3721-372N in FIG. 37A. According to some embodiments, as shown in FIG. 37A, each of the input conversion circuits 3721-372N includes an operational amplifier and a third transistor.

[0320] The structure of the input conversion circuit in FIG. 37A will be described below with reference to FIG. 37B, where the input conversion circuit 372i in FIG. 37B can be any one of the plurality of input conversion circuits 3721-372N in FIG. 37A.

[0321] As shown in FIG. 37B, the input conversion circuit 372i includes an operational amplifier 372i1 and a third transistor 372i2, where an output terminal of the operational amplifier 372i1 is connected to a column input terminal corresponding to a column of the input conversion circuit, a non-inverting input terminal of the operational amplifier 372i receives a first reference voltage V ref1 ; the third transistor 372i2, where a first terminal of the third transistor 372i2 is connected to an inverting input terminal of the operational amplifier 372i1, a second terminal of the third transistor 372i2 is connected to the output terminal of the operational amplifier 372i1, and a gate terminal of the third transistor 372i2 receives a second reference voltage V ref2 ; and a current input terminal that receives an input current I INi corresponding to the input conversion circuit and is connected to a connection point of the first terminal of the third transistor 372i2 and the inverting input terminal of the operational amplifier 372i1.

[0322] According to embodiments as described in the present disclosure, by providing an input conversion circuit composed of a transistor and an operational amplifier at the column input terminal of each column in the memory array, the input conversion circuit can form a current mirror circuit with the memory cells in its corresponding column to reduce noise in the circuit to ensure stable operation of the memory array.

[0323] According to some embodiments, the first reference voltage V ref1 may be the same as the second reference voltage V ref2 .

[0324] According to some embodiments, the resistance between the drain and the source of the third transistor 372i2 can be adjusted by the second reference voltage V ref2 , so as to achieve the effect of the current mirror.

[0325] It should be understood that, although FIG. 37A shows that the gate terminal of the second transistor in the memory cell in the same row is connected to the control input corresponding to the row, and the second terminal of the second transistor in the memory cell in the same column is connected to the write input corresponding to the column, it is also possible to be arranged as in FIG. 36B that the gate terminal of the second transistor in the memory cell in the same column is connected to the control input corresponding to the column, and the second terminal of the second transistor in the memory cell in the same row is connected to the write input corresponding to the row.

[0326] According to some embodiments, the plurality of conversion circuits further comprises a plurality of output conversion circuits corresponding to the plurality of rows, wherein each output conversion circuit is configured to convert a current from a row output terminal of a row corresponding to the output conversion circuit into an output voltage corresponding to the row. According to embodiments as described in the present disclosure, by converting the output current of the row output terminal of the memory array into an output voltage respectively, it facilitates further processing of the subsequent results of the computation performed by the memory array.

[0327] FIGS. 38A-38B show a schematic diagram of a compute-in-memory circuit 3800 according to an exemplary embodiment of the present disclosure. According to some embodiments, the features and / or effects of the memory 3510 and the plurality of input conversion circuits 3521-352N described above with reference to FIG. 35, the memory array 3610 and the plurality of input conversion circuits 3621-362N in FIGS. 36A-36B, and the memory array 3710 and the plurality of input conversion circuits 3721-372N in FIG. 37A can also be applied to the memory array 3810 and the plurality of input conversion circuits 3821-382N in FIG. 38A.

[0328] According to some embodiments, as shown in FIG. 38A, for each row in the memory array, the output conversion circuit corresponding to the row converts the row output current of the row (i.e., the sum of the output currents of the first terminals of the first transistors of all the memory cells in the row) into an output voltage corresponding to the row.

[0329] The structure of the output conversion circuit 384i in FIG. 38A will be described below with reference to FIG. 38B, wherein the output conversion circuit 384i in FIG. 38B can be any one of the plurality of output conversion circuits 3841-384M in FIG. 38A.

[0330] According to some embodiments, as shown in FIG. 38B, the output conversion circuit 384i comprises an operational amplifier 384i1, the inverting input terminal of the operational amplifier 384i1 is connected to the row output terminal corresponding to the row of the output conversion circuit, and the non-inverting input terminal of the operational amplifier receives a third reference voltage V ref3; and a resistor 384i2 connected between the inverting input of the operational amplifier 384i1 and the output of the operational amplifier 384i1.

[0331] According to some embodiments, the output voltages of the plurality of output conversion circuits 3841-384M in FIG. 38A can be further output to a next compute-and-store circuit for a subsequent computation (e.g., a next matrix multiplication operation).

[0332] It should be appreciated that while FIG. 38A shows that the gate terminal of the second transistor in a memory cell in the same row is connected to a control input corresponding to the row, and the second terminal of the second transistor in a memory cell in the same column is connected to a write input corresponding to the column, it is also possible to arrange, as in FIG. 36B, that the gate terminal of the second transistor in a memory cell in the same column is connected to a control input corresponding to the column, and the second terminal of the second transistor in a memory cell in the same row is connected to a write input corresponding to the row.

[0333] FIG. 39 shows a flowchart of a method 3900 for controlling a compute-and-store circuit (e.g., the compute-and-store circuits 3500, 3600, 3700, and 3800 described above) as described in the present disclosure, according to an exemplary embodiment of the present disclosure. As shown in FIG. 39, the method 3900 includes:

[0334] Step S3901: for each input conversion circuit, applying an input current corresponding to the input conversion circuit to the input conversion circuit, wherein the input current corresponding to the input conversion circuit is determined based on input data corresponding to a column of the input conversion circuit.

[0335] According to some embodiments, each memory cell further includes a storage capacitor having a first terminal connected to the gate terminal of the first transistor of the memory cell and a second terminal connected to the ground, and the method further includes, for any memory cell in the compute-and-store circuit, adjusting the charge stored by the storage capacitor of any memory cell to adjust the weight stored by any memory cell. According to some embodiments, in each memory cell, there is a parasitic capacitor between the gate terminal of the first transistor and the ground, and the method further includes, for any memory cell in the compute-and-store circuit, adjusting the charge stored by the parasitic capacitor of any memory cell to adjust the weight stored by any memory cell.

[0336] According to some embodiments, the gate terminal of the second transistor in the memory cell in the same row is connected to a control input corresponding to the row, the second terminal of the second transistor in the memory cell in the same column is connected to a write input corresponding to the column, the compute- store circuit further comprises a programming circuit, and the method further comprises: via the programming circuit, for each row in the memory array, generating a program control voltage corresponding to the row, and outputting the program control voltage corresponding to the row to the control input of the row to control turn-on or turn-off of the second transistor of the memory cell in the row; and via the programming circuit, for each column in the memory array, generating a program write voltage corresponding to the column, and outputting the program write voltage corresponding to the column to the write input of the column to control the voltage between the gate terminal of the first transistor of the memory cell in the column and the ground point.

[0337] According to some embodiments, the gate terminal of the second transistor in the memory cell in the same column is connected to a control input corresponding to the column, the second terminal of the second transistor in the memory cell in the same row is connected to a write input corresponding to the row, the compute- store circuit further comprises a programming circuit, and the method further comprises: via the programming circuit, for each column in the memory array, generating a program control voltage corresponding to the column, and outputting the program control voltage corresponding to the column to the control input of the column to control turn-on or turn-off of the second transistor of the memory cell in the column; and via the programming circuit, for each row in the memory array, generating a program write voltage corresponding to the row, and outputting the program write voltage corresponding to the row to the write input of the row to control the voltage between the gate terminal of the first transistor of the memory cell in the row and the ground point.

[0338] According to some embodiments, the input conversion circuit can be a circuit structure as described with reference to FIGS. 37A-37B, and thus can form a current mirror circuit structure when providing the input to the memory cells in the compute-in-memory circuit, thereby reducing noise in the circuit to ensure stable operation of the memory array. According to some embodiments, the input conversion circuit includes an operational amplifier, an output of the operational amplifier is connected to a column input corresponding to a column of the input conversion circuit, a third transistor, a first terminal of the third transistor is connected to an inverting input of the operational amplifier, a second terminal of the third transistor is connected to the output of the operational amplifier, and a current input that receives an input current corresponding to the input conversion circuit and is connected to a connection point of the first terminal of the third transistor and the inverting input of the operational amplifier, and the method further includes applying a first reference voltage to the inverting input of the operational amplifier and applying a second reference voltage to a gate terminal of the third transistor of the plurality of input conversion circuits, and for each output conversion circuit of the plurality of output conversion circuits, outputting a voltage at the output of the operational amplifier of the output conversion circuit to a column input corresponding to a column of the output conversion circuit.

[0339] According to some embodiments, the plurality of conversion circuits further includes a plurality of output conversion circuits corresponding to a plurality of rows, wherein each output conversion circuit is configured to convert a current from a row output corresponding to the output conversion circuit to an output voltage corresponding to the row of the output conversion circuit, and the method further includes, for each output conversion circuit, determining output data corresponding to the row of the output conversion circuit based on the output voltage of the output conversion circuit.

[0340] According to some embodiments, the output conversion circuit includes an operational amplifier, an inverting input of the operational amplifier is connected to a row output corresponding to a row of the output conversion circuit, a non-inverting input of the operational amplifier receives a third reference voltage, and a resistance is connected between the inverting input of the operational amplifier and an output of the operational amplifier, and wherein determining, for each output conversion circuit, output data corresponding to the row of the output conversion circuit based on the output voltage of the output conversion circuit includes, for each output conversion circuit, determining output data corresponding to the row of the output conversion circuit based on a voltage at the output of the operational amplifier of the output conversion circuit.

[0341] FIG. 40 shows a schematic diagram of a chip 4000 according to example embodiments of the present disclosure. According to some embodiments, the chip 4000 includes a compute-in-memory circuit 4001 as described in the present disclosure.

[0342] The memory-computing circuit and the control method thereof and the chip as described in the present disclosure can be used in a terminal such as a computer, a mobile phone, a tablet computer, and the like to perform relevant operations. Other essential components of the memory-computing circuit should be understood by those skilled in the art, and are not described here in detail, nor should they be considered as a limitation on the present disclosure.

[0343] In the above embodiments, the description of different embodiments focuses on different aspects, and the parts not described or recorded in detail in a certain embodiment can refer to the related description of other embodiments. The above different embodiments can be freely combined according to needs. And with the evolution of technology, the elements described in the present disclosure can be replaced by equivalent elements that appear after the present disclosure.

Claims

1. A storage circuit, comprising: a storage unit, the storage unit comprising a first transistor, a second transistor and a capacitor; wherein the first transistor comprises a first terminal, a second terminal and a first driving terminal; the second transistor comprises a third terminal, a fourth terminal and a second driving terminal; the first transistor comprises a first oxide semiconductor structure, a channel is formed in the first oxide semiconductor structure between the first terminal and the second terminal and controlled by the first driving terminal; the first terminal of the first transistor, the second driving terminal of the second transistor and the capacitor are connected; the storage circuit comprises a storage unit group, the storage unit group comprises a plurality of storage units; in the storage units within the storage unit group, the first driving terminal of the first transistor is connected to a first control terminal, and the second terminal of the first transistor is connected to a second control terminal; the first control terminal and the second control terminal are configured to control weight data stored in the storage units within the storage unit group; the third terminal of the second transistor in the plurality of storage units within the storage unit group is respectively connected to a plurality of input terminals, and the fourth terminal of the second transistor in the plurality of storage units within the storage unit group is connected to an output terminal; the storage unit group is configured to receive a plurality of input signals through the plurality of input terminals, convert the plurality of input signals into an output signal based on the weight data stored in the plurality of storage units within the storage unit group, and output the output signal at the output terminal.

2. The storage circuit according to claim 1, wherein, The first oxide semiconductor structure has a band gap greater than or equal to 1.65 eV.

3. The storage circuit according to claim 1 or 2, wherein, The first oxide semiconductor structure comprises an indium gallium zinc oxide structure, a germanium-doped indium germanium oxide structure, or an indium tin oxide structure.

4. The storage circuit according to any one of claims 1 to 3, wherein, The first driving terminal of the first transistor in the plurality of storage units within the storage unit group is connected to the same first control terminal, and the second terminal of the first transistor in the plurality of storage units within the storage unit group is connected to different second control terminals; or The first driving terminal of the first transistor in the plurality of storage units within the storage unit group is connected to different first control terminals, and the second terminal of the first transistor in the plurality of storage units within the storage unit group is connected to the same second control terminal.

5. The storage circuit of claim 4, wherein, The storage circuit comprises a storage unit array, and the storage units in the storage unit group are located in a row in the storage unit array, wherein in the storage unit array: the first driving terminals of the first transistors in the storage units located in the same row are connected in common to the same first control terminal, and the second terminals of the first transistors in the storage units located in the same column are connected in common to the same second control terminal; or the first driving terminals of the first transistors in the storage units located in the same column are connected in common to the same first control terminal, and the second terminals of the first transistors in the storage units located in the same row are connected in common to the same second control terminal. The third terminal of the second transistor in the storage unit in the same column is connected to the same input terminal in the plurality of input terminals, and the third terminal of the second transistor in the storage unit in different columns is connected to different input terminals in the plurality of input terminals; the fourth terminal of the second transistor in the storage unit in the same row is connected to the same output terminal in common.

6. The storage circuit of claim 4, wherein, The storage circuit comprises a storage unit array, and the storage units in the storage unit group are located in a column in the storage unit array, wherein the storage unit array comprises: The first driving terminal of the first transistor in the storage unit in the same row is connected to the same first control terminal in common, and the second terminal of the first transistor in the storage unit in the same column is connected to the same second control terminal in common; or the first driving terminal of the first transistor in the storage unit in the same column is connected to the same first control terminal in common, and the second terminal of the first transistor in the storage unit in the same row is connected to the same second control terminal in common. The third terminal of the second transistor in the storage unit in the same row is connected to the same input terminal in the plurality of input terminals in common, and the third terminal of the second transistor in the storage unit in different rows is connected to different input terminals in the plurality of input terminals; the fourth terminal of the second transistor in the storage unit in the same column is connected to the same output terminal in common.

7. The storage circuit according to any one of claims 1 to 6, wherein, The storage circuit comprises a plurality of storage unit groups, and the plurality of storage unit groups comprise a first storage unit group and a second storage unit group, the first storage unit group comprises a first storage unit, and the second storage unit group comprises a second storage unit; The third terminal of the second transistor in the first storage unit and the third terminal of the second transistor in the second storage unit are connected to the same input line in common or in a common terminal, and the input line is connected to one of the plurality of input terminals.

8. The storage circuit of claim 7, wherein, The plurality of storage unit groups further comprise a third storage unit group and a fourth storage unit group, the third storage unit group comprises a third storage unit, and the fourth storage unit group comprises a fourth storage unit; The third terminal of the second transistor in the third storage unit and the third terminal of the second transistor in the fourth storage unit are connected to the same input line in common or in a common terminal.

9. The storage circuit according to claim 7 or 8, wherein, The first storage unit group comprises a first column of storage units, the second storage unit group comprises a second column of storage units, and the first column of storage units and the second column of storage units are adjacent; or The first storage unit group comprises a first row of storage units, the second storage unit group comprises a second row of storage units, and the first row of storage units and the second row of storage units are adjacent.

10. The storage circuit according to any one of claims 1 to 3, wherein, The storage unit group comprises a first storage unit sub-group and a second storage unit sub-group, the first storage unit sub-group comprises a first storage unit, and the second storage unit sub-group comprises a second storage unit; a third terminal of the second transistor in the first storage unit and a third terminal of the second transistor in the second storage unit are connected to different input terminals in the plurality of input terminals, and a fourth terminal of the second transistor in the first storage unit and a fourth terminal of the second transistor in the second storage unit are connected to the same output terminal in common.

11. The storage circuit of claim 10, wherein, a first driving terminal of the first transistor in the first storage unit and a first driving terminal of the first transistor in the second storage unit are connected to a same first control terminal, and a second terminal of the first transistor in the first storage unit and a second terminal of the first transistor in the second storage unit are connected to different second control terminals; or, a first driving terminal of the first transistor in the first storage unit and a first driving terminal of the first transistor in the second storage unit are connected to different first control terminals, and a second terminal of the first transistor in the first storage unit and a second terminal of the first transistor in the second storage unit are connected to a same second control terminal.

12. The storage circuit of claim 11, wherein, the first storage unit sub-group comprises first column storage units, and the second storage unit sub-group comprises second column storage units; or, the first storage unit sub-group comprises first row storage units, and the second storage unit sub-group comprises second row storage units.

13. The storage circuit of claim 12, wherein, the first column storage units and the second column storage units are adjacent; or, the first row storage units and the second row storage units are adjacent.

14. The storage circuit of any one of claims 1-13, wherein, the first driving terminal of the first transistor comprises a gate; the first terminal of the first transistor comprises a source, and the second terminal of the first transistor comprises a drain; or the first terminal of the first transistor comprises a drain, and the second terminal of the first transistor comprises a source.

15. The storage circuit of any one of claims 1-14, wherein, the second driving terminal of the second transistor comprises a gate; the third terminal of the second transistor comprises a source, and the fourth terminal of the second transistor comprises a drain; or the third terminal of the second transistor comprises a drain, and the fourth terminal of the second transistor comprises a source.

16. The storage circuit of any one of claims 1-15, wherein, the second transistor comprises a second oxide semiconductor structure, and a channel between the third terminal and the fourth terminal of the second transistor is formed in the second oxide semiconductor structure and controlled by the second driving terminal.

17. A memory and computing device, comprising: the memory circuit according to any one of claims 1-16; a control circuit configured to control a working state of the memory circuit.

18. An electronic device, comprising the memory and computing device according to claim 17.

Images