An etching method for the epitaxial structure of a type-2 superlattice semiconductor device

Abstract

The present invention relates to the etching method within the scope of semiconductor device fabrication processes, in particular; relates to an etching method developed for the epitaxial structure (10) of a type-2 InAs / GaSb superlattice semiconductor device, which minimizes the device performance degrading effects encountered after etching, comprising the process steps of etching the InAs / GaSb layers in a plasma environment with selected etching gases, forming an etching zone, cooling and coating the InAs / GaSb layers with plasma polymerization gases to eliminate the negative effects of the exposed bonds on the performance, respectively, with at least three repetitions.

Description

[0001] AN ETCHING METHOD FOR THE EPITAXIAL STRUCTURE OF A TYPE-2 SUPERLATTICE SEMICONDUCTOR DEVICE

[0002] Technical Field

[0003] This invention relates to the etching method within the scope of semiconductor device fabrication processes, in particular; it relates to an etching method developed for the epitaxial structure of a type-2 InAs / GaSb superlattice semiconductor device, which minimizes the effects that reduce the performance of the device encountered after the etching process, which includes the process steps of etching the InAs / GaSb layers in a plasma environment formed with selected etching gases with at least three repetitions, respectively, forming an etching zone, cooling and coating with gases with plasma polymerization properties in order to eliminate the negative effects of the exposed bonds on the surface on the performance.

[0004] State of the Art

[0005] Type-2 InAs / GaSb superlattice semiconductor epitaxial structures have characteristic features such as enabling the band gap to be tuned as desired, absorbing the light incident on the surface due to inter-mini-band transitions, and having a highly uniformity structure, albeit due to the technological sophistication of III-V group-based material growth methods. Due to these properties, the epitaxial structure of type-2 InAs / GaSb superlattice semiconductor is widely used in infrared photo-sensing detector studies that can operate in short wavelength infrared (SWIR; 1-3 pm), medium wavelength infrared (MWIR; 3-6 pm) and long wavelength infrared (LWIR; 6-15 pm) wavelength ranges. Among the factors affecting the dark current mechanisms in type-2 InAs / GaSb superlattice semiconductor devices; factors such as strain between epitaxial layers, wafer defects, impurities formed during growth are factors that depend on the parameters related to epitaxial growth and thus generally cannot be controlled during the fabrication process; factors such as surface morphology, exposed bonds on the surface and oxidation of the surface are among the factors that depend on the methods and conditions applied during the fabrication process and thus can be controlled. Improvement of these fabrication-related factors is of great importance in terms of improving the device performance to be obtained.

[0006] In type-2 InAs / GaSb superlattice semiconductor device fabrication processes, the etching process step is known to have a significant effect on device performance. In this etching process, the surface leakage current effects encountered due to the exposed bonds after etching and the structure of the resulting etching wall (sidewall) play an important role in the device performance; thus, studies to reduce sidewall passivation and leakage current effects continue at full speed today.

[0007] In the US patent document on polarity inversion in type-2 InAs / GaSb superlattice photodiodes with publication number US7692183 B2, which is included in the known state of the art, the type-2 InAs / GaSb superlattice infrared detector obtained by etching by dry etching with a mixture of BCh based etching gases and then immersing in CeHsO? based etching chemical liquids to reduce the roughness of the side walls of the crest formed is described. In said etching process, only etching is performed and there is no additional treatment step. Thus, the bonds exposed on the surface of the device reacting with corrosive gases and chemical liquids remain exposed without being electronically neutralized. This situation adversely affects the performance of the device, and an effective and practical method is presented as a solution to this problem encountered in the technical field related to the invention described in detail below.

[0008] In the invention regarding type-2 superlattice long wavelength infrared detector in the utility model certificate of the People's Republic of China with publication number CN213601879U, which is included in the known state of the art, there are comparisons between dry etching and wet etching as etching method and photoresist and silicon dioxide (SiCh) passivation layer coating as surface passivation. Accordingly, the sample with dry etching and SiCh passivation layer coating shows lower dark current than the sample with wet etching and photoresist passivation layer coating. However, in this method, since the passivation coating is not applied to the sample after the dry etching process without contact with air in the same environment, there is a problem that the bonds exposed on the surface after the etching process bind with oxygen, forming undesired Ga-0 and In-0 bonds. Said bonds exposed on the surface; If SiO2 n layer is coated on the oxide layer consisting of these bonds, it causes a new dark current mechanism to form on the device surface. The dark current mechanism formed in this way is referred to as “interfacial trap charges” in the relevant technical field.

[0009] As a result, there is a need for a new method that will eliminate the problems that reduce the device performance, such as surface roughness on the side wall after etching and leakage current problems due to exposed bonds on the surface, as mentioned above in the known state of the art and provide a solution to the technique. Brief Description of The Invention

[0010] This invention relates to an etching method in semiconductor fabrication processes, and in particular to an etching method developed for the epitaxial structure of a stype-2 InAs / GaSb superlattice semiconductor, which minimizes the device performance degrading effects encountered after the etching process.

[0011] A primary object of the invention is to develop an etching method comprising the process steps of etching and coating, respectively, with at least three repetitions.

[0012] An object of the invention is to develop an etching method for obtaining a smooth wall structure after the etching process step.

[0013] An object of the invention is to provide an etching method that minimizes the leakage current problem after the etching process step.

[0014] Another object of the invention is to develop an etching method comprising a coating process step that eliminates undesirable effects by eliminating the contact of the bonds exposed on the surface with air after the etching process step.

[0015] Another object of the invention is to develop an etching method comprising a coating process step that ensures the smoothness of the wall structure without allowing contact with air after the etching process step.

[0016] Another object of the invention is to provide a practical and reproducible etching method for the epitaxial structure of a type-2 InAs / GaSb superlattice semiconductor.

[0017] In order to realize all the advantages mentioned above, which will be understood from the following detailed description, the present invention is an etching method for the type-2 InAs / GaSb superlattice semiconductor device epitaxial structure, in particular;

[0018] - providing an type-2 InAs / GaSb superlattice semiconductor device epitaxial structure obtained by growth on a substrate, a hard mask coating on the front side of said epitaxial structure by photolithography,

[0019] - loading the mask-coated epitaxial construct on the front side into the reactor, said mask includes the process steps of forming an etching zone on the front face of the coated epitaxial structure by inductively coupled plasma reactive ion etching method starting from the substrate using etching gases, each time towards deeper layers, respectively, applying cooling and coating process steps with at least three repetitions and removing from the reactor. The structural and characteristic features and all the advantages of the invention will be more clearly understood by means of the figures given below and the detailed description given with references to these figures, and therefore the evaluation should be made by taking these figures and detailed description into consideration.

[0020] Brief Description of Figures

[0021] Exemplary embodiments of an etching method developed for the inventive type-2 superlattice semiconductor device epitaxial structure are shown in the accompanying figures, wherein:

[0022] Figure- 1. An example of said epitaxial structure in the preferred embodiment of the invention is a cross-sectional view.

[0023] Figure-2. An exemplary view of the first etching zone in the preferred embodiment of the invention.

[0024] Figure-3. An exemplary view of the first insulating layer coating in the preferred embodiment of the invention.

[0025] Figure-4. An exemplary view of the second etching zone in the preferred embodiment of the invention.

[0026] Figure-5. An exemplary view of the second insulating layer coating in the preferred embodiment of the invention.

[0027] Figure-6. An example view of the third etching zone formed by the inventive method.

[0028] Figure-7. An example view of the side wall coating obtained by the inventive method.

[0029] The parts in the figures are numbered individually and the corresponding terms are given below, epitaxial structure (10) substrate (1) buffer layer (2) n-type contact layer (3) hole barrier layer (4) absorption layer (5) electron barrier layer (6) p-type contact layer (7) p-type cap layer (8) mask (9) first etching zone (11) first insulating layer (12) second etching zone (13) second insulating layer (14) third etching zone (15) side wall coating (16)

[0030] Detailed Description of The Invention

[0031] This invention relates to the etching method in semiconductor fabrication processes, in particular; relates to an etching method developed for the epitaxial structure (10) of a type-2 InAs / GaSb superlattice semiconductor device, which minimizes the device performance degrading effects encountered after the etching process, comprising the process steps of etching InAs / GaSb layers in a plasma environment formed with selected etching gases, forming an etching zone, cooling and coating with plasma polymerization gases in order to eliminate the negative effects of the exposed bonds on the surface on the performance, respectively, with at least three repetitions. The inventive etching method essentially comprises the following process steps;

[0032] - providing an epitaxial structure (10) of a type-2 InAs / GaSb superlattice semiconductor device obtained by growths on a substrate (1),

[0033] - hard mask (9) coating by photolithography on the front side of said epitaxial structure (10),

[0034] - the epitaxial structure (10) coated on the resulting hard mask (9), forming an etching zone on it by inductively coupled plasma reactive ion etching (ICP-RIE), cooling and loading into the reactor for the implementation of the coating process steps, and respectively,

[0035] - the etching gases are used from the substrate (1) through the front face of the epitaxial structure (10) coated on the said mask (9) to form an etching zone to deeper layers each time, cooling the epitaxial structure obtained after each etching process by keeping it in the same vacuum environment by preventing contact with air, coating the cooled structure with polymer material insulating layer on the etched walls along the etching depth without removing it from the reactor,

[0036] - performing the said etching zone formation, cooling, coating process steps with at least three repetitions respectively, and obtaining the side wall coating (16) with the final coating process step, and removing it from the reactor. The Type-2 InAs / GaSb superlattice semiconductor device epitaxial structure (10) of the preferred embodiment of the invention; comprising a GaSb buffer layer (2), an n-type InAs / GaSb contact layer (3), InAs / GaSb / AlSb hole barrier layer (4), InAs / GaSb absorption layer (5), InAs / GaSb electron barrier layer (6), InAs / GaSb p-type contact layer (7), p-type doped GaSb cap layer (8) grown respectively on a substrate (1), and; Figure-1 shows an example cross-sectional view of the epitaxial structure (10) of the said semiconductor device. In the preferred embodiment of the invention, the n-type contact layer (3) doping material is silicon (Si), and beryllium (Be) is used as doping e material in the p-type contact layer (7) and p-type cap layer (8). The epitaxial structure (10) used in the inventive etching method is an infrared photo-sensing detector device epitaxial structure which can operate in short wavelength infrared (1-3 pm), medium wavelength infrared (3-6 pm) and long wavelength infrared (6-15 pm) wavelength ranges; the inventive method is not limited to the said epitaxial structure (10). The etching method described in the invention can be used in any semiconductor device epitaxial structure consisting of layers with different properties and their combinations, where performance losses due to etching during fabrication processes should be prevented.

[0037] In the inventive etching method, after providing the epitaxial structure (10), a hard mask (9) coating process is carried out on the front face of the substrate (1) in this epitaxial structure (10). In the preferred embodiment of the invention, silicon nitrate (SiNx) is used as the mask (9) material, and SiNxor silicon dioxide (SiCh) is used in general embodiments of the invention. In the said mask (9) coating process, SiN hard mask (9) is first coated on the front surface of the said substrate (1) by plasma enhancent chemical vapor deposition (PECVD) method and patterned by photolithography method. The patterned hard mask (9) is etched with sulphur hexafluoride (SFe,), oxygen (O2) and argon (Ar) gases by reactive ion etching method under 0.2 Pa pressure and 250°C temperature conditions. After this etching process, it is necessary to remove the undesired photoresist layer on the structure obtained; for this purpose, the said photoresist layer is cleaned with acetone (CsHeO) and isopropanol alcohol (CsHsO), and the photoresist remaining on the surface is cleaned with oxygen gas (O2) under plasma conditions by reactive ion etching method. In the invention, after the process steps of coating, patterning, etching, and cleaning, the mask (9) coating process is completed, and an exemplary view of the said mask (9) is given in Figure-2.

[0038] In this invention, the epitaxial structure (10), on the front side of which a hard mask (9) is coated, is loaded into the reactor at least three times in a row by the inventive inductively coupled plasma reactive ion etching method to perform the etching zone formation, cooling, and coating process steps respectively.

[0039] In the related art of the invention, it is known that the bonds remaining on the surface after the etching process causes surface leakage currents to occur; and the solution of this problem is of great importance in the related art. This problem is caused by the exposure of the device to air after etching; when the device is removed from the reactor, these bonds in contact with oxygen gas (O2) in the air react and cause the formation of In-0 and Ga-0 compounds on the surface. These compounds cause an increase in surface leakage currents; in order to prevent the formation of these compounds and to minimize surface leakage currents, the present invention prevents the bonds exposed after the etching zone formation process step from coming into contact with air. The method disclosed in the present invention comprises the process step of coating an insulating layer which provides passivation of the etched surface after each etching zone forming process step in order to prevent contact of the said compounds with air. In other words, the most important feature of the present invention is that the etching process, which is commonly carried out in a single step, is carried out in at least three steps, and by coating the etched surface with an insulating layer after each etching zone forming process step, a smooth etching wall is obtained, and leakage current effects caused by exposed bonds on the surface are prevented. With the method provided in the present invention, a side wall coating (16) is obtained with the final insulating layer coating process step performed by applying the etching zone forming, cooling, and coating process steps respectively and with at least three repetitions. The said side wall coating (16) process is a kind of treatment process applied on the etched surface up to the total etching depth, and by means of this coating, the exposed bonds on the surface are neutralized.

[0040] In the invention, at least a three-stage etching method is applied on the front face of the epitaxial structure (10) coated on the mask (9) loaded into the reactor with the help of selected etching gases starting from the substrate (1). Said selected etching gases are; BCh, CI2, CH4, H2 and Ar, and includes all combinations thereof. In the etching method subject to the invention, the process steps of forming the etching zone, cooling, and coating the insulating layer are applied respectively and with at least three repetitions without removing from the vacuum environment. After each etching zone formation process step, it is necessary to cool the environment before proceeding to the coating process step with the insulating layer along the etched surface of the epitaxial structure obtained; for this purpose, the obtained structure is kept for 200-300 s without removing it from the etching environment and the reactor temperature is reduced to the range of 30-50°C. When the environment temperature decreases to the desired value, an insulating layer coating process step is applied to the side wall formed along the etching depth in the said epitaxial structure; for this purpose, the polymer material is coated by inductively coupled plasma reactive ion etching method using CHF3 and Ar gases under 30°C electrode temperature and 5 Pa pressure. In the coating process step of the inventive method, fluorocarbon (CxFy) is used as the said polymer material.

[0041] In the preferred embodiment of the invention, an etching method comprising the process steps of forming an etching zone, cooling, and coating, respectively, applied in three repetitions, is described. Accordingly, after the epitaxial structure (10), on the front side of which a hard mask (9) is coated, is loaded into the reactor, the process step of forming the first etching zone (11) is applied; this process step uses BCh and Ar gases with flow rates of 16.2 cm3 / min and 15.5 cm3 / min, respectively, under conditions of 0.2 Pa reactor pressure, 200°C electrode temperature, 180 s etching time. In the process step of forming the first etching zone (11) in the preferred embodiment of the invention, the etching depth is in the range of 600-800 nm, and an example view of said first etching zone (11) is shown in Figure-2.

[0042] In this invention, in order to minimize surface leakage currents, it is ensured that the exposed bonds are prevented from contacting with air after the process step of forming the first etching zone (11). In other words, in the inventive etching method, there is a first insulating layer (12) coating process step to provide passivation of the etched surface, and the environment temperature should be reduced to the desired level for the said coating to be carried out. Thus, in the invention, there is a cooling process step between each etching zone forming process step and the coating process step. In the said cooling process step, type-2 InAs / GaSb superlattice semiconductor device epitaxial structure (10) is kept in a vacuum environment for 300 seconds without contact with air and cooled down to 30°C, which is the appropriate temperature for coating. In other words, in the cooling process step in the preferred embodiment of the invention, the environment temperature is cooled down to 30°C, and not only in the first but also in each cooling process step, the cooled temperature value is the same.

[0043] In the inventive etching method, after the first cooling process step is completed, the structure obtained after the first cooling process step is not removed from the reactor at all, and the first insulating layer (12) coating process step is performed on the mutually formed side walls of the first etching zone (11). For this purpose, the exposed bonds of the p-type GaSb cap layer (8), p-type contact layer (7) and electron barrier layer (6) are passivated by coating the polymer material using CHF 3 and Ar gases by inductively coupled plasma reactive ion etching method under 30°C electrode temperature and 5 Pa pressure. In the first insulating layer (12) coating process step of the invention, the process time is 150 seconds, and the coating thickness is 20 nm. Fluorocarbon (CxFy) material is used as the said polymer material in the invention. Figure-3 shows an example view of the first insulating layer (12) in the preferred embodiment of the invention.

[0044] In the etching method in the preferred embodiment of the invention, after the first insulating layer (12) coating process step, there is a second etching zone (13) formation process step applied by changing only the environment pressure and temperature without changing the environment in which the obtained structure is located. This process step uses BCh and Ar gases with flow rates of 16.2 cm3 / min and 15.5 cm3 / min, respectively, under conditions of 0.15 Pa reactor pressure, 200°C electrode temperature, 170 s etching time. In the process step of forming the second etching zone (13) in the preferred embodiment of the invention, the etching depth is in the range of 1.8-2 pm, and Figure-4 shows an example view of the said second etching zone (13).

[0045] In the inventive method, there is a second insulating layer (14) coating process step applied to the side walls of the second etching zone (13) without removing the structure obtained after the formation of the second etching zone (13) from the reactor, and the type-2 InAs / GaSb superlattice semiconductor device epitaxial structure (10) obtained before this coating is kept in a vacuum environment for 300 s without contact with air and cooled down to 30°C, which is the appropriate temperature for coating. After this cooling process, the structure obtained is ready for coating, and the exposed bonds of the InAs / GaSb absorption layer (5) for the said second insulating layer (14) are coated with polymer material using CHF 3 and Ar gases by inductively coupled plasma reactive ion etching method under 30°C electrode temperature and 5 Pa pressure. In the coating process step of the second insulating layer (14) of the invention, the process time is 150 s, and the coating thickness is 20 nm. Figure-5 shows an example view of the second insulating layer (14) in the preferred embodiment of the invention.

[0046] In the preferred embodiment of the invention, the etching method is applied in three repetitions, and after the second insulating layer (14) coating process step, there is a third etching zone (15) formation process step. In the third repetition of the method of the invention, only the reactor pressure and temperature are changed without changing the environment, thus preventing the obtained structure from coming into contact with air. In this process step, BCh and Ar gases with flow rates of 16.2 cm3 / min and 15.5 cm3 / min, respectively, are used under the conditions of 0.12 Pa reactor pressure, 200°C electrode temperature and 50 s etching time. In the process step of forming the third etching zone (15) in the preferred embodiment of the invention, the etching depth is in the range of 250-350 nm, and Figure-6 shows an example view of the said third etching zone (15).

[0047] In the inventive method, there is a final coating process step on the side wall formed along the third etching zone (15) without removing the structure obtained after the formation of the third etching zone (15) from the reactor, and the epitaxial structure (10) of a type-2 InAs / GaSb superlattice semiconductor device obtained before this coating is kept in a vacuum environment for 300 s without contact with air and cooled to 30°C, which is the appropriate temperature for coating. After this cooling process, the resulting structure is ready for coating and the side wall covering (16) is obtained together with the third and final coating in the preferred embodiment of the invention. For this purpose, the exposed bonds on the surface of the n-type InAs / GaSb contact layer (3) up to the etched depth are coated with polymer material using CHF3 and Ar gases by inductively coupled plasma reactive ion etching method under 30°C electrode temperature and 5 Pa pressure. In the last insulating layer coating process step of the invention, the process time is 150 s, and the coating thickness is 20 nm. Figure-7 shows an example view of the side wall coating (16) in the preferred embodiment of the invention.

[0048] In the preferred embodiment of the invention, the desired etching depth is achieved with the third etching zone (15) formed in the third repetition, and the side wall coating (16) is obtained by the third insulating layer coating process on both opposite side walls of the said third etching zone (15). The said sidewall coating (16) obtaining process is a kind of treatment process in which the etching surface is coated to the total depth of etching and neutralization of the exposed bonds on the surface is provided by this coating. In this way, a smooth wall is obtained, and surface leakage currents are reduced. Through this etching method consisting of etching zone formation, cooling, and coating process steps respectively, which are applied at least three times without removing from the vacuum environment subject to the present invention, the said effects that adversely affect the device performance are prevented; and an effective and practical solution is provided to the leakage current problem encountered in the relevant technique.

Claims

CLAIMS1. An etching method for the epitaxial structure (10) of a type-2 InAs / GaSb superlattice semiconductor device,, characterized in comprising steps of;- providing an epitaxial structure (10) of a type-2 InAs / GaSb superlattice semiconductor device obtained by growth on a substrate (1), coating a hard mask (9) on front side of the epitaxial structure (10) by photolithography,- loading the epitaxial structure (10) into a reactor with the mask (9) coated on its front side,- using inductively coupled plasma reactive ion etching method on the front side of the epitaxial structure (10) coated on said mask (9) by using etching gases starting from the substrate (1), applying process steps of forming etching zone, cooling, and coating respectively towards deeper layers each time with at least three repetitions; and removing from the reactor.

2. An etching method according to claim 1, characterized in that said epitaxial structure (10) is an infrared photo-sensing detector device epitaxial structure structured to operate in long, medium, and short wavelength infrared wavelength ranges.

3. An etching method according to claim 1, characterized in that n-type contact layer (3) is doped with silicon (Si) material.

4. An etching method according to claim 1, characterized in that p-type contact layer (7) and said p-type cap layer (8) are doped with beryllium (Be) material.

5. An etching method according to claim 1, characterized in that the epitaxial structure obtained after each etching zone forming process in said cooling process step is cooled to a temperature of 30-50°C by maintaining the epitaxial structure in a vacuum environment for 200-300 s without removing it from the etching environment.

6. An etching method according to claim 1, characterized in that a polymer material is coated by inductively coupled plasma reactive ion etching using CHF 3 and Ar gases at an electrode temperature of 30°C and a pressure of 5 Pa along the etched depth after each etching zone forming process with cooling.

7. An etching method according to claim 6, characterized in that said polymer material is fluorocarbon (CxFy).

8. An etching method according to claim 1, characterized in that, after said epitaxial structure (10) is loaded into the reactor, said etching zone forming, cooling, and coating process steps are performed in three repetitions, first, second and third, respectively.

9. An etching method according to claim 8, characterized in that, in the process step of forming said first etching zone (11), the reactor pressure is 0.2 Pa, the electrode temperature is 200°C and the etching time is 180 seconds.

10. An etching method according to claim 9, characterized in that, in the process step of forming said first etching zone (11), the etching depth is in the range of 600-800 nm.

11. An etching method according to claim 8, characterized in that, in the process step of forming said second etching zone (13), the reactor pressure is 0.15 Pa, the electrode temperature is 200°C and the etching time is 170 seconds.

12. An etching method according to claim 11, characterized in that, in the process step of forming said second etching zone (13), the etching depth is in the range of 1.8-2 pm.

13. An etching method according to claim 8, characterized in that, in the process step of forming said third etching zone (15), the reactor pressure is 0.12 Pa, the electrode temperature is 200°C and the etching time is 50 s.

14. An etching method according to claim 13, characterized in that, in the process step of forming said third etching zone (15), the etching depth is in the range of 250-350 nm.

15. An etching method according to claim 1 or 8, characterized in that, in the process step of forming each etching zone, BCh and Ar gases with flow rates of 16.2 cm3 / min and 15.5 cm3 / min, respectively, are used.

16. A method of etching according to claim 1 or 8, characterized in that, said etching gases are BCh, Ch, CPU, Ph or Ar and any combination thereof.

17. An etching method according to claim 1 or 8, characterized in that said cooling process step is carried out in a vacuum environment for 300 s until the temperature decreases to 30°C.

18. An etching method according to claim 1 or 8, characterized in that said coating step comprises coating the side walls formed at each etching depth with a thickness of 20 nm by inductively coupled plasma reactive ion etching, wherein the coating conditions are 30°C electrode temperature, 5 Pa pressure, 150 s coating time using CHF3 and Ar gases.

19. An etching method according to claim 1, characterized in that silicon nitrate (SiNx) material is used for said mask (9).

20. An etching method according to claim 1, characterized in that silicon dioxide (SiCh) material is used for said mask (9).

21. An etching method according to claim 1, characterized in that, in the process step of coating said mask (9), the process steps of coating by plasma enhancent chemical vapor deposition method, patterning by photolithography method, etching and cleaning are applied respectively on the front face of the substrate (1).

22. An etching method according to claim 1 or 21, characterized in that the patterned mask (9) is etched by reactive ion etching with sulphur hexafluoride (SFe), oxygen (O2) and argon (Ar) gases at a pressure of 0.2 Pa and a temperature of 250°C.

23. An etching method according to claim 1 or 21, characterized in that undesired photoresist layer on the etched mask (9) is removed with acetone (CsHeO) and isopropanol alcohol (CsHsO), and the remaining photoresist on the surface is removed by reactive ion etching with oxygen gas (O2) under plasma conditions.

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