Apparatus and method for increasing LLC converter hold-up time

Abstract

A power converter includes a transformer having a pair of secondary windings coupled together via a common node, a hold-up circuit that includes a first controllable switch coupled with the common node. The first controllable switch is controlled into a non-conduction mode during a first portion of a hold-up time condition to prevent current flowing through a first secondary winding of the pair of secondary windings from flowing from the common node through the hold-up circuit. The first controllable switch is also controlled into a conduction mode during a second portion of the hold-up time condition to enable current flowing through the first secondary winding to flow from the common node through the hold-up circuit. No portion of the current flowing through the first secondary winding flows through a second secondary winding of the pair of secondary windings during the control of the first controllable switch into the conduction mode.

Description

INVENTION TITLEAPPARATUS AND METHOD FOR INCREASING LLC CONVERTER HOLD-UP TIMECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present invention claims the benefit to and priority of U.S. Provisional Application No. 63 / 658,949, filed June 12, 2024. The entire disclosure of the above application is incorporated herein by reference.TECHNICAL FIELD

[0002] Aspects of the disclosure relate to output power distribution, and more particularly to increasing a hold-up time in resonant LLC power converters.BACKGROUND

[0003] Resonant LLC converter topology is widely used due to its zero-voltage-switching (ZVS) capability, low-voltage stress, high efficiency performance, and its ability to achieve high power density. However, there is a trade-off between the high efficiency and long holdup time performance in a resonant converter.

[0004] Generally, the hold-up time of a converter is the amount of time (typically in milliseconds) that a power converter can continue to generate output within a specified range after an input power interruption. Efficiency can be increased significantly with, for example, increasing the transformer magnetizing inductance Lm. However, the hold-up time will consequently decrease as well. Alternatively, efficiency may be sacrificed for long hold-up time performance. For example, to get a longer hold up time, a lower Lm may be designed. However, this action will lower efficiency.BRIEF STATEMENT

[0005] In accordance with one aspect of the present disclosure, a power converter includes a transformer that includes a pair of secondary windings serially coupled together via a common node, a hold-up circuit that includes a first controllable switch coupled with the common node, and a controller. The controller controls the first controllable switch into a non-conduction mode during a first portion of a hold-up time condition to prevent current flowing through a first secondary winding of the pair of secondary windings from flowing from the common node through the hold-up circuit. The controller controls the first controllable switch into a conduction mode during a second portion of the hold-up time condition to enable currentflowing through the first secondary winding to flow from the common node through the holdup circuit. No portion of the current flowing through the first secondary winding flows through a second secondary winding of the pair of secondary windings during the control of the first controllable switch into the conduction mode.

[0006] In accordance with another aspect of the present disclosure, a method of controlling a circuit having a transformer and a hold-up circuit, the transformer having a pair of secondary windings serially coupled together via a common node, and the hold-up circuit having a first controllable switch coupled with the common node includes controlling the first controllable switch into a non-conduction mode during a first portion of a hold-up time condition to prevent current flowing through a first secondary winding of the pair of secondary windings from flowing from the common node through the hold-up circuit. The method also includes controlling the first controllable switch into a non-conduction mode during a second portion of the hold-up time condition to enable current flowing through the first secondary winding to flow from the common node through the hold-up circuit. No portion of the current flowing through the first secondary winding flows through a second secondary winding of the pair of secondary windings during the control of the first controllable switch into the conduction mode.

[0007] In accordance with another aspect of the present disclosure, a power converter includes a transformer includes a primary winding and first and second secondary windings serially coupled together via a common node. The power converter also includes a pair of switches serially coupled together and coupled with the primary winding and includes a holdup circuit coupled in parallel with the first and second secondary windings and includes a pair of diodes serially coupled together via a serial node and a first controllable switch coupled between the common node and the serial node. A controller determines a hold-up time condition and generates a hold-up signal waveform. The hold-up signal waveform includes a first portion to control the first controllable switch into a non-conduction mode during a first portion of the hold-up time condition to prevent current flowing through the first secondary winding from flowing from the common node through the hold-up circuit. The hold-up signal waveform also includes a second portion includes a pulse to control the first controllable switch into a conduction mode during a second portion of the hold-up time condition to enable current flowing through the first secondary winding to flow from the common node through the holdup circuit. No portion of the current flowing through the first secondary winding flows throughthe second secondary winding during the control of the first controllable switch into the conduction mode.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings illustrate embodiments presently contemplated for carrying out the invention.

[0009] In the drawings:

[0010] FIG. 1 is a circuit block diagram illustrating a power converter according to an example.

[0011] FIG. 2 illustrates a resonant half-bridge LLC converter according to an example.

[0012] FIG. 3 illustrates timing of gate drives of various switches of the hold-up circuit of the LLC converter of FIG. 2 during a hold-up period according to an example.

[0013] FIGS. 4, 5 and 6 illustrate operation of the rectifying circuit of the LLC converter of FIG. 2 during a hold-up operation period according to an example.

[0014] FIGS. 7, 8 and 9 illustrate operation of the rectifying circuit of the LLC converter of FIG. 2 during a hold-up operation period according to another example.

[0015] FIGS. 10 and 11 illustrate alternative embodiments of rectifying / hold-up circuits for hold-up extension according to examples.

[0016] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure. Note that corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.DETAILED DESCRIPTION

[0017] Examples of the present disclosure will now be described more fully with reference to the accompanying drawings. The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses.

[0018] Example embodiments are provided so that this disclosure will be thorough and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

[0019] Although the disclosure hereof is detailed and exact to enable those skilled in the art to practice the invention, the physical embodiments herein disclosed merely exemplify the invention which may be embodied in other specific structures. While the preferred embodiment has been described, the details may be changed without departing from the invention, which is defined by the claims.

[0020] FIG. 1 illustrates a circuit block diagram of a power converter 100 having a primary side 101 and a secondary side 102. The power converter 100 receives a voltage such as an AC voltage from a voltage source 103 via a voltage input 104 having input terminals 105, 106 and converts the received voltage to a DC voltage for supply to a load 107 via a voltage output 108. An AC-DC converter such as a power factor correction PFC converter 109 converts the input AC voltage to a DC voltage that is output to a bulk capacitor 110 and to a DC-DC converter implemented according to aspects disclosed herein as an LLC converter 1 11. In an example, the PFC converter 109 includes a bridged or a bridgeless PFC circuit (not shown) that boosts the input AC voltage to a higher voltage and supplies the boosted DC voltage to the bulk capacitor 110 and to the LLC converter 111.

[0021] The power converter 100 also includes a control circuit 112 for controlling one or more power switches (not shown) in the power converters 109, 111. As shown in FIG. 1, the control circuit 112 includes a primary side controller 113, a secondary side controller 114, and an isolation component 115 coupled between the primary side controller 113 and the secondaryside controller 114. The isolation component 115 may include, for example, an optocoupler, a transformer, etc. Further, either of the primary side controller 113 or the secondary side controller 114 may be eliminated in favor of control of the LLC converter 11 1 being provided by the remaining controller.

[0022] The primary side controller 113 controls one or more power switches in the AC-DC power converter 109. For example, the primary side controller 113 may generate one or more control signals 116 for controlling the power switches of the AC-DC power converter 109 for correcting a power factor. The control signals 116 may be generated based on a sensed parameter 117 (e.g., an AC input current, an AC input voltage and / or a DC bulk voltage) of the AC-DC power converter 109, the power converter 100, etc. As shown in FIG. 1, the secondary side controller 1 14 controls switches (FIG. 2) in the resonant LLC power converter 1 11. For example, the secondary side controller 114 may generate one or more control signals 118 for controlling one or more power switches (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) and / or one or more synchronous rectifiers (e.g., MOSFETs).

[0023] FIG. 2 illustrates a circuit diagram for the LLC converter 111 of FIG. 1 according to an example. As shown, the LLC converter 111 is a resonant half-bridge LLC series converter. However, other resonant converters are contemplated such as a full-bridge LLC series converter, half- or full-bridge LCC converters, LC converters, and the like. The LLC converter 1 11 includes two power switches 200-201 on a primary side 202 of the LLC converter 111 coupled to a voltage input 203 having a pair of input terminals 204-205, two capacitors 206- 207, a transformer 208, a resonant inductor 209 coupled to a primary side 210 of the transformer 208, and rectifying circuit 211 on a secondary side 212 of the LLC converter 111 coupled to a secondary side 213 of the transformer 208. In one embodiment, the power switches 200-201 are metal-oxide-semiconductor field-effect transistors (MOSFETs); however, other controllable switches such as relays, transistors, and the like may be used. The controllable switches 200-201 are serially coupled together via a common node 214. The capacitors 206- 207, the inductor 209, and a magnetizing inductance (e.g., Lm) of the transformer 208 form the resonant LLC tank. The rectifying circuit 211 is shown as a full- wave rectifier including a pair of controllable switches 215-216 (e.g., synchronous rectifier switches) coupled to a pair of secondary windings Nsl, Ns2 of the transformer 208. The switches 215, 216 have a respective first terminal 217, 218 coupled together at a common node 219. A second terminal 220 of the synchronous rectifier switch 215 is coupled with the secondary winding Ns2 and with a firstterminal 221 of the hold-up circuit 227, while a second terminal 222 of the synchronous rectifier switch 216 is coupled with the secondary winding Nsl and a second terminal 223 of the hold-up circuit 227. The secondary windings Nsl , Ns2 may be formed as separate windings serially coupled together via a common node 224 in one embodiment. In another embodiment, the common node 224 is a center tap on a single secondary winding dividing the single secondary winding into the first secondary winding Nsl and the second secondary winding Ns2. The synchronous rectifier switches 215, 216 may be MOSFETs, transistors, relays, or other controllable switch devices. In other configurations, the rectifying circuit 211 may include diodes in place of the synchronous rectifier switches 215-216.

[0024] As shown in FIG. 2, secondary side controller 114 may be configured to drive the power switches 200-201 through an isolation component 225 using pulse-width modulation (PWM) signals. In one example, the isolation component 225 may be the isolation component 115 illustrated in FIG. 1 or be a part thereof. In other examples, the isolation component 225 may be an additional isolation component for controlling the power switches 200-201. As illustrated, an LLC primary controller 226 (shown in phantom) may be included for controlling the power switches 200-201 on the primary side 202 of the LLC converter 111 in one implementation while the isolation component 225 serves as a communication bridge between the controllers 114, 226.

[0025] A controllable hold-up circuit 227 is coupled with the transformer secondary side windings Nsl , Ns2. The hold-up circuit 227 includes a pair of diodes 228, 229 coupled to each other in series via a serial node 230 coupled with the anodes of the diodes 228, 229 while being coupled in parallel with the serial-coupled transformer secondary side windings Nsl, Ns2. The cathode of the diode 228 is coupled with the second terminal 223 of the hold-up circuit 227 while the cathode of the diode 229 is coupled with the first terminal 221 of the hold-up circuit 227. A controllable switch 231 (e.g., a MOSFET, transistor, or relay, etc.) is coupled to the serial node 230 between the diodes 228, 229 and to the positive output voltage node 232, which is coupled with the common node 224. The secondary side controller 1 14 is coupled to the hold-up circuit 227 and controls the hold-up circuit 227 during a hold-up operation into a conducting state that connects the serial node 230 and the positive output voltage node 232 during one state while disconnecting the serial node 230 from the positive output voltage node 232 in a non-conducting state during another state.

[0026] Referring to FIGS. 1 and 2, during a normal operating condition (e.g., wherein the input power from the voltage source 103 to the voltage input 104 is on or is greater than or equal to a predetermined threshold as may be determined, for example, by comparison of the input voltage or current sensed via a voltage or current sensor 119 to the predetermined threshold), the controller 114 controls the hold-up circuit 227 into its off state by disabling control signals to the hold-up circuit 227 (e.g., such as to a gate of a switching element 231 of the hold-up circuit 227). During the normal operating condition, the power switches 200-201 are alternately turned on and off as are synchronous rectifier switches 215-216 to achieve the high efficiency, low EMI, and high power density benefits of the resonant LLC converter topology. Turning the synchronous rectifier switches 215-216 and any of the other controllable switches disclosed herein into on and off states includes controlling a control input or terminal of the contrllable switch (e.g., a gate terminal of a MOSFET) to cause the switchable device to enter a conduction mode (e.g., the “on” state) or a non-conduction mode (e.g., the “off’ state).

[0027] However, in response to a failure in the voltage source 103 to deliver sufficient voltage to the power converter 100 or in response to any equivalent condition that would prompt the voltage across the bulk capacitor 110 to drop below a predetermined bulk capacitor threshold, the controller 114 is programmed to identify the presence of ahold-up time condition and to subsequently generate control signals (together with LLC primary controller 226 if included) to extend power delivery to the voltage output 108.

[0028] In response to detecting a hold-up time condition, FIG. 3 illustrates a control scheme 300 employable by the secondary side controller 114 to extend delivery of the desired voltage output for a hold-up time period. An output voltage 301 of, for example, 12V as illustrated in FIG. 3, is the target output voltage intended to be maintained and / or output during the hold-up time. The output voltage 301 also corresponds with the output voltage desired during operation of the power converter 100 (FIG. 1) in a normal operating condition outside of the hold-up time condition.

[0029] Control scheme 300 illustrates three sets of gate drive timings 302, 303, 304 used during the hold-up time condition of FIG. 3. Gate drive timing 302 illustrates gate timing pulses 305, 306 of a first PWM signal waveform 307 for controlling the on / off states of the primary side high-side power switch 200 and gate timing pulse 308, 309 of a second PWM signal waveform 10 for controlling the on / off states of the secondary side synchronous rectifierswitch 215. The gate drive timing 302 is used in the presence of a 4-Ve phase of the LLC converter 111 according to an example.

[0030] Gate drive riming 303 illustrates gate timing pulses 311, 312, 313 of a third PWM signal waveform 314 for controlling the on / off states of the primary side low-side power switch 201 and gate timing pulses 315, 316 of a fourth PWM signal waveform 317 for controlling the on / off states of the secondary side synchronous rectifier switch 216. The gate drive timing 303 is used in the presence of a -Ve phase of the LLC converter 1 11 according to an example.

[0031] The third gate drive timing 304 illustrates gate timing pulses 318, 319, 320 of a holdup PWM signal waveform 321 or controlling the on / off states of the hold-up switch 231. The gate drive timing 304 is used in the presence of both the 4-Ve and -Ve phases of the LLC converter 111 according to an example.

[0032] Referring to FIGS. 1-3, the input voltage to the LLC converter 111 during the holdup time condition may be supplied by the energy stored in the bulk capacitor 110 prior to the loss of input voltage. The stored energy allows the LLC converter 111 to continue providing an output voltage for a period of time.

[0033] The control scheme 300 includes PWM control signal waveforms for controlling the on and off states of the power switches 200, 201, the synchronous rectifier switches 215, 216, and the switch 231 of the hold-up circuit 227. In the control scheme 300 illustrated in FIG. 3, the synchronous rectifier switch 216 is maintained in its off or non-conducting mode.

[0034] FIGS. 4-6 illustrate operation of the rectifying circuit 211 during a 4-Ve phase of the control scheme 300 of FIG. 3 according to an example. Referring to FIGS. 3 and 4, gate timing pulses 305, 308 cause the power switch 200 and the synchronous rectifier switch 215 to turn on at the beginning of the 4-Ve phase. FIG. 4 illustrates current flow in the secondary side 212 of the LLC converter 111 in response to pulses 305, 308. As shown, the hold-up circuit 227 is not turned on, and no current flows through the hold-up circuit 227 during this portion of the 4-Ve phase. In addition, since the synchronous rectifier switch 216 is controlled or maintained into its non-conduction mode throughout the 4-Ve phase, no current flows through the secondary winding Nsl during this +V phase shown in FIG. 4 or in any of the other 4-Ve or - Ve phases described in FIGS. 5-9 hereinbelow.

[0035] After gate timing pulse 308 is finished, the synchronous rectifier switch 215 is turned off, and the gate timing pulse 318 of the hold-up PWM signal waveform 321 turns on the holdup switch 231. As shown in FIG. 5, current flows in a circuit through the hold-up switch 231, the diode 229, and the secondary transformer winding Ns2. As a result, the voltage (V2) across the secondary transformer winding Ns2 decreases, and the inductance of transformer 208 decreases so that holdup time is extended. In this portion of the -i-Ve phase, the current flows through the hold-up circuit 227 and the secondary winding Ns2 but not through the secondary winding Nsl .

[0036] After the gate timing pulse 318 is finished, the hold-up switch 231 is turned off, and the current flows as illustrated in FIG. 6. When the hold-up switch 231 is not conducing, the current flows through the secondary winding Ns2, the output capacitor Cl , and the body diode of the synchronous rectifier switch 215. As shown, the hold-up circuit 227 is not turned on, and no current flows through the hold-up circuit 227 during this portion of the 4-Ve phase. With the control of the hold-up circuit 227 as described above, the synchronous rectifier switch 215 suffers little to no voltage stress, and current is delivered to Cl and output Vo. In this manner, circuit efficiency is high. The gate timing pulse 305 is turned off at the end of the -Ve phase, and the power switch 200 accordingly turns off.

[0037] FIGS. 7-9 illustrate operation of the rectifying circuit 211 during a hold-up time control similar to that of FIGS. 4-6 in the presence of a -Ve phase of the control scheme 300 of FIG. 3 according to an example. Referring to FIGS. 3 and 7, gate timing pulses 312, 315 cause the power switch 210 and the synchronous rectifier switch 216 to turn on at the beginning of the -Ve phase. FIG. 7 illustrates current flow in the secondary side 212 of the LLC converter 1 1 1 in response to pulses 312, 315. As shown, the hold-up circuit 227 is not turned on, and no current flows through the hold-up circuit 227 during this portion of the -Ve phase.

[0038] After gate timing pulse 315 is finished, the synchronous rectifier switch 216 is turned off, and the gate timing pulse 319 of the hold-up PWM signal waveform 321 turns on the holdup switch 231. As shown in FIG. 8, current flows in a circuit through the hold-up switch 231, the diode 228, and the secondary transformer winding Nsl. As a result, the voltage (VI) across the secondary transformer winding Nsl decreases, and the inductance of transformer 208 decreases so that holdup time is extended. In this portion of the -Ve phase, the current flows through the hold-up circuit 227 and the secondary winding Ns2 but not through the secondary winding Nsl.

[0039] After the gate timing pulse 319 is finished, the hold-up switch 231 is turned off, and the current flows as illustrated in FIG. 9. When the hold-up switch 231 is not conducing, the current flows through the secondary winding Nsl, the output capacitor Cl, and the body diode of the synchronous rectifier switch 216. As shown, the hold-up circuit 227 is not turned on, and no current flows through the hold-up circuit 227 during this portion of the +Ve phase. The synchronous rectifier switch 216 suffers little to no voltage stress, and current is delivered to Cl and output Vo. In this manner, circuit efficiency is high. The gate timing pulse 312 is turned off at the end of the -Ve phase, and the power switch 201 accordingly turns off.

[0040] Gate timing pulses 306, 309 and 320 operate to engage switches 200, 215, and 231 as described above with respect to the +Ve phase to cause a subsequent 4-Ve phase to happen as described above. Alternating 4-Ve and -Ve phases are controlled while there is sufficient energy stored in the bulk capacitor 110 to produce the desired output voltage 301. Due to the embodiments described herein, the hold-up time condition is extended beyond less-efficient methods known in the art.

[0041] FIG. 10 illustrates a hold-up time extension circuit 1000 according to another example. The hold-up time extension circuit 1000 includes a first series -coupled switch assembly 1001 coupled in parallel across the secondary winding Nsl. Series-coupled switch assembly 1001 includes a A second series -coupled switch assembly 1002 (shown in phantom) may also be coupled in parallel across the secondary winding Ns2 if desired.. Operation of the switch assemblies 1001, 1002 may be accomplished by controlling their respective control terminals 1003, 1004 in a similar manner as that of controlling the hold-up switch 231 as described above in FIGS. 3-9. As an example, gate timing pulses 318, 320 (and other similar 4-Ve phase hold-up gate timing pulses) may be used to control the operating modes of the switches of the switch assembly 1001 via the control terminal 1003 while the gate timing pulse 319 (and other similar -Ve phase hold-up gate timing pulses) may be used to control the operating modes of the switches of the switch assembly 1002 via the control terminal 1004.

[0042] FIG. 11 illustrates an embodiment of the rectifying circuit 211 illustrated in FIG. 2. As shown, the anodes and cathodes of the diodes 228, 229 are reversed as compared with that shown in FIG. 2. Accordingly, the cathodes of the diodes 228, 229 are coupled together via the serial node 230 while the anode of the diode 228 is coupled with the second terminal 223 of the hold-up circuit 227 and the anode of the diode 229 is coupled with the first terminal 221 of the hold-up circuit 227. Operation of the hold-up switch 231 during a hold-up operation mayproduce that shown in FIGS. 7-9 in the presence of a -i-Ve phase of the LLC converter 111 and as that shown in FIGS. 4-6 in the presence of a -Ve phase of the LLC converter 111.

[0043] While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the present disclosure. Additionally, while various embodiments of the present disclosure have been described, it is to be understood that aspects of the present disclosure may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description but is only limited by the scope of the appended claims.

Claims

CLAIMS1. A power converter comprising : a transformer comprising a pair of secondary windings, the pair of secondary windings serially coupled together via a common node; a hold-up circuit comprising a first controllable switch coupled with the common node; a controller to: control the first controllable switch into a non-conduction mode during a first portion of a hold-up time condition to prevent current flowing through a first secondary winding of the pair of secondary windings from flowing from the common node through the hold-up circuit; and control the first controllable switch into a conduction mode during a second portion of the hold-up time condition to enable current flowing through the first secondary winding to flow from the common node through the hold-up circuit; wherein no portion of the current flowing through the first secondary winding flows through a second secondary winding of the pair of secondary windings during the control of the first controllable switch into the conduction mode.

2. The power converter of claim 1 further comprising: a second controllable switch comprising: a first terminal coupled with the first secondary winding and with a first terminal of the hold-up circuit: and a second terminal; a third controllable switch comprising: a first terminal coupled with the second secondary winding and with a second terminal of the hold-up circuit; and a second terminal coupled with the second terminal of the first secondary winding via a common node.

3. The power converter of claim 2, wherein the hold-up circuit further comprises a pair of diodes serially coupled together via a serial node; wherein the first controllable switch is coupled between the common node and the serial node; and wherein the pair of diodes is coupled between the first terminal of the hold-up circuit and the second terminal of the hold-up circuit.

4. The power converter of claim 3, wherein the pair of diodes comprises: a first diode comprising: a cathode coupled with the first terminal of the hold-up circuit; and an anode; and a second diode comprising: a cathode coupled with the second terminal of the hold-up circuit; and an anode coupled with the anode of the first diode.

5. The power converter of claim 3, wherein the pair of diodes comprises: a first diode comprising: an anode coupled with the first terminal of the hold-up circuit: and a cathode; and a second diode comprising: an anode coupled with the second terminal of the hold-up circuit; and a cathode coupled with the cathode of the first diode.

6. The power converter of claim 1 , wherein the controller further: controls the first controllable switch into the non-conduction mode during a third portion of the hold-up time condition to prevent current flowing through the first secondary winding from flowing from the common node through the hold-up circuit; controls the second controllable switch into the conduction mode during the first portion of the hold-up time condition; andcontrols the second controllable switch into the non-conduction mode during the second and third portions of the hold-up time condition; wherein the second portion occurs between the first portion and the third portion of the hold-up time condition.

7. The power converter of claim 6, wherein the controller further controls the third controllable switch into the non-conduction mode during each of the first, second, and third portions of the hold-up time condition.

8. The power converter of claim 6, wherein the controller further controls a fourth controllable switch coupled with a primary winding of the transformer into the conduction mode during each of the first, second, and third portions of the hold-up time condition.

9. The power converter of claim 1 , wherein the pair of secondary windings comprise a single secondary winding having a center tap dividing the single secondary winding into the pair of secondary windings.

10. A method of controlling a circuit having a transformer and a hold-up circuit, the transformer having a pair of secondary windings serially coupled together via a common node, and the hold-up circuit having a first controllable switch coupled with the common node, the method comprising: controlling the first controllable switch into a non-conduction mode during a first portion of a hold-up time condition to prevent current flowing through a first secondary winding of the pair of secondary windings from flowing from the common node through the hold-up circuit; and controlling the first controllable switch into a non-conduction mode during a second portion of the hold-up time condition to enable current flowing through the first secondary winding to flow from the common node through the hold-up circuit: wherein no portion of the current flowing through the first secondary winding flows through a second secondary winding of the pair of secondary windings during the control of the first controllable switch into the conduction mode.

11. The method of claim 10 further comprising: controlling the first controllable switch into the non -conduction mode during a third portion of the hold-up time condition to prevent current flowing through the first secondary winding from flowing from the common node through the hold-up circuit; controlling the second controllable switch into the conduction mode during the first portion of the hold-up time condition; and controlling the second controllable switch into the non-conduction mode during the second and third portions of the hold-up time condition; wherein the second portion occurs between the first portion and the third portion of the hold-up time condition.

12. The method of claim 11 further comprising controlling the third controllable switch into the non-conduction mode during each of the first, second, and third portions of the hold-up time condition.

13. The method of claim 11 further comprising controlling a fourth controllable switch coupled with a primary winding of the transformer into the conduction mode during each of the first, second, and third portions of the hold-up time condition.

14. The method of claim 10 further comprising: comparing an input power with a threshold; and maintaining control of the first controllable switch into the non-conduction mode in response to a voltage or a current of the input power being greater than or equal to the threshold.

15. The method of claim 14 further comprising controlling the first controllable switch into the conduction mode during the second portion of the hold-up time condition in response to the voltage or of the input power being less than the threshold.

16. A power converter comprising :a transformer comprising: a primary winding; first and second secondary windings serially coupled together via a common node; a pair of switches serially coupled together and coupled with the primary w inding; a hold-up circuit coupled in parallel with the first and second secondary windings and comprising: a pair of diodes serially coupled together via a serial node: a first controllable switch coupled between the common node and the serial node; a controller to: determine a hold-up time condition; and generate a hold-up signal waveform comprising: a first portion to control the first controllable switch into a nonconduction mode during a first portion of the hold-up time condition to prevent current flowing through the first secondary winding from flowing from the common node through the hold-up circuit; and a second portion comprising a pulse to control the first controllable switch into a conduction mode during a second portion of the holdup time condition to enable current flowing through the first secondary winding to flow from the common node through the hold-up circuit; wherein no portion of the current flowing through the first secondary winding flows through the second secondary winding during the control of the first controllable switch into the conduction mode.

17. The power converter of claim 16, wherein the common node serially coupling the pair of secondary windings comprises a center tap.

18. The power converter of claim 16 further comprising a resonant inductor serially coupled between the primary winding and the common node.

19. The power converter of claim 16, wherein the pair of diodes comprise: a first diode comprising: a cathode; and an anode; and a second diode comprising: a cathode; and an anode serially coupled with the anode of the first diode; wherein the serially coupled first and second secondary windings are coupled in parallel with the serially coupled first and second diodes via the cathodes of the first and second diodes.

20. The power converter of claim 16, wherein the controller, in determining the hold-up time condition, determines the hold-up time condition by: comparing an input power with a threshold; and determining the hold-up time condition in response to a voltage or a current of the input power being greater than or equal to the threshold.

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