Display substrate and manufacturing method therefor, and display device

Abstract

Disclosed are a display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a base; a planarization layer provided on the base, the planarization layer being provided with at least one first auxiliary hole; an auxiliary electrode located on the side of the planarization layer close to the base, at least part of the auxiliary electrode being exposed by the first auxiliary hole; a light-emitting device layer located on the side of the planarization layer away from the base, the light-emitting device layer comprising a first electrode layer, a light-emitting structure layer, and a second electrode layer sequentially arranged in a direction moving away from the base, and the first electrode layer comprising a plurality of first electrodes spaced apart from each other; and a connection electrode located on the side of the second electrode layer close to the base, the connection electrode comprising a first connection portion located on the side wall of the first auxiliary hole and a second connection portion electrically connected to the auxiliary electrode, wherein the light-emitting structure layer is provided with a first hollow portion corresponding to the first connection portion, and a second electrode is electrically connected to the first connection portion by means of the first hollow portion.

Description

Display substrate and its manufacturing method, display device Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate and its manufacturing method, and a display device. Background Technology

[0002] With the development of Organic Light Emitting Display (OLED) technology, OLED display devices have been widely used. In OLED display devices, the cathode of the light-emitting device is a single, continuous cathode layer. In some products, the cathode layer is electrically connected to an auxiliary electrode to reduce the resistance of the cathode layer. Summary of the Invention

[0003] This disclosure provides a display substrate, a method for manufacturing the same, and a display device.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0005] Substrate;

[0006] A planarization layer is disposed on the substrate, and the planarization layer has at least one first auxiliary hole;

[0007] An auxiliary electrode is located on the side of the planarization layer near the substrate, and at least a portion of the auxiliary electrode is exposed by the first auxiliary hole;

[0008] The light-emitting device layer is located in the planarization layer away from the substrate. The light-emitting device layer includes a first electrode layer, a light-emitting structure layer, and a second electrode layer arranged sequentially in a direction away from the substrate. The first electrode layer includes a plurality of first electrodes spaced apart from each other. The orthographic projection of the plurality of first electrodes on the substrate does not overlap with the orthographic projection of the first auxiliary hole on the substrate.

[0009] A connection electrode is located on the side of the second electrode layer near the substrate. The connection electrode is electrically connected to the second electrode layer. The connection electrode includes: a first connection portion located on the sidewall of the first auxiliary hole, and a second connection portion electrically connected to the auxiliary electrode.

[0010] The light-emitting structure layer has a first hollow portion corresponding to the first connecting portion, and the second electrode is electrically connected to the first connecting portion through the first hollow portion.

[0011] In some embodiments, the second electrode layer includes a first sub-layer and a second sub-layer disposed sequentially along a direction away from the substrate. The first sub-layer has a second cutout portion corresponding to the first cutout portion, and the second sub-layer is electrically connected to the first connection portion through the first cutout portion and the second cutout portion.

[0012] In some embodiments, the connecting electrode is disposed in the same layer as the first electrode.

[0013] In some embodiments, the included angle between the first connecting portion and the second connecting portion is between 110° and 130°.

[0014] In some embodiments, the thickness of the planarization layer is between 2 and 8 micrometers.

[0015] In some embodiments, a first portion of the auxiliary electrode is exposed by the auxiliary aperture, and the orthographic projection of the first portion onto the substrate is within the orthographic projection range of the connecting electrode onto the substrate;

[0016] The first connection portion includes a first conductive layer and a second conductive layer disposed sequentially along a direction away from the substrate, wherein the reactivity of the first conductive layer is less than that of the auxiliary electrode.

[0017] In some embodiments, the display substrate further includes a passivation layer located between the planarization layer and the substrate, and a second auxiliary hole is formed on the passivation layer, wherein the orthographic projections of the second auxiliary hole and the first auxiliary hole on the substrate overlap.

[0018] In this embodiment, at least a portion of the auxiliary electrode is located in the second auxiliary hole; or, the auxiliary electrode is located on the side of the passivation layer closer to the substrate.

[0019] In some embodiments, the orthogonal projection of the surface of the passivation layer away from the substrate onto the substrate lies within the orthogonal projection range of the planarization layer onto the substrate.

[0020] In some embodiments, the display substrate further includes a pixel defining layer located between the first electrode layer and the second electrode layer, and having a plurality of receiving holes and at least one third auxiliary hole, each receiving hole corresponding to a first electrode and exposing at least a portion of the corresponding first electrode; the light-emitting structure layer includes a light-emitting layer located in each of the receiving holes;

[0021] The orthographic projection of the third auxiliary hole on the substrate overlaps with the orthographic projection of the first auxiliary hole on the substrate.

[0022] In some embodiments, the first cutout exposes at least a portion of the sidewall of the third auxiliary hole.

[0023] In some embodiments, the third auxiliary hole has a first opening toward the substrate and a second opening away from the substrate, wherein the orthographic projection of the first opening onto the substrate is within the orthographic projection range of the first auxiliary hole onto the substrate.

[0024] In some embodiments, the cross-section of the third auxiliary hole parallel to the substrate gradually increases in the direction close to the substrate.

[0025] In some embodiments, the connection electrode further includes a third connection portion located on the surface of the planarization layer away from the substrate, and the pixel defining layer covers the surface of the third connection portion away from the substrate;

[0026] The first connecting portion is located between the second connecting portion and the third connecting portion, and the first connecting portion is connected to the second connecting portion and the third connecting portion.

[0027] In some embodiments, the display substrate further includes a driving circuit layer located on the side of the planarization layer near the substrate, and the first electrode is electrically connected to the driving circuit layer through a via on the planarization layer; the vias corresponding to the plurality of first electrodes are arranged in an array;

[0028] The orthographic projection of the first auxiliary hole on the substrate is located between the orthographic projections of two adjacent vias on the substrate in the same row or column.

[0029] In some embodiments, a plurality of the first auxiliary holes are provided between at least two adjacent vias.

[0030] Secondly, this disclosure also provides a display device, which includes the above-described display substrate.

[0031] Thirdly, this disclosure also provides a method for manufacturing a display substrate, comprising:

[0032] An auxiliary electrode and a planarization layer are sequentially formed on a substrate. The planarization layer is located on the side of the auxiliary electrode away from the substrate and has at least one first auxiliary hole.

[0033] A connection electrode and a light-emitting device layer are formed on the side of the planarization layer away from the substrate. The light-emitting device layer includes a first electrode layer, a light-emitting structure layer, and a second electrode layer arranged sequentially in a direction away from the substrate. The first electrode layer includes a plurality of first electrodes spaced apart from each other, and the orthographic projection of the plurality of first electrodes on the substrate does not overlap with the orthographic projection of the first auxiliary hole on the substrate. The connection electrode is located on the side of the second electrode layer close to the substrate and is electrically connected to the second electrode layer. The connection electrode includes a first connection portion located on the sidewall of the first auxiliary hole and a second connection portion located at the bottom of the first auxiliary hole, and the second connection portion is electrically connected to the auxiliary electrode. The light-emitting structure layer has a first cutout portion corresponding to the first connection portion, and the second electrode is electrically connected to the first connection portion through the first cutout portion.

[0034] In some embodiments, the light-emitting structure layer is formed by a vapor deposition process to give the light-emitting structure layer a first hollow portion;

[0035] The steps for forming the second electrode layer include:

[0036] A first sub-layer is formed by a vapor deposition process, so that the first sub-layer has a second hollow portion corresponding to the first hollow portion;

[0037] A continuous second sub-layer is formed by a sputtering process, and the second sub-layer is electrically connected to the first connecting portion through the first cutout portion and the second cutout portion. Attached Figure Description

[0038] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0039] Figure 1 is a schematic diagram of the region division of the display substrate provided in some embodiments.

[0040] Figure 2 is a schematic diagram of the structure of the sub-pixel region provided in some embodiments.

[0041] Figure 3A is a schematic diagram of the connection principle between the second electrode layer and the auxiliary electrode provided in some embodiments.

[0042] Figure 3B is a schematic diagram of the planarization layer, passivation layer and auxiliary electrode in Figure 3A.

[0043] Figure 4 is an enlarged view of region Q in Figure 3A.

[0044] Figure 5A is a plan view of the display substrate provided in the first embodiment of this disclosure.

[0045] Figure 5B is a cross-sectional view along line A-A' in Figure 5A provided in the first embodiment of this disclosure.

[0046] Figure 6 is a cross-sectional view along line B-B' in Figure 5A provided in the first embodiment of this disclosure.

[0047] Figure 7 is a schematic diagram of some of the membrane layers in Figure 6.

[0048] Figure 8 is a schematic diagram of the pixel defining layer, passivation layer, planarization layer and connecting electrode in Figure 7.

[0049] Figure 9 is a plan view of the pixel defining layer and the vias on the planarization layer provided in the first embodiment of this disclosure.

[0050] Figure 10A is a plan view of the display substrate provided in the second embodiment of this disclosure.

[0051] Figure 10B is a cross-sectional view along line D-D' in Figure 10A provided in the second embodiment of this disclosure.

[0052] Figure 11 is a cross-sectional view along line D-D' in Figure 10A provided in the third embodiment of this disclosure.

[0053] Figure 12 is a schematic diagram of the light-emitting structure layer and the second sub-layer in Figure 11.

[0054] Figure 13 is a cross-sectional view along line D-D' in Figure 10A provided in the fourth embodiment of this disclosure.

[0055] Figure 14 is a cross-sectional view along line D-D' in Figure 10A provided in the fifth embodiment of this disclosure.

[0056] Figure 15 is a plan view of the display substrate provided in the sixth embodiment of this disclosure.

[0057] Figure 16 is a cross-sectional view along line C-C' in Figure 15 provided in the sixth embodiment of this disclosure.

[0058] Figures 17A to 17H are schematic diagrams illustrating the manufacturing process of a display substrate provided in one example of this disclosure. Detailed Implementation

[0059] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0061] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] Figure 1 is a schematic diagram of the region division of a display substrate provided in some embodiments. As shown in Figure 1, the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display area AA includes multiple sub-pixel areas P. Figure 2 is a schematic diagram of the structure of a sub-pixel area provided in some embodiments. As shown in Figure 2, the display substrate includes: a substrate SUB, a driving circuit layer 11 disposed on the substrate SUB, a passivation layer PVX, a planarization layer PLN, a pixel delimiting layer PDL, and multiple light-emitting devices 50. The driving circuit layer 11 includes multiple pixel driving circuits, which are used to provide driving signals to the light-emitting devices 50. The pixel driving circuits may include multiple transistors and at least one capacitor. The passivation layer PVX is disposed on the side of the driving circuit layer 11 away from the substrate SUB, and the planarization layer PLN is disposed on the side of the passivation layer PVX away from the substrate SUB. The pixel delimiting layer PDL and the multiple light-emitting devices 50 are disposed on the side of the planarization layer PLN away from the substrate SUB. Each light-emitting device 50 corresponds to one sub-pixel area P. The light-emitting device 50 includes a first electrode 51, a light-emitting layer 53, and a second electrode 52 sequentially disposed along a direction away from the substrate SUB. The first electrode 51 is electrically connected to a corresponding pixel driving circuit through a via V0 penetrating the planarization layer PLN and the passivation layer PVX. The pixel defining layer PDL is located on the side of the layer containing the first electrode 51 away from the substrate SUB and has receiving holes Sp corresponding to the light-emitting devices 50, exposing at least a portion of the corresponding first electrode 51. The second electrodes 52 of multiple light-emitting devices 50 are connected to form a continuous second electrode layer 520.

[0066] In one example, the first electrode 51 is a reflective electrode, and the second electrode layer 520 includes a first sublayer 521 and a second sublayer 522 sequentially disposed along a direction away from the substrate SUB. The first sublayer 521 is made of a metallic material and has a small thickness to achieve a transmissive-reflective effect, thereby forming a microcavity between the first electrode 51 and the second electrode 52. The second sublayer 522 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0067] To reduce the resistance of the second electrode layer 520, an auxiliary electrode 35 is provided on the side of the passivation layer PVX facing the substrate SUB, and the second electrode layer 520 and the auxiliary electrode 35 are electrically connected outside the area where the light-emitting device 50 is located. For example, at position B in FIG1, the second electrode layer 520 and the auxiliary electrode 35 are electrically connected. FIG3A is a schematic diagram of the connection principle between the second electrode layer and the auxiliary electrode provided in some embodiments, FIG3B is a schematic diagram of the planarization layer, passivation layer and auxiliary electrode in FIG3A, and FIG4 is an enlarged view of region Q in FIG3A. As shown in FIG3A to FIG4, the planarization layer PLN has a first auxiliary hole V1, and the passivation layer PVX has a second auxiliary hole V2. The first auxiliary hole V1 and the second auxiliary hole V2 are connected, and the orthogonal projection of either the first auxiliary hole V1 or the second auxiliary hole V2 on the substrate SUB does not overlap with the orthogonal projection of the pixel defining layer on the substrate SUB. A partition structure 20 is provided on the side of the auxiliary electrode 35 away from the substrate SUB. A portion of the orthographic projection of the partition structure 20 onto the substrate SUB lies within the orthographic projection range of the first auxiliary aperture V1 onto the substrate SUB. The partition structure 20 includes a first partition layer 21, a second partition layer 22, and a third partition layer 23 arranged sequentially along the direction away from the substrate SUB. A portion of the first partition layer 21 is located on the side of the planarization layer PLN away from the substrate SUB, and another portion is located in the first auxiliary aperture V1, thereby electrically connecting to the auxiliary electrode 35. The orthographic projections of the first partition layer 21 and the third partition layer 23 onto the substrate SUB both cover the orthographic projection of the second partition layer 22 onto the substrate SUB, and the edges of the orthographic projections of the first partition layer 21 and the third partition layer 23 are spaced apart from the edge of the orthographic projection of the second partition layer 22. During the fabrication of the display substrate, a first sublayer 521 and a light-emitting material layer are formed using a vapor deposition process. Due to the good linearity of the vapor deposition process, the first sublayer 521 and the light-emitting material layer are separated by the partition structure 20 at its edge. The portion of the light-emitting material layer located within a single receiving hole Sp serves as the light-emitting layer 53 of the light-emitting device 50. The second sublayer 522 is formed using a sputtering process. The sputtering process provides good film continuity, allowing for the formation of a continuous second sublayer 522. Furthermore, the second sublayer 522 is electrically connected to the first partition layer 21 at its edge, thereby achieving electrical connection with the auxiliary electrode 35.

[0068] In Figures 3A and 4, the partition structure 20 has a relatively complex structure and manufacturing process, resulting in a low yield.

[0069] To address the aforementioned technical problems, this disclosure provides a display substrate. Figure 5A is a plan view of the display substrate provided in a first embodiment of this disclosure; Figure 5B is a cross-sectional view along line A-A' in Figure 5A provided in the first embodiment of this disclosure; Figure 6 is a cross-sectional view along line B-B' in Figure 5A provided in the first embodiment of this disclosure; Figure 7 is a schematic diagram of some film layers in Figure 6; Figure 8 is a schematic diagram of the pixel defining layer, passivation layer, planarization layer, and connecting electrode in Figure 7; Figure 9 is a plan view of the vias on the pixel defining layer and planarization layer provided in the first embodiment of this disclosure. As shown in Figures 5A to 8, the display substrate includes: a substrate SUB, a planarization layer PLN, an auxiliary electrode 35, a light-emitting device layer, and a connecting electrode 60. The substrate SUB can be a rigid substrate made of materials such as glass, or a flexible substrate made of flexible organic materials such as polyimide (PI). The planarization layer PLN is disposed on the substrate SUB, and the planarization layer PLN has at least one first auxiliary via V1. The auxiliary electrode 35 is located on the side of the planarization layer PLN closest to the substrate SUB, and the orthographic projection of the auxiliary electrode 35 onto the substrate SUB overlaps with that of the first auxiliary hole V1, thus exposing at least a portion of the auxiliary electrode 35 through the first auxiliary hole V1. The light-emitting device layer is located on the side of the planarization layer PLN furthest from the substrate SUB. The light-emitting device layer includes a first electrode layer, a light-emitting structure layer 530, and a second electrode layer 520 sequentially arranged in a direction away from the substrate SUB. The light-emitting device layer can be divided into multiple light-emitting devices 50. The first electrode layer includes first electrodes 51 of the multiple light-emitting devices 50, the light-emitting structure layer 530 includes light-emitting layers 53 of the multiple light-emitting devices 50, and the second electrode layer 520 includes second electrodes 52 of the multiple light-emitting devices 50. The orthographic projections of the multiple first electrodes 51 onto the substrate SUB do not overlap with the orthographic projections of the first auxiliary hole V1 onto the substrate SUB.

[0070] The connecting electrode 60 is located on the side of the second electrode layer 520 near the substrate SUB and is electrically connected to the second electrode layer 520. The connecting electrode 60 includes a first connecting portion 61 and a second connecting portion 62 connected together. The first connecting portion 61 is located on the sidewall of the first auxiliary hole V1, and the second connecting portion 62 is located at the bottom of the first auxiliary hole V1. The second connecting portion 62 is electrically connected to the auxiliary electrode 35. The light-emitting structure layer 530 has a first cutout portion A1 corresponding to the first connecting portion 61. The second electrode 52 is electrically connected to the first connecting portion 61 through the first cutout portion A1, thereby being electrically connected to the auxiliary electrode 35.

[0071] In this embodiment, the partition structure 20 shown in FIG2 is not required. Instead, a first hollow portion A1 is formed on the light-emitting structure layer 530, allowing the second electrode 52 to be electrically connected to the first connecting portion 61 through the first hollow portion A1, thereby achieving electrical connection with the auxiliary electrode 35. In actual production, a first auxiliary hole V1 with a relatively steep sidewall can be formed, and the light-emitting structure layer 530 can be formed using a vapor deposition process. At least a portion of the second electrode 52 and the connecting electrode 60 can be formed using a sputtering process, so that the light-emitting structure layer 530 breaks at the position corresponding to the sidewall of the first auxiliary hole V1 to form the first hollow portion A1, and the second electrode 52 is electrically connected to the connecting electrode 60 through the first hollow portion A1.

[0072] The display substrate in the embodiments of this disclosure will now be described in conjunction with the accompanying drawings.

[0073] As shown in Figure 5B, in some embodiments, a buffer layer BFL is disposed on the substrate SUB to prevent or reduce the diffusion of metal atoms and / or impurities from the substrate SUB into the active layer. The buffer layer BFL may comprise inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0074] As shown in Figure 5B, the driving circuit layer 11 is disposed on the buffer layer BFL. The driving circuit layer 11 includes multiple pixel driving circuits, each including multiple transistors 30 and at least one capacitor 40. Only one transistor 30 and one capacitor 40 are shown in Figure 5B. The active layer 31 of the transistor 30 is disposed on the buffer layer BFL. The active layer 31 includes a channel portion and source connection portions and drain connection portions located on both sides of the channel portion. The source connection portions are connected to the source 33 of the transistor 30, and the drain connection portions are connected to the drain 34 of the transistor 30. Both the source connection portions and the drain connection portions may be doped with impurities (e.g., N-type impurities or P-type impurities) with a higher impurity concentration than the channel portion. The channel portion is directly opposite the gate 32 of the transistor 30. When the voltage signal applied to the gate 32 reaches a certain value, a carrier path is formed in the channel portion, forming a path that turns on the source 33 and drain 34 of the transistor 30.

[0075] As shown in Figures 5B to 8, in some embodiments, a first gate insulating layer GI1 is disposed on the side of the active layer 31 away from the substrate SUB. The material of the first gate insulating layer GI1 may include silicon compounds and metal oxides. For example, the material of the first gate insulating layer GI1 includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. Furthermore, the first gate insulating layer GI1 can be a single layer or multiple layers.

[0076] As shown in Figures 5B to 8, in some embodiments, a first gate electrode layer is disposed on a first gate insulating layer GI1. The first gate electrode layer includes the gate 32 of each transistor 30 and the first electrode plate 41 of the capacitor 40. The material of the first gate electrode layer may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the first gate electrode layer may include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate electrode layer may have a single layer or multiple layers.

[0077] As shown in Figures 5B to 8, in some embodiments, a second gate insulating layer GI2 is disposed on the side of the first gate electrode layer away from the substrate SUB, and the material of the second gate insulating layer GI2 may include, for example, silicon compounds.

[0078] As shown in Figures 5B to 8, in some embodiments, the second gate electrode layer is disposed on the side of the second gate insulating layer GI2 away from the substrate SUB. The second gate electrode layer may include the second electrode plate 42 of the capacitor 40. The material of the second gate electrode layer may be selected from the materials of the first gate electrode layer listed above.

[0079] As shown in Figures 5B to 8, in some embodiments, an interlayer insulating layer (ILD) is disposed on the second gate electrode layer. The material of the interlayer insulating layer (ILD) may include, for example, silicon compounds, metal oxides, etc. Specifically, silicon compounds and metal oxides listed above can be selected, which will not be elaborated here.

[0080] As shown in Figure 5B, a first source-drain conductive layer is disposed on the interlayer insulating layer (ILD). The first source-drain conductive layer may include the source 33 and drain 34 of each transistor 30. The source 33 is electrically connected to the source connection portion, and the drain 34 is electrically connected to the drain connection portion. The first source-drain conductive layer may be a single layer or multiple layers made of metal, such as Mo / Al / Mo, Ti / Al / Ti, or Cu / Mo / Nb.

[0081] In some embodiments, the auxiliary electrode 35 is disposed on the same layer as the source 33 and drain 34 of the transistor 30.

[0082] As shown in Figures 5B to 8, in some embodiments, a passivation layer PVX is disposed on the side of the first source / drain conductive layer away from the substrate SUB. The material of the passivation layer PVX may include silicon compounds, such as silicon oxide, silicon nitride, or silicon oxynitride. A second auxiliary hole V2 is formed on the passivation layer PVX, and an auxiliary electrode 35 is located on the side of the passivation layer PVX closer to the substrate SUB, with a portion of the auxiliary electrode 35 exposed by the second auxiliary hole V2.

[0083] As shown in Figures 5B to 8, in some embodiments, the planarization layer PLN is located on the side of the passivation layer PVX away from the substrate SUB. The surface of the planarization layer PLN away from the substrate SUB is substantially flat. The planarization layer PLN is made of an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, and other resin-based materials.

[0084] The planarization layer PLN has a first auxiliary hole V1 at the position corresponding to the auxiliary electrode 35. In some embodiments, the thickness of the planarization layer PLN is between 2 and 8 micrometers, thereby increasing the probability of breakage of the light-emitting structure layer 530. Preferably, the thickness of the planarization layer PLN is between 4 and 5 micrometers to further increase the probability of breakage of the light-emitting structure layer 530 at the sidewall position of the first auxiliary hole V1. For example, the thickness of the planarization layer PLN is 4 micrometers, or 4.5 micrometers, or 5 micrometers.

[0085] In some embodiments, the orthographic projections of the second auxiliary hole V2 and the first auxiliary hole V1 onto the substrate SUB overlap. The slope angle α of the sidewall of the first auxiliary hole V1 (i.e., the angle between the side of the first auxiliary hole V1 and the surface of the planarization layer PLN facing the substrate SUB) is between 50° and 90°, thereby increasing the probability of breakage of the light-emitting structure layer 530. Preferably, the slope angle α of the sidewall of the first auxiliary hole V1 is between 70° and 80° to further increase the probability of breakage of the light-emitting structure layer 530. For example, the slope angle α of the sidewall of the first auxiliary hole V1 is 70°, or 73°, or 75°, or 78°, or 80°.

[0086] In some embodiments, the orthographic projection of the first auxiliary hole V1 onto the substrate SUB can be rectangular, circular, elliptical, hexagonal, or other irregular shapes. The orthographic projection of the second auxiliary hole V2 onto the substrate SUB can be the same as or substantially the same as the orthographic projection of the first auxiliary hole V1 onto the substrate SUB.

[0087] In some embodiments, the first electrode 51 and the connecting electrode 60 are both located on one side of the planarization layer PLN, and the connecting electrode 60 and the first electrode 51 are disposed in the same layer, thereby simplifying the fabrication process. In the embodiments of this disclosure, "disposed in the same layer" means that the two structures are formed from the same material layer through a patterning process, and therefore they are in the same layer in terms of their stacking relationship; however, this does not mean that the distances between the two structures and the substrate SUB are necessarily the same.

[0088] In some embodiments, as shown in Figures 6 to 8, the connecting electrode 60 includes a first connecting portion 61, a second connecting portion 62, and a third connecting portion 63. The first connecting portion 61 is located on the sidewall of the first auxiliary hole V1 and between the second connecting portion 62 and the third connecting portion 63. The first connecting portion 61 is electrically connected to the second connecting portion 62 and the third connecting portion 63. The second connecting portion 62 is located at the bottom of the first auxiliary hole V1 and is electrically connected to the auxiliary electrode 35. The third connecting portion 63 is located on the side of the planarization layer PLN away from the substrate SUB. The connecting electrode 60 can be formed using a sputtering process, allowing it to be continuously distributed on the sidewall of the first auxiliary hole V1. Accordingly, the angle β between the first connecting portion 61 and the second connecting portion 62 is complementary to the slope angle α of the first auxiliary hole V1. For example, the included angle β between the first connecting portion 61 and the second connecting portion 62 is between 90° and 130°, preferably between 100° and 110°.

[0089] In some embodiments, as shown in Figures 6 to 8, a first portion of the auxiliary electrode 35 is exposed by a first auxiliary hole V1, and the orthographic projection of the first portion onto the substrate SUB lies within the orthographic projection range of the connecting electrode 60 onto the substrate SUB. The second connection portion 62 of the connecting electrode 60 includes a first conductive layer 611, a second conductive layer 612, and a third conductive layer 613 sequentially disposed along a direction away from the substrate SUB. The reactivity of the first conductive layer 611 is less than that of the auxiliary electrode 35, thereby enabling the connecting electrode 60 to protect the auxiliary electrode 35 while electrically connecting the second electrode layer 520 to the auxiliary electrode 35, preventing the auxiliary electrode 35 from being corroded by water and oxygen.

[0090] In some embodiments, the auxiliary electrode 35 may include a stack of Ag / ITO, or a stack of Mo / ITO, or a stack of Al / ITO, or a stack of Cu / ITO, or a stack of Cu / Mo / ITO.

[0091] In some embodiments, the first conductive layer 611 is made of a transparent conductive material such as indium tin oxide (ITO), and the second conductive layer 612 is made of a metal, for example, the second conductive layer 612 is a stack of one or more of Cu metal layers and MoNb alloy layers. The third conductive layer 613 is made of a transparent conductive material such as ITO, thereby protecting the second conductive layer 612.

[0092] In this configuration, the materials of the first connecting portion 61 and the third connecting portion 63 of the connecting electrode 60 are the same as those of the second connecting portion 62. That is, both the first connecting portion 61 and the third connecting portion 63 can include the aforementioned first conductive layer 611, second conductive layer 612, and third conductive layer 613. Furthermore, as described above, the first electrode 51 is disposed in the same layer as the connecting electrode 60. That is, the first electrode 51 can include: a first transparent conductive layer disposed in the same layer as the first conductive layer 611 and made of the same material; a metal layer disposed in the same layer as the second conductive layer 612 and made of the same material; and a second transparent conductive layer disposed in the same layer as the third conductive layer 613 and made of the same material. In this case, the first electrode 51 can serve as a reflective electrode. The second transparent conductive layer, in addition to protecting the metal layer, can also increase the work function of the first electrode 51 and reduce the hole injection barrier.

[0093] In some embodiments, as shown in Figures 6 to 8, the orthogonal projection of the connecting electrode 60 onto the substrate SUB can cover the edge portion of the orthogonal projection of the first auxiliary hole V1 onto the substrate SUB. Of course, in other embodiments, the orthogonal projection of the connecting electrode 60 onto the substrate SUB can completely cover the orthogonal projection of the first auxiliary hole V1 onto the substrate SUB.

[0094] In some embodiments, in FIG6, the orthographic projection of the passivation layer PVX away from the substrate SUB onto the substrate SUB is within the orthographic projection range of the planarization layer PLN onto the substrate SUB. This is beneficial to increase the height difference between the third connection portion 63 and the second connection portion 62 of the connecting electrode 60, thereby facilitating the disconnection of the light-emitting structure layer 530 at the position corresponding to the first connection portion 61.

[0095] In some embodiments, as shown in Figures 5B to 8, the display substrate further includes a pixel defining layer PDL. The pixel defining layer PDL is located on the side of the first electrode layer away from the substrate SUB and has a plurality of receiving holes Sp and at least one third auxiliary hole V3. Each receiving hole Sp corresponds to a first electrode 51 and exposes at least a portion of the corresponding first electrode 51. The orthographic projections of the third auxiliary hole V3 and the first auxiliary hole V1 on the substrate SUB overlap.

[0096] For example, the orthographic projection of the third auxiliary hole V3 onto the substrate SUB can be the same or approximately the same as the orthographic projection of the first auxiliary hole V1 onto the substrate SUB.

[0097] In some embodiments, as shown in FIG8, the cross-section of the third auxiliary hole V3 gradually decreases along the direction close to the substrate SUB. The cross-section of the third auxiliary hole V3 refers to the cross-section of the third auxiliary hole V3 parallel to the substrate SUB.

[0098] It should be noted that in Figures 6 and 7, when the thickness of the pixel defining layer PDL is small and the sidewall slope angle of the third auxiliary hole V3 is small (i.e., the sidewall is relatively gentle), the light-emitting structure layer 530 and the first sub-layer 521 can be attached to the sidewall of the third auxiliary hole V3; when the thickness of the pixel defining layer PDL is large, or the sidewall slope angle of the third auxiliary hole V3 is large (i.e., the sidewall is relatively steep), the light-emitting structure layer 530 and the first sub-layer 521 will both break at the position of the sidewall of the third auxiliary hole V3.

[0099] The light-emitting structure layer 530 includes a light-emitting layer 53 located in each receiving hole Sp. The second electrode layer 520 is located on the side of the pixel defining layer PDL away from the substrate SUB, and includes a first sub-layer 521 and a second sub-layer 522 arranged sequentially in a direction away from the substrate SUB. The first sub-layer 521 forms a second cutout A2 at a position corresponding to the first connection portion 61. The second sub-layer 522 is a continuous film layer and is electrically connected to the first connection portion 61 through the first cutout A1 and the second cutout A2.

[0100] In some embodiments, the first sublayer 521 may be made of a metallic material, which may be an alloy of one or more of Mg, Ag, and Al, such as a MgAg alloy. The second sublayer 522 may be made of a transparent conductive material. When the second electrode 52 uses a metallic first sublayer 521 and a transparent second sublayer 522, the thickness of the first sublayer 521 can be adjusted to give it a semi-transparent and semi-reflective characteristic, thereby forming a microcavity between the second electrode 52 and the first electrode 51.

[0101] The first sublayer 521 can be formed by vapor deposition to prevent contamination of the light-emitting structure layer 530 during its preparation. The second sublayer 522 can be formed by sputtering to ensure that it is a continuous film.

[0102] As described above, the first electrode 51 of the light-emitting device 50 is electrically connected to the driving circuit layer 11 through a via V0 on the planarization layer PLN. In one example, multiple light-emitting devices 50 are arranged in an array, and correspondingly, as shown in Figure 9, the vias V0 corresponding to the multiple first electrodes 51 are arranged in an array. There can be multiple first auxiliary holes V1, and the orthographic projection of each first auxiliary hole V1 on the substrate SUB lies between the orthographic projections of two adjacent vias V0 on the substrate SUB in the same row. Of course, in other examples, the orthographic projection of each first auxiliary hole V1 on the substrate SUB may also lie between the orthographic projections of two adjacent vias V0 on the substrate SUB in the same column. In one example, at most one first auxiliary hole V1 is provided between two adjacent vias V0 in the same row and between two adjacent vias V0 in the same column.

[0103] In some embodiments, the total number of first auxiliary holes V1 on the display substrate can be multiple, and the distribution density of the first auxiliary holes V1 can be set according to actual needs.

[0104] Figure 10A is a plan view of the display substrate provided in the second embodiment of the present disclosure, and Figure 10B is a cross-sectional view along line D-D' in Figure 10A provided in the second embodiment of the present disclosure. The film structure shown in Figure 10B is similar to that in Figure 6. The differences between the two will be described below.

[0105] In Figure 10B, the orthographic projection of the second auxiliary hole V2 on the substrate SUB is located inside the orthographic projection of the first auxiliary hole V1 on the substrate SUB, and the passivation layer PVX overlaps with the orthographic projection of the first connection portion 61 on the substrate SUB. For example, in Figure 10B, the orthographic projection of the connection electrode 60 on the substrate SUB completely covers the orthographic projection of the first auxiliary hole V1 on the substrate SUB, and the second connection portion 62 is electrically connected to the auxiliary electrode 35 through the second auxiliary hole V2.

[0106] The other structures in Figure 10B are the same as those in Figure 6, and will not be described again here.

[0107] Figure 11 is a cross-sectional view along line D-D' in Figure 10A provided in the third embodiment of this disclosure. Figure 12 is a schematic diagram of the light-emitting structure layer and the second sub-layer in Figure 11. The display substrate shown in Figure 11 is similar to that in Figure 10B. The differences between the two will be described below.

[0108] In Figure 11, the third auxiliary hole V3 on the pixel defining layer PDL has a first opening facing the substrate SUB (i.e., the bottom opening of the third auxiliary hole V3) and a second opening away from the substrate SUB (i.e., the top opening of the third auxiliary hole V3). The orthographic projection of the first opening on the substrate SUB is within the orthographic projection range of the first auxiliary hole V1 on the substrate SUB. In addition, the first cutout A1 exposes at least a portion of the sidewall of the third auxiliary hole V3, which is beneficial to increasing the ramp height of the first sub-layer 521 and the light-emitting structure layer 530, thereby facilitating the breakage of the first sub-layer 521 and the light-emitting structure layer 530, and also beneficial to reducing the overall orthographic projection area of ​​the first auxiliary hole V1 and the third auxiliary hole V3 on the substrate SUB, which is beneficial to achieving high resolution.

[0109] For example, the top edge of the inner side surface of the first connecting portion 61 coincides with or substantially coincides with the edge of the first opening of the third auxiliary hole V3. Here, the "inner side surface" of the first connecting portion 61 refers to the surface of the first connecting portion 61 that is away from the sidewall of the first auxiliary hole V1; the "top edge" refers to the edge that is away from the substrate SUB.

[0110] Figure 13 is a cross-sectional view along line D-D' in Figure 10A provided in the fourth embodiment of this disclosure. The display substrate shown in Figure 13 is similar to that in Figure 11. The differences between the two will be described below.

[0111] In Figure 13, the orthographic projection of the passivation layer PVX away from the substrate SUB onto the substrate SUB is within the orthographic projection range of the planarization layer PLN onto the substrate SUB. That is, the surface of the passivation layer PVX away from the substrate SUB is covered by the planarization layer PLN, which helps to increase the height difference between the third connection portion 63 and the second connection portion 62 of the connecting electrode 60, and further helps the light-emitting structure layer 530 to disconnect at the position corresponding to the first connection portion 61.

[0112] In Figure 13, at least a portion of the auxiliary electrode 35 is located in the second auxiliary hole V2. For example, the entire auxiliary electrode 35 can be located in the second auxiliary hole V2. This increases the contact area between the connecting electrode 60 and the auxiliary electrode 35, thus reducing the contact resistance, given that the area of ​​the first auxiliary hole V1 is constant. Furthermore, this structure helps to reduce the size of the third auxiliary hole V3 and the first auxiliary hole V1, thereby facilitating the achievement of high resolution on the display substrate.

[0113] Figure 14 is a cross-sectional view along line D-D' in Figure 10A provided in the fifth embodiment of this disclosure. The display substrate shown in Figure 14 is similar to that in Figure 13. The differences between the two will be described below.

[0114] In Figure 14, the cross-section of the third auxiliary hole V3 of the pixel defining layer PDL gradually increases along the direction close to the substrate SUB, which facilitates the breakage of the light-emitting structure layer 530 and the first sub-layer 521 at the sidewall position of the third auxiliary hole V3 and the position of the first connection 61 when the light-emitting structure layer 530 and the first sub-layer 521 are formed by vapor deposition.

[0115] For example, in FIG14, a portion of the surface of the third connection portion 63 away from the substrate SUB is exposed by the third auxiliary hole V3. In this case, when the second sublayer 522 is sputtered to form, the second sublayer 522 can contact the surface of the third connection portion 63 away from the substrate SUB, thereby improving the connection reliability.

[0116] Figure 15 is a plan view of the display substrate provided in the sixth embodiment of this disclosure, and Figure 16 is a cross-sectional view along line C-C' in Figure 15 provided in the sixth embodiment of this disclosure. Unlike Figure 9, in Figure 15, a plurality of first auxiliary holes V1 are provided between at least two adjacent vias V0 located in the same row. The provision of a plurality of first auxiliary holes V1 between two adjacent vias V0 means that there are multiple orthogonal projections of first auxiliary holes V1 between the orthogonal projections of two adjacent vias V0 onto the substrate SUB. For example, two, three, or four first auxiliary holes V1 are provided between two adjacent vias V0 in the same row.

[0117] Figure 15 illustrates the example of multiple first auxiliary holes V1 being provided between two adjacent vias V0 in the same row. Alternatively, multiple first auxiliary holes V1 can be provided between at least two adjacent vias V0 in the same column.

[0118] At the location of a single first auxiliary hole V1 in Figure 16, the film structure is basically the same as that at the location of a single first auxiliary hole V1 in Figure 13. That is, the structure on each side of the dashed line L is basically the same as the structure in Figure 13. Please refer to the description in Figure 13 for details, which will not be repeated here. Of course, at the location of a single first auxiliary hole V1 in Figure 16, the film structure can also be set with reference to Figure 10B, Figure 11, or Figure 14.

[0119] In Figure 15, the third auxiliary hole V3 and the first auxiliary hole V1 can correspond one-to-one. It should be noted that in other embodiments, when there are multiple first auxiliary holes V1 between two adjacent vias V0, the orthographic projection of the multiple first auxiliary holes V1 on the substrate SUB can overlap with the orthographic projection of the same third auxiliary hole V3 on the substrate SUB.

[0120] It should be noted that the display substrate in the above embodiments may also include an encapsulation layer. The encapsulation layer is located on the side of the light-emitting device layer away from the substrate SUB and is used to encapsulate the light-emitting device layer to prevent moisture and / or oxygen from the external environment from corroding the light-emitting device 50. In some embodiments, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer arranged sequentially along the direction away from the substrate SUB. Both the first and second inorganic encapsulation layers may be made of highly dense inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx). The organic encapsulation layer may be made of a polymer material containing a desiccant or a polymer material that can block moisture. For example, a polymer resin may be used to relieve the stress of the first and second inorganic encapsulation layers, and it may also include a water-absorbing material such as a desiccant to absorb water, oxygen, and other substances that penetrate the interior.

[0121] This disclosure also provides a method for manufacturing a display substrate, including:

[0122] S1. An auxiliary electrode and a planarization layer are sequentially formed on the substrate. The planarization layer is located on the side of the auxiliary electrode away from the substrate and has at least one first auxiliary hole.

[0123] S2. A connecting electrode and a light-emitting device layer are formed on the side of the planarization layer away from the substrate. The light-emitting device layer includes a first electrode layer, a light-emitting structure layer, and a second electrode layer arranged sequentially in a direction away from the substrate. The first electrode layer includes a plurality of first electrodes spaced apart from each other, and the orthographic projection of the plurality of first electrodes on the substrate does not overlap with the orthographic projection of the first auxiliary hole on the substrate. The connecting electrode is located on the side of the second electrode layer close to the substrate and is electrically connected to the second electrode layer. The connecting electrode includes a first connecting portion located on the sidewall of the first auxiliary hole and a second connecting portion located at the bottom of the first auxiliary hole. The second connecting portion is electrically connected to the auxiliary electrode. The light-emitting structure layer has a first cutout portion corresponding to the first connecting portion, and the second electrode is electrically connected to the first connecting portion through the first cutout portion.

[0124] Figures 17A to 17H are schematic diagrams of the manufacturing process of a display substrate provided in an example of this disclosure. The manufacturing method of the display substrate in the embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0125] S11. As shown in Figure 17A, a driving circuit layer 11 is formed on the substrate SUB. The driving circuit layer 11 includes multiple pixel driving circuits and auxiliary electrodes 35. The auxiliary electrodes 35 are disposed on the same layer as the source 33 and drain 34 of the transistors 30 in the pixel driving circuits.

[0126] S12. As shown in Figure 17B, a passivation layer PVX is formed, and a second auxiliary hole V2 is formed in the passivation layer PVX at the position corresponding to the auxiliary electrode 35.

[0127] S13. As shown in Figure 17C, a planarization layer PLN is formed on the side of the passivation layer PVX away from the substrate SUB. The planarization layer PLN has a via V0 at the position corresponding to each pixel driving circuit and a first auxiliary via V1 at the position corresponding to the second auxiliary via V2.

[0128] S14. As shown in Figure 17D, a connecting electrode 60 and a first electrode layer are simultaneously formed on the side of the planarization layer PLN away from the substrate SUB. The first electrode layer includes multiple first electrodes 51, each corresponding to a pixel driving circuit. The first electrodes 51 are electrically connected to the pixel driving circuit through vias V0 on the planarization layer PLN. The connecting electrode 60 includes a first connecting portion 61, a second connecting portion 62, and a third connecting portion 63. The first connecting portion 61 is located on the sidewall of the first auxiliary hole V1, the second connecting portion 62 is located at the bottom of the first auxiliary hole V1 and is electrically connected to the auxiliary electrode 35, and the third connecting portion 63 is located on the surface of the planarization layer PLN away from the substrate SUB.

[0129] In the preparation of the connecting electrode 60 and the first electrode layer, a continuous film layer is first formed by sputtering, and then the connecting electrode 60 and multiple first electrodes 51 are formed by patterning.

[0130] S15. As shown in Figure 17E, a pixel defining layer PDL is formed. The pixel defining layer PDL has multiple receiving holes Sp and a third auxiliary hole V3. The receiving holes Sp correspond one-to-one with the first electrode 51. Each receiving hole Sp exposes at least a portion of the first electrode 51. The orthographic projections of the third auxiliary hole V3 and the first auxiliary hole V1 on the substrate SUB overlap.

[0131] S16. As shown in Figure 17F, a light-emitting structure layer 530 is formed by vapor deposition. The light-emitting structure layer 530 includes a light-emitting layer 53 located in each receiving hole Sp, and a first hollow portion A1 is formed in the light-emitting structure layer 530 at the position corresponding to the sidewall of the first auxiliary hole V1.

[0132] S17. As shown in Figure 17G, a first sub-layer 521 of the second electrode layer 520 is formed by vapor deposition. The first sub-layer 521 forms a second hollow portion A2 at the position of the sidewall corresponding to the first auxiliary hole V1.

[0133] S18. As shown in Figure 17H, a second sub-layer 522 of the second electrode layer 520 is formed by sputtering. The second sub-layer 522 is a continuous film layer and is electrically connected to the first connecting part 61 through the first cutout part A1 and the second cutout part A2.

[0134] This disclosure also provides a display device, including the display substrate described in the above embodiments.

[0135] The display device can include any device or product with display functionality. For example, the display device can be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (such as head-mounted devices, electronic clothing, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smartwatches), television set, etc.

[0136] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising: a substrate; a planarization layer disposed on the substrate, the planarization layer being provided with at least one first auxiliary hole; an auxiliary electrode located on a side of the planarization layer close to the substrate, at least part of the auxiliary electrode being exposed by the first auxiliary hole; a light-emitting device layer located on a side of the planarization layer away from the substrate, the light-emitting device layer comprising a first electrode layer, a light-emitting structure layer and a second electrode layer disposed in sequence in a direction away from the substrate; the first electrode layer comprising a plurality of first electrodes spaced apart from each other, a projection of the plurality of first electrodes on the substrate having no overlap with a projection of the first auxiliary hole on the substrate; a connecting electrode located on a side of the second electrode layer close to the substrate, the connecting electrode being electrically connected to the second electrode layer, the connecting electrode comprising a first connecting portion located on a sidewall of the first auxiliary hole and a second connecting portion electrically connected to the auxiliary electrode; wherein the light-emitting structure layer has a first hollow portion corresponding to the first connecting portion, and the second electrode is electrically connected to the first connecting portion through the first hollow portion. The second electrode layer comprises a first sub-layer and a second sub-layer disposed in sequence in a direction away from the substrate, the first sub-layer has a second hollow portion corresponding to the first hollow portion, and the second sub-layer is electrically connected to the first connecting portion through the first hollow portion and the second hollow portion. The connecting electrode is disposed in the same layer as the first electrode. An included angle between the first connecting portion and the second connecting portion is between 110° and 130°. The thickness of the planarization layer is between 2 and 8 microns. A first part of the auxiliary electrode is exposed by the auxiliary hole, and a projection of the first part on the substrate is located within a projection range of the connecting electrode on the substrate. The first connecting portion comprises a first conductive layer and a second conductive layer disposed in sequence in a direction away from the substrate, and the first conductive layer has a lower reactivity than the auxiliary electrode. 2.The display substrate of claim 1, wherein, The display substrate further comprises a passivation layer located between the planarization layer and the substrate, the passivation layer being provided with a second auxiliary hole, and a projection of the second auxiliary hole on the substrate overlaps with a projection of the first auxiliary hole on the substrate. 3.The display substrate of claim 1, wherein, At least part of the auxiliary electrode is located in the second auxiliary hole, or the auxiliary electrode is located on a side of the passivation layer close to the substrate. 4.The display substrate of claim 1, wherein, A projection of a surface of the passivation layer away from the substrate on the substrate is located within a projection range of the planarization layer on the substrate. 5.The display substrate of claim 1, wherein, The display substrate further comprises a pixel definition layer located between the first electrode layer and the second electrode layer, and provided with a plurality of accommodating holes and at least one third auxiliary hole, each accommodating hole corresponds to one first electrode and exposes at least part of the corresponding first electrode, and the light-emitting structure layer comprises a light-emitting layer located in each accommodating hole. 6.The display substrate according to any one of claims 1-5, wherein, A projection of the third auxiliary hole on the substrate overlaps with a projection of the first auxiliary hole on the substrate. The first hollow portion exposes at least part of a sidewall of the third auxiliary hole. 7.The display substrate according to any one of claims 1-5, wherein, ​ ​ 8.The display substrate of claim 7, wherein, ​ 9.The display substrate according to any one of claims 1 to 5, wherein ​ ​ 10.The display substrate of claim 9, wherein, ​ 11.The display substrate of claim 9, wherein, The third auxiliary hole has a first opening toward the substrate and a second opening away from the substrate, and a projection of the first opening on the substrate is located within a projection range of the third auxiliary hole on the substrate. 12.The display substrate of claim 9, wherein, A cross section of the third auxiliary hole parallel to the substrate gradually increases in a direction close to the substrate. 13.The display substrate of claim 9, wherein, The connection electrode further includes a third connection portion located on a surface of the planarization layer away from the substrate, and the pixel definition layer covers a surface of the third connection portion away from the substrate. The first connection portion is located between the second connection portion and the third connection portion, and the first connection portion is connected with the second connection portion and the third connection portion. 14.The display substrate according to any one of claims 1 to 5, wherein The display substrate further includes a driving circuit layer located on a side of the planarization layer close to the substrate, and the first electrode is electrically connected with the driving circuit layer through a via on the planarization layer; the vias corresponding to the plurality of first electrodes are arranged in an array. The projection of the first auxiliary hole on the substrate is located between projections of two adjacent vias in the same row or the same column on the substrate. 15.The display substrate of claim 14, wherein, A plurality of first auxiliary holes are arranged between at least two adjacent vias.

16. A display device comprising: The display substrate includes any one of claims 1-15.

17. A manufacturing method of a display substrate, comprising: forming an auxiliary electrode and a planarization layer on a substrate in sequence, the planarization layer being located on a side of the auxiliary electrode away from the substrate, and at least one first auxiliary hole being formed in the planarization layer; forming a connection electrode and a light emitting device layer on a side of the planarization layer away from the substrate; the light emitting device layer includes a first electrode layer, a light emitting structure layer and a second electrode layer arranged in sequence away from the substrate; the first electrode layer includes a plurality of first electrodes spaced from each other, and projections of the plurality of first electrodes on the substrate do not overlap with a projection of the first auxiliary hole on the substrate; the connection electrode is located on a side of the second electrode layer close to the substrate and is electrically connected with the second electrode layer, and the connection electrode includes a first connection portion located on a side wall of the first auxiliary hole and a second connection portion located at a bottom of the first auxiliary hole, and the second connection portion is electrically connected with the auxiliary electrode; the light emitting structure layer has a first hollow portion corresponding to the first connection portion, and the second electrode is electrically connected with the first connection portion through the first hollow portion.

18. The method of manufacturing according to claim 17, wherein, The light emitting structure layer is formed by an evaporation process, so that the light emitting structure layer has a first hollow portion; The step of forming the second electrode layer includes: forming a first sub-layer by an evaporation process, so that the first sub-layer has a second hollow portion corresponding to the first hollow portion; forming a continuous second sub-layer by a sputtering process, and the second sub-layer is electrically connected with the first connection portion through the first hollow portion and the second hollow portion.

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