Semiconductor device and method for manufacturing same

Abstract

A semiconductor device (1) is provided with: a substrate (10); an electron transport layer (14) provided above the substrate (10); a first electron supply layer (16) provided above the electron transport layer (14); a p-type gate layer (18) provided above the first electron supply layer (16); a second electron supply layer (20) that is provided above the first electron supply layer (16) so as to cover the upper surface (18a) and the lateral surface (18b) of the p-type gate layer (18); and a gate electrode (30) that is electrically connected to the p-type gate layer (18) through an opening (22) provided in the second electron supply layer (20).

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing the same.

[0002] Nitride semiconductors, typified by GaN, are wide-gap semiconductors characterized by a large breakdown field and a high saturated drift velocity of electrons. For example, the bandgaps of GaN and AlN are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for achieving high output and high breakdown voltage, is currently being actively conducted.

[0003] Patent Document 1 and Non-Patent Document 1 disclose a HEMT (High Electron Mobility Transistor) provided with a gate recess. In the HEMT disclosed in Patent Document 1 and Non-Patent Document 1, a normally-off operation is achieved by adjusting the threshold value using the gate recess.

[0004] Patent No. 6132242

[0005] H. Handa et al., “High-Speed ​​Switching and Current-Collapse-Free Operation by GaN Gate Injection Transistors with Thick GaN Buffer on Bulk GaN Substrates”, IEEE International Electron Devices Meeting (IEDM), Dec. 2016, pp. 256-259

[0006] However, forming the gate recess requires etching of the crystal-grown semiconductor layer, which can easily become contaminated with impurities, resulting in unstable threshold voltages.

[0007] It is also possible to achieve normally-off operation without forming a gate recess by thinning the electron supply layer. However, a thinner electron supply layer reduces the concentration of the generated two-dimensional electron gas (2DEG), which can lead to a problem of increased on-resistance. Furthermore, a thinner electron supply layer can lead to a problem of current collapse.

[0008] Therefore, the present disclosure provides a semiconductor device including a transistor that achieves reduced on-resistance or suppression of current collapse while stabilizing the threshold for normally-off operation, and a method for manufacturing the same.

[0009] A semiconductor device according to one aspect of the present disclosure includes a substrate, an electron transit layer provided above the substrate, a first electron supply layer provided above the electron transit layer, a first p-type semiconductor layer provided above the first electron supply layer, a second electron supply layer provided above the first electron supply layer so as to cover an upper surface and a side surface of the first p-type semiconductor layer, and a gate electrode electrically connected to the first p-type semiconductor layer through an opening provided in the second electron supply layer.

[0010] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the steps of: forming an electron transit layer, a first electron supply layer, and a first p-type semiconductor layer in this order above a substrate by crystal growth; patterning the first p-type semiconductor layer by removing a portion of the first p-type semiconductor layer to form a predetermined shape; forming a second electron supply layer by crystal growth so as to cover the patterned first p-type semiconductor layer and the first electron supply layer; removing a portion of the second electron supply layer to expose at least a portion of an upper surface of the first p-type semiconductor layer; and forming a gate electrode so as to cover the exposed portion of the upper surface of the first p-type semiconductor layer.

[0011] According to the present disclosure, it is possible to provide a semiconductor device including a transistor that achieves reduced on-resistance or suppression of current collapse while stabilizing the threshold for normally-off operation, and a method for manufacturing the same.

[0012] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of a semiconductor device according to a comparative example. FIG. 3 is a diagram for explaining a problem with the semiconductor device according to the comparative example. FIG. 4A is a cross-sectional view for explaining a step included in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4B is a cross-sectional view for explaining a step included in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4C is a cross-sectional view for explaining a step included in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4D is a cross-sectional view for explaining a step included in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. FIG. 7 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. FIG. 8 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. FIG. 9 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment. FIG. 10 is a cross-sectional view of a semiconductor device according to a sixth modification of the first embodiment. FIG. 11A is a cross-sectional view of a semiconductor device according to a seventh modification of the first embodiment. FIG. 11B is a cross-sectional view of a semiconductor device according to an eighth modification of the first embodiment. FIG. 12 is a plan view of a semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to the second embodiment. FIG. 14 is a plan view showing a mounting layout of the semiconductor device according to the second embodiment. FIG. 15 is a plan view of a semiconductor device according to a first modified example of the second embodiment. FIG. 16A is a cross-sectional view of a semiconductor device according to the first modified example of the second embodiment. FIG. 16B is a cross-sectional view of a semiconductor device according to a second modified example of the second embodiment. FIG. 17 is a cross-sectional view of a semiconductor device according to a third modified example of the second embodiment. FIG. 18 is a cross-sectional view of a semiconductor device according to a fourth modified example of the second embodiment. FIG. 19 is a cross-sectional view of a semiconductor device according to a fifth modified example of the second embodiment. FIG. 20 is a cross-sectional view of a semiconductor device according to the third embodiment. FIG. 21 is a cross-sectional view of a semiconductor device according to the fourth embodiment.

[0013] (Summary of the Present Disclosure) A semiconductor device according to a first aspect of the present disclosure includes a substrate, an electron transit layer provided above the substrate, a first electron supply layer provided above the electron transit layer, a first p-type semiconductor layer provided above the first electron supply layer, a second electron supply layer provided above the first electron supply layer so as to cover an upper surface and a side surface of the first p-type semiconductor layer, and a gate electrode electrically connected to the first p-type semiconductor layer through an opening provided in the second electron supply layer.

[0014] As a result, the transistor threshold can be adjusted by the thickness of the first electron supply layer directly below the first p-type semiconductor layer, making it easy to achieve normally-off operation. Furthermore, in areas where the first p-type semiconductor layer is not provided, the second electron supply layer can increase the amount of carriers supplied to the electron transit layer, thereby reducing on-resistance and suppressing current collapse. Thus, the semiconductor device according to this aspect can achieve normally-off operation, reducing on-resistance, and suppressing current collapse without forming a gate recess. Because no gate recess is required, the first electron supply layer and the first p-type semiconductor layer can be formed continuously, preventing impurities such as siloxane from being mixed into the interface between the first p-type semiconductor layer and the first electron supply layer. This stabilizes the threshold.

[0015] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, including a source electrode and a drain electrode provided above the first electron supply layer and electrically connected to the electron transit layer.

[0016] This allows the semiconductor device to include a so-called lateral transistor, which can easily reduce the gate-drain capacitance Cgd and increase the switching speed.

[0017] A semiconductor device according to a third aspect of the present disclosure is the semiconductor device according to the second aspect, wherein the source electrode is provided so as to cover a first recess recessed from the upper surface of the second electron supply layer toward the substrate, and the drain electrode is provided so as to cover a second recess recessed from the upper surface of the second electron supply layer toward the substrate.

[0018] This makes it possible to reduce the contact resistance of each of the source electrode and the drain electrode.

[0019] A semiconductor device according to a fourth aspect of the present disclosure is the semiconductor device according to the third aspect, wherein the first recess and the second recess each penetrate the second electron supply layer and reach the first electron supply layer.

[0020] This makes it possible to reduce the contact resistance of each of the source electrode and the drain electrode.

[0021] A semiconductor device according to a fifth aspect of the present disclosure is a semiconductor device according to the third aspect, wherein the first recess and the second recess respectively penetrate the second electron supply layer and the first electron supply layer to reach the electron transit layer.

[0022] This allows each of the source electrode and the drain electrode to come into contact with the 2DEG generated in the electron supply layer, thereby further reducing the contact resistance of each of the source electrode and the drain electrode.

[0023] A semiconductor device according to a sixth aspect of the present disclosure is the semiconductor device according to any one of the first to fifth aspects, further comprising a spacer layer provided between the electron transit layer and the first electron supply layer, the spacer layer having a band gap larger than both the electron transit layer and the first electron supply layer.

[0024] This makes it possible to suppress alloy scattering in the first electron supply layer, thereby improving the mobility of the 2DEG and reducing the on-resistance.

[0025] A semiconductor device according to a seventh aspect of the present disclosure is a semiconductor device according to any one of the first to sixth aspects, further comprising an insulating film provided between the gate electrode and the second electron supply layer.

[0026] This makes it possible to suppress leakage current flowing through the surface of the second electron supply layer.

[0027] A semiconductor device according to an eighth aspect of the present disclosure is the semiconductor device according to any one of the first to seventh aspects, further comprising a second p-type semiconductor layer provided between the first electron supply layer and the first p-type semiconductor layer, the second p-type semiconductor layer having a band gap smaller than both the first electron supply layer and the first p-type semiconductor layer.

[0028] This allows the first electron supply layer, the second p-type semiconductor layer, and the first p-type semiconductor layer to form a quantum well structure, which improves the light emission efficiency during operation, increases the number of carriers excited by light, and reduces the on-resistance.

[0029] A semiconductor device according to a ninth aspect of the present disclosure is the semiconductor device according to any one of the first to eighth aspects, wherein the first electron supply layer is a nitride semiconductor layer containing at least one of In, Al, and Ga, and the second electron supply layer is a nitride semiconductor layer containing at least one of In, Al, and Ga.

[0030] This allows the first electron supply layer and the second electron supply layer to have the same composition, improving the film quality of the second electron supply layer and improving the electrical characteristics of the transistor.

[0031] A semiconductor device according to a tenth aspect of the present disclosure is the semiconductor device according to any one of the first to eighth aspects, wherein the first electron supply layer is a nitride semiconductor layer containing at least one of In, Al, and Ga, and the second electron supply layer is an oxide layer containing gallium oxide as a main component.

[0032] This allows the 2DEG to be generated near the interface between the second electron supply layer and the first electron supply layer. The generation of two layers of 2DEG creates a multi-channel state, which further reduces the on-resistance.

[0033] A semiconductor device according to an eleventh aspect of the present disclosure is a semiconductor device according to any one of the second to fifth aspects, comprising a plurality of the gate electrodes, the plurality of gate electrodes being arranged between the source electrode and the drain electrode in a planar view of the substrate, and capable of being set to different potentials from each other.

[0034] This allows the direction of current flowing between the source and drain electrodes to be changed, enabling the semiconductor device to be used as a bidirectional device and easily realizing diode operation of the transistor.

[0035] A semiconductor device according to a twelfth aspect of the present disclosure is a semiconductor device according to any one of the second to fifth aspects, further comprising a back electrode provided below the substrate and electrically connected to the source electrode, and the substrate is conductive.

[0036] This allows the conductive substrate to function as a source field plate, thereby reducing the gate-drain capacitance Cgd and increasing the switching speed. Since the capacitance Cgd is the feedback capacitance Crss itself, the semiconductor device according to this embodiment, which has a small feedback capacitance Crss, is useful for hard switching.

[0037] A semiconductor device according to a thirteenth aspect of the present disclosure is a semiconductor device according to any one of the second to fifth aspects, further comprising a back electrode provided below the substrate and electrically connected to the source electrode, and the substrate has insulating properties.

[0038] This allows the drain-source capacitance Cds to be reduced because a back electrode set to the source potential is provided below the insulating substrate. Since the capacitance Cds is a main component of the output capacitance Coss, the semiconductor device according to this embodiment, which has a small output capacitance Coss, is useful for soft switching.

[0039] A semiconductor device according to a fourteenth aspect of the present disclosure is the semiconductor device according to any one of the second to fifth aspects, wherein the semiconductor device can be divided into an active region and an isolation region in a plan view of the substrate, and further includes: a source pad provided in the isolation region so as to cover a third opening extending from the second electron supply layer to at least the substrate; a source wiring provided above the source electrode in the active region and electrically connected to the source pad and the source electrode; a drain pad provided in the isolation region and above the second electron supply layer; a drain wiring provided above the drain electrode in the active region and electrically connected to the drain pad and the drain electrode; and a back surface electrode provided below the substrate, wherein the back surface electrode is electrically connected to the source pad through the third opening.

[0040] This allows the back electrode to be used for heat dissipation, thereby improving the heat dissipation performance of the semiconductor device.

[0041] A semiconductor device according to a fifteenth aspect of the present disclosure is a semiconductor device according to the fourteenth aspect, further comprising an interlayer insulating film provided between the second electron supply layer and the source pad, the source wiring, the drain pad, and the drain wiring.

[0042] This makes it possible to suppress the influence of the source pad, source wiring, drain pad, and drain wiring on the operating portion of the transistor. Also, the interlayer insulating film can be made thicker to flatten the upper surface, and the source pad, source wiring, drain pad, and drain wiring can be formed accurately on a flat surface.

[0043] A semiconductor device according to a sixteenth aspect of the present disclosure is the semiconductor device according to the fourteenth or fifteenth aspect, further comprising a graphene capping layer covering a surface of at least one of the source pad, the drain pad, the source wiring, and the drain wiring.

[0044] This provides a graphene capping layer with high thermal conductivity, further improving the heat dissipation of the semiconductor device.

[0045] A semiconductor device according to a seventeenth aspect of the present disclosure is a semiconductor device according to the sixteenth aspect, wherein at least a portion of each of the source pad, the drain pad, the source wiring, and the drain wiring is made of at least one metal selected from the group consisting of Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these metals.

[0046] This can promote the growth of graphene, improve the film quality of the graphene cap layer, and further improve the heat dissipation properties of the semiconductor device.

[0047] A semiconductor device according to an eighteenth aspect of the present disclosure is a semiconductor device according to the sixteenth aspect, wherein at least a portion of each of the source pad, the drain pad, the source wiring, and the drain wiring has a first metal layer made of Pd, Ag, or Au, and a second metal layer formed on the surface of the first metal layer and made of at least one metal selected from Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these metals.

[0048] This can promote the growth of graphene, improve the film quality of the graphene cap layer, and further improve the heat dissipation properties of the semiconductor device.

[0049] A semiconductor device according to a nineteenth aspect of the present disclosure is a semiconductor device according to any one of the fourteenth to eighteenth aspects, further comprising a protective film containing a polymer material provided above the source wiring and the drain wiring.

[0050] By using a polymer material that is excellent in at least one of heat resistance, insulating properties, and water resistance, the quality of semiconductor devices can be improved.

[0051] A semiconductor device according to a twentieth aspect of the present disclosure is the semiconductor device according to the first aspect, further comprising: an n-type semiconductor layer provided above the substrate; a third p-type semiconductor layer provided above the n-type semiconductor layer; a source electrode provided above the first electron supply layer and electrically connected to the electron transit layer; and a drain electrode provided below the substrate, wherein the electron transit layer, the first electron supply layer, and the second electron supply layer are provided so as to cover an inner surface of a fourth opening that penetrates the third p-type semiconductor layer and reaches the n-type semiconductor layer, and an upper side of the third p-type semiconductor layer, and the gate electrode and the first p-type semiconductor layer are provided at positions overlapping an upper surface of the third p-type semiconductor layer in a plan view of the substrate.

[0052] This semiconductor device includes a so-called vertical transistor, which can easily achieve a large current and a high breakdown voltage.

[0053] A method for manufacturing a semiconductor device according to a twenty-first aspect of the present disclosure includes the steps of: forming an electron transit layer, a first electron supply layer, and a first p-type semiconductor layer in this order above a substrate by crystal growth; patterning the first p-type semiconductor layer by removing a portion of the first p-type semiconductor layer to form a predetermined shape; forming a second electron supply layer by crystal growth so as to cover the patterned first p-type semiconductor layer and the first electron supply layer; removing a portion of the second electron supply layer to expose at least a portion of an upper surface of the first p-type semiconductor layer; and forming a gate electrode so as to cover the exposed portion of the upper surface of the first p-type semiconductor layer.

[0054] This makes it possible to prevent impurities such as siloxane from being mixed into the interface between the first p-type semiconductor layer and the first electron supply layer. Furthermore, the second electron supply layer can reduce on-resistance or suppress current collapse. Therefore, it is possible to manufacture a semiconductor device including a transistor with a stabilized threshold voltage for normally-off operation while reducing on-resistance or suppressing current collapse.

[0055] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0056] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0057] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0058] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangular or trapezoidal, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0059] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction." A "vertical" semiconductor device refers to a device in which the main path of current, such as drain current or forward current, is vertical, i.e., a device in which the main current passes vertically through the substrate. A "lateral" semiconductor device refers to a device in which the main path of current, such as drain current or forward current, is horizontal, i.e., a device in which the main current does not pass through the substrate.

[0060] Furthermore, the side on which the heterostructure is provided with respect to the substrate is considered to be "upper" or "upper side," and the opposite side is considered to be "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged closely together and the two components are in contact with each other.

[0061] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the semiconductor device, that is, a view of the main surface of the substrate from the front.

[0062] In addition, in this specification, "A and B overlap in a plan view" means that at least a part of A overlaps with at least a part of B. In other words, this includes cases where only a part of A overlaps with only a part of B, where all of A overlaps with B, where all of B overlaps with A, and where A and B completely overlap with each other.

[0063] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘHereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN, where x, 1-xy, and y represent the composition ratios of Al, Ga, and In, respectively.

[0064] Furthermore, n-type and p-type indicate the conductivity types of semiconductors, and are conductivity types of opposite polarity. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor. － The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., a so-called lightly doped state. ＋ Type and n － Both types are examples of n-type, and may be referred to as n-type without distinction. ＋ Type and p － The same is true for types.

[0065] Furthermore, "A contains B as a main component" means that B has the highest composition ratio among the elements constituting A. Furthermore, a layer made of material X such as GaN or AlGaN, and a layer constituted by material X, mean that the layer contains substantially only material X. However, the layer may contain other elements as impurities, such as elements that are unavoidable in manufacturing, at a rate of 1 at % or less.

[0066] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0067] First Embodiment [Configuration] First, the configuration of a semiconductor device according to a first embodiment will be described with reference to FIG.

[0068] Fig. 1 is a cross-sectional view of a semiconductor device 1 according to this embodiment. In Fig. 1, each component of the semiconductor device 1, such as a semiconductor layer, an insulating layer, and an electrode, is shaded with diagonal lines to indicate a cross section. Note that the shaded cross section of the electron transit layer 14 is omitted. The same applies to the other cross-sectional views from Fig. 2 onwards.

[0069] The semiconductor device 1 shown in FIG. 1 is a normally-off lateral field effect transistor (FET). That is, the threshold voltage of the semiconductor device 1 is greater than 0 V. In the semiconductor device 1, for example, the source electrode 32 is grounded, and a positive potential is applied to the drain electrode 34. When a potential below the threshold voltage, such as 0 V or a negative potential, is applied to the gate electrode 30, the semiconductor device 1 is in a non-conductive state, i.e., off, and no current flows between the source electrode 32 and the drain electrode 34. When a positive potential exceeding the threshold voltage is applied to the gate electrode 30, the semiconductor device 1 is in a conductive state, i.e., on, and a current flows from the drain electrode 34 to the source electrode 32. The current flowing from the drain electrode 34 to the source electrode 32 when the device is on is also called a drain current. The drain current flows in a direction parallel to the main surface of the substrate 10, i.e., laterally.

[0070] The semiconductor device 1 according to this embodiment is a nitride semiconductor device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component. Specifically, the buffer layer 12, the electron transit layer 14, the first electron supply layer 16, the p-type gate layer 18, and the second electron supply layer 20 each contain a nitride semiconductor as a main component.

[0071] The semiconductor device 1 is a device having an AlGaN / GaN heterostructure. Due to spontaneous polarization and piezoelectric polarization occurring on the (0001) plane of GaN, a high concentration of 2DEG (2 Dimensional Electron Gas) 17 is generated near the heterointerface. Therefore, even in an undoped state, a 1×10 １３ cm －２ The semiconductor device 1 is a HEMT including a 2DEG 17 as a channel.

[0072] As shown in FIG. 1, the semiconductor device 1 includes a substrate 10, a buffer layer 12, an electron transit layer 14, a first electron supply layer 16, a p-type gate layer 18, a second electron supply layer 20, a gate electrode 30, a source electrode 32, and a drain electrode 34.

[0073] The substrate 10 is a substrate made of a nitride semiconductor such as GaN. The planar shape of the substrate 10 is, for example, rectangular, but is not limited thereto. The substrate 10 may be a semiconductor substrate such as a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate, or may be an insulating substrate such as sapphire or diamond. Alternatively, the substrate 10 may be a semiconductor substrate that is conductive due to the addition of n-type impurities, or may be a conductive substrate such as a graphite substrate containing graphene.

[0074] The buffer layer 12 is a nitride semiconductor layer provided above the substrate 10. Specifically, the buffer layer 12 is provided in contact with the upper surface of the substrate 10. The buffer layer 12 has a stacked structure of multiple semiconductor layers made of Group III nitride semiconductors such as AlN, AlGaN, and GaN. The buffer layer 12 is provided to reduce the lattice constant between the electron transit layer 14 provided above it and the substrate 10, thereby improving the film quality of the electron transit layer 14. The buffer layer 12 does not necessarily have to be provided.

[0075] The electron transit layer 14 is a nitride semiconductor layer provided above the substrate 10. Specifically, the electron transit layer 14 is provided in contact with the upper surface of the buffer layer 12. The electron transit layer 14 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the electron transit layer 14 is a layer made of undoped GaN. A portion of the electron transit layer 14 may be made n-type by adding an impurity such as Si. The thickness of the electron transit layer 14 is, for example, 150 nm, but is not particularly limited.

[0076] The electron transit layer 14 is a layer including a channel of the semiconductor device 1, and is a channel layer through which a drain current flows when the semiconductor device 1 is turned on. Specifically, a 2DEG 17 is generated in the electron transit layer 14 near the interface with the first electron supply layer 16. The 2DEG 17 extends parallel to the main surface of the substrate 10 along the interface between the electron transit layer 14 and the first electron supply layer 16.

[0077] The first electron supply layer 16 is a nitride semiconductor layer provided above the electron transit layer 14. Specifically, the first electron supply layer 16 is provided in contact with the upper surface of the electron transit layer 14. The first electron supply layer 16 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the first electron supply layer 16 is a layer made of undoped AlGaN. The first electron supply layer 16 has a larger band gap than the electron transit layer 14. Therefore, an AlGaN / GaN heterointerface is formed between the first electron supply layer 16 and the electron transit layer 14. The first electron supply layer 16 supplies electrons to a channel region (i.e., 2DEG 17) formed in the electron transit layer 14.

[0078] The thickness of the first electron supply layer 16 is, for example, but not limited to, 15 nm to 25 nm. The thickness of the first electron supply layer 16 is substantially uniform. That is, no gate recess is provided on the upper surface of the first electron supply layer 16.

[0079] The p-type gate layer 18 is an example of a first p-type semiconductor layer, and is a nitride semiconductor layer provided above the first electron supply layer 16. Specifically, the p-type gate layer 18 is provided in contact with the upper surface 16a of the first electron supply layer 16. The p-type gate layer 18 is provided between the source electrode 32 and the drain electrode 34 and spaced apart from each other. In other words, the p-type gate layer 18 covers only a portion of the upper surface 16a of the first electron supply layer 16. A region that is not covered by the p-type gate layer 18 is provided on the upper surface 16a.

[0080] The p-type gate layer 18 is a p-type nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the p-type gate layer 18 is a layer made of p-type GaN. The p-type gate layer 18 is doped with, for example, Mg as a p-type impurity. The p-type gate layer 18 has, for example, a thickness of 200 nm and a carrier concentration of 1×10 １９ cm －３ The p-type gate layer 18 is a film made of p-type GaN. The thickness and carrier concentration of the p-type gate layer 18 are merely examples and can be changed as appropriate. The p-type gate layer 18 may also be a p-type oxide semiconductor such as NiO.

[0081] The provision of the p-type gate layer 18 raises the potential of the conduction band edge of the channel portion. This reduces the carrier concentration directly below the p-type gate layer 18, shifting the threshold voltage of the transistor to the positive side. This allows the semiconductor device 1 to be easily realized as a normally-off FET. The p-type gate layer 18 is a layer for adjusting the threshold voltage of the transistor, and can also be called a threshold voltage adjustment layer.

[0082] The second electron supply layer 20 is a nitride semiconductor layer provided above the first electron supply layer 16 so as to cover the upper surface 18a and side surface 18b of the p-type gate layer 18. Specifically, the second electron supply layer 20 is provided in contact with each of the upper surface 18a and side surface 18b of the p-type gate layer 18 and the upper surface 16a of the first electron supply layer 16. The second electron supply layer 20 is not provided between the lower surface of the p-type gate layer 18 and the upper surface 16a of the first electron supply layer 16.

[0083] The second electron supply layer 20 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the second electron supply layer 20 is a layer made of undoped AlGaN. The second electron supply layer 20 has a larger band gap than the electron transit layer 14. Therefore, the second electron supply layer 20 supplies electrons to a channel region (i.e., 2DEG 17) formed in the electron transit layer 14.

[0084] The thickness of the second electron supply layer 20 is, for example, 40 nm to 50 nm, but is not limited thereto. The thickness of the second electron supply layer 20 is substantially uniform. For example, the thickness of the second electron supply layer 20 is thicker than the thickness of the first electron supply layer 16. For example, the thickness of the second electron supply layer 20 is a value that, when added to the thickness of the first electron supply layer 16, becomes 65 nm. By not making the sum of the thicknesses of the second electron supply layer 20 and the first electron supply layer 16 too large, it is possible to suppress the occurrence of cracks and the like on the surface of the second electron supply layer 20. The second electron supply layer 20 has an opening 22 for exposing at least a portion of the upper surface 18 a of the p-type gate layer 18.

[0085] The gate electrode 30 is electrically connected to the p-type gate layer 18 through the opening 22. Specifically, the gate electrode 30 is provided above the p-type gate layer 18 so as to cover the opening 22. The gate electrode 30 is in contact with the upper surface 18a of the p-type gate layer 18 within the opening 22.

[0086] The gate electrode 30 is formed using a conductive material such as a metal. For example, the gate electrode 30 can be made of a material that forms an ohmic contact with p-type GaN. For example, the gate electrode 30 can be made of palladium (Pd), nickel (Ni)-based material, tungsten silicide (WSi), platinum (Pt), gold (Au), or the like. The gate electrode 30 is a single-layer film or a multilayer film formed using a metal element or an alloy of two or more metals.

[0087] The source electrode 32 and the drain electrode 34 are provided above the first electron supply layer 16 and electrically connected to the electron transit layer 14. Specifically, the source electrode 32 and the drain electrode 34 are provided in contact with the upper surface of the second electron supply layer 20. The source electrode 32 and the drain electrode 34 are provided spaced apart from the gate electrode 30 and the p-type gate layer 18 so as to sandwich the gate electrode 30 and the p-type gate layer 18 therebetween.

[0088] The source electrode 32 and the drain electrode 34 are each formed using a conductive material such as a metal. For example, the source electrode 32 and the drain electrode 34 can each be made of a material that forms an ohmic contact with n-type GaN. The source electrode 32 and the drain electrode 34 are a single-layer film or a multilayer film formed using a metal or an alloy of two or more metals. For example, titanium (Ti), aluminum (Al), molybdenum (Mo), hafnium (Hf), etc. can be used as the source electrode 32 and the drain electrode 34. The source electrode 32 and the drain electrode 34 have, for example, the same composition. The source electrode 32 and the drain electrode 34 can be formed in the same process.

[0089] [Characteristic Configuration] Next, the characteristic configuration of the semiconductor device 1 according to the present embodiment will be described while comparing it with a semiconductor device according to a comparative example. First, the structure of the semiconductor device according to the comparative example and its problems will be described with reference to FIGS. 2 and 3 .

[0090] Fig. 2 is a cross-sectional view of a semiconductor device 1x according to a comparative example. Fig. 3 is a diagram for explaining a problem with the semiconductor device 1x according to the comparative example.

[0091] The semiconductor device 1x shown in FIG. 2 differs from the semiconductor device 1 according to the present embodiment in that it does not include a second electron supply layer 20 and includes an electron supply layer 16x with a gate recess 16r instead of the first electron supply layer 16. The gate recess 16r is a recess recessed from the top surface of the electron supply layer 16x toward the substrate 10. A p-type gate layer 18 is provided to cover the gate recess 16r. By providing the gate recess 16r, the thickness of the electron supply layer 16x is reduced in a portion overlapping the gate recess 16r in a plan view. This reduces the threshold voltage and enables normally-off operation of the semiconductor device 1x. On the other hand, the thickness of the electron supply layer 16x can be increased in a portion where the gate recess 16r is not provided, thereby reducing the on-resistance and suppressing current collapse.

[0092] On the other hand, to form the gate recess 16r, the electron supply layer 16x, which has been deposited to a uniform thickness, is etched. After removing a portion of the electron supply layer 16x by etching, the p-type gate layer 18 is formed by crystal regrowth. In other words, the electron supply layer 16x and the p-type gate layer 18 cannot be deposited continuously. As a result, as shown in FIG. 2, an impurity region 16y containing impurities is formed along the inner surface of the gate recess 16r.

[0093] The impurity mixed into the impurity region 16y is, for example, siloxane present in a clean room. The impurity region 16y mixed with siloxane can shift the threshold value of the transistor to the negative side, as shown in FIG. 3. FIG. 3 also shows the current-voltage characteristics of the transistor. The horizontal axis represents the gate-source voltage (gate voltage), and the vertical axis represents the drain current. The gate voltage at which the drain current begins to increase represents the threshold value of the transistor.

[0094] Furthermore, impurities other than siloxane may be mixed in, which may also cause the threshold voltage to fluctuate to the positive or negative side. Thus, when the impurity region 16y is formed by forming the gate recess 16r, the threshold voltage of the transistor is unstable.

[0095] In contrast, in the semiconductor device 1 according to the present embodiment, the first electron supply layer 16 is provided with a second electron supply layer 20 instead of the gate recess 16r. In a region of the substrate 10 where the second electron supply layer 20 is provided without overlapping with the p-type gate layer 18 in a plan view, the concentration of the 2DEG 17 depends on the total thickness of the first electron supply layer 16 and the second electron supply layer 20. Therefore, by providing the second electron supply layer 20, the concentration of the 2DEG 17 can be increased, thereby realizing a reduction in on-resistance and suppression of current collapse.

[0096] Furthermore, the threshold voltage of the transistor depends on the thickness of the first electron supply layer 16 located directly below the p-type gate layer 18. Therefore, by reducing the thickness of the first electron supply layer 16, the threshold voltage can be made larger than 0 V. This makes it possible to realize a normally-off operation of the transistor.

[0097] In this way, the semiconductor device 1 can achieve normally-off operation, reduced on-resistance, and suppressed current collapse without providing the gate recess 16r. Because the gate recess 16r is not required, the first electron supply layer 16 and the p-type gate layer 18 can be formed continuously. This makes it difficult for a region containing impurities such as siloxane to be formed at the interface between the first electron supply layer 16 and the p-type gate layer 18, thereby stabilizing the threshold voltage.

[0098] As described above, according to this embodiment, it is possible to realize a semiconductor device 1 including a transistor with a stabilized threshold for normally-off operation while realizing a reduction in on-resistance or suppression of current collapse.

[0099] Furthermore, in the semiconductor device 1, by thickening the second electron supply layer 20, the concentration of the 2DEG 17 can be increased, thereby more effectively reducing the on-resistance and suppressing current collapse. Alternatively, instead of or in addition to thickening the second electron supply layer 20, the Al composition ratio of the second electron supply layer 20 may be increased. For example, the Al composition ratio of the second electron supply layer 20 may be higher than the Al composition ratio of the first electron supply layer 16. Specifically, the Al composition ratio of the first electron supply layer 16 may be 18% or more and 22% or less, while the Al composition ratio of the second electron supply layer 20 may be 20% or more and 25% or less. Increasing the Al composition ratio of the second electron supply layer 20 is expected to improve the carrier barrier properties and reduce the likelihood of electrons being trapped in the surface states of AlGaN. Furthermore, by not increasing the Al composition ratio of the first electron supply layer 16 too much, a decrease in carrier mobility due to alloy scattering can be suppressed.

[0100] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 1 according to this embodiment will be described with reference to Figures 4A to 4D. Figures 4A to 4D are cross-sectional views for explaining one step included in the manufacturing method of the semiconductor device 1 according to this embodiment.

[0101] First, as shown in FIG. 4A , the buffer layer 12, the electron transit layer 14, the first electron supply layer 16, and the p-type semiconductor layer 18A are formed in this order by crystal growth above the substrate 10. Specifically, as shown in FIG. 4A , a nitride semiconductor is crystal-grown on the main surface of the substrate 10 by epitaxial growth, such as MOCVD (Metal Oxide Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). By adjusting growth conditions such as raw materials, growth temperature, and growth time, the composition, film thickness, impurity concentration, and other properties can be optimized for each layer. The buffer layer 12, the electron transit layer 14, the first electron supply layer 16, and the p-type semiconductor layer 18A are formed consecutively in the same growth furnace without exposure to the atmosphere. The formation of the buffer layer 12 may be omitted.

[0102] Next, the p-type semiconductor layer 18A is patterned into a predetermined shape by removing a portion thereof. Specifically, as shown in FIG. 4A, a resist 90 is formed. The resist 90 is a photosensitive photoresist and is provided so as to cover only the region of the upper surface 18a of the p-type semiconductor layer 18A where the p-type gate layer 18 is to be formed. Dry etching is performed using the resist 90 as a mask to remove the portion of the p-type semiconductor layer 18A that is not covered by the resist 90. As a result, the p-type gate layer 18 is formed as shown in FIG. 4B.

[0103] A damaged region 18c is formed on the side surface 18b of the p-type gate layer 18 due to etching. The damaged region 18c may cause a shift in the threshold voltage and / or an increase in leakage current. Alternatively, an electric field may be easily concentrated in the damaged region 18c, which may reduce the breakdown voltage of the semiconductor device 1.

[0104] Next, as shown in FIG. 4C , a second electron supply layer 20 is formed by crystal growth so as to cover the patterned p-type gate layer 18 and the first electron supply layer 16. For example, a nitride semiconductor such as AlGaN is crystal-grown at high temperature by epitaxial growth such as MOCVD. The temperature of the crystal growth (also called regrowth) is, for example, 1000° C. or higher and 1100° C. or lower. Damage to the side surface 18 b of the p-type gate layer 18 is repaired by the high-temperature treatment.

[0105] Next, a portion of the second electron supply layer 20 is removed to expose a portion of the upper surface 18a of the p-type gate layer 18. Specifically, as shown in FIG. 4D , a resist 92 having an opening 92a is formed. The resist 92 is a photosensitive photoresist and has the opening 92a located at a position overlapping the upper surface 18a of the p-type gate layer 18 in a plan view. The upper surface of the second electron supply layer 20 is exposed at the bottom of the opening 92a. Using the resist 92 as a mask, the portion of the second electron supply layer 20 exposed in the opening 92a is removed by a low-damage etching method. Examples of the low-damage etching method include neutral beam etching and photoelectrochemical (PEC) etching. As a result, the opening 22 shown in FIG. 1 is formed in the second electron supply layer 20, exposing the upper surface 18a of the p-type gate layer 18.

[0106] Next, the gate electrode 30 is formed so as to cover the exposed portion of the upper surface 18a of the p-type gate layer 18. For example, a metal film is formed by EB (Electron Beam) evaporation or sputtering, and then patterned by etching, lift-off, or the like, to form the gate electrode 30 in a predetermined shape. By bringing the gate electrode 30 into contact with the p-type gate layer 18, a good ohmic connection can be achieved.

[0107] Next, a metal film is formed and patterned to form the source electrode 32 and the drain electrode 34, thereby manufacturing the semiconductor device 1 shown in Fig. 1. The source electrode 32 and the drain electrode 34 may be formed before the gate electrode 30, or may be formed simultaneously.

[0108] As described above, in the method for manufacturing the semiconductor device 1, the incorporation of impurities such as siloxane into the interface between the first electron supply layer 16 and the p-type gate layer 18 is suppressed. This makes it possible to manufacture a semiconductor device 1 including a transistor with a stabilized threshold for normally-off operation. Furthermore, the second electron supply layer 20 can reduce on-resistance and suppress current collapse.

[0109] Furthermore, the semiconductor device 1 according to this embodiment also provides the effects of increasing the breakdown voltage and further reducing the on-resistance, as will be described below.

[0110] In the semiconductor device 1, a voltage applied between the gate electrode 30 and the drain electrode 34 tends to concentrate an electric field on the side surface 18b of the p-type gate layer 18 on the drain electrode 34 side. If the damaged region 18c were to remain, the semiconductor device 1 would not be able to withstand the electric field concentration and may be destroyed. In contrast, in the semiconductor device 1 according to this embodiment, damage to the p-type gate layer 18 can be repaired when the second electron supply layer 20 is formed. Because the damaged region 18c is less likely to remain, the semiconductor device 1 can withstand the electric field concentration, thereby achieving a high breakdown voltage.

[0111] Furthermore, compound semiconductors such as GaN and GaAs are direct transition semiconductors, which have high light generation efficiency. Therefore, when p-type GaN, AlGaN, or GaN is used for the p-type gate layer 18, the first electron supply layer 16, and the electron transit layer 14, a reduction in on-resistance due to light emission can be expected.

[0112] Specifically, during operation of the semiconductor device 1, a light emission phenomenon occurs near the interface between the p-type gate layer 18 and the first electron supply layer 16 in response to the voltage supplied to the gate electrode 30. For example, when a voltage of 3.4 V or more is applied between the gate electrode 30 and the source electrode 32, light with a wavelength of 365 nm is emitted near the interface between the p-type gate layer 18 and the first electron supply layer 16. It is known that at the heterointerface between AlGaN (first electron supply layer 16) and GaN (electron transit layer 14), carriers are excited by light with a wavelength of 280 nm or more and 390 nm or less, and the carrier density of the 2DEG 17 increases.

[0113] In this embodiment, the incorporation of impurities such as siloxane into the vicinity of the interface between the p-type gate layer 18 and the first electron supply layer 16 is suppressed, thereby increasing the light emission efficiency. This is expected to increase the carrier density of the 2DEG 17, thereby reducing the sheet resistance directly below the p-type gate layer 18. This allows the on-resistance of the semiconductor device 1 to be reduced.

[0114] (Variations of Embodiment 1) Next, a description will be given of several variations of the above-described embodiment 1. The following description will focus on differences from embodiment 1 and differences between the variations, and explanations of commonalities will be omitted or simplified.

[0115] 5 is a cross-sectional view of a semiconductor device 1A according to a first modification of the first embodiment. The semiconductor device 1A shown in Fig. 5 differs from the semiconductor device 1 shown in Fig. 1 in that a source opening 36 and a drain opening 38 are provided.

[0116] The source opening 36 is an example of a first recess, and is recessed from the upper surface of the second electron supply layer 20 toward the substrate 10. Specifically, the source opening 36 penetrates the second electron supply layer 20 and the first electron supply layer 16 to reach the electron transit layer 14. A bottom surface 36a of the source opening 36 is below the interface between the electron transit layer 14 and the first electron supply layer 16, i.e., is closer to the substrate 10. Therefore, an end of the 2DEG 17 generated in the electron transit layer 14 is exposed on a sidewall 36b of the source opening 36.

[0117] In this modification, the source electrode 32 is provided to cover the source opening 36. Specifically, the source electrode 32 contacts and covers the bottom surface 36a and the sidewall 36b of the source opening 36. Since the source electrode 32 can be in direct contact with the 2DEG 17, the contact resistance of the source electrode 32 with the channel (2DEG 17) can be reduced. The bottom surface 36a may be flush with the interface between the electron transit layer 14 and the first electron supply layer 16.

[0118] The drain opening 38 is an example of a second recess, and is recessed from the upper surface of the second electron supply layer 20 toward the substrate 10. Specifically, the drain opening 38 penetrates the second electron supply layer 20 and the first electron supply layer 16 to reach the electron transit layer 14. A bottom surface 38a of the drain opening 38 is below the interface between the electron transit layer 14 and the first electron supply layer 16, i.e., is closer to the substrate 10. Therefore, an end of the 2DEG 17 generated in the electron transit layer 14 is exposed on a sidewall 38b of the drain opening 38.

[0119] In this modification, the drain electrode 34 is provided to cover the drain opening 38. Specifically, the drain electrode 34 contacts and covers each of the bottom surface 38a and sidewalls 38b of the drain opening 38. Since the drain electrode 34 can be in direct contact with the 2DEG 17, the contact resistance of the drain electrode 34 with the channel (2DEG 17) can be reduced. Note that the bottom surface 38a may be flush with the interface between the electron transit layer 14 and the first electron supply layer 16.

[0120] The source opening 36 and the drain opening 38 are formed by dry etching or the like after forming the second electron supply layer 20 and before forming the source electrode 32 and the drain electrode 34. Note that one of the source opening 36 and the drain opening 38 does not necessarily have to be provided.

[0121] 6 is a cross-sectional view of a semiconductor device 1B according to Modification 2 of Embodiment 1. The semiconductor device 1B shown in Fig. 6 differs from the semiconductor device 1 shown in Fig. 1 in that it includes a spacer layer 15.

[0122] The spacer layer 15 is provided between the electron transit layer 14 and the first electron supply layer 16. Specifically, the spacer layer 15 is provided between the upper surface of the electron transit layer 14 and the lower surface of the first electron supply layer 16 so as to be in contact with both. The spacer layer 15 has a band gap larger than both the electron transit layer 14 and the first electron supply layer 16.

[0123] The spacer layer 15 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the spacer layer 15 is a layer made of undoped AlN. The thickness of the spacer layer 15 is, for example, about 1 nm. The spacer layer 15 is formed by epitaxial growth continuously after the formation of the electron transit layer 14 and before the formation of the first electron supply layer 16.

[0124] In this way, the semiconductor device 1B includes the spacer layer 15, which can suppress alloy scattering in the first electron supply layer 16. Therefore, in the semiconductor device 1B, the mobility of the 2DEG 17 can be improved and the on-resistance can be reduced.

[0125] 7 is a cross-sectional view of a semiconductor device 1C according to Modification 3 of Embodiment 1. The semiconductor device 1C shown in Fig. 7 differs from the semiconductor device 1 shown in Fig. 1 in that it includes an insulating film 24.

[0126] The insulating film 24 is provided between the gate electrode 30 and the second electron supply layer 20. Specifically, the insulating film 24 is in contact with and covers the upper surface of the second electron supply layer 20 and the side surface of the opening 22 provided in the second electron supply layer 20. A portion of the insulating film 24 is in contact with the upper surface 18 a of the p-type gate layer 18 within the opening 22.

[0127] The insulating film 24 is an electrically insulating film. Specifically, the insulating film 24 contains at least one of oxygen (O) and nitrogen (N), and silicon (Si). For example, the insulating film 24 is a film made of SiN, but SiO ２ The insulating film 24 is a single layer film, but may have a laminated structure of a plurality of insulating films.

[0128] The insulating film 24 is formed after the opening 22 is formed in the second electron supply layer 20 and before the gate electrode 30 is formed. For example, the insulating film 24 is formed by depositing an insulating film by plasma CVD (Chemical Vapor Deposition) or the like and then removing a portion of the insulating film by etching so as to expose a portion of the upper surface 18 a of the p-type gate layer 18. The insulating film 24 may not be provided in the opening 22 of the second electron supply layer 20 and may cover only the upper surface of the second electron supply layer 20. In this case, the insulating film 24 can be formed by depositing an insulating film by plasma CVD or the like before forming the opening 22 of the second electron supply layer 20 and then successively removing the insulating film and the second electron supply layer 20 by etching to form the opening 22.

[0129] In this way, the semiconductor device 1C, by including the insulating film 24, can suppress the leakage current that flows along the surface of the second electron supply layer 20. Specifically, it can suppress the leakage current that flows between the drain and gate when a high voltage is applied between the gate electrode 30 and the drain electrode 34. It can also suppress the leakage current between the source and gate.

[0130] 8 is a cross-sectional view of a semiconductor device 1D according to a fourth modification of the first embodiment. The semiconductor device 1D shown in Fig. 8 differs from the semiconductor device 1C shown in Fig. 7 in that it has a stacked structure of a p-type gate layer 18 and a p-type gate layer 26.

[0131] The p-type gate layer 26 is an example of a second p-type semiconductor layer, and is provided between the first electron supply layer 16 and the p-type gate layer 18. Specifically, the p-type gate layer 26 is provided between the upper surface 16 a of the first electron supply layer 16 and the lower surface of the p-type gate layer 18 so as to be in contact with both. The p-type gate layer 26 has a smaller band gap than both the first electron supply layer 16 and the p-type gate layer 18.

[0132] The p-type gate layer 26 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the p-type gate layer 26 is a layer made of p-type InGaN. The p-type gate layer 26 may be InN. The band gap of InN is approximately 0.7 eV, and the band gap of GaN is approximately 3.4 eV. The band gap of p-type InGaN depends on the In composition ratio and the Ga composition ratio, but is greater than 0.7 eV and less than 3.4 eV. The band gap of AlGaN is greater than the band gap of GaN.

[0133] The thickness of the p-type gate layer 26 is, for example, 10 nm or less, but is not limited to this. The p-type gate layer 26 is formed successively by epitaxial growth after the formation of the first electron supply layer 16 and before the formation of the p-type gate layer 18. The p-type gate layer 26 and the p-type gate layer 18 are formed into a predetermined shape by collectively patterning a stack of semiconductor films that have been successively formed. As a result, the p-type gate layer 26 and the p-type gate layer 18 have the same shape and size in a plan view.

[0134] In this way, the p-type gate layer 26 is provided, which has a band gap smaller than both the first electron supply layer 16 and the p-type gate layer 18, and therefore a quantum well structure is formed by the first electron supply layer 16, the p-type gate layer 26, and the p-type gate layer 18. This further improves the light-emitting efficiency when a voltage of 3.4 V or more is applied to the gate electrode 30, thereby enhancing the effect of reducing the on-resistance.

[0135] 9 is a cross-sectional view of a semiconductor device 1E according to Modification 5 of Embodiment 1. The semiconductor device 1E shown in Fig. 9 differs from the semiconductor device 1C shown in Fig. 7 in that it includes a second electron supply layer 21 instead of the second electron supply layer 20, and that it is provided with a source opening 36E and a drain opening 38E.

[0136] The second electron supply layer 21 is different from the second electron supply layer 20 in that it is an oxide layer containing gallium oxide as a main component. Gallium oxide is, for example, κ-Ga ２ O３ and the band gap is about 4.9 eV. For example, when the first electron supply layer 16 is made of Al ０．２ Ga ０．８ In the case where the second electron supply layer 21 is N, the band gap of the second electron supply layer 21 is larger than the band gap of the first electron supply layer 16, and the polarization is also large. In this case, as shown in FIG. 9 , 2DEG 19 is also formed at the interface between the second electron supply layer 21 and the first electron supply layer 16. That is, the semiconductor device 1E becomes a device having multiple channels of 2DEG 17 and 2DEG 19. This allows for a further reduction in on-resistance.

[0137] Gallium oxide has a refractive index of less than 2.0 at a wavelength of 365 nm, which is smaller than the refractive index of 2.7 of GaN. This has the effect of confining light within the second electron supply layer 21. This improves the utilization efficiency of light generated at the interface between the p-type gate layer 18 and the first electron supply layer 16, thereby increasing the carrier concentration of the 2DEGs 17 and 19. This further enhances the effect of reducing the on-resistance.

[0138] The source opening 36E and the drain opening 38E are examples of a first recess and a second recess, respectively, and differ from the source opening 36 and the drain opening 38 of the semiconductor device 1A according to the first modification in their depths, i.e., the positions of their bottom surfaces 36a and 38a. Specifically, the source opening 36E and the drain opening 38E each penetrate the second electron supply layer 21 to reach the first electron supply layer 16. The bottom surfaces 36a and 38a are the surfaces of the first electron supply layer 16. Note that the source opening 36E and the drain opening 38E may penetrate the first electron supply layer 16, similar to the source opening 36 and the drain opening 38.

[0139] The second electron supply layer 21 containing gallium oxide as a main component has a higher resistance than the second electron supply layer 20 containing AlGaN as a main component. In this modification, the source opening 36E and the drain opening 38E are provided, so that the contact resistance of each of the source electrode 32 and the drain electrode 34 can be reduced.

[0140] 10 is a cross-sectional view of a semiconductor device 1F according to Modification 6 of Embodiment 1. The semiconductor device 1F shown in Fig. 10 differs from the semiconductor device 1E shown in Fig. 9 in that the insulating film 24 is also provided between the side surface 18b of the p-type gate layer 18 and the second electron supply layer 21.

[0141] In this modification, the second electron supply layer 21 is not in contact with the p-type gate layer 18. The entire top surface 18a and side surface 18b of the p-type gate layer 18 are covered with an insulating film 24, except for the portion in contact with the gate electrode 30. This increases the distance between the 2DEG 19 and the p-type gate layer 18. That is, in a plan view of the substrate 10, the distance between the end of the 2DEG 19 on the gate electrode 30 side and the side surface 18b of the p-type gate layer 18 can be increased. This reduces the leakage current through the 2DEG 19. This allows the semiconductor device 1F to have a high breakdown voltage.

[0142] 11A is a cross-sectional view of a semiconductor device 1G according to a seventh modification of the first embodiment. In Fig. 11A, the gate-drain capacitance Cgd and the drain-source capacitance Cds, as well as the fact that the source electrode 32 and the back surface electrode 40 are grounded, are schematically represented by circuit symbols. This also applies to Fig. 11B.

[0143] 1A includes a substrate 10A and a back electrode 40 instead of the substrate 10. The substrate 10A is a conductive substrate. For example, the substrate 10A may be an n-type GaN substrate doped with a high concentration of n-type impurities, or a graphite substrate including graphene.

[0144] The back electrode 40 is provided below the substrate 10A and is electrically connected to the source electrode 32. Specifically, the back electrode 40 is provided in contact with the lower surface of the substrate 10A. The back electrode 40 and the source electrode 32 are set to a ground potential, i.e., are grounded. The back electrode 40 is formed using a conductive metal material. For example, Ti, Au, etc. can be used as the metal material.

[0145] In the semiconductor device 1G according to this modification, the conductive substrate 10A functions as a source field plate, thereby reducing the gate-drain capacitance Cgd and increasing the switching speed. Meanwhile, the distance between the drain electrode 34 and the substrate 10A is shortened, increasing the drain-source capacitance Cds. The capacitance Cgd is the feedback capacitance Crss itself, and the capacitance Cds is the output capacitance Coss. The semiconductor device 1G according to this modification, which has a small feedback capacitance Crss, is useful in hard switching circuits.

[0146] 11B is a cross-sectional view of a semiconductor device 1H according to an eighth modification of the first embodiment. Compared to the semiconductor device 1 shown in FIG. 1, the semiconductor device 1H shown in FIG. 11B includes a substrate 10B and a back electrode 40 instead of the substrate 10. The substrate 10B is an insulating substrate. For example, the substrate 10B is an insulating substrate such as sapphire or diamond.

[0147] The back electrode 40 is provided below the substrate 10B and is electrically connected to the source electrode 32. Specifically, the back electrode 40 is provided in contact with the lower surface of the substrate 10B. The back electrode 40 and the source electrode 32 are set to a ground potential, i.e., are grounded. The back electrode 40 is formed using a conductive metal material. For example, Ti, Au, etc. can be used as the metal material.

[0148] In the semiconductor device 1H according to this modification, the substrate 10B does not function as a source field plate, so the gate-drain capacitance Cgd is larger than in the semiconductor device 1G. On the other hand, the distance between the drain electrode 34 and the back surface electrode 40 is longer, so the drain-source capacitance Cds is smaller. The semiconductor device 1H according to this embodiment, which has a small output capacitance Coss, is useful for soft switching circuits such as zero voltage switching.

[0149] In this way, the semiconductor device 1G according to the seventh modification and the semiconductor device 1H according to the eighth modification can be used selectively depending on the application.

[0150] The features of the first embodiment and the first to eighth modifications described above can be combined as appropriate, provided there is no contradiction. For example, at least one of the source opening 36 and the drain opening 38 of the first modification may be provided in the semiconductor devices 1B to 1H of the second to eighth modifications. Furthermore, for example, the spacer layer 15 of the second modification may be provided in the semiconductor devices 1A, 1C to 1H of the first, third to eighth modifications. Furthermore, for example, the p-type gate layer 26 of the fourth modification may be provided in the semiconductor devices 1E, 1H, and fifth to eighth embodiments. Furthermore, for example, the insulating film 24 may not be provided in the semiconductor devices 1D to 1F of the fourth to sixth modifications.

[0151] Second Embodiment Next, a second embodiment will be described. In the second embodiment, a chip layout structure of a semiconductor device will be described. The following description will focus on the differences between the first embodiment and its modifications, and the description of commonalities will be omitted or simplified.

[0152] 12 and 13 are respectively a plan view and a cross-sectional view of the semiconductor device 100 according to this embodiment. Fig. 13 shows a cross section taken along line XIII-XIII in Fig. 12.

[0153] 12, the semiconductor device 100 includes a gate pad 50G, a source pad 52S, a drain pad 54D, a gate wiring 50, a plurality of source wirings 52, and a plurality of drain wirings 54. The plurality of source wirings 52 and the plurality of drain wirings 54 are arranged alternately one by one.

[0154] 13, the semiconductor device 100 includes a substrate 10, a buffer layer 12, an electron transit layer 14, a first electron supply layer 16, a p-type gate layer 18, a second electron supply layer 20, a gate electrode 30, a source electrode 32, and a drain electrode 34, similar to the semiconductor device 1 shown in FIG. 1. The semiconductor device 100 further includes a back electrode 40 and an interlayer insulating film 60.

[0155] The interlayer insulating film 60 is provided between the second electron supply layer 20 and the source pad 52S, the source wiring 52, the drain pad 54D, and the drain wiring 54. Specifically, the interlayer insulating film 60 is provided above the second electron supply layer 20 so as to cover at least a portion of each of the gate electrode 30, the source electrode 32, and the drain electrode 34.

[0156] The interlayer insulating film 60 contains, for example, at least one of oxygen (O) and nitrogen (N), and silicon (Si). For example, the interlayer insulating film 60 is a film made of SiN, but SiO ２ The interlayer insulating film 60 has a laminated structure of a plurality of insulating films, but may also be a single layer film.

[0157] As shown in FIG. 12, a semiconductor device 100 can be divided into an active region 101 and an isolation region 102 in a plan view.

[0158] The active region 101 is a region within a rectangular area surrounded by a dashed line in FIG. 12 . The active region 101 is the main operating region of the semiconductor device 100. Specifically, the active region 101 is a region that serves as a main current path when the semiconductor device 100 is turned on. The active region 101 is provided with a gate electrode 30, a source electrode 32, and a drain electrode 34. A plurality of source electrodes 32 and a plurality of drain electrodes 34 are alternately arranged side by side with the gate electrode 30 sandwiched between them. In addition, in the active region 101, as shown in FIG. 13 , a 2DEG 17 is generated near the interface between the electron transit layer 14 and the first electron supply layer 16.

[0159] The element isolation region 102 is a region other than the active region 101. The element isolation region 102 is provided around the active region 101 and is also referred to as a peripheral region. In the element isolation region 102, at least the electron transit layer 14 is made highly resistive to prevent the generation of 2DEG 17. The element isolation region 102 is also referred to as an inactive region. The high resistance is achieved by ion implantation of, for example, iron (Fe) or boron (B). The ion implantation may be performed only in the region of the electron transit layer 14 where 2DEG 17 may be generated, or may be performed throughout the electron transit layer 14. The ion implantation may also be performed in the buffer layer 12, the first electron supply layer 16, and the second electron supply layer 20. Furthermore, a gate pad 50G, a source pad 52S, and a drain pad 54D are provided in the element isolation region 102. The element isolation region 102 is also referred to as a pad region.

[0160] The gate pad 50G, the source pad 52S, and the drain pad 54D, as well as the gate wiring 50, the plurality of source wirings 52, and the plurality of drain wirings 54, are all provided above the second electron supply layer 20. The gate wiring 50 and the plurality of source wirings 52 are provided at different heights, with a part of the interlayer insulating film 60 provided between them to prevent them from contacting each other. Note that the height represents the distance from the main surface of the substrate 10. For example, the gate wiring 50 is provided so as to extend inside the interlayer insulating film 60 in a direction parallel to the main surface of the substrate 10. The plurality of source wirings 52 and the plurality of drain wirings 54 are provided on the upper surface of the interlayer insulating film 60.

[0161] In this embodiment, there is a one-to-one correspondence between the source wirings 52 and the source electrodes 32. The source wirings 52 are provided above the corresponding source electrodes 32 in the active region 101. The source wirings 52 are electrically connected to the source pads 52S and the corresponding source electrodes 32.

[0162] Furthermore, there is a one-to-one correspondence between the drain wirings 54 and the drain electrodes 34. The drain wirings 54 are provided above the corresponding drain electrodes 34 in the active region 101. The drain wirings 54 are electrically connected to the drain pads 54D and the corresponding drain electrodes 34.

[0163] The gate pad 50G, source pad 52S, and drain pad 54D are all provided on the upper surface of the interlayer insulating film 60. The gate pad 50G and the gate wiring 50 are electrically connected by a conductive via or the like provided in the interlayer insulating film 60. Alternatively, the gate pad 50G and the gate wiring 50 may be provided at the same height. In this case, an opening is provided in the interlayer insulating film 60 to expose the gate pad 50G.

[0164] The gate pad 50G, source pad 52S, and drain pad 54D, as well as the gate wiring 50, the plurality of source wirings 52, and the plurality of drain wirings 54, are all formed using a metal material. Metals with low resistivity and high thermal conductivity, such as Au or Cu, can be used as metal materials for the pads and wiring. The pads and wiring are single-layer metal films made of a single metal or an alloy of two or more metals, but may also be laminated films made of multiple metal films with different compositions.

[0165] 14 is a plan view showing a mounting layout of the semiconductor device 100 according to this embodiment. The semiconductor device 100 is bonded to the die frame 76 using a solder material or the like. This electrically connects the back electrode 40 of the semiconductor device 100 and the die frame 76.

[0166] 14 , wires 78 are connected to each of the gate pad 50G, the source pad 52S, and the drain pad 54D. The wires 78 are conductive metal wires made of Au, Al, Cu, or the like. The wires 78 are also called bonding wires. The multiple wires 78 specifically include wires 78g, 78sf, 78ss, and 78d.

[0167] Specifically, the gate pad 50G is connected to the gate terminal 70 via a wire 78g. The source pad 52S is connected to the source force terminal 72 via a plurality of wires 78sf, and is connected to the source sense terminal 73 via a wire 78ss. The drain pad 54D is connected to the drain terminal 74 via a plurality of wires 78d. The number of wires 78 connecting each pad to each terminal is not particularly limited.

[0168] The gate terminal 70, the source force terminal 72, and the drain terminal 74 are terminals for receiving external potentials to be supplied to the gate electrode 30, the source electrode 32, and the drain electrode 34, respectively. The source sense terminal 73 is a terminal for detecting the source potential. The source sense terminal 73 does not necessarily have to be provided. The layout and shape of each terminal are not particularly limited. Since the die frame 76 and the source force terminal 72 are electrically connected, the source electrode 32 and the back electrode 40 can be electrically connected.

[0169] In the present embodiment, an example has been shown in which the semiconductor device 100 has a configuration similar to that of the semiconductor device 1 according to the first embodiment, but the present invention is not limited to this. The semiconductor device 100 may have a configuration similar to that of the semiconductor devices 1A to 1H according to the first to eighth modifications of the first embodiment.

[0170] In addition, in the present embodiment, the source electrode 32 and the drain electrode 34 each have a shape that is elongated in the y-axis direction in plan view, but this is not limiting. The shape, size, layout, etc. in plan view can be changed as appropriate.

[0171] According to the semiconductor device 100 of this embodiment, electrical connection to each electrode and mounting can be easily performed.

[0172] (Modifications of Embodiment 2) Next, a description will be given of several modifications of the above-described embodiment 2. The following description will focus on differences from embodiment 2 and differences between the modifications, and explanations of commonalities will be omitted or simplified.

[0173] 15 is a plan view of a semiconductor device 100A according to a first modification of the second embodiment. Fig. 16A is a cross-sectional view of the semiconductor device 100A according to the first modification of the second embodiment. Fig. 16A shows a cross section taken along line XVI-XVI shown in Fig. 15.

[0174] 15 differs from the semiconductor device 100 shown in Fig. 12 in that a source via hole 56 is provided in the element isolation region 102. As shown in Fig. 16A , the source via hole 56 is an example of a third opening that extends from the second electron supply layer 20 to at least the substrate 10. In the example shown in Fig. 16A , the source via hole 56 penetrates all of the interlayer insulating film 60, the second electron supply layer 20, the first electron supply layer 16, the electron transit layer 14, the buffer layer 12, and the substrate 10.

[0175] In this modification, a plurality of source via holes 56 are provided. A source pad 52S is provided so as to cover the plurality of source via holes 56. Specifically, as shown in FIG. 16A , the source pad 52S is provided along the inner surface of each of the plurality of source via holes 56 and reaches the back surface electrode 40. The source pad 52S is in contact with the back surface electrode 40, and is thereby electrically connected to the back surface electrode 40. In other words, the back surface electrode 40 is electrically connected to the source pad 52S via the source via hole 56.

[0176] This allows the heat generated when the device is turned on to be efficiently propagated via the source pad 52S to the back surface electrode 40. Since the back surface electrode 40 can be used for heat dissipation, the heat dissipation properties of the semiconductor device 100A can be improved.

[0177] 16B is a cross-sectional view of a semiconductor device 100B according to a second modification of the second embodiment. Like FIG. 16A, FIG. 16B corresponds to the cross section taken along line XVI-XVI shown in FIG.

[0178] 16A, the semiconductor device 100B shown in Fig. 16B differs from the semiconductor device 100A shown in Fig. 16A in that a conductive substrate 10A is provided instead of the substrate 10. Furthermore, in the semiconductor device 100B, the source via hole 56 does not penetrate through the substrate 10A. The source pad 52S is in contact with the substrate 10A, but is not in contact with the back surface electrode 40.

[0179] Since the substrate 10A is conductive, the source pad 52S can be electrically connected to the back surface electrode 40 via the substrate 10A. Furthermore, by using a material with high conductivity and heat dissipation properties for the substrate 10A, the heat dissipation properties of the semiconductor device 100B can be improved. Materials with high thermal conductivity, such as SiC, diamond, or graphite containing graphene, can be used for the substrate 10 or 10A.

[0180] 17 and 18 are cross-sectional views of a semiconductor device 100C according to a third modification of the second embodiment. Fig. 17 corresponds to the cross section taken along line XVII-XVII shown in Fig. 15. Fig. 18 corresponds to the cross section taken along line XVI-XVI shown in Fig. 15.

[0181] As shown in FIG. 17, the semiconductor device 100C differs from the semiconductor device 100 shown in FIG. 13 in that it includes a graphene cap layer 58 and a protective film 80.

[0182] The graphene cap layer 58 covers the surfaces of the source pad 52S, the drain pad 54D, the source wiring 52, and the drain wiring 54. Specifically, the graphene cap layer 58 contacts and covers the top and side surfaces of each pad and wiring. The graphene cap layer 58 includes graphene, multilayer graphene, or graphite.

[0183] In this modification, at least a portion of each of the source pad 52S, the drain pad 54D, the source wiring 52, and the drain wiring 54 is made of at least one metal selected from Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these metals. Specifically, at least the surface layer of each of the source pad 52S, the drain pad 54D, the source wiring 52, and the drain wiring 54 is made of at least one metal selected from Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these metals. This allows for the promotion of graphene growth on the surfaces of each of the source pad 52S, the drain pad 54D, the source wiring 52, and the drain wiring 54. For example, the graphene cap layer 58 is formed by growing graphene after forming each pad and each wiring. The source material is CH ４ Graphene can be grown selectively on exposed metal portions at temperatures ranging from about 200° C. to about 400° C. using hydrocarbon gases such as SiO 2 .

[0184] Graphene, multilayer graphene, and graphite have high thermal conductivity. Therefore, heat can be efficiently transferred to the back surface electrode 40 via the source pad 52S provided with the graphene cap layer 58. In addition, the drain pad 54D may be formed larger than the source pad 52S. By forming the graphene cap layer 58 so as to cover the surface of the drain pad 54D, the drain pad 54D can function as a heat sink.

[0185] Furthermore, the graphene cap layer 58 can suppress electromigration. Therefore, by forming the graphene cap layer 58 so as to cover the surfaces of the source wiring 52 and the drain wiring 54, it is possible to suppress an increase in resistance and disconnection of the source wiring 52 and the drain wiring 54.

[0186] The graphene cap layer 58 may not be provided on at least one of the source pad 52S, the drain pad 54D, the source wiring 52, and the drain wiring 54. For example, the graphene cap layer 58 may be provided on the source wiring 52 and the drain wiring 54, but not on the source pad 52S and the drain pad 54D. Alternatively, the graphene cap layer 58 may be provided on the source pad 52S and the drain pad 54D, but not on the source wiring 52 and the drain wiring 54.

[0187] The protective film 80 is provided above the source wiring 52 and the drain wiring 54. Specifically, the protective film 80 contacts and covers the graphene cap layer 58 provided on the surface of each of the source wiring 52 and the drain wiring 54.

[0188] The protective film 80 includes a polymer material. In this specification, a polymer material refers to a material composed of a compound with a molecular weight of 10,000 or more. For example, the protective film is formed using a material with excellent heat resistance, insulating properties, and water resistance, such as polybenzoxazole (PBO). This can suppress discharge in the air and water intrusion.

[0189] 19 is a cross-sectional view of a semiconductor device 100D according to a fourth modification of the second embodiment. Fig. 19 corresponds to the cross section taken along line XVI-XVI shown in Fig. 15 .

[0190] 19, the semiconductor device 100D differs from the semiconductor device 100C shown in FIG. 18 in that the source pad 52S has a stacked structure. Specifically, the source pad 52S has metal layers 52a and 52b. Although not shown, the drain pad 54D, the source wiring 52, and the drain wiring 54 also have metal layers 52a and 52b.

[0191] The metal layer 52a is an example of a first metal layer and is made of Pd, Ag, or Au. The metal layer 52b is an example of a second metal layer and is made of at least one of Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these. The metal layer 52b is provided on the surface of the metal layer 52a. The metal layer 52b is provided between the metal layer 52a and the graphene cap layer 58 and serves as a base layer for growing graphene.

[0192] For example, the metal layer 52a may be formed using a material with a lower electrical resistivity than the metal layer 52b. This allows both the metal layer 52a to reduce the resistance of each wiring and each pad and the metal layer 52b to promote graphene growth. The metal layer 52a may also be formed using a material with a higher thermal conductivity than the metal layer 52b. This allows both the metal layer 52a to improve the heat transfer effect of each wiring and each pad and the metal layer 52b to promote graphene growth. For example, the thickness of the metal layer 52a is greater than the thickness of the metal layer 52b. This allows both the reduction in resistance and / or the heat transfer effect of each wiring and each pad to be improved.

[0193] The features of the second embodiment and the first to fourth modifications described above can be combined as appropriate, provided there is no contradiction. The features of the first to eighth modifications of the first embodiment can be combined as appropriate with the semiconductor devices 100 and 100A to 100D, provided there is no contradiction. For example, the semiconductor device 100 may be provided with the source opening 36 and the drain opening 38 of the first modification of the first embodiment. For example, the semiconductor device 100 may include the spacer layer 15 of the second modification of the first embodiment. For example, the semiconductor device 100 may include the insulating film 24 of the third modification of the first embodiment. For example, the semiconductor device 100 may include the p-type gate layer 26 of the fourth modification of the first embodiment. For example, the semiconductor device 100 may include the second electron supply layer 21 of the fifth or sixth modification of the first embodiment. The substrate 10 of the semiconductor device 100 may be a conductive substrate 10A or an insulating substrate 10B. The same applies to the semiconductor devices 100A to 100D.

[0194] Third Embodiment Next, a third embodiment will be described. In the third embodiment, a semiconductor device including a transistor with a double gate structure will be described. The following description will focus on the differences from the first embodiment and its modifications, and the description of commonalities will be omitted or simplified.

[0195] 20 is a cross-sectional view of a semiconductor device 200 according to the third embodiment. The semiconductor device 200 shown in Fig. 20 differs from the semiconductor device 1 according to the first embodiment in that it further includes a p-type gate layer 218 and a gate electrode 230. The semiconductor device 200 has a double-gate structure (also referred to as a dual-gate structure) including two gate electrodes 30 and 230.

[0196] The p-type gate layer 218 has the same configuration as the p-type gate layer 18 and is arranged side by side between the source electrode 32 and the drain electrode 34. The p-type gate layer 218 is electrically isolated from the p-type gate layer 18. In this embodiment, the second electron supply layer 20 is provided so as to cover not only the top surface 18a and the side surface 18b of the p-type gate layer 18, but also the top surface 218a and the side surface 218b of the p-type gate layer 218. The second electron supply layer 20 has an opening 222 for exposing at least a portion of the top surface 218a of the p-type gate layer 218.

[0197] The gate electrode 230 has the same configuration as the gate electrode 30, and is arranged side by side between the source electrode 32 and the drain electrode 34. The gate electrode 230 is electrically connected to the p-type gate layer 218 through an opening 222 provided in the second electron supply layer 20. Specifically, the gate electrode 230 is in contact with the upper surface 218a of the p-type gate layer 218 within the opening 222.

[0198] The gate electrode 230 and the gate electrode 30 can be set to different potentials. The semiconductor device 200 is a four-terminal drive device in which potentials can be set independently for the four electrodes, namely, the gate electrode 230, the gate electrode 30, the source electrode 32, and the drain electrode 34. By adjusting the potentials set for the four electrodes, namely, the gate electrode 230, the gate electrode 30, the source electrode 32, and the drain electrode 34, the semiconductor device 200 can be operated as a bidirectional device such as a bidirectional switch. The semiconductor device 200 can also function as a diode.

[0199] Note that the features of the semiconductor device 200 according to the first to eighth modifications of the first embodiment can be combined as appropriate, provided that no contradictions exist. For example, the semiconductor device 200 may be provided with the source opening 36 and the drain opening 38 according to the first modification of the first embodiment. For example, the semiconductor device 200 may include the spacer layer 15 according to the second modification of the first embodiment. For example, the semiconductor device 200 may include the insulating film 24 according to the third modification of the first embodiment. For example, the semiconductor device 200 may include the p-type gate layer 26 according to the fourth modification of the first embodiment. For example, the semiconductor device 200 may include the second electron supply layer 21 according to the fifth or sixth modification of the first embodiment. The substrate 10 of the semiconductor device 200 may be a conductive substrate 10A or an insulating substrate 10B.

[0200] Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a semiconductor device including a vertical transistor will be described. The following description will focus on differences from the first embodiment and its modifications, and description of commonalities will be omitted or simplified.

[0201] 21 is a cross-sectional view of a semiconductor device 300 according to the fourth embodiment. The semiconductor device 300 shown in FIG. 21 is a normally-off vertical FET. In the semiconductor device 300, a source electrode 332 is provided above a substrate 310, and a drain electrode 334 is provided below the substrate 310. Therefore, when the semiconductor device 300 is turned on, a drain current flows in the thickness direction of the substrate 310, i.e., in the vertical direction.

[0202] 21 , the semiconductor device 300 includes a substrate 310, a drift layer 311, a block layer 312, an underlayer 313, an electron transit layer 314, a first electron supply layer 316, a p-type gate layer 318, a second electron supply layer 320, a gate electrode 330, a source electrode 332, and a drain electrode 334. The substrate 310, the electron transit layer 314, the first electron supply layer 316, the p-type gate layer 318, the second electron supply layer 320, the gate electrode 330, the source electrode 332, and the drain electrode 334 correspond to the substrate 10, the electron transit layer 14, the first electron supply layer 16, the p-type gate layer 18, the second electron supply layer 20, the gate electrode 30, the source electrode 32, and the drain electrode 34 of the semiconductor device 1 according to the first embodiment, respectively. For corresponding components, differences will be mainly described.

[0203] The substrate 310 is a substrate made of a nitride semiconductor. The substrate 310 has a thickness of 300 μm and a carrier concentration of 1×10 １８ cm －３ n ＋ The substrate 310 is a substrate made of GaN of the nitride semiconductor type. The substrate 310 does not have to be a nitride semiconductor substrate. For example, the substrate 310 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like.

[0204] The drift layer 311 is an example of an n-type semiconductor layer provided above the substrate 310. The drift layer 311 is, for example, an n-type semiconductor layer having a thickness of 8 μm. － The drift layer 311 is a film made of GaN of the type. The donor concentration of the drift layer 311 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ As an example, １６ cm －３ The carbon concentration (C concentration) of the drift layer 311 is, for example, 1×10 １５ cm －３ 2 x 10 or more １７ cm －３ The drift layer 311 is provided in contact with, for example, the upper surface (main surface) of the substrate 310 .

[0205] The block layer 312 is an example of a third p-type semiconductor layer provided above the drift layer 311. The block layer 312 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The block layer 312 is a film made of p-type GaN, and is provided in contact with the upper surface of the drift layer 311.

[0206] Although the block layer 312 is formed by crystal growth, it may be formed by, for example, implanting magnesium (Mg) into the formed i-GaN. Furthermore, the block layer 312 may be an insulating layer obtained by implanting iron (Fe) or boron (B) instead of a p-type nitride semiconductor layer.

[0207] Furthermore, a high-resistance layer having a higher resistance than the block layer 312 and the drift layer 311 may be provided between the block layer 312 and the drift layer 311. The high-resistance layer is, for example, a carbon-doped GaN layer. By providing the high-resistance layer, punch-through can be suppressed and the breakdown voltage of the semiconductor device 300 can be increased.

[0208] In this embodiment, as shown in FIG. 21 , the block layer 312 is in contact with the source electrode 332. Therefore, the block layer 312 is fixed to the source potential applied to the source electrode 332. This achieves a high breakdown voltage for the semiconductor device 300. For example, when a reverse voltage is applied to the pn junction formed between the block layer 312 and the drift layer 311, specifically when the drain electrode 334 has a higher potential than the source electrode 332, a depletion layer extends to the drift layer 311, thereby enabling a high breakdown voltage for the semiconductor device 300. In this embodiment, the drain electrode 334 has a higher potential than the source electrode 332 in both the off and on states, except in the case of reverse conduction. This achieves a high breakdown voltage for the semiconductor device 300.

[0209] The base layer 313 is an example of a semiconductor layer provided between the block layer 312 and the electron transit layer 314. The base layer 313 is a high-resistance layer having a higher resistance than the block layer 312. The base layer 313 is, for example, a film made of undoped GaN (i-GaN) with a thickness of 200 nm. The base layer 313 is provided in contact with both the block layer 312 and the electron transit layer 314.

[0210] The underlayer 313 may be an insulating layer or a semi-insulating layer. For example, the underlayer 313 may be a film made of carbon-doped GaN (C—GaN). The carbon concentration of the underlayer 313 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The underlayer 313 may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the underlayer 313 is lower than the carbon concentration and oxygen concentration of the underlayer 313, and may be, for example, 5×10 １６ cm －３ or less than or equal to 2×10 １６ cm －３ It may be the following:

[0211] The semiconductor device 300 has an opening 325 that penetrates the base layer 313 and the block layer 312 and reaches the drift layer 311. The opening 325 is an example of a fourth opening. For example, the opening 325 has an elongated shape along the y-axis direction in a plan view of the substrate 310. The opening 325 is formed so that the opening area increases with increasing distance from the substrate 310. Specifically, a bottom surface 325a of the opening 325 is parallel to the major surface of the substrate 310, and a sidewall 325b of the opening 325 is obliquely inclined. As shown in FIG. 21 , the cross-sectional shape of the opening 325 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. The sidewall 325b may be perpendicular to the bottom surface 325a.

[0212] The electron transit layer 314, the first electron supply layer 316, and the second electron supply layer 320 are provided to cover the inner surface of the opening 325 and the upper part of the block layer 312. Specifically, the electron transit layer 314 contacts and covers the bottom surface 325a and sidewall 325b of the opening 325, as well as the upper surface of the base layer 313. The electron transit layer 314, the first electron supply layer 316, and the second electron supply layer 320 each have a curved shape that conforms to the inner surface of the opening 325. The 2DEG 317 generated near the interface between the electron transit layer 314 and the first electron supply layer 316 also has a curved shape that conforms to the inner surface of the opening 325.

[0213] The gate electrode 330 and the p-type gate layer 318 are provided at positions overlapping the upper surface of the block layer 312 in a plan view of the substrate 310. The gate electrode 330 and the p-type gate layer 318 are provided on both sides outside the opening 325 in the x-axis direction. The gate electrode 330 and the p-type gate layer 318 are provided between the opening 325 and the source electrode 332.

[0214] The source electrode 332 is provided at a position away from the opening 325 in a plan view of the substrate 310. In this embodiment, the source electrode 332 is provided so as to cover the source opening 336. The source electrode 332 can be in direct contact with the 2DEG 317 exposed on the sidewall 336b of the source opening 336. This can reduce the contact resistance of the source electrode 332 with the channel (2DEG 317).

[0215] The source opening 336 is an example of a first recess, and is recessed from the upper surface of the second electron supply layer 20 toward the substrate 310. Specifically, the source opening 336 penetrates the second electron supply layer 320, the first electron supply layer 316, and the electron transit layer 314 to reach the block layer 312. A bottom surface 336a of the source opening 336 is the upper surface of the block layer 312, but is not limited to this. The bottom surface 336a may be located below the interface between the block layer 312 and the underlayer 313, i.e., at a position closer to the substrate 310.

[0216] The drain electrode 334 is provided below the substrate 310. Specifically, the drain electrode 334 is provided in contact with the lower surface of the substrate 310.

[0217] 21 , the semiconductor device 300 includes an interlayer insulating film 60, a source wiring 52, a graphene cap layer 58, and a protective film 80. The interlayer insulating film 60, the source wiring 52, the graphene cap layer 58, and the protective film 80 are the same as the interlayer insulating film 60, the source wiring 52, the graphene cap layer 58, and the protective film 80 included in the semiconductor device 100 according to the second embodiment. The semiconductor device 300 may also include the gate pad 50G and the source pad 52S according to the second embodiment. Note that the interlayer insulating film 60, the source wiring 52, the graphene cap layer 58, and the protective film 80 do not necessarily have to be provided.

[0218] In this manner, even in the semiconductor device 300 including a vertical transistor, the first electron supply layer 316 and the p-type gate layer 318 can be continuously formed. This prevents impurities such as siloxane from being mixed into the interface between the first electron supply layer 316 and the p-type gate layer 318. This allows the transistor threshold to be stabilized while realizing normally-off operation. Furthermore, since the first electron supply layer 316 and the second electron supply layer 320 are provided in the portion where the p-type gate layer 318 is not provided, it is possible to achieve reduced on-resistance and suppression of current collapse, similar to the semiconductor device 1 according to the first embodiment.

[0219] In this embodiment, the p-type block layer 312 set to the source potential and the source wiring 52 are provided to surround the p-type gate layer 318. The block layer 312 and the source wiring 52 function as a source field plate, thereby reducing the gate-drain capacitance Cgd.

[0220] An example of a method for manufacturing the semiconductor device 300 is as follows. First, semiconductor films that will form the drift layer 311, the block layer 312, and the base layer 313 are formed above the substrate 310 by crystal growth using an epitaxial growth method such as MOCVD or HVPE. By adjusting growth conditions such as the raw materials, growth temperature, and growth time, the composition, film thickness, impurity concentration, and the like can be adjusted to values ​​appropriate for each layer. The formation of the base layer 313 may be omitted. Next, an opening 325 is formed that penetrates the base layer 313 and the block layer 312 and reaches the drift layer 311. The opening 325 is formed by, for example, dry etching or the like.

[0221] Next, semiconductor films that will form the electron transit layer 314, the first electron supply layer 316, and the p-type gate layer 318 are formed by crystal growth, such as an epitaxial growth method like MOCVD or HVPE, so as to cover the inner surface of the opening 325 and the upper surface of the base layer 313. By adjusting growth conditions such as the raw materials, growth temperature, and growth time, it is possible to obtain appropriate values ​​for the composition, film thickness, impurity concentration, and the like for each layer. The electron transit layer 314, the first electron supply layer 316, and the p-type gate layer 318 are formed consecutively in the same growth furnace without being exposed to the atmosphere during the process.

[0222] Next, the p-type semiconductor film that will become the base of the p-type gate layer 318 is patterned into a predetermined shape to form the p-type gate layer 318. The patterning is performed by dry etching or the like, similar to the formation of the p-type gate layer 18 in the first embodiment.

[0223] Next, a semiconductor film that will become the base of the second electron supply layer 320 is formed by crystal growth, such as an epitaxial growth method, such as MOCVD or HVPE, so as to cover the top surface 318 a and side surface 318 b of the p-type gate layer 318. As in the formation of the second electron supply layer 20 according to the first embodiment, the crystal growth is performed at a high temperature, thereby repairing damage to the side surface 318 b of the p-type gate layer 318.

[0224] Next, after forming a source opening 336 by dry etching or the like, the source electrode 332, the gate electrode 330, and the drain electrode 334 are formed. The order in which the source electrode 332, the gate electrode 330, and the drain electrode 334 are formed is not particularly limited. For example, the drain electrode 334 may be formed after the gate pad 50G, the source pad 52S, and the like are formed.

[0225] Next, an interlayer insulating film 60 is formed by plasma CVD or the like, and then openings are formed to expose portions of the source electrode 332 and the gate electrode 330, followed by the formation of the source wiring 52, gate wiring 50, source pad 52S, and gate pad 50G. Each wiring and each pad is formed by plating or the like. After forming a metal film by sputtering or vapor deposition or the like, each wiring and each pad may be formed by patterning by etching, lift-off, or the like.

[0226] After forming the wirings and pads, graphene is grown to form the graphene cap layer 58. Thereafter, a protective film 80 made of a polymer material is formed by spin coating or the like.

[0227] In this manner, it is possible to manufacture the semiconductor device 300 shown in Fig. 21. The above-described method for manufacturing the semiconductor device 300 is merely an example, and can be modified as appropriate.

[0228] While the semiconductor device and the manufacturing method thereof according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0229] For example, the semiconductor device does not have to be a nitride semiconductor device. That is, the semiconductor layers included in the semiconductor device may contain a semiconductor other than a nitride semiconductor as a main component. For example, the electron transit layer, the first electron supply layer, the p-type semiconductor layer, and the second electron supply layer may contain gallium arsenide (GaAs) as a main component. Alternatively, the electron transit layer, the first electron supply layer, the p-type semiconductor layer, and the second electron supply layer may contain Si or SiC as a main component.

[0230] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0231] The semiconductor device according to the present disclosure can be used for power transistors used in power supply circuits such as main inverters mounted on various electric vehicles (xEVs: Electric Vehicles), on-board chargers, and general-purpose inverters such as power conditioners.

[0232] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 100, 100A, 100B, 100C, 100D, 200, 300 Semiconductor device 10, 10A, 10B, 310 Substrate 12 Buffer layer 14, 314 Electron transit layer 15 Spacer layer 16, 316 First electron supply layer 16a, 18a, 218a, 318a Upper surface 17, 19, 317 2DEG 18, 26, 218, 318 P-type gate layer 18A P-type semiconductor layer 18b, 218b, 318b Side surface 18c Damaged region 20, 21, 320 Second electron supply layer 22, 92a, 222 Opening 24 Insulating film 30, 230, 330 Gate electrode 32, 332 Source electrode 34, 334 Drain electrode 36, 36E, 336 Source opening 36a, 38a, 325a, 336a Bottom surface 36b, 38b, 325b, 336b Side wall 38, 38E Drain opening 40 Back electrode 50 Gate wiring 50G Gate pad 52 Source wiring 52a, 52b Metal layer 52S Source pad 54 Drain wiring 54D Drain pad 56 Source via hole 58 Graphene cap layer 60 Interlayer insulating film 70 Gate terminal 72 Source force terminal 73 Source sense terminal 74 Drain terminal 76 Die frame 78, 78d, 78g, 78sf, 78ss Wire 80 Protective film 90, 92 Resist 101 Active region 102 Element isolation region 311 Drift layer 312 Block layer 313 Underlayer 325 Opening

Claims

A substrate; an electron transit layer provided above the substrate; a first electron supply layer provided above the electron transit layer; a first p-type semiconductor layer provided above the first electron supply layer; a second electron supply layer provided above the first electron supply layer so as to cover an upper surface and a side surface of the first p-type semiconductor layer; a gate electrode electrically connected to the first p-type semiconductor layer through an opening provided in the second electron supply layer; Semiconductor devices. 　 a source electrode and a drain electrode provided above the first electron supply layer and electrically connected to the electron transit layer; The semiconductor device of claim 1 . 　 the source electrode is provided so as to cover a first recess that is recessed from the upper surface of the second electron supply layer toward the substrate, the drain electrode is provided so as to cover a second recess that is recessed from the upper surface of the second electron supply layer toward the substrate; The semiconductor device of claim 2 . 　 the first recess and the second recess each penetrate the second electron supply layer to reach the first electron supply layer; The semiconductor device of claim 3 . 　 the first recess and the second recess penetrate the second electron supply layer and the first electron supply layer, respectively, to reach the electron transit layer; The semiconductor device of claim 3 . 　 a spacer layer provided between the electron transit layer and the first electron supply layer, the spacer layer having a band gap larger than both the electron transit layer and the first electron supply layer; The semiconductor device according to any one of claims 1 to 5. 　 further comprising an insulating film provided between the gate electrode and the second electron supply layer; The semiconductor device according to any one of claims 1 to 5. 　 a second p-type semiconductor layer provided between the first electron supply layer and the first p-type semiconductor layer, the second p-type semiconductor layer having a band gap smaller than both the first electron supply layer and the first p-type semiconductor layer; The semiconductor device according to any one of claims 1 to 5. 　 the first electron supply layer is a nitride semiconductor layer containing at least one of In, Al, and Ga; the second electron supply layer is a nitride semiconductor layer containing at least one of In, Al, and Ga; The semiconductor device according to any one of claims 1 to 5. 　 the first electron supply layer is a nitride semiconductor layer containing at least one of In, Al, and Ga; the second electron supply layer is an oxide layer containing gallium oxide as a main component; The semiconductor device according to any one of claims 1 to 5. 　 a plurality of the gate electrodes; the plurality of gate electrodes are provided between the source electrode and the drain electrode in a plan view of the substrate, and different potentials can be set to the gate electrodes; The semiconductor device according to any one of claims 2 to 5. 　 a backside electrode provided below the substrate and electrically connected to the source electrode; The substrate is electrically conductive. The semiconductor device according to any one of claims 2 to 5. 　 a backside electrode provided below the substrate and electrically connected to the source electrode; The substrate has insulating properties. The semiconductor device according to any one of claims 2 to 5. 　 the semiconductor device can be divided into an active region and an isolation region in a plan view of the substrate; a source pad provided in the element isolation region so as to cover a third opening extending from the second electron supply layer to at least the substrate; a source wiring provided above the source electrode in the active region and electrically connected to the source pad and the source electrode; a drain pad provided in the element isolation region and above the second electron supply layer; a drain wiring provided above the drain electrode in the active region and electrically connected to the drain pad and the drain electrode; a back electrode provided below the substrate, the rear surface electrode is electrically connected to the source pad through the third opening. The semiconductor device according to any one of claims 2 to 5. 　 an interlayer insulating film provided between the second electron supply layer and the source pad, the source wiring, the drain pad, and the drain wiring; 15. The semiconductor device of claim 14. 　 a graphene cap layer covering at least one surface of the source pad, the drain pad, the source wiring, and the drain wiring; 15. The semiconductor device of claim 14. 　 At least a portion of each of the source pad, the drain pad, the source wiring, and the drain wiring is made of at least one metal selected from the group consisting of Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these metals.

17. The semiconductor device of claim 16. 　 At least a portion of each of the source pad, the drain pad, the source wiring, and the drain wiring is a first metal layer made of Pd, Ag, or Au; a second metal layer formed on a surface of the first metal layer and made of at least one metal selected from Cu, Ru, Ir, Rh, Pt, Fe, Co, and Ni, or an alloy containing at least two of these metals; 17. The semiconductor device of claim 16. 　 a protective film containing a polymer material provided above the source wiring and the drain wiring; 15. The semiconductor device of claim 14. 　 an n-type semiconductor layer provided above the substrate; a third p-type semiconductor layer provided above the n-type semiconductor layer; a source electrode provided above the first electron supply layer and electrically connected to the electron transit layer; a drain electrode provided below the substrate, the electron transit layer, the first electron supply layer, and the second electron supply layer are provided so as to cover an inner surface of a fourth opening that penetrates the third p-type semiconductor layer and reaches the n-type semiconductor layer, and an upper portion of the third p-type semiconductor layer; the gate electrode and the first p-type semiconductor layer are provided at positions overlapping an upper surface of the third p-type semiconductor layer in a plan view of the substrate; The semiconductor device of claim 1 . 　 forming an electron transit layer, a first electron supply layer, and a first p-type semiconductor layer in this order above a substrate by crystal growth; patterning the first p-type semiconductor layer into a predetermined shape by removing a portion of the first p-type semiconductor layer; forming a second electron supply layer by crystal growth so as to cover the patterned first p-type semiconductor layer and the first electron supply layer; removing a portion of the second electron supply layer to expose at least a portion of an upper surface of the first p-type semiconductor layer; forming a gate electrode so as to cover the exposed portion of the top surface of the first p-type semiconductor layer; A method for manufacturing semiconductor devices.

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