Voltage RAMP generator for analog-to-digital conversion and solid-state imaging device

Abstract

A voltage ramp generator includes unit cells (331) electrically connected in parallel. Each unit cell switches between an on-state and an off-state in response to a cell-specific select signal (S1-Sn). A current mirror circuit (350) copies a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch. An error detection circuit (390) generates an active first error signal (ERR) if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

Description

[0001] 73656

[0002] 1

[0003] VOLTAGE RAMP GENERATOR FOR ANALOG-TO-DIGITAL CONVERSION AND SOLID-

[0004] STATE IMAGING DEVICE

[0005] The present disclosure relates to a voltage ramp generator for analog-to-digital conversion. More particularly, the present disclosure relates to a voltage ramp generator for analog-to-digital conversion of pixel voltages in solid-state imaging devices and to a solid-state imaging device including a voltage ramp generator.

[0006] BACKGROUND

[0007] Active image sensors in solid-state imaging devices include photoelectric conversion elements that generate a photocurrent with a current rating that is proportional to the received radiation intensity. A pixel circuit converts the small photocurrent into a pixel voltage with a comparatively large voltage amplitude. A downstream analog-to-digital converter converts the pixel voltage from the pixel circuit into a digital pixel value. For this purpose, the analog-to-digital converter comprises a voltage ramp generator outputting a falling voltage ramp signal, a comparator circuit that compares the pixel voltage with the falling voltage ramp signal, and a counter circuit that counts regular clock pulses until the voltage level of the voltage ramp signal falls below the voltage level of the pixel voltage. The number of counted clock pulses results in the digital pixel value. The digital pixel values obtained from all pixel circuits of the image sensor for the same exposure describe a digital image. Computer vision methods utilize automatic feature recognition and extraction methods to obtain relevant information from the digital image or a digital image sequence in order to control higher-level processes in the fields of surveillance, information gathering, and automated process control.

[0008] SUMMARY

[0009] Failures in the voltage ramp signal can distort the digital images and affect the results of computer vision methods that use the image information obtained from the digital images. In production-level test methods, the voltage ramp generator is controlled to generate a ramp signal pattern. The comparator circuit of an analog-to-digital converter receives the ramp signal pattern and compares the ramp signal pattern with a predefined reference voltage supplied to the pixel signal line to control the counter of the analog-to-digital converter. A digital core compares the digital results of the analog-to-digital conversion with target values, and a failure flag is asserted if a deviation between a target value and a corresponding digital result of the analog-to-digital conversion is outside a predefined permissible range. The present disclosure has been made in view of the above circumstances, and it is therefore sought to provide a voltage ramp generator that outputs reliable information about the status and functionality of the voltage ramp generator.

[0010] The present disclosure inter alia mitigates deficiencies in production-level testing. For this purpose, a voltage ramp generator according to the present disclosure includes unit cells electrically connected in parallel. Each unit cell switches between an on-state and an off-state in response to a cell-specific select signal. A current mirror circuit copies a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch. An error detection circuit generates an 73656

[0011] 2 active first error signal if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

[0012] The current mirror circuit provides the basis for an economic built-in self-test (BIST) capability for a digital-to-analog converter part of the voltage ramp generator. The switches and currents in the unit cells can be tested one by one and independently from other components of the voltage ramp generator and the analog -to-digital conversion part converting the analog pixel voltage into the digital pixel value. The result is not affected by the accuracy of the further components of the pixel readout periphery such as reference voltages or by noise in the readout chain. Testing on production level becomes less complex. The BIST can also be performed after each power-up and / or even repeated in test periods after power-up.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0015] FIG. l is a schematic block diagram illustrating an imaging apparatus as an example for an electronic device including a solid-state imaging device with voltage ramp generator with BIST capability in accordance with the embodiments.

[0016] FIG. 2 is a simplified block diagram illustrating a configuration example of a solid-state imaging device that includes a voltage ramp generator with BIST capability in accordance with an embodiment.

[0017] FIG. 3 is a simplified circuit diagram of a voltage ramp generator including a current mirror circuit for one detection branch in accordance with an embodiment.

[0018] FIG. 4 is a simplified circuit diagram of a voltage ramp generator including a current mirror circuit for one detection branch, an accumulator resistor and electronic switches to control operation modes of the voltage ramp generator in accordance with an embodiment.

[0019] FIG. 5 is a simplified circuit diagram of a voltage ramp generator including a current mirror circuit for two detection branches in accordance with another embodiment.

[0020] FIG. 6 is a circuit diagram of an error detection circuit of the voltage ramp generator of FIG. 5 in accordance with an embodiment.

[0021] FIG. 7 is a timing diagram illustrating control signals and output signals of the voltage ramp generator of

[0022] FIG. 5 with an error detection circuit as illustrated in FIG. 6 in accordance with an embodiment. 3

[0023] FIG. 8 is a simplified circuit diagram of a voltage ramp generator including a current mirror circuit with a reference field effect transistor and two detection field effect transistors for two detection branches in accordance with another embodiment.

[0024] FIG. 9 is a simplified block diagram illustrating a configuration example of a solid-state imaging device that includes a voltage ramp generator with BIST capability in accordance with another embodiment.

[0025] FIG. 10 is a diagram showing an example of a laminated structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0026] FIG. 11 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0027] FIG. 12 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 11.

[0028] DETAILED DESCRIPTION

[0029] Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

[0030] Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. Directly electrically connected electronic elements are connected through a low-resistive wiring, an ohmic contact and / or a unipolar semiconductor junction.

[0031] The load path of a transistor is the controlled current path through a transistor. A voltage applied to the gate of a field effect transistor controls the current flow through the load path (controlled path) between source and drain of the FET by field effect.

[0032] A digital signal alternates between at least one active level and at least one inactive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. For each signal separately, the active level can be a digital high level and the inactive level a digital low level, or the active level can be the digital low level and the inactive level the digital high level. 4

[0033] Though in the following a technology for voltage ramp generator failure detection in solid-state imaging devices is described in the context of certain types of row-wise pixel readouts, the technology may also be used for other types of pixel circuits and other pixel readout schemes.

[0034] In FIG. 1, an imaging apparatus 1 includes an optical system 91, a solid-state imaging device 90, a storage unit 92, and a control unit 93. The optical system 91 includes one or more lenses and various mechanisms such as an autofocus mechanism and a diaphragm mechanism, and guides light from an object to a light receiving surface of the solid-state imaging device 90.

[0035] The solid-state imaging device 90 includes an image sensor assembly having a plurality of active pixel circuits for intensity readout. Each pixel circuit converts incident radiation into electric signals by photoelectric conversion, and outputs pixel voltages with a voltage level monotonically increasing with increasing intensity of the incident radiation. The solid-state imaging device 90 converts the pixel voltages into digital pixel values and further includes a signal processing unit that performs predetermined signal processing on the digital pixel values to obtain image data.

[0036] The storage unit 92 stores the image data, e.g., frames output from the solid-state imaging device 90 in a storage medium. The storage medium may include a volatile storage medium and / or non-volatile storage medium. The non-volatile storage medium may be or include a flash memory or a hard disk drive. The nonvolatile storage medium may be or include a dynamic random -access memory (DRAM).

[0037] The control unit 93 controls the solid-state imaging device 90 such that the solid-state imaging device 90 performs an imaging operation. The imaging operation includes obtaining images from a scene and outputting image data including information about the images.

[0038] FIG. 2 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 includes a signal processing unit 80 and an image sensor assembly 70. The image sensor assembly 70 includes a row decoder / driver 30, a pixel array 10, a group signal processing unit 20 that includes a plurality of group signal processing circuits 200, a digital readout unit 40, and a sensor controller 50.

[0039] The pixel array unit 10 includes a plurality of identical pixel circuits 100. The pixel circuits 100 may be any active pixel sensors (APS) for intensity readout with one or two photoelectric conversion elements and three, four or more pixel transistors. The pixel circuits 100 convert incident radiation into a pixel internal voltage that is a monotonic function of the intensity of incident radiation detected by the pixel circuit 100 in an exposure period. When a pixel circuit 100 is selected in a row readout period, the selected pixel circuit 100 outputs a pixel voltage controlled by the pixel internal voltage to a pixel signal line 19.

[0040] The pixel circuits 100 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column form a pixel column. A subset of pixel circuits 100 assigned to the same row form a pixel row. 5

[0041] The row decoder / driver 30 controls the pixel circuits 100 by generating pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control reset states, exposure time, internal temporal storage of the illumination information, and the readout of the pixel circuits 100. The row decoder / driver 30 outputs the control signals for operating the pixel transistors of the pixel circuits 100 on pixel control lines 13 according to driver timing signals supplied from the sensor controller 50.

[0042] The row decoder / driver 30 controls all pixel circuits 100 of a selected group of pixel circuits 100 synchronously. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row, all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. The following part of the description refers toe “pixel rows” as examples for “groups of pixel circuits” for simplicity.

[0043] The pixel circuits 100 of a pixel output group sequentially pass information about the pixel internal voltage that depends on an illumination intensity detected by the pixel circuits 100 in an exposure period to at least one pixel signal line (vertical signal line) 19. Each pixel output group may include some pixel circuits 100 of one pixel column, all pixel circuits 100 of one pixel column, or some or all pixel circuits 100 of more than one pixel column. The following part of the description refers to “pixel columns” as examples for “pixel output groups” for simplicity.

[0044] Each pixel circuit 100 includes an amplifier transistor 102 in a source follower configuration with an element of the group signal processing unit 20. A load path of the amplifier transistor 102 is electrically connected between a positive pixel supply potential VDDH and the pixel signal line 19. Each pixel signal line 19 sequentially conveys the pixel voltages from the pixel circuits 100 of one of the pixel columns to the group signal processing unit 20.

[0045] The column signal processing unit 20 includes a column signal processing circuit 200 for each pixel signal line 19, at least one voltage ramp generator 300 and at least one counter circuit 26. The column signal processing circuit 200 converts the pixel voltage into digital pixel values, may preprocess the digital pixel values and outputs the digital pixel values or the preprocessed digital pixel values to the digital readout unit 40. Each column signal processing circuit 200 includes a constant current source 210, a comparator circuit 220, and a digital counting circuit 230.

[0046] The constant current source 210 complements the amplifier transistor 102 of the selected pixel circuit 100 to a source follower that outputs the pixel voltage of a selected pixel circuit 100 to a first input of the comparator circuit 220 in a row readout period. The constant current source 210 sinks a constant current.

[0047] The column signal processing unit 20 may include one voltage ramp generator 300 for each column signal processing circuit 200. In the illustrated example, one single global voltage ramp generator 300 supplies the same voltage ramp signal VRMP to all column signal processing circuits 200.

[0048] The voltage ramp generator 300 may output the voltage ramp signal VRMP in response to an active ramp enable signal REN. The voltage ramp signal VRMP includes a ramp section in which the voltage ramp 6 signal VRMP falls from a high voltage level to a low voltage level continuously or in small steps. The voltage ramp signal VRMP is applied to the second inputs of the comparator circuits 220 in the row readout periods. The comparator circuit 220 outputs an active comparator output signal when the voltage level of the voltage ramp signal VRMP falls below the voltage level of the pixel voltage applied to the first input of the comparator circuit 220.

[0049] The voltage ramp generator 300 includes a BIST circuit and outputs an active error flag signal ERR when an error condition is fulfilled, wherein the error condition indicates a malfunction of a component of the voltage ramp generator 300. The error flag signal ERR can be transmitted to the sensor controller 50 and / or to a signal interface of the image sensor assembly 70.

[0050] The column signal processing unit 20 may include one counter circuit 26 or each column signal processing circuit 200. In the illustrated example, one global counter circuit supplies the same count signals to all column signal processing circuits 200.

[0051] The counter circuit 26 outputs a digital count value of a digital counter on a digital bus to data inputs of the digital counting circuits 230 in response to an active count enable signal CEN. The active count enable signal CEN and the active ramp enable signal REN have a predetermined temporal relationship to each other and to the beginning of the row readout period. The digital counting circuit 230 latches the current count value applied to the data inputs with a transition from an inactive comparator output signal to the active comparator output signal. The latched count value represents the digital pixel value of the pixel voltage obtained from the pixel circuit 100 in the row readout period. The comparator circuit 220 and the digital counting circuit 230 form an analog-to-digital converter. The digital readout unit 40 may store digital values obtained in data phases and preset phases for correlated double sampling (CDS) and / or digital double sampling (DDS). The digital readout unit 40 receives and temporarily stores the digital pixel values from the column signal processing unit 20.

[0052] The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the row decoder / driver 30. The sensor controller 50 generates the ramp enable signal REN and / or other signals for controlling the voltage ramp generator 300, and the count enable signal CEN for controlling the counter circuit 26. The sensor controller 50 may generate a readout control signal that controls the readout of the digital values from the readout digital readout unit 40 to the signal processing unit 80 and / or to a digital interface. The sensor controller 50 may also control the BIST portion of the voltage ramp generator 300.

[0053] FIG. 3 shows the voltage ramp generator 300 of FIG. 2. The voltage ramp generator 300 includes unit cells 330 which are electrically connected in parallel. Each unit cell 330 is configured to switch between an on- state and an off-state in response to a cell-specific select signal SI, S2, . . . , Sn. A current mirror circuit 350 is configured to copy a reference current IREF controlled by the unit cells 330 at a predefined current ratio into a first detector current ID1 flowing in a first detection branch 370. An error detection circuit 390 is configured to generate an active first error signal ERR1 if the first detector current ID 1 exceeds an upper threshold current ITH1 or falls below a lower threshold current ITH2. 7

[0054] Each unit cell 330 may supply an integer multiple k of a nominal unit current 10. For example, the integer multiple k for all unit cells 330 may be equal 1. Alternatively, for a voltage ramp generator 300 with n unit cells, the integer multiple k for the unit cells 330 may increase according to 2mwith m increasing from 0 to k-1.

[0055] In the illustrated embodiment, each unit cell 330 includes a unit field effect transistor 331 and a unit switch 333 electrically connected in series between a positive supply potential VDD and a current summation node 339.

[0056] The cell-specific select signals SI, S2, ... , Sn control the unit switches 333 in order to provide a desired total current at the current summation node 339, wherein an active cell-specific select signal SI, S2, . . . , Sn switches on the respective unit switch 333 and an inactive cell-specific select signal SI, S2, . . . , Sn switches off the respective unit switch 333. The unit switches 333 may be FETs receiving the cell-specific select signals SI, S2, ... , Sn at the gates.

[0057] The unit field effect transistors 331 may be p channel field effect transistors (pFETs) receiving a constant voltage bias V0 at the gates. The unit field effect transistors 331 may have a same channel length. More particularly, the unit field effect transistors 331 may be processed side-by-side so that significant transistor dimensions including the channel lengths are to a high degree identical. The unit field effect transistors 331 may have the same channel widths or integer multiples of a unit channel width.

[0058] The voltage ramp generator 300 includes further elements for converting the total current flowing through the active unit cells 330 into a voltage ramp signal VRMP and for controlling a change of the operation mode of the voltage ramp generator 300 between a conversion mode in conversion periods and a test mode in test periods.

[0059] The voltage ramp generator 300 may be in the test mode for tests on production level. Alternatively or in addition, the voltage ramp generator 300 may change from the conversion mode to the test mode directly after power-up, at regular intervals, in response to a change in an operating condition, and / or in response to a specific control signal.

[0060] In the conversion mode, the voltage ramp generator 300 outputs a voltage ramp signal VRMP, wherein the voltage ramp signal VRMP includes periods of constant voltage and periods of linearly decreasing or increasing voltage. The current mirror circuit 350 may be disabled and / or a signal path between the current summation node 339 and the current mirror circuit 350 may be interrupted. The cell-specific select signals SI, S2, ... , Sn can be controlled to digitally count down by one from a high digital count value to a low digital count value, so that the total current provided at the current summation node 339 is reduced by the unit current 10 with each count value.

[0061] In the test mode, the total current through the active unit cells 330 delivers the reference current IREF. The current mirror circuit 350 copies the reference current IREF into the first detector current IDE Apart from the current mirror circuit 350 and the unit cells 330, the current summation node 339 may be isolated such 8 that the total current through the unit cells 330 flows through the current mirror circuit 350. The cell-specific select signals SI, S2, . . . , Sn can be controlled in such a way that the unit switches 333 are switched on and off individually one after the other and only one of the unit field effect transistors 331 supplies current at a time.

[0062] The current mirror circuit 350 includes at least a first transistor between the current summation node 339 and a reference supply potential VSS and a second transistor through which the first detector current ID1 flows when the current mirror circuit 350 is active.

[0063] The first transistor and the second transistor may form a differential pair with equal nominal characteristics and low transistor-to-transistor deviations, wherein the predetermined current ratio ID I : IREF between the first detector current ID 1 and the reference current can be equal 1.

[0064] The current mirror circuit 350 may have a Widlar current mirror configuration with only the first transistor in the reference branch and only the second transistor in the first detection branch 370, a Wilson current mirror with an additional transistor in the first detection branch 370, or any other type of current mirror.

[0065] In a test period, the unit cells 330 are successively turned on and off one-by-one. When a unit cell 330 is turned on, the unit cell 330 is active and the actual current through the respective unit cell 330 provides the reference current IREF for the current mirror circuit 350. The current mirror circuit 350 copies the reference current IREF at the predefined current ratio into the first detector current ID 1 in the first detection branch 370. In the first detection branch 370 a deviation of the reference current IREF from the nominal unit current 10 is assessed.

[0066] The first detector load 375 supports the assessment of the first detector current ID1 through a voltage or current comparison. For example, the first detector load 375 may generate a voltage drop which is a function of the first detector current ID1, wherein the error detection circuit 390 includes a voltage comparator comparing the voltage drop with one reference voltage or two reference voltages. Other examples may directly compare the first detector current ID 1 with a constant threshold current and detect the current flow direction of a differential current between the constant threshold current and the first detector current IDE

[0067] The error detection circuit 390 may generate an active first error signal ERR1 if the first detector current ID1 exceeds an upper threshold current ITH1 or falls below a lower threshold current ITH2 and in this way tests whether the components of the respective unit cell 330 comply with predefined requirements.

[0068] The current mirror circuit 350, the detection branch 370 and the error detection circuit 390 form a self- contained, compact BIST circuit with low complexity, which enables fast testing of the critical components of the voltage ramp generator 300 with high accuracy.

[0069] FIG. 4 shows a voltage ramp generator 300 with an accumulator resistor 342 and a first electronic switch 344 electrically connected in series with each other and with the unit cells 330, wherein the first electronic switch 344 is configured to switch off a current flow through the accumulator resistor 342 in a test period. 73656

[0070] 9

[0071] In the operation periods, an active conversion enable signal RD_EN turns on the first electronic switch 344 and the accumulator resistor 340 adds up the currents through all active unit cells 330. The voltage ramp signal VRMP can be tapped across the accumulator resistor 340. An instantaneous voltage level of the voltage ramp signal VRMP depends on the digital number applied via the cell-specific select signals SI, S2, . . . , Sn. In the test periods, the conversion enable signal RD_EN is inactive and the first electronic switch 344 is off.

[0072] The first electronic switch 344 may be a single field effect transistor or a combination of field effect transistors, e.g., a transmission gate.

[0073] The voltage ramp generator 300 of FIG. 4 further includes a second electronic switch 346 electrically connected in series with the unit cells 330, wherein the second electronic switch 346 is configured to switch on the reference current IREF through the current mirror circuit 350 in a test period.

[0074] In the test periods, an active test enable signal BIST_EN turns on the second electronic switch 346 and the total current through the active unit cells 330 determines the reference current IREF in a reference branch of the current mirror circuit 350. The instantaneous reference current IREF is a function of the digital number applied via the cell-specific select signals SI, S2, ... , Sn. For example, only one of the unit cells 330 is active at a time. In the conversion periods, the test enable signal BIST_EN can be inactive and the second electronic switch 346 can be off.

[0075] The second electronic switch 344 may be a single field effect transistor or a combination of field effect transistors, e.g., a transmission gate.

[0076] The voltage ramp generator 300 may include more than one detection branch and may include one single detection branch 370 in cases when it is known that one failure pattern dominates the other, for example, when only deviations to higher unit currents are expected.

[0077] In FIG. 5, the voltage ramp generator 300 includes a current mirror circuit 350 that is further configured to copy the reference current IREF at a predefined current ratio into a second detector current ID2 flowing in a second detection branch 380, wherein the error detection circuit 390 is configured to generate the active first error signal ERR1 when the first detector current ID1 exceeds the upper threshold current ITH1 and generate an active second error signal ERR2 when the second detector current ID2 falls below the lower threshold current ITH2.

[0078] The first detector current ID1 and the second detector current ID2 may be different, e.g. different integer multiples of the nominal unit current 10. In the following examples, the first detector current ID1 and the second detector current ID2 are equal.

[0079] The first detector load 375 may include a constant current source supplying the upper threshold current ITH1 (I0+ITH). As long as the reference current IREF supplied from a unit cell 330 is lower than the upper 73656

[0080] 10 threshold current ITH1, the error detection circuit 390 drains the differential current between the reference current IREF and the upper threshold current ITH1. When the reference current IREF supplied from the unit cell 330 exceeds the upper threshold current ITH1, the error detection circuit 390 supplies the differential current. The error detection circuit 390 detects the change of a flow direction of the differential current and generates an active first error signal ERR1.

[0081] Analogously, the second detector load 385 may include a constant current source supplying the lower threshold current ITH2 (I0-ITH). The second detector load 385 may include a constant current source supplying the lower threshold current ITH2. As long as the reference current IREF supplied from a unit cell 330 is higher than the lower threshold current ITH2, the error detection circuit 390 supplies the differential current between the reference current IREF and the lower threshold current ITH2. When the reference current IREF supplied from the unit cell 330 falls below the lower threshold current ITH2, the error detection circuit 390 drains the differential current. The error detection circuit 390 detects the change of the flow direction of the differential current and generates an active second error signal ERR2.

[0082] With two different detection branches, the BIST circuit can detect both when the reference current IREF is too low and when the reference current IREF is too high.

[0083] FIG. 6 shows an error detection circuit 390 that is configured to generate an active error flag signal ERR when the first error signal ERR1 and / or the second error signal ERR2 are / is active.

[0084] The error detection circuit 390 includes a first comparator circuit 391 configured to output the first error signal ERR1 when the first detector current ID1 exceeds the upper threshold current ITH1, and a second comparator circuit 392 configured to output the second error signal ERR2, when the second detector current ID2 falls below the lower threshold current ITH2. The first comparator circuit 391 may include a noninverting Schmitt trigger. The second comparator circuit 392 may include an inverting Schmitt trigger, e.g. a non-inverting Schmitt trigger and an inverter inverting the output signal of the non-inverting Schmitt trigger.

[0085] The error detection circuit 390 may output the first and second error signals ERR1, ERR2 independently from each other in order to inform a high-level processing instance in more detail about the fault type detected.

[0086] In the illustrated embodiment, the error detection circuit 390 further includes a gate circuit 398 configured to output an active signal when at least one of the first and second error signals ERR1, ERR2 is active.

[0087] Further in the illustrated embodiment, the error detection circuit 390 includes a latch circuit 399 configured to latch the error flag signal ERR in response to a clock signal CLK.

[0088] The latch circuit 399 may latch the output signal of the gate circuit 398 in response to a rising or falling edge of a clock signal CLK. The error detection circuit 390 outputs the latched signal output form the latch circuit 399 as the error flag signal ERR. 73656

[0089] 11

[0090] FIG. 7 shows a timing diagram with the control signals for the voltage ramp generator 300 of FIG. 5, the clock signal CLK for the error detection circuit 390 of FIG. 6, and with the error flag signal ERR output from the error detection circuit 390. In this example, the active level is the logic “high” level, and the inactive level is the logic “low” level for all control signals.

[0091] In the example shown, all control signals are controlled synchronously and change with the rising edge of the clock signal CLK. Alternatively, the control signals may change synchronously with the falling edge of the clock signal CLK, or at least one control signal can change independently of the clock signal CLK.

[0092] At t=tO, the voltage ramp generator 300 is in the conversion mode with active conversion enable signal RD_EN and inactive test enable signal BIST_EN. At t=t 11, the conversion enable signal RD_EN changes to inactive and the test enable signal BIST_EN to active. The voltage ramp generator 300 changes into the test mode and the test period begins.

[0093] Synchronously, the cell-specific select signal S 1 for the first unit cell 330 becomes active, while the other cell-specific select signals 2, ... , Sn remain inactive. The first unit cell 330 is under test and the result of the comparison is valid shortly after as indicated by the period CS0. At t=t 12, the latch circuit 399 latches the result for the test of the first unit cell 330 with the falling edge of the clock signal CLK. The resulting latched error flag signal ERR is inactive (“0”) if the current supplied by the first unit cell 330 is within a predefined permissible range.

[0094] With the next rising edge of the clock signal CLK at t=t21, the cell-specific select signal SI for the first unit cell 330 becomes inactive, the cell-specific select signal S2 for the second unit cell 330 becomes active, and the other cell-specific select signals 3, ... , Sn remain inactive. The second unit cell 330 is under test and the result of the comparison is valid shortly after as indicated by the period CS1. At t=t22, the latch circuit 399 latches the result of the test of the second unit cell 330 with the next falling edge of the clock signal CLK. The resulting latched error flag signal ERR is active (“1”) if the current supplied by the second unit cell 330 is outside the predefined permissible range.

[0095] The test is continued with each further unit cell 330. With the next rising edge of the clock signal CLK after the result for the test of the last unit cell 330 has been latched, the voltage ramp generator exits the test mode and re-enters the conversion mode at the end of the test period at t=tn2.

[0096] FIG. 8 shows a voltage ramp generator 300 with a current mirror circuit 350 that includes a reference field effect transistor 351 and a first detection field effect transistor 352 in the first detection branch 370, wherein the reference current flows through the reference field effect transistor 351, and wherein gates of the reference field effect transistor 351 and the first detection field effect transistor 352 are electrically connected.

[0097] The gates of the reference field effect transistor 351 and the first detection field effect transistor 352 can be directly electrically connected with no further elements in-between as shown in FIG. 8. Alternatively, a 73656

[0098] 12 further element, e.g., a resistive element may be electrically connected in series between the gates of the reference field effect transistor 351 and the first detection field effect transistor 352.

[0099] The reference field effect transistor 351 may be in a diode configuration, wherein the drain and the gate of the reference field effect transistor 351 can be directly connected as shown. Alternatively, the current mirror circuit 350 may have a buffered feedback configuration.

[0100] The controlled load path of the reference field effect transistor 351 can be directly connected between the current summation node 339 and the reference potential VSS as shown. Alternatively, the current mirror circuit 350 may have a full Wilson mirror configuration with the load path of another field effect transistor electrically connected between the load path of the reference field effect transistor 351 and the reference potential VSS.

[0101] The controlled load path of the first detection field effect transistor 352 can be directly connected between the first detector load 375 and the reference potential VSS as shown. For the full Wilson mirror configuration, the load path of another field effect transistor is electrically connected between the load path of the first detection field effect transistor 352 and the reference potential VSS, wherein the gates of the two additional field effect transistors are electrically connected. Alternatively, the current mirror circuit 350 may have a simple Wilson mirror configuration with the load path of another field effect transistor electrically connected between the first detector load 375 and the load path of the reference field effect transistor 351.

[0102] The reference field effect transistor 351 and the first detection field effect transistor 352 form a matched pair.

[0103] The reference field effect transistor 351 and the first detection field effect transistor 352 have the same nominal characteristics and low device-to-device deviations as regards the transistor parameters and may be configured as differential pair.

[0104] The current mirror circuit 350 further includes a second detection field effect transistor 353, wherein the gate of the reference field effect transistor 351 and a gate of the second detection field effect transistor 353 are electrically connected.

[0105] The reference field effect transistor 351, the first detection field effect transistor 352 and the second detection field effect transistor 353 may have equal nominal characteristics.

[0106] In addition, the characteristics of the reference field effect transistor 351, the first detection field effect transistor 352 and the second detection field effect transistor 353 may show only small device-to-device deviations. The gates of the reference field effect transistor 351, the first detection field effect transistor 352, and the second detection field effect transistor 353 can be directly electrically connected to each other. 73656

[0107] 13

[0108] The reference field effect transistor 351, the first detection field effect transistor 352, and the second detection field effect transistor 353 can be n channel field effect transistors (nFETs) with the sources directly electrically connected to each other and to the reference potential VSS.

[0109] The first detection branch 370 includes a first constant current source 371 electrically connected between a positive supply voltage line 301 and the first detection field effect transistor 352, the second detection branch 380 comprises a second constant current source 381 electrically connected between the positive supply voltage line 301 and the second detection field effect transistor 353, and wherein the first constant current source 371 and the second constant current source 381 are configured to supply different constant currents.

[0110] The first constant current source 371 forms the first detector load 375 of FIG. 5 and may include a first load field effect transistor. The second constant current source 381 forms the second detector load 385 of FIG. 5 and may include a second load field effect transistor, wherein constant gate bias voltages are applied to both the first load field effect transistor and the second load field effect transistor.

[0111] The first constant current source 371 supplies the upper threshold current ITH1 and the second constant current source 381 supplies the lower threshold current ITH2. With a symmetrical tolerance window around the nominal unit current 10, the upper threshold current is equal to I0+ITH and the lower threshold current ITH2 is equal to I0-ITH, where ITH is the amount of the maximum permissible deviation from the unit current 10.

[0112] The first and second threshold currents I0+ITH, I0-ITH may be adjusted by the channel widths of the first and second load field effect transistors and / or the gate bias applied to the gates of the first and second load field effect transistors.

[0113] In the illustrated example, the first and second load field effect transistors for the first and second constant current sources 371, 381 receive the same constant voltage bias V0 at the gates as the gates of the unit field effect transistors 331. In an example case, the maximum permissible deviation ITH may be programmable in a range of about 0.25*10.

[0114] The first error signal ERR1 becomes active when the first detector current ID 1 exceeds the first threshold current I0+ITH. The second error signal ERR2 becomes active when the second detector current ID2 falls below the second threshold current I0-ITH.

[0115] FIG. 9 shows another configuration example of a solid-state imaging device 90 with a signal processing unit 80, an image sensor assembly 70, a row decoder / driver 30, a pixel array 10, a group signal processing unit 20, and a digital readout unit 40 as described with reference to FIG. 2.

[0116] More particularly, the solid-state imaging device 90 includes a pixel circuit 100 configured to output a pixel voltage, wherein the pixel voltage is a function of received radiation intensity. An analog-to-digital converter 220, 230 is configured to convert the pixel voltage into a digital pixel value by comparing the 73656

[0117] 14 pixel voltage with a voltage ramp signal VRMP generated by a voltage ramp generator 300. The voltage ramp generator 300 includes unit cells 330 electrically connected in parallel, wherein each unit cell 330 is configured to switch between an on-state and an off-state in response to cell-specific select signal SI, S2, . . . , Sn. A current mirror circuit 350 is configured to copy a reference current controlled by the unit cells 330 at a predefined current ratio into at least a first detector current flowing in a first detection branch. An error detection circuit 390 is configured to generate an active first error signal if the first detector current exceeds an upper threshold current or falls below a lower threshold current.

[0118] Each unit cell 330 may include a unit field effect transistor and a unit switch electrically connected in series between a positive supply potential and a current summation node, wherein the unit field effect transistors have a same channel length. A sensor controller 50 is configured to switch on the unit field effect transistors one by one in a test period.

[0119] The voltage ramp generator 300 may further include an accumulator resistor and a first electronic switch electrically connected in series with the unit cells, wherein the sensor controller 50 is further configured to switch off the first electronic switch in the test period.

[0120] For example, the first electronic switch is configured as the first electronic switch 344 shown in FIG. 4 and includes a field effect transistor, and the sensor controller 50 outputs an active conversion enable signal RD_EN to switch on the field effect transistor.

[0121] The voltage ramp generator 300 may further include a second electronic switch electrically connected in series with the unit cells and configured to switch on and off the reference current through the current mirror circuit 350, wherein the sensor controller 50 is further configured to switch on the second electronic switch 346 in the test period.

[0122] For example, the second electronic switch is configured as the second electronic switch 346 shown in FIG. 4 and includes a field effect transistor, and the sensor controller 50 outputs an active test enable signal BIST_EN to switch on the field effect transistor.

[0123] FIG. 10 is a diagram illustrating an example in which the image sensor assembly 70 of FIG. 2 is formed by a stacked CMOS image sensor (CIS) having a two-layer structure with a first chip 910 (radiation receiving chip) and a second chip 920 (processing chip). The radiation receiving chip includes at least the photoelectric conversion elements. For example, the radiation receiving chip may include only the photoelectric conversion elements, only the conversion portions of the pixel circuits, or the conversion portions and at least some elements of the PWM portions of the pixel circuits. The image sensor assembly is formed as one sensor by bonding the radiation receiving chip and the processing chip while electrically bringing contact pads on the radiation receiving chip in contact with corresponding contact pads on the processing chip. 73656

[0124] 15

[0125] FIG. 11 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

[0126] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 11, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0127] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0128] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0129] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0130] The imaging section 12031 may be or may include an image sensor assembly of a solid-state imaging device according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and / or invisible light such as infrared rays or the like.

[0131] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor assembly of a solid-state imaging device according to the embodiments 73656

[0132] 16 of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. Based on detection information input from the driver state detecting section 12041 , the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

[0133] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0134] In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0135] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0136] The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 11, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

[0137] FIG. 12 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0138] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the 73656

[0139] 17 interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0140] Incidentally, FIG. 12 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0141] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor assembly of a solid-state imaging device according to the embodiments of the present disclosure.

[0142] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

[0143] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value 73656

[0144] 18 and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0145] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0146] The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying a solid-state imaging device according to the embodiments of the present disclosure, an internal error detection can be implemented, and reliability of the system can be enhanced.

[0147] Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0148] The solid-state imaging device according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, a solid-state imaging device according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

[0149] Specifically, in the field of image reproduction, the solid-state imaging device according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including a solid-state imaging device according to the embodiments may be integrated in an in-vehicle sensorthat captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like. 73656

[0150] 19

[0151] In the field of home appliances, the solid-state imaging device according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the solid-state imaging device according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and / or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device according to the embodiments may be integrated in any type of sensor, e.g., a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

[0152] In the field of security, the solid-state imaging device according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, a solid-state imaging device according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, a solid-state imaging device according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid- state imaging device can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

[0153] The present technology can also be configured as described below: [1] A voltage ramp generator (300) includes unit cells (330), a current mirror circuit (350), and an error detection circuit (390). The unit cells (330) are electrically connected in parallel, wherein each unit cell (330) is configured to switch between an on-state and an off-state in response to a cell-specific select signal. The current mirror circuit (350) is configured to copy a reference current controlled by the unit cells (330) at a predefined current ratio into a first detector current flowing in a first detection branch (370). The error detection circuit (390) is configured to generate an active first error signal if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

[0154] [2] The voltage ramp generator according to [1], further including: an accumulator resistor (342) and a first electronic switch (344) electrically connected in series with each other and with the unit cells (330), wherein the first electronic switch (344) is configured to switch off a current flow through the accumulator resistor (342) in a test period.

[0155] [3] The voltage ramp generator according to any of [1] and [2], further including: a second electronic switch (346) electrically connected in series with the unit cells (330), wherein the second electronic switch (346) is configured to switch on the reference current through the current mirror circuit (350) in a test period.

[0156] [4] The voltage ramp generator according to any of [1] to [3], wherein the current mirror circuit (350) is further configured to copy the reference current at a predefined current ratio into a second detector current flowing in a second detection branch (380), and wherein the error detection circuit (390) is configured to generate the active first error signal when the first detector current exceeds the upper threshold current and 73656

[0157] 20 generate an active second error signal when the second detector current falls below the lower threshold current.

[0158] [5] The voltage ramp generator according to [4], wherein the error detection circuit (390) is configured to generate an active error flag signal when the first error signal and / or the second error signal is active.

[0159] [6] The voltage ramp generator according to [5], wherein the error detection circuit (390) includes a latch circuit (399) configured to latch the error flag signal.

[0160] [7] The voltage ramp generator according to any of [1] to [6], wherein the current mirror circuit (350) includes a reference field effect transistor (351) and a first detection field effect transistor (352) in the first detection branch (370), wherein the reference current flows through the reference field effect transistor (351), and wherein gates of the reference field effect transistor (351) and the first detection field effect transistor (352) are electrically connected.

[0161] [8] The voltage ramp generator according to [7], wherein the reference field effect transistor (351) and the first detection field effect transistor (352) form a matching pair.

[0162] [9] The voltage ramp generator according to any of [7] and [8], wherein the current mirror circuit (350) further includes a second detection field effect transistor (353) and wherein the gate of the reference field effect transistor (351) and a gate of the second detection field effect transistor (353) are electrically connected.

[0163]

[0010] The voltage ramp generator according to [9], wherein the reference field effect transistor (351), the first detection field effect transistor (352) and the second detection field effect transistor (353) have equal nominal characteristics.

[0164]

[0011] The voltage ramp generator according to

[0010] , wherein the first detection branch (370) includes a first constant current source (371) electrically connected between a positive supply voltage line (301) and the first detection field effect transistor (352), the second detection branch (380) includes a second constant current source (381) electrically connected between the positive supply voltage line (301) and the second detection field effect transistor (353), and wherein the constant current source (371) and the second constant current source (381) are configured to supply different constant currents.

[0165]

[0012] The present technology can also be configured as a solid-state imaging device (90) that includes: a pixel circuit (100) configured to output a pixel voltage, wherein the pixel voltage is a function of received radiation intensity; an analog -to-digital converter (220, 230) configured to convert the pixel voltage into a digital pixel value by comparing the pixel voltage with a voltage ramp signal generated by a voltage ramp generator (300), the voltage ramp generator (300) including: unit cells (330) electrically connected in parallel, each unit cell (330) configured to switch between an on-state and an off-state in response to cellspecific select signal; a current mirror circuit (350) configured to copy a reference current controlled by the unit cells (330) at a predefined current ratio into a first detector current flowing in a first detection branch 73656

[0166] 21

[0167] (370); and an error detection circuit (390) configured to generate an active first error signal if the first detector current exceeds an upper threshold current or falls below a lower threshold current.

[0168]

[0013] The solid-state imaging device (90) according to

[0012] , wherein each unit cell (330) includes a unit field effect transistor (331) and a unit switch (333) electrically connected in series between a positive supply potential and a current summation node (339), and wherein the unit field effect transistors (331) have a same channel length; and further including: a sensor controller (50) configured to switch on the unit field effect transistors (331) one by one in a test period.

[0014] The solid-state imaging device according to

[0013] , further including: an accumulator resistor (342) and a first electronic switch (344) electrically connected in series with the unit cells (330), and wherein the sensor controller (50) is further configured to switch off the first electronic switch (344) in the test period.

[0169]

[0015] The solid-state imaging device according to any of

[0013] and

[0014] , further including: a second electronic switch (346) electrically connected in series with the unit cells (330) and configured to switch on and off the reference current through the current mirror circuit (350), and wherein the sensor controller (50) is further configured to switch on the second electronic switch (346) in the test period.

Claims

1. 7365622CLAIMS1. A voltage ramp generator, comprising: unit cells electrically connected in parallel, each unit cell configured to switch between an on-state and an off-state in response to a cell-specific select signal; a current mirror circuit configured to copy a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch; and an error detection circuit configured to generate an active first error signal if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

2. The voltage ramp generator according to claim 1, further comprising: an accumulator resistor and a first electronic switch electrically connected in series with each other and with the unit cells, wherein the first electronic switch is configured to switch off a current flow through the accumulator resistor in a test period.

3. The voltage ramp generator according to claim 1, further comprising: a second electronic switch electrically connected in series with the unit cells, wherein the second electronic switch is configured to switch on the reference current through the current mirror circuit in a test period.

4. The voltage ramp generator according to claim 1, wherein the current mirror circuit is further configured to copy the reference current at a predefined current ratio into a second detector current flowing in a second detection branch, and wherein the error detection circuit is configured to generate the active first error signal when the first detector current exceeds the upper threshold current and generate an active second error signal when the second detector current falls below the lower threshold current.

5. The voltage ramp generator according to claim 4, wherein the error detection circuit is configured to generate an active error flag signal when the first error signal and / or the second error signal is active.

6. The voltage ramp generator according to claim 5, wherein the error detection circuit comprises a latch circuit configured to latch the error flag signal.

7. The voltage ramp generator according to claim 1, wherein the current mirror circuit comprises a reference field effect transistor and a first detection field effect transistor in the first detection branch, wherein the reference current flows through the reference field effect transistor, and wherein gates of the reference field effect transistor and the first detection field effect transistor are electrically connected.

8. The voltage ramp generator according to claim 7,7365623 wherein the reference field effect transistor and the first detection field effect transistor form a matching pair.

9. The voltage ramp generator according to claim 7, wherein the current mirror circuit further comprises a second detection field effect transistor and wherein the gate of the reference field effect transistor and a gate of the second detection field effect transistor are electrically connected.

10. The voltage ramp generator according to claim 9, wherein the reference field effect transistor, the first detection field effect transistor and the second detection field effect transistor have equal nominal characteristics.

11. The voltage ramp generator according to claim 10, wherein the first detection branch comprises a first constant current source electrically connected between a positive supply voltage line and the first detection field effect transistor, the second detection branch comprises a second constant current source electrically connected between the positive supply voltage line and the second detection field effect transistor, and wherein the constant current source and the second constant current source are configured to supply different constant currents.

12. A solid-state imaging device, comprising: a pixel circuit configured to output a pixel voltage, wherein the pixel voltage is a function of received radiation intensity; an analog-to-digital converter configured to convert the pixel voltage into a digital pixel value by comparing the pixel voltage with a voltage ramp signal generated by a voltage ramp generator, the voltage ramp generator comprising: unit cells electrically connected in parallel, each unit cell configured to switch between an on-state and an off-state in response to cell-specific select signal; a current mirror circuit configured to copy a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch; and an error detection circuit configured to generate an active first error signal if the first detector current exceeds an upper threshold current or falls below a lower threshold current.

13. The solid-state imaging device according to the preceding claim, wherein each unit cell comprises a unit field effect transistor and a unit switch electrically connected in series between a positive supply potential and a current summation node, and wherein the unit field effect transistors have a same channel length; and further comprising: a sensor controller configured to switch on the unit field effect transistors one by one in a test period.

14. The solid-state imaging device according to the claim 13, further comprising: an accumulator resistor and a first electronic switch electrically connected in series with the unit cells,wherein the sensor controller is further configured to switch off the first electronic switch in the test period.

15. The solid-state imaging device according to the claim 13, further comprising: a second electronic switch electrically connected in series with the unit cells and configured to switch on and off the reference current through the current mirror circuit, wherein the sensor controller is further configured to switch on the second electronic switch in the test period.

Images