Method for integrating CMOS device in double-polysilicon self-aligned bipolar junction transistor process, and structure

Abstract

Disclosed in the present invention are a method for integrating a CMOS device in a double-polysilicon self-aligned bipolar junction transistor process and a structure. The method comprises: successively forming an N-type primary buried layer (103) of a double-polysilicon self-aligned bipolar junction transistor, a P-type primary buried layer (104) of an NMOS, and an N-type secondary buried layer (105) of a PMOS; forming an epitaxial layer (106) on an SOI silicon substrate; forming in the epitaxial layer (106) a P-type well region (107) of the NMOS and an N-type well region (108) of the PMOS; and steps such as forming all-dielectric island isolation of the double-polysilicon self-aligned bipolar junction transistor and the NMOS / PMOS. The semiconductor device of the present invention can achieve various combinations of high-performance NPN / PNP and CMOS devices, and effectively improve the overall device characteristics of the process, so as to meet wider and higher-demanding application technical fields and improve the electrical performance of chips.

Description

A method and structure for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process. Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically a method and structure for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process. Background Technology

[0002] Analog integrated circuits and mixed-signal circuits, as an indispensable part of current circuit systems, will find increasing use in applications requiring high-speed, high-performance communication or external interfaces. With the increasing demand for higher-performance products such as high density, low power consumption, and high-speed, high-drive capability, coupled with the continuous shrinking of linewidths and the advantages of CMOS voltage drive, as well as the need for related high-precision AD / DA products, integrating CMOS into bipolar process platforms has become a new direction. Bipolar circuits are characterized by high speed, strong current drive capability, and high analog accuracy, while CMOS circuits have unparalleled advantages in high integration and low power consumption. In today's integrated circuit manufacturing industry, which constantly pursues higher performance and perfection, the perfect combination of the complementary advantages of these two processes has given rise to the new BiCMOS process.

[0003] High-speed BiCMOS process platforms have long been a gap in domestic bipolar process platforms, playing an irreplaceable role in the manufacturing of high-end high-speed amplifiers and high-precision AD / DA chips. These chips are widely used in various precision communication equipment, high-precision testing instruments, and automotive electronics. Currently, these products are all imported from abroad. In particular, high-speed BiCMOS currently faces many challenges, such as high process integration, complex manufacturing processes, high costs, and difficulty in guaranteeing yield. To overcome these challenges, continuous research and improvement of manufacturing process technologies are needed to enhance circuit performance and reliability.

[0004] Therefore, there is an urgent need for a method that can integrate high-speed bipolar transistors and CMOS devices in a single manufacturing process without significantly increasing process complexity. Summary of the Invention

[0005] The purpose of this invention is to provide a method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, comprising the following steps:

[0006] 1) Provide SOI silicon substrate.

[0007] 2) The N-type primary buried layer of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer of the NMOS, and the N-type secondary buried layer of the PMOS are formed sequentially.

[0008] 3) An epitaxial layer is formed on an SOI silicon substrate.

[0009] 4) Form the P-type well region of NMOS and the N-type well region of PMOS in the epitaxial layer.

[0010] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and NMOS / PMOS, including trench isolation oxide layer and trench isolation polycrystalline silicon.

[0011] 6) Perform N-type through-hole implantation of the collector of the dual polycrystalline self-aligned bipolar junction transistor and connect it to the N-type primary buried layer.

[0012] 7) Form a selectively oxidized field oxide layer, rinse away excess silicon nitride and oxide layers, and form active and field regions in the dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS regions, respectively.

[0013] 8) Grow the gate oxide layer to form the gate oxide layer.

[0014] 9) Remove the gate oxide from the region of the dual polycrystalline self-aligned bipolar junction transistor, and retain the gate oxide in the NMOS / PMOS region.

[0015] 10) Deposit the first layer of polysilicon, perform general injection first, and then use a photomask to sequentially perform gate polysilicon injection for N-type / P-type bipolar transistors and NMOS / PMOS.

[0016] 11) Etch away excess polysilicon to form the polysilicon collector, polysilicon base, polysilicon gate of NMOS, and polysilicon gate of PMOS for dual polysilicon self-aligned bipolar junction transistors.

[0017] 12) Perform heavy doping on the source and drain of NMOS / PMOS and heavy doping on the BACK end well to form P-well heavy doping, N-well heavy doping, N-type source region and N-type drain region of NMOS, and P-type source region and P-type drain region of PMOS.

[0018] 13) Deposit a TEOS metal front dielectric layer, remove the oxide layer and polysilicon to form the base region window of the bipolar transistor.

[0019] 14) P-type base region implantation, connected with the P-heavily doped outer base region 128 diffused into silicon through polycrystalline silicon to form a double base region.

[0020] 15) An L-shaped sidewall structure emission window is formed by multiple deposition and etching processes.

[0021] 16) Deposit a second layer of polysilicon, use a photomask to implant and form the emitter region of the double polysilicon self-aligned bipolar junction transistor, etch out the excess polysilicon to form the polysilicon emitter of the double polysilicon self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region by annealing the emitter region.

[0022] 17) Deposit metal to form the collector, emitter, source, drain, gate, and back metal structures of the integrated CMOS device.

[0023] Furthermore, the P-type primary buried layer of the NMOS is located between the N-type primary buried layer and the N-type secondary buried layer of the PMOS, and does not contact the N-type primary buried layer or the N-type secondary buried layer of the PMOS.

[0024] Furthermore, the bottom trench isolation oxide layer is in contact with the oxide layer on the SOI substrate.

[0025] Furthermore, in step 7), the field oxide layer of the selectively oxidized structure is formed by photomask.

[0026] In step 9), the gate oxide of the double polycrystalline self-aligned bipolar junction transistor region is removed by wet etching using a photomask.

[0027] In step 11), excess polycrystalline material is removed by dry etching using a photomask.

[0028] In step 12), the oxide layer and polycrystalline material are removed by dry etching using a photomask.

[0029] In step 16), a photomask is used to perform dry etching to remove excess polysilicon to form the polysilicon emitter of a double polysilicon self-aligned bipolar junction transistor.

[0030] Furthermore, the sidewall structure emission region window includes a sidewall oxide layer and a sidewall silicon nitride layer.

[0031] Furthermore, the steps of depositing metal to form the collector, emitter, source, drain, gate, and back metal structures of the integrated CMOS device include:

[0032] Holes are opened in the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor, and metal is deposited to form collector metal and base metal.

[0033] Emitter metal is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0034] Holes are opened and metals are deposited on the N-type source region, drain region, and P-well heavily doped silicon substrate of NMOS to form source metal, drain metal, and BACK terminal metal.

[0035] A hole is opened on the gate polysilicon of the NMOS and metal is deposited to form the gate metal.

[0036] Holes are opened and metals are deposited on the P-type source region, drain region, and N-well heavily doped silicon substrate of PMOS to form source metal, drain metal, and BACK terminal metal.

[0037] A hole is opened on the gate polysilicon of the PMOS and metal is deposited to form the gate metal.

[0038] Furthermore, the SOI silicon substrate includes a P-type substrate, an oxide layer on the substrate, and silicon on the oxide layer, or the SOI silicon substrate is a single-crystal silicon substrate.

[0039] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0040] Furthermore, the dual polycrystalline self-aligned bipolar junction transistor is an NPN, a PNP, or a combination of NPN and PNP.

[0041] Furthermore, the polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

[0042] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor (DPT) process, wherein the DPT with integrated CMOS devices is fabricated by the method described above.

[0043] The technical effects of this invention are undeniable. This invention provides a method and structure for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process. Without significantly increasing the overall process complexity and technical difficulty, it achieves the integration of dual-polycrystalline self-aligned polycrystalline silicon emitter transistors and CMOS devices using the same process flow.

[0044] The beneficial effects of this invention are as follows:

[0045] 1) This invention proposes a method and structure for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process. Without significantly increasing the overall process complexity and technical difficulty, the integration of dual-polycrystalline self-aligned polycrystalline silicon emitter transistors and CMOS devices is achieved in the same process flow, reducing process costs and improving processing efficiency. It is particularly suitable for the development of high-speed BiCMOS related processes.

[0046] 2) The semiconductor device in this invention can realize various combinations of high-performance NPN / PNP and CMOS devices, effectively improving the overall device characteristics of the process, so as to meet the application technology fields with wider and higher requirements and improve the electrical performance of the chip. Attached Figure Description

[0047] Figure 1 is a schematic diagram of the steps of the method for integrating CMOS devices in the dual polycrystalline self-aligned bipolar junction transistor process of the present invention.

[0048] Figures 2-10 show process flow diagrams of the method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to an embodiment of the present invention.

[0049] In the figure: P-type substrate 100, oxide layer on substrate 101, silicon on oxide layer 102, N-type primary buried layer 103, P-type primary buried layer 104, N-type secondary buried layer 105, epitaxial layer 106, P-type well region 107, N-type well region 108, trench isolation oxide layer 109, trench isolation polysilicon 110, N-type through-hole 111, field oxide layer 112, gate oxide layer 113, polysilicon collector 114, polysilicon base 115, NMOS polysilicon gate 116, PMOS Polysilicon gate 117, P-well heavily doped 118, N-well heavily doped 121, N-type source region 119, N-type drain region 120, P-type source region 122, P-type drain region 123, TEOS metal front dielectric layer 124, sidewall oxide layer 125, sidewall silicon nitride 126, polysilicon emitter 127, P-heavily doped outer base region 128, P-type base region 129, N-type heavily doped emitter region 130, collector metal 131, base metal 132, emitter metal 133, NMOS BACK terminal metal 134, NMOS source metal 135, NMOS gate metal 136, NMOS drain metal 137, PMOS BACK terminal metal 138, PMOS source metal 139, PMOS gate metal 140, PMOS drain metal 141. Detailed Implementation

[0050] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0051] Example 1:

[0052] Referring to Figures 1 to 10, a method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process includes the following steps:

[0053] 1) Provide SOI silicon substrate.

[0054] 2) The N-type primary buried layer 103 of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer 104 of the NMOS, and the N-type secondary buried layer 105 of the PMOS are formed sequentially.

[0055] 3) An epitaxial layer 106 is formed on an SOI silicon substrate.

[0056] 4) A P-type well region 107 of NMOS and an N-type well region 108 of PMOS are formed in the epitaxial layer 106.

[0057] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and NMOS / PMOS, including trench isolation oxide layer 109 and trench isolation polycrystalline silicon 110.

[0058] 6) Perform N-type penetration injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor 111, and connect it with the N-type primary buried layer 103.

[0059] 7) Form a selectively oxidized field oxide layer 112, rinse away excess silicon nitride and oxide layers, and form an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and the NMOS / PMOS region, respectively.

[0060] 8) The gate oxide layer is grown to form gate oxide layer 113.

[0061] 9) Remove the gate oxide from the region of the dual polycrystalline self-aligned bipolar junction transistor, and retain the gate oxide in the NMOS / PMOS region.

[0062] 10) Deposit the first layer of polysilicon, perform general injection first, and then use a photomask to sequentially perform gate polysilicon injection for N-type / P-type bipolar transistors and NMOS / PMOS.

[0063] 11) Etch away excess polysilicon to form a polysilicon collector 114, a polysilicon base 115, a polysilicon gate 116 for NMOS, and a polysilicon gate 117 for PMOS for dual polysilicon self-aligned bipolar junction transistors.

[0064] 12) Perform heavy doping on the source and drain of NMOS / PMOS and heavy doping on the BACK end well to form P-well heavy doping 118, N-well heavy doping 121, N-type source region 119 and N-type drain region 120 of NMOS, and P-type source region 122 and P-type drain region 123 of PMOS.

[0065] 13) Deposit a TEOS metal front dielectric layer 124, remove the oxide layer and polysilicon, and form the base region window of the bipolar transistor.

[0066] 14) The P-type base region 129 is implanted and connected to the P-doped outer base region 128 diffused into the polycrystalline silicon, forming a double base region through the polycrystalline silicon base connection.

[0067] 15) An L-shaped sidewall structure emission window is formed by multiple deposition and etching processes.

[0068] 16) Deposit a second layer of polysilicon, use a photomask to implant and form the emitter region of the double polysilicon self-aligned bipolar junction transistor, etch out excess polysilicon to form the polysilicon emitter 127 of the double polysilicon self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region 130 by annealing the emitter region.

[0069] 17) Deposit metal to form the collector, emitter, source, drain, gate, and back metal structures of the integrated CMOS device.

[0070] The P-type primary buried layer 104 of the NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS, and does not contact the N-type primary buried layer 103 or the N-type secondary buried layer 105 of the PMOS.

[0071] The bottom trench isolation oxide layer 109 is in contact with the oxide layer 101 on the SOI substrate.

[0072] In step 7), the selectively oxidized field oxygen layer 112 is formed by photomask.

[0073] In step 9), the gate oxide of the double polycrystalline self-aligned bipolar junction transistor region is removed by wet etching using a photomask.

[0074] In step 11), excess polycrystalline material is removed by dry etching using a photomask.

[0075] In step 13), the oxide layer and polycrystalline material are removed by dry etching using a photomask.

[0076] In step 16), a photomask is used to perform dry etching to remove excess polysilicon to form the polysilicon emitter 127 of the double polysilicon self-aligned bipolar junction transistor.

[0077] The sidewall structure emission region window includes a sidewall oxide layer 125 and a sidewall silicon nitride layer 126.

[0078] The steps of depositing metal to form the collector, emitter, source, drain, gate, and back metal structures of an integrated CMOS device include:

[0079] Holes are made in the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor, and metal is deposited to form collector metal 131 and base metal 132.

[0080] Emitter metal 133 is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0081] Holes are made and metals are deposited on the N-type source region, drain region, and P-well heavily doped silicon substrate of the NMOS to form source metal 135, drain metal 137 and BACK terminal metal 134.

[0082] A hole is opened on the gate polysilicon of the NMOS and metal is deposited to form the gate metal 136.

[0083] Holes are made in the P-type source region, drain region, and N-well heavily doped silicon substrate of the PMOS and metal is deposited to form source metal 139, drain metal 141 and BACK terminal metal 138.

[0084] A hole is opened on the gate polysilicon of the PMOS and metal is deposited to form the gate metal 140.

[0085] The SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single-crystal silicon substrate.

[0086] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0087] The dual polycrystalline self-aligned bipolar junction transistor is an NPN, a PNP, or a combination of NPN and PNP.

[0088] The polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

[0089] Example 2:

[0090] A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process includes the following steps:

[0091] 1) Provide SOI silicon substrate.

[0092] 2) The N-type primary buried layer 103 of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer 104 of the NMOS, and the N-type secondary buried layer 105 of the PMOS are formed sequentially.

[0093] 3) An epitaxial layer 106 is formed on an SOI silicon substrate.

[0094] 4) A P-type well region 107 of NMOS and an N-type well region 108 of PMOS are formed in the epitaxial layer 106.

[0095] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and NMOS / PMOS, including trench isolation oxide layer 109 and trench isolation polycrystalline silicon 110.

[0096] 6) Perform N-type penetration injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor 111, and connect it with the N-type primary buried layer 103.

[0097] 7) Form a selectively oxidized field oxide layer 112, rinse away excess silicon nitride and oxide layers, and form an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and the NMOS / PMOS region, respectively.

[0098] 8) The gate oxide layer is grown to form gate oxide layer 113.

[0099] 9) Remove the gate oxide from the region of the dual polycrystalline self-aligned bipolar junction transistor, and retain the gate oxide in the NMOS / PMOS region.

[0100] 10) Deposit the first layer of polysilicon, perform general injection first, and then use a photomask to sequentially perform gate polysilicon injection for N-type / P-type bipolar transistors and NMOS / PMOS.

[0101] 11) Etch away excess polysilicon to form a polysilicon collector 114, a polysilicon base 115, a polysilicon gate 116 for NMOS, and a polysilicon gate 117 for PMOS for dual polysilicon self-aligned bipolar junction transistors.

[0102] 12) Perform heavy doping on the source and drain of NMOS / PMOS and heavy doping on the BACK end well to form P-well heavy doping 118, N-well heavy doping 121, N-type source region 119 and N-type drain region 120 of NMOS, and P-type source region 122 and P-type drain region 123 of PMOS.

[0103] 13) Deposit a TEOS metal front dielectric layer 124, remove the oxide layer and polysilicon, and form the base region window of the bipolar transistor.

[0104] 14) The P-type base region 129 is implanted and connected to the P-doped outer base region 128 diffused into the polycrystalline silicon, forming a double base region through the polycrystalline silicon base connection.

[0105] 15) An L-shaped sidewall structure emission window is formed by multiple deposition and etching processes.

[0106] 16) Deposit a second layer of polysilicon, use a photomask to implant and form the emitter region of the double polysilicon self-aligned bipolar junction transistor, etch out excess polysilicon to form the polysilicon emitter 127 of the double polysilicon self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region 130 by annealing the emitter region.

[0107] 17) Deposit metal to form the collector, emitter, source, drain, gate, and back metal structures of the integrated CMOS device.

[0108] Example 3:

[0109] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, with the same technical content as in Embodiment 2, further wherein the P-type primary buried layer 104 of the NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS, and is not in contact with the N-type primary buried layer 103 or the N-type secondary buried layer 105 of the PMOS.

[0110] Example 4:

[0111] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-3, further wherein the bottom trench isolation oxide layer 109 of the trench isolation layer is in contact with the oxide layer 101 on the SOI substrate.

[0112] Example 5:

[0113] A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-4, further wherein, in step 7), the selectively oxidized field oxide layer 112 is formed by photomask.

[0114] In step 9), the gate oxide of the double polycrystalline self-aligned bipolar junction transistor region is removed by wet etching using a photomask.

[0115] In step 11), excess polycrystalline material is removed by dry etching using a photomask.

[0116] In step 13), the oxide layer and polycrystalline material are removed by dry etching using a photomask.

[0117] In step 16), a photomask is used to perform dry etching to remove excess polysilicon to form the polysilicon emitter 127 of the double polysilicon self-aligned bipolar junction transistor.

[0118] Example 6:

[0119] A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-5, further wherein the sidewall structure emitter window includes a sidewall oxide layer 125 and a sidewall silicon nitride layer 126.

[0120] Example 7:

[0121] A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, with the technical content being the same as any one of embodiments 2-6, further comprising the steps of depositing metal to form the collector, emitter, source, drain, gate, and back terminal metal structures of the integrated CMOS device, including:

[0122] Holes are made in the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor, and metal is deposited to form collector metal 131 and base metal 132.

[0123] Emitter metal 133 is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0124] Holes are made and metals are deposited on the N-type source region, drain region, and P-well heavily doped silicon substrate of the NMOS to form source metal 135, drain metal 137, and BACK terminal metal 134.

[0125] A hole is opened on the gate polysilicon of the NMOS and metal is deposited to form the gate metal 136.

[0126] Holes are made in the P-type source region, drain region, and N-well heavily doped silicon substrate of the PMOS and metal is deposited to form source metal 139, drain metal 141 and BACK terminal metal 138.

[0127] A hole is opened on the gate polysilicon of the PMOS and metal is deposited to form the gate metal 140.

[0128] Example 8:

[0129] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-7, further wherein the SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single-crystal silicon substrate.

[0130] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0131] Example 9:

[0132] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-8, further wherein the dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of NPN and PNP.

[0133] Example 10:

[0134] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-9, further wherein the polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

[0135] Example 11:

[0136] A method for integrating CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, wherein the dual polycrystalline self-aligned bipolar junction transistor with integrated CMOS devices is prepared by the method described in any one of Examples 1-10.

[0137] Example 12:

[0138] A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, the technical solution of which is as follows:

[0139] 1) Provide an SOI silicon substrate (including a P-type substrate 100, an oxide layer 101 on the substrate, and silicon on the oxide layer 102).

[0140] 2) Next, an N-type primary buried layer 103 is formed for the dual polycrystalline self-aligned bipolar junction transistor (left), a P-type primary buried layer 104 is formed for the NMOS (middle), and an N-type secondary buried layer 105 is formed for the PMOS (right).

[0141] 3) An epitaxial layer 106 is formed on the substrate.

[0142] 4) Form a P-type well region 107 for NMOS and an N-type well region 108 for PMOS in the epitaxial layer.

[0143] 5) Forming a dual polycrystalline self-aligned bipolar junction transistor and an all-dielectric island isolation for NMOS / PMOS, including a trench isolation oxide layer 109 and a trench isolation polycrystalline silicon layer 110. The bottom trench isolation oxide layer 109 is in contact with the oxide layer 101 on the SOI substrate.

[0144] 6) Perform N-type penetration injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor 111, and connect it with the N-type primary buried layer 103.

[0145] 7) Using a photomask, a selectively oxidized field oxide layer 112 is formed, and excess silicon nitride and oxide layers are washed away to form active and field regions in the dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS regions, respectively.

[0146] 8) Next, the gate oxide layer is grown to form the gate oxide layer 113.

[0147] 9) Use a photomask to remove the gate oxide of the dual polycrystalline self-aligned bipolar junction transistor region by wet etching, while retaining the gate oxide of the NMOS / PMOS region.

[0148] 10) Deposit the first layer of polysilicon, perform general injection first, and then use a photomask to sequentially perform gate polysilicon injection for N-type / P-type bipolar transistors and NMOS / PMOS.

[0149] 11) Use a photomask to remove excess polysilicon through dry etching to form a polysilicon collector 114, a polysilicon base 115, a polysilicon gate 116 for NMOS, and a polysilicon gate 117 for PMOS for dual polysilicon self-aligned bipolar junction transistors.

[0150] 12) Based on this, the source and drain regions of NMOS / PMOS and the BACK end well are heavily doped to form P-well heavy doping 118, N-well heavy doping 121, N-type source region 119 and N-type drain region 120 of NMOS, and P-type source region 122 and P-type drain region 123 of PMOS.

[0151] 13) Deposit a TEOS metal front dielectric layer 124, and use a photomask to remove the oxide layer and polysilicon by dry etching to form the base region window of the bipolar transistor.

[0152] 14) The P-type base region 129 is implanted and connected to the P-doped outer base region 128 diffused into the polycrystalline silicon, forming a double base region through the polycrystalline silicon base connection.

[0153] 15) Then, an L-shaped sidewall structure emission window is formed by multiple deposition and etching processes, including a sidewall oxide layer 125 and a sidewall silicon nitride layer 126.

[0154] 16) Deposit a second layer of polysilicon, use a photomask to implant and form the emitter region of the double polysilicon self-aligned bipolar junction transistor, use a photomask to dry etch out excess polysilicon to form the polysilicon emitter 127 of the double polysilicon self-aligned bipolar junction transistor, and form an N-type heavily doped emitter region 130 by annealing the emitter region.

[0155] 17) Holes are opened and metals are deposited on the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor to form collector metal 131 and base metal 132. Metals are deposited on the polycrystalline silicon emitter of the dual polycrystalline self-aligned bipolar junction transistor to form emitter metal 133. Holes are opened and metals are deposited on the heavily doped silicon substrate of the N-type source region, drain region, and P-well region of the NMOS to form source metal 135, drain metal 137, and BACK terminal metal 134. Holes are opened and metals are deposited on the gate polycrystalline of the NMOS to form gate metal 136. Holes are opened and metals are deposited on the heavily doped silicon substrate of the P-type source region, drain region, and N-well region of the PMOS to form source metal 139, drain metal 141, and BACK terminal metal 138. Holes are opened and metals are deposited on the gate polycrystalline of the PMOS to form gate metal 140.

[0156] The SOI silicon substrate (including a P-type substrate, an oxide layer on the substrate, and silicon on the oxide layer) can also be a single-crystal silicon substrate.

[0157] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0158] The dual polycrystalline self-aligned bipolar junction transistor can be NPN, PNP, or a combination of both.

[0159] The polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

Claims

1. A method of integrating CMOS devices in a bipolar process, characterized by, Includes the following steps: 1) Provide SOI silicon substrate. 2) The N-type primary buried layer (103) of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer (104) of the NMOS, and the N-type secondary buried layer (105) of the PMOS are formed sequentially. 3) An epitaxial layer (106) is formed on the SOI silicon substrate. 4) Form a P-type well region (107) of NMOS and an N-type well region (108) of PMOS in the epitaxial layer (106); 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and NMOS / PMOS, including a trench isolation oxide layer (109) and a trench isolation polycrystalline silicon layer (110); 6) Perform N-type penetration (111) injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor and connect it with the N-type primary buried layer (103); 7) Form a selectively oxidized field oxide layer (112), rinse away excess silicon nitride and oxide layer, and form active region and field region in the dual polycrystalline self-aligned bipolar junction transistor and NMOS / PMOS regions respectively; 8) The gate oxide layer is grown to form the gate oxide layer (113); 9) Remove the gate oxide from the region of the dual polycrystalline self-aligned bipolar junction transistor, while retaining the gate oxide in the NMOS / PMOS region; 10) Deposit the first layer of polysilicon, perform general injection first, and then use a photomask to sequentially perform gate polysilicon injection for N-type / P-type bipolar transistors and NMOS / PMOS; 11) Etch away excess polysilicon to form the polysilicon collector (114), polysilicon base (115), polysilicon gate (116) of NMOS, and polysilicon gate (117) of PMOS of dual polysilicon self-aligned bipolar junction transistor; 12) Perform heavy doping on the source and drain of NMOS / PMOS and heavy doping on the BACK end well to form P-well heavy doping (118), N-well heavy doping (121), N-type source region (119) and N-type drain region (120) of NMOS, and P-type source region (122) and P-type drain region (123) of PMOS. 13) Deposit a TEOS metal front dielectric layer (124), remove the oxide layer and polysilicon to form the base region window of the bipolar transistor; 14) A P-type base region (129) is implanted and connected to the P-doped outer base region 128 diffused into the polycrystalline silicon through the polycrystalline silicon base to form a double base region; 15) An L-shaped sidewall structure emission region window is formed through multiple deposition and etching processes; 16) Deposit a second layer of polysilicon, use a photomask to implant and form the emitter region of the double polysilicon self-aligned bipolar junction transistor, etch out excess polysilicon to form the polysilicon emitter of the double polysilicon self-aligned bipolar junction transistor (127), and form an N-type heavily doped emitter region (130) by annealing the emitter region. 17) Deposit metal to form the collector, emitter, source, drain, gate, and back metal structures of the integrated CMOS device.

2. The method of integrating CMOS devices in a bipolar process as claimed in claim 1, wherein: The P-type primary buried layer (104) of the NMOS is located between the N-type primary buried layer (103) and the N-type secondary buried layer (105) of the PMOS, and does not contact the N-type primary buried layer (103) or the N-type secondary buried layer (105) of the PMOS.

3. The method of integrating CMOS devices in a bipolar process as claimed in claim 1, wherein: The bottom trench isolation oxide layer (109) is in contact with the oxide layer (101) on the SOI substrate.

4. The method of integrating CMOS devices in a bipolar process as claimed in claim 1, wherein: In step 7), the selectively oxidized field oxide layer (112) is formed using a photomask; In step 9), the gate oxide of the double polycrystalline self-aligned bipolar junction transistor region is removed by wet etching using a photomask; In step 11), excess polycrystalline material is removed by dry etching using a photomask; In step 13), the oxide layer and polycrystalline material are removed by dry etching using a photomask; In step 16), a photomask is used to perform dry etching to remove excess polysilicon to form the polysilicon emitter (127) of a double polysilicon self-aligned bipolar junction transistor.

5. A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The sidewall structure emission region window includes a sidewall oxide layer (125) and a sidewall silicon nitride layer (126).

6. The method of integrating CMOS devices in a bipolar process as claimed in claim 1, wherein, The steps of depositing metal to form the collector, emitter, source, drain, gate, and back metal structures of an integrated CMOS device include: Holes are opened and metal is deposited on the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor to form collector metal (131) and base metal (132); Emitter metal is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor (133); Holes are made and metals are deposited on the N-type source region, drain region, and P-well heavily doped silicon substrate of NMOS to form source metal (135), drain metal (137) and BACK terminal metal (134). A hole is opened on the gate polysilicon of the NMOS and metal is deposited to form the gate metal (136); Holes are made in the P-type source region, drain region, and N-well heavily doped silicon substrate of PMOS and metal is deposited to form source metal (139), drain metal (141) and BACK terminal metal (138). A hole is opened on the gate polysilicon of the PMOS and metal is deposited to form the gate metal (140).

7. The method of integrating CMOS devices in a bipolar process as claimed in claim 1, wherein: The SOI silicon substrate includes a P-type substrate (100), an oxide layer (101) on the substrate, and silicon (102) on the oxide layer, or the SOI silicon substrate is a single-crystal silicon substrate. The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

8. A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The dual polycrystalline self-aligned bipolar junction transistor is an NPN, a PNP, or a combination of NPN and PNP.

9. The method of integrating CMOS devices in a bipolar process as claimed in claim 1, wherein: The polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

10. A method for integrating CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, characterized in that: The dual polycrystalline self-aligned bipolar junction transistor of the integrated CMOS device is prepared by the method described in any one of claims 1-9.

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