Method and structure for integrating thick- and thin-gate-oxide CMOS devices in dual-poly self-aligned bipolar junction transistor process

Abstract

Disclosed in the present invention are a method and structure for integrating thick- and thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process. The method comprises: providing an SOI silicon substrate; sequentially forming an N-type first buried layer (103) of a dual-poly self-aligned bipolar junction transistor, a P-type first buried layer (104) of a thin-gate-oxide NMOS, and a P-type second buried layer (105) of a thick-gate-oxide NMOS; forming an epitaxial layer (106) on the SOI silicon substrate; and forming a P-type first well region (107) of the thin-gate-oxide NMOS and a P-type second well region (108) of the thick-gate-oxide NMOS in the epitaxial layer. The semiconductor device in the present invention enables various combinations of high-performance NPN / PNP and thick- and thin-gate-oxide CMOS devices, thereby effectively improving the overall device characteristics of the process, meeting higher demands for broader application fields, and improving the electrical performance of chips.

Description

A method and structure for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process. Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically a method and structure for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process. Background Technology

[0002] Analog integrated circuits and mixed-signal circuits, as an indispensable part of current circuit systems, will find increasing use in applications requiring high-speed, high-performance communication or external interfaces. With the increasing demand for higher-performance products such as high density, low power consumption, and high-speed, high-drive capability, coupled with the continuous shrinking of linewidths and the advantages of CMOS voltage drive, as well as the need for related high-precision AD / DA products, integrating CMOS into bipolar process platforms has become a new direction. Bipolar circuits are characterized by high speed, strong current drive capability, and high analog accuracy, while CMOS circuits have unparalleled advantages in high integration and low power consumption. In today's integrated circuit manufacturing industry, which constantly pursues higher performance and perfection, the perfect combination of the complementary advantages of these two processes has given rise to the new BiCMOS process.

[0003] High-speed BiCMOS process platforms have long been a gap in domestic bipolar process platforms, playing an irreplaceable role in the manufacturing of high-end high-speed amplifiers and high-precision AD / DA chips. These chips are widely used in various precision communication equipment, high-precision testing instruments, and automotive electronics. Currently, these products are all imported from abroad. In particular, high-speed BiCMOS currently faces many challenges, such as high process integration, complex manufacturing processes, high costs, and difficulty in guaranteeing yield. To overcome these challenges, continuous research and improvement of manufacturing process technologies are needed to enhance circuit performance and reliability.

[0004] Therefore, there is an urgent need for a method that can integrate high-speed bipolar transistors and CMOS devices in a single manufacturing process without significantly increasing process complexity. Summary of the Invention

[0005] The purpose of this invention is to provide a method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, characterized by comprising the following steps:

[0006] 1) Provide SOI silicon substrate.

[0007] 2) The N-type primary buried layer of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer of the thin gate oxide NMOS, and the P-type secondary buried layer of the thick gate oxide NMOS are formed sequentially.

[0008] 3) An epitaxial layer is formed on an SOI silicon substrate.

[0009] 4) Form a P-type primary well region for a thin-gate oxide NMOS and a P-type secondary well region for a thick-gate oxide NMOS in the epitaxial layer.

[0010] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and thin gate oxide NMOS / thick gate oxide NMOS, including trench isolation oxide layer and trench isolation polycrystalline silicon.

[0011] 6) Perform N-type through-hole implantation of the collector of the dual polycrystalline self-aligned bipolar junction transistor and connect it with the N-type primary buried layer.

[0012] 7) Form a selectively oxidized field oxide layer, rinse away excess silicon nitride, and form active and field regions in the dual polycrystalline self-aligned bipolar junction transistor and the thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0013] 8) Remove the pre-oxide layer in the thin gate oxide NMOS / thick gate oxide NMOS regions.

[0014] 9) Grow a thick gate oxide layer to form a thick gate oxide layer.

[0015] 10) Remove the gate oxide of the thin-gate oxide NMOS, and retain the gate oxide of the bipolar transistor and the thick-gate oxide NMOS region.

[0016] 11) Grow the gate oxide layer to form a thin gate oxide layer.

[0017] 12) Deposit the first layer of polysilicon and perform gate polysilicon implantation.

[0018] 13) Remove excess polysilicon to form the polysilicon gate region of thin-gate oxide NMOS and the polysilicon gate region of thick-gate oxide NMOS.

[0019] 14) Perform source and drain heavy doping on thin-gate oxide NMOS and LDD implantation and source and drain heavy doping on thick-gate oxide NMOS.

[0020] 15) Deposit the first dielectric layer before depositing TEOS metal, and remove the oxide layer in the bipolar transistor region.

[0021] 16) Deposit a second layer of polysilicon, perform contact implantation of the outer base region and collector, remove excess polysilicon, and form a polysilicon collector and a polysilicon base.

[0022] 17) Deposit the second dielectric layer before the TEOS metal, remove the oxide layer and polysilicon, and form the base region window of the bipolar transistor.

[0023] 18) P-type base region implantation, connected with the P-heavily doped outer base region 132 diffused into silicon through polycrystalline silicon to form a double base region.

[0024] 19) An L-shaped sidewall structure emitter window is formed by multiple deposition and etching processes, including a sidewall oxide layer and a sidewall silicon nitride layer.

[0025] 20) Forming a polycrystalline silicon emitter and an N-type heavily doped emitter region for a dual polycrystalline self-aligned bipolar junction transistor.

[0026] 21) Deposit metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

[0027] Furthermore, the P-type primary buried layer of the NMOS is located between the N-type primary buried layer and the N-type secondary buried layer of the PMOS, and does not contact the N-type primary buried layer or the N-type secondary buried layer of the PMOS.

[0028] Furthermore, the bottom trench isolation oxide layer is in contact with the oxide layer on the SOI substrate.

[0029] Furthermore, in step 7), a field oxide layer with a selectively oxidized structure is formed using a photomask.

[0030] In step 8), the pre-oxide layer in the thin gate oxide NMOS / thick gate oxide NMOS region is removed by wet etching using a photomask.

[0031] In step 10), the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photomask.

[0032] In step 13), excess polycrystalline material is removed by dry etching using a photomask.

[0033] In step 15), the oxide layer of the bipolar transistor region is removed by wet etching using a photomask.

[0034] In step 16), a photomask is used to implant the outer base region and the collector contact, and the excess polysilicon is removed by dry etching using a photomask.

[0035] In step 17), the oxide layer and polycrystalline material are removed by dry etching using a photomask.

[0036] Further, in step 14), after performing source and drain heavy doping on the thin gate oxide NMOS and LDD implantation and source and drain heavy doping on the thick gate oxide NMOS, the P-type primary well heavy doping, N-type source region, and N-type drain region of the thin gate oxide NMOS are formed, and the P-type secondary well heavy doping, source region LDD, drain region LDD, N-type source region, and N-type drain region of the thick gate oxide NMOS are formed.

[0037] Furthermore, in step 20), the steps of forming the polycrystalline silicon emitter and the N-type heavily doped emitter region of the dual polycrystalline self-aligned bipolar junction transistor are as follows:

[0038] A third layer of polysilicon is deposited, and the emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photomask.

[0039] The excess polysilicon is etched away using a photomask to form the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0040] N-type heavily doped emitter regions are formed by emitter annealing.

[0041] Further, the step of depositing metal to form a dual polycrystalline self-aligned bipolar junction transistor metal structure includes:

[0042] Holes are opened in the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor, and metal is deposited to form collector metal and base metal.

[0043] Emitter metal is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0044] Holes are opened and metals are deposited on the N-type source region, drain region, and P-well of the thin gate oxide NMOS to form source metal, drain metal, and BACK terminal metal.

[0045] A hole is opened and metal is deposited on the gate polysilicon of a thin gate oxide NMOS to form the gate metal. A hole is opened and metal is deposited on the P-type source region, drain region, and N-well heavily doped silicon substrate of a thick gate oxide NMOS to form the source metal, drain metal, and BACK terminal metal.

[0046] A hole is opened on the gate polysilicon of a thick gate oxide NMOS and metal is deposited to form the gate metal.

[0047] Furthermore, the SOI silicon substrate includes a P-type substrate, an oxide layer on the substrate, and silicon on the oxide layer, or the SOI silicon substrate is a single-crystal silicon substrate.

[0048] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0049] The dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of both.

[0050] The thin-gate oxide NMOS / thick-gate oxide NMOS refers to NMOS, PMOS, or a combination of both.

[0051] Furthermore, the polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

[0052] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor (DPT) process, wherein the DPT with integrated thick and thin gate oxide CMOS devices is fabricated by the method.

[0053] The technical effects of this invention are undeniable. This invention provides a method and structure for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process. Without significantly increasing the overall process complexity and technical difficulty, it achieves the integration of dual polycrystalline self-aligned polycrystalline silicon emitter transistors and thick and thin gate oxide CMOS devices using the same process flow.

[0054] The beneficial effects of this invention are as follows:

[0055] 1) This invention proposes a method and structure for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process. Without significantly increasing the overall process complexity and technical difficulty, the integration of dual polycrystalline self-aligned polycrystalline silicon emitter transistors and thick and thin gate oxide CMOS devices is achieved in the same process flow, reducing process costs and improving processing efficiency. It is particularly suitable for the development of high-speed BiCMOS related processes.

[0056] 2) The semiconductor devices in this invention can realize various combinations of high-performance NPN / PNP and thick and thin gate oxide CMOS devices, effectively improving the overall device characteristics of the process, so as to meet the application technology fields with wider and higher requirements and improve the electrical performance of the chip. Attached Figure Description

[0057] Figure 1 is a schematic diagram of the steps of the method for integrating thick and thin gate oxide CMOS devices in the dual polycrystalline self-aligned bipolar junction transistor process of the present invention.

[0058] Figures 2-16 show the process flow diagrams of the method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to an embodiment of the present invention.

[0059] In the figure: P-type substrate 100, oxide layer on substrate 101, silicon on oxide layer 102, N-type primary buried layer 103, P-type primary buried layer 104, P-type secondary buried layer 105, epitaxial layer 106, P-type primary well region 107, P-type secondary well region 108, trench isolation oxide layer 109, trench isolation polysilicon 110, N-type through-hole 111, field oxide layer 112, thick gate oxide layer 113, thin gate oxide layer 114, thin gate oxide NMOS polysilicon gate 115, thick gate oxide NMOS polysilicon gate 116, thick gate oxide NMOS source region LDD 117, thick gate oxide NMOS drain region LDD 118, heavily doped P-type primary well 119, thin gate oxide NMOS N-type source region 120, thin gate oxide NMOS N-type drain region 121, heavily doped P-type secondary well 122, thick gate oxide NMOS N-type source region 123, thick gate oxide 124. NMOS N-type drain region, 125. First dielectric layer before TEOS metal, 126. Polysilicon collector, 127. Polysilicon base, 128. Second dielectric layer before TEOS metal, 129. Sidewall oxide layer, 130. Sidewall silicon nitride, 131. Polysilicon emitter, 132. P-type heavily doped outer base region, 133. P-type base region, 134. N-type heavily doped emitter region, 135. Collector metal, 136. Base metal, 137. Emitter metal, 138. Thin gate oxide NMOS BACK terminal metal, 139. Thin gate oxide NMOS source metal, 140. Thin gate oxide NMOS gate metal, 141. Thin gate oxide NMOS drain metal, 142. Thick gate oxide NMOS BACK terminal metal, 143. Thick gate oxide NMOS source metal, 144. Thick gate oxide NMOS gate metal, 145. Thick gate oxide NMOS drain metal. Detailed Implementation

[0060] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0061] Example 1:

[0062] Referring to Figures 1-16, a method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process includes the following steps:

[0063] 1) Provide SOI silicon substrate.

[0064] 2) The N-type primary buried layer 103 of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer 104 of the thin gate oxide NMOS, and the P-type secondary buried layer 105 of the thick gate oxide NMOS are formed sequentially.

[0065] 3) An epitaxial layer 106 is formed on an SOI silicon substrate.

[0066] 4) A P-type primary well region 107 for a thin gate oxide NMOS and a P-type secondary well region 108 for a thick gate oxide NMOS are formed in the epitaxial layer.

[0067] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and thin gate oxide NMOS / thick gate oxide NMOS, including trench isolation oxide layer 109 and trench isolation polycrystalline silicon 110.

[0068] 6) Perform N-type penetration injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor 111, and connect it with the N-type primary buried layer 103.

[0069] 7) Form a selectively oxidized field oxide layer 112, rinse away excess silicon nitride, and form an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and the thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0070] 8) Remove the pre-oxide layer 146 in the thin gate oxide NMOS / thick gate oxide NMOS region.

[0071] 9) A thick gate oxide layer is grown to form a thick gate oxide layer 113.

[0072] 10) Remove the gate oxide of the thin-gate oxide NMOS, and retain the gate oxide of the bipolar transistor and the thick-gate oxide NMOS region.

[0073] 11) Grow a gate oxide layer to form a thin gate oxide 114.

[0074] 12) Deposit the first layer of polysilicon and perform gate polysilicon implantation.

[0075] 13) Remove excess polysilicon to form the polysilicon gate region 115 of the thin gate oxide NMOS and the polysilicon gate region 116 of the thick gate oxide NMOS.

[0076] 14) Perform source and drain heavy doping on thin-gate oxide NMOS and LDD implantation and source and drain heavy doping on thick-gate oxide NMOS.

[0077] 15) Before depositing the first dielectric layer 125 of TEOS metal, remove the oxide layer of the bipolar transistor region.

[0078] 16) Deposit a second layer of polysilicon, perform contact implantation of the outer base region and collector, remove excess polysilicon, and form a polysilicon collector 126 and a polysilicon base 127.

[0079] 17) Deposit the second dielectric layer 128 before the TEOS metal, remove the oxide layer and polysilicon, and form the base region window of the bipolar transistor.

[0080] 18) P-type base region 133 is implanted and connected to the P-heavily doped outer base region 132 diffused into the polycrystalline silicon, forming a double base region through the polycrystalline silicon base connection.

[0081] 19) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching processes, including a sidewall oxide layer 129 and a sidewall silicon nitride layer 130.

[0082] 20) Forming a polysilicon emitter 131 and an N-type heavily doped emitter region 134 for a dual polysilicon self-aligned bipolar junction transistor.

[0083] 21) Deposit metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

[0084] The P-type primary buried layer 104 of the NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS, and does not contact the N-type primary buried layer 103 or the N-type secondary buried layer 105 of the PMOS.

[0085] The bottom trench isolation oxide layer 109 is in contact with the oxide layer 101 on the SOI substrate.

[0086] In step 7), a field oxide layer 112 with a selectively oxidized structure is formed using a photomask.

[0087] In step 8), the pre-oxide layer 146 in the thin gate oxide NMOS / thick gate oxide NMOS region is removed by wet etching using a photomask.

[0088] In step 10), the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photomask.

[0089] In step 13), excess polycrystalline material is removed by dry etching using a photomask.

[0090] In step 15), the oxide layer of the bipolar transistor region is removed by wet etching using a photomask.

[0091] In step 16), a photomask is used to implant the outer base region and the collector contact, and the excess polysilicon is removed by dry etching using a photomask.

[0092] In step 17), the oxide layer and polycrystalline material are removed by dry etching using a photomask.

[0093] In step 14), after performing source and drain heavy doping on the thin gate oxide NMOS and LDD implantation and source and drain heavy doping on the thick gate oxide NMOS, the following structures are formed: P-type primary well heavy doping 119, N-type source region 120, and N-type drain region 121 on the thin gate oxide NMOS, and P-type secondary well heavy doping 122, source region LDD 117, drain region LDD 118, N-type source region 123, and N-type drain region 124 on the thick gate oxide NMOS.

[0094] In step 20), the steps for forming the polysilicon emitter 131 and the N-type heavily doped emitter region 134 of the dual polysilicon self-aligned bipolar junction transistor are as follows:

[0095] A third layer of polysilicon is deposited, and the emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photomask.

[0096] The excess polysilicon is etched away using a photomask to form the polysilicon emitter 131 of the dual polysilicon self-aligned bipolar junction transistor.

[0097] N-type heavily doped emitter region 134 is formed by emitter region annealing.

[0098] The steps of depositing metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure include:

[0099] Holes are made in the polycrystalline collector region and the polycrystalline base region of the dual polycrystalline self-aligned bipolar junction transistor, and metal is deposited to form collector metal 135 and base metal 136.

[0100] Emitter metal 137 is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0101] Holes are opened and metals are deposited on the N-type source region, drain region, and P-well of the thin gate oxide NMOS to form source metal 139, drain metal 141, and BACK terminal metal 138.

[0102] A hole is opened and metal is deposited on the gate polysilicon of the thin gate oxide NMOS to form gate metal 136. A hole is opened and metal is deposited on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick gate oxide NMOS to form source metal 143, drain metal 145, and BACK terminal metal 142.

[0103] A hole is opened on the gate polysilicon of the thick gate oxide NMOS and metal is deposited to form the gate metal 144.

[0104] The SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single-crystal silicon substrate.

[0105] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0106] The dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of both.

[0107] The thin-gate oxide NMOS / thick-gate oxide NMOS refers to NMOS, PMOS, or a combination of both.

[0108] The polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

[0109] Example 2:

[0110] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process includes the following steps:

[0111] 1) Provide SOI silicon substrate.

[0112] 2) The N-type primary buried layer 103 of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer 104 of the thin gate oxide NMOS, and the P-type secondary buried layer 105 of the thick gate oxide NMOS are formed sequentially.

[0113] 3) An epitaxial layer 106 is formed on an SOI silicon substrate.

[0114] 4) A P-type primary well region 107 for a thin gate oxide NMOS and a P-type secondary well region 108 for a thick gate oxide NMOS are formed in the epitaxial layer.

[0115] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and thin gate oxide NMOS / thick gate oxide NMOS, including trench isolation oxide layer 109 and trench isolation polycrystalline silicon 110.

[0116] 6) Perform N-type penetration injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor 111, and connect it with the N-type primary buried layer 103.

[0117] 7) Form a selectively oxidized field oxide layer 112, rinse away excess silicon nitride, and form an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and the thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0118] 8) Remove the pre-oxide layer 146 in the thin gate oxide NMOS / thick gate oxide NMOS region.

[0119] 9) A thick gate oxide layer is grown to form a thick gate oxide layer 113.

[0120] 10) Remove the gate oxide of the thin-gate oxide NMOS, and retain the gate oxide of the bipolar transistor and the thick-gate oxide NMOS region.

[0121] 11) Grow a gate oxide layer to form a thin gate oxide 114.

[0122] 12) Deposit the first layer of polysilicon and perform gate polysilicon implantation.

[0123] 13) Remove excess polysilicon to form the polysilicon gate region 115 of the thin gate oxide NMOS and the polysilicon gate region 116 of the thick gate oxide NMOS.

[0124] 14) Perform source and drain heavy doping on thin-gate oxide NMOS and LDD implantation and source and drain heavy doping on thick-gate oxide NMOS.

[0125] 15) Before depositing the first dielectric layer 125 of TEOS metal, remove the oxide layer of the bipolar transistor region.

[0126] 16) Deposit a second layer of polysilicon, perform contact implantation of the outer base region and collector, remove excess polysilicon, and form a polysilicon collector 126 and a polysilicon base 127.

[0127] 17) Deposit the second dielectric layer 128 before the TEOS metal, remove the oxide layer and polysilicon, and form the base region window of the bipolar transistor.

[0128] 18) P-type base region 133 is implanted and connected to the P-heavily doped outer base region 132 diffused into the polycrystalline silicon, forming a double base region through the polycrystalline silicon base connection.

[0129] 19) An L-shaped sidewall structure emission region window is formed by multiple deposition and etching processes, including a sidewall oxide layer 129 and a sidewall silicon nitride layer 130.

[0130] 20) Forming a polysilicon emitter 131 and an N-type heavily doped emitter region 134 for a dual polysilicon self-aligned bipolar junction transistor.

[0131] 21) Deposit metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

[0132] Example 3:

[0133] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, with the same technical content as in Embodiment 2, further wherein the P-type primary buried layer 104 of the NMOS is located between the N-type primary buried layer 103 and the N-type secondary buried layer 105 of the PMOS, and does not contact the N-type primary buried layer 103 or the N-type secondary buried layer 105 of the PMOS.

[0134] Example 4:

[0135] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-3, further wherein the bottom trench isolation oxide layer 109 of the trench isolation layer is in contact with the oxide layer 101 on the SOI substrate.

[0136] Example 5:

[0137] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-4, further wherein, in step 7, a field oxide layer 112 with a selective oxide structure is formed using a photomask.

[0138] In step 8, the pre-oxide layer 146 in the thin gate oxide NMOS / thick gate oxide NMOS region is removed by wet etching using a photomask.

[0139] In step 10, the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photomask.

[0140] In step 13, excess polycrystalline material is removed by dry etching using a photomask.

[0141] In step 15, the oxide layer of the bipolar transistor region is removed by wet etching using a photomask.

[0142] In step 16, a photomask is used to implant the outer base region and the collector contact, and the excess polysilicon is removed by dry etching using the photomask.

[0143] In step 17, the oxide layer and polycrystalline material are removed by dry etching using a photomask.

[0144] Example 6:

[0145] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, with the same technical content as any one of embodiments 2-5, further wherein, in step 14, after performing source and drain heavy doping of the thin gate oxide NMOS and LDD implantation and source and drain heavy doping of the thick gate oxide NMOS, P-type primary well heavy doping 119, N-type source region 120, and N-type drain region 121 of the thin gate oxide NMOS are formed, and P-type secondary well heavy doping 122, source region LDD 117, drain region LDD 118, N-type source region 123, and N-type drain region 124 of the thick gate oxide NMOS are formed.

[0146] Example 7:

[0147] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-6, further comprising the following steps in step 20: forming the polycrystalline silicon emitter 131 and the N-type heavily doped emitter region 134 of the dual polycrystalline self-aligned bipolar junction transistor.

[0148] A third layer of polysilicon is deposited, and the emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photomask.

[0149] The excess polysilicon is etched away using a photomask to form the polysilicon emitter 131 of the dual polysilicon self-aligned bipolar junction transistor.

[0150] N-type heavily doped emitter region 134 is formed by emitter region annealing.

[0151] Example 8:

[0152] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, with the technical content being the same as any one of embodiments 2-7, further comprising the step of depositing metal to form a dual-polycrystalline self-aligned bipolar junction transistor metal structure, including:

[0153] Holes are made in the polycrystalline collector region and the polycrystalline base region of the dual polycrystalline self-aligned bipolar junction transistor, and metal is deposited to form collector metal 135 and base metal 136.

[0154] Emitter metal 137 is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor.

[0155] Holes are opened and metals are deposited on the N-type source region, drain region, and P-well of the thin gate oxide NMOS to form source metal 139, drain metal 141, and BACK terminal metal 138.

[0156] A hole is opened and metal is deposited on the gate polysilicon of the thin gate oxide NMOS to form gate metal 136. A hole is opened and metal is deposited on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick gate oxide NMOS to form source metal 143, drain metal 145, and BACK terminal metal 142.

[0157] A hole is opened on the gate polysilicon of the thick gate oxide NMOS and metal is deposited to form the gate metal 144.

[0158] Example 9:

[0159] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-8. Further, the SOI silicon substrate includes a P-type substrate 100, an oxide layer 101 on the substrate, and silicon 102 on the oxide layer, or the SOI silicon substrate is a single crystal silicon substrate.

[0160] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0161] The dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of both.

[0162] The thin-gate oxide NMOS / thick-gate oxide NMOS refers to NMOS, PMOS, or a combination of both.

[0163] Example 10:

[0164] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, the technical content of which is the same as any one of embodiments 2-9, further wherein the polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

[0165] Example 11:

[0166] A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process, wherein the dual polycrystalline self-aligned bipolar junction transistor integrating the thick and thin gate oxide CMOS devices is prepared by the method described in any one of Examples 1-10.

[0167] Example 12:

[0168] A method and structure for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, the technical solution of which is as follows:

[0169] 1) Provide an SOI silicon substrate (including a P-type substrate 100, an oxide layer 101 on the substrate, and silicon on the oxide layer 102).

[0170] 2) Next, an N-type primary buried layer 103 is formed for the dual polycrystalline self-aligned bipolar junction transistor (left), a P-type primary buried layer 104 is formed for the thin gate oxide NMOS (middle), and a P-type secondary buried layer 105 is formed for the thick gate oxide NMOS (right).

[0171] 3) An epitaxial layer 106 is formed on the substrate.

[0172] 4) A P-type primary well region 107 for a thin gate oxide NMOS and a P-type secondary well region 108 for a thick gate oxide NMOS are formed in the epitaxial layer.

[0173] 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and thin-gate oxide NMOS / thick-gate oxide NMOS, including a trench isolation oxide layer 109 and a trench isolation polycrystalline silicon layer 110. The bottom trench isolation oxide layer 109 is in contact with the oxide layer 101 on the SOI substrate.

[0174] 6) Perform N-type penetration injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor 111, and connect it with the N-type primary buried layer 103.

[0175] 7) Using a photomask, a selectively oxidized field oxide layer 112 is formed, excess silicon nitride is washed away, and active and field regions are formed in the dual polycrystalline self-aligned bipolar junction transistor and the thin gate oxide NMOS / thick gate oxide NMOS regions, respectively.

[0176] 8) Use a photomask to remove the pre-oxide layer 146 in the thin gate oxide NMOS / thick gate oxide NMOS region by wet etching.

[0177] 9) Growth of a thick gate oxide layer is carried out to form a thick gate oxide layer 113.

[0178] 10) Use a photomask to remove the gate oxide of the thin-gate oxide NMOS by wet etching, while retaining the gate oxide of the bipolar transistor and the thick-gate oxide NMOS region.

[0179] 11) Grow a gate oxide layer to form a thin gate oxide 114.

[0180] 12) Deposit the first layer of polysilicon and perform gate polysilicon implantation.

[0181] 13) Use a photomask to remove excess polysilicon through dry etching to form the polysilicon gate region 115 of the thin gate oxide NMOS and the polysilicon gate region 116 of the thick gate oxide NMOS.

[0182] 14) Based on this, perform heavy source and drain doping on the thin-gate oxide NMOS and LDD implantation and heavy source and drain doping on the thick-gate oxide NMOS. This forms the P-type primary well heavy doping 119, N-type source region 120, and N-type drain region 121 of the thin-gate oxide NMOS, and the P-type secondary well heavy doping 122, source region LDD 117, drain region LDD 118, N-type source region 123, and N-type drain region 124 of the thick-gate oxide NMOS.

[0183] 15) Before depositing the first dielectric layer 125 of TEOS metal, the oxide layer of the bipolar transistor region is removed by wet etching using a photomask.

[0184] 16) Deposit the second layer of polysilicon, use a photomask to implant the outer base region and collector contacts, and use a photomask to remove excess polysilicon by dry etching to form the polysilicon collector 126 and the polysilicon base 127.

[0185] 17) Deposit the second dielectric layer 128 before the TEOS metal, and use a photomask to remove the oxide layer and polysilicon through dry etching to form the base region window of the bipolar transistor.

[0186] 18) P-type base region 133 is implanted and connected to the P-heavily doped outer base region 132 diffused into the polycrystalline silicon, forming a double base region through the polycrystalline silicon base connection.

[0187] 19) Then, an L-shaped sidewall structure emission window is formed by multiple deposition and etching processes, including a sidewall oxide layer 129 and a sidewall silicon nitride layer 130.

[0188] 20) Deposit the third layer of polysilicon, use a photomask to implant and form the emitter region of the double polysilicon self-aligned bipolar junction transistor, use a photomask to dry etch out the excess polysilicon to form the polysilicon emitter 131 of the double polysilicon self-aligned bipolar junction transistor, and form the N-type heavily doped emitter region 134 by annealing the emitter region.

[0189] 21) Holes are opened and metals are deposited on the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor to form collector metal 135 and base metal 136. Metals are deposited on the polycrystalline silicon emitter of the dual polycrystalline self-aligned bipolar junction transistor to form emitter metal 137. Holes are opened and metals are deposited on the N-type source region, drain region, and P-well heavily doped silicon substrate of the thin gate oxide NMOS to form source metal 139, drain metal 141, and BACK terminal metal 138. Holes are opened and metals are deposited on the gate polycrystalline of the thin gate oxide NMOS to form gate metal 136. Holes are opened and metals are deposited on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick gate oxide NMOS to form source metal 143, drain metal 145, and BACK terminal metal 142. Holes are opened and metals are deposited on the gate polycrystalline of the thick gate oxide NMOS to form gate metal 144.

[0190] The SOI silicon substrate (including a P-type substrate, an oxide layer on the substrate, and silicon on the oxide layer) can also be a single-crystal silicon substrate.

[0191] The materials of the SOI silicon substrate include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon.

[0192] The dual polycrystalline self-aligned bipolar junction transistor can be NPN, PNP, or a combination of both.

[0193] The thin-gate oxide NMOS / thick-gate oxide NMOS can be NMOS, PMOS, or a combination of both. The polysilicon collector, polysilicon base, and polysilicon emitter are composed of one or more repeating structural units.

Claims

1. [Amended according to Rule 26, 22.01.2025] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, characterized in that, Includes the following steps: 1) Provide SOI silicon substrates; 2) The N-type primary buried layer (103) of the dual polycrystalline self-aligned bipolar junction transistor, the P-type primary buried layer (104) of the thin gate oxide NMOS, and the P-type secondary buried layer (105) of the thick gate oxide NMOS are formed sequentially. 3) An epitaxial layer (106) is formed on the SOI silicon substrate; 4) A P-type primary well region (107) of a thin gate oxide NMOS and a P-type secondary well region (108) of a thick gate oxide NMOS are formed in the epitaxial layer; 5) Forming a fully dielectric island isolation for dual polycrystalline self-aligned bipolar junction transistors and thin gate oxide NMOS / thick gate oxide NMOS, including trench isolation oxide layer (109) and trench isolation polycrystalline silicon (110); 6) Perform N-type penetration (111) injection of the collector of the dual polycrystalline self-aligned bipolar junction transistor and connect it with the N-type primary buried layer (103); 7) Form a selectively oxidized field oxide layer (112), rinse away excess silicon nitride, and form an active region and a field region in the dual polycrystalline self-aligned bipolar junction transistor and the thin gate oxide NMOS / thick gate oxide NMOS regions, respectively. 8) Remove the pre-oxide layer (146) in the thin gate oxide NMOS / thick gate oxide NMOS region; 9) A thick gate oxide layer is grown to form a thick gate oxide layer (113); 10) Remove the gate oxide of the thin-gate oxide NMOS, and retain the gate oxide of the bipolar transistor and the thick-gate oxide NMOS region; 11) A thin gate oxide layer is grown to form a thin gate oxide layer (114); 12) Deposit the first layer of polysilicon and perform gate polysilicon implantation; 13) Remove excess polysilicon to form the polysilicon gate region of thin gate oxide NMOS (115) and the polysilicon gate region of thick gate oxide NMOS (116); 14) Perform source and drain heavy doping on thin-gate oxide NMOS and LDD implantation and source and drain heavy doping on thick-gate oxide NMOS; 15) Deposit the first dielectric layer (125) before depositing the TEOS metal, and remove the oxide layer in the bipolar transistor region; 16) Deposit the second layer of polysilicon, perform contact implantation of the outer base region and collector, remove excess polysilicon, and form polysilicon collector (126) and polysilicon base (127). 17) Deposit the second dielectric layer (128) before the TEOS metal, remove the oxide layer and polysilicon, and form the base region window of the bipolar transistor; 18) A P-type base region (133) is implanted and connected to the P-doped outer base region 132 diffused into the polycrystalline silicon through the polycrystalline silicon base to form a double base region; 19) An L-shaped sidewall structure emission window is formed by multiple deposition and etching processes, including a sidewall oxide layer (129) and a sidewall silicon nitride layer (130); 20) Forming a polysilicon emitter (131) and an N-type heavily doped emitter region (134) for a dual polysilicon self-aligned bipolar junction transistor; 21) Deposit metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure.

2. The method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The P-type primary buried layer (104) of the NMOS is located between the N-type primary buried layer (103) and the N-type secondary buried layer (105) of the PMOS, and does not contact the N-type primary buried layer (103) or the N-type secondary buried layer (105) of the PMOS.

3. The method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The bottom trench isolation oxide layer (109) is in contact with the oxide layer (101) on the SOI substrate.

4. [Amended according to Rule 26, 22.01.2025] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 7), a field oxide layer (112) with a selectively oxidized structure is formed using a photomask; In step 8), the pre-oxide layer in the thin gate oxide NMOS / thick gate oxide NMOS region is removed by wet etching using a photomask (146); In step 10), the gate oxide of the thin gate oxide NMOS is removed by wet etching using a photomask; In step 13), excess polycrystalline material is removed by dry etching using a photomask; In step 15), the oxide layer of the bipolar transistor region is removed by wet etching using a photomask; In step 16), a photomask is used to implant the outer base region and the collector contact, and the excess polycrystalline material is removed by dry etching using a photomask. In step 17), the oxide layer and polycrystalline material are removed by dry etching using a photomask.

5. A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 14), after performing source and drain heavy doping on the thin gate oxide NMOS and LDD implantation and source and drain heavy doping on the thick gate oxide NMOS, the thin gate oxide NMOS is formed with P-type primary well heavy doping (119), N-type source region (120), and N-type drain region (121), and the thick gate oxide NMOS is formed with P-type secondary well heavy doping (122), source region LDD (117), drain region LDD (118), N-type source region (123), and N-type drain region (124).

6. [Amended according to Rule 26, 22.01.2025] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: In step 20), the steps of forming the polycrystalline silicon emitter (131) and the N-type heavily doped emitter region (134) of the dual polycrystalline self-aligned bipolar junction transistor are as follows: A third layer of polysilicon is deposited, and the emitter region of a double polysilicon self-aligned bipolar junction transistor is formed by implantation using a photomask; The excess polysilicon is etched away using a photomask to form the polysilicon emitter of the dual polysilicon self-aligned bipolar junction transistor (131). N-type heavily doped emitter regions (134) are formed by emitter annealing.

7. A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The steps of depositing metal to form a double polycrystalline self-aligned bipolar junction transistor metal structure include: Holes are opened and metal is deposited on the polycrystalline collector region and the double base region of the dual polycrystalline self-aligned bipolar junction transistor to form collector metal (135) and base metal (136); Emitter metal is formed by depositing metal on the polysilicon emitter of a dual polysilicon self-aligned bipolar junction transistor (137); Holes are opened and metals are deposited on the N-type source region, drain region, and P-well heavily doped silicon substrate of thin gate oxide NMOS to form source metal (139), drain metal (141) and BACK terminal metal (138). A hole is opened and metal is deposited on the gate polysilicon of the thin gate oxide NMOS to form the gate metal (136). A hole is opened and metal is deposited on the P-type source region, drain region, and N-well heavily doped silicon substrate of the thick gate oxide NMOS to form the source metal (143), drain metal (145), and BACK terminal metal (142). A hole is opened on the gate polysilicon of the thick gate oxide NMOS and metal is deposited to form the gate metal (144).

8. [Amended according to Rule 26, 22.01.2025] A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The SOI silicon substrate includes a P-type substrate (100), an oxide layer (101) on the substrate, and silicon (102) on the oxide layer; or, the SOI silicon substrate is a single-crystal silicon substrate. The material of the SOI silicon substrate includes bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium silicon; The dual polycrystalline self-aligned bipolar junction transistor is NPN, PNP, or a combination of both. The thin-gate oxide NMOS / thick-gate oxide NMOS refers to NMOS, PMOS, or a combination of both.

9. A method for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor process according to claim 1, characterized in that: The polycrystalline silicon collector, polycrystalline silicon base, and polycrystalline silicon emitter are composed of one or more repeating structural units.

10. A method for integrating thick and thin gate oxide CMOS devices in a dual-polycrystalline self-aligned bipolar junction transistor process, characterized in that: The dual polycrystalline self-aligned bipolar junction transistor integrating thick and thin gate oxide CMOS devices is prepared by the method described in any one of claims 1-9.

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