Phase offset reduction between beam forming integrated circuit (BFIC) channels

Abstract

An apparatus includes a first coupler that couples a first portion of a test signal to a first input of first beam forming integrated circuit (BFIC) electronics and second portion of the test signal to second input of second BFIC electronics. A second coupler combines a first output signal from the first BFIC electronics and a second output signal from the second BFIC electronics. The collective phase offset due to the first coupler and the second coupler is 180 degrees. During a test mode, a controller eliminates, or at least reduces, a difference in phase between the first and second BFIC electronics by adjusting a phase shifter in at least one of the BFIC electronics. The BFIC electronics have the same phase offset when the power detected by a power detector at the second coupler output is zero. The controller applies the control signals during beam forming operation of the electronics.

Description

KWIC 00013 PC-1 -PHASE OFFSET REDUCTION BETWEEN BEAM FORMING INTEGRATED CIRCUIT (BFIC) CHANNELSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to Provisional Application No. 63 / 704,387, entitled “INTER-CHIP PHASE DIFFERENCE DETECTING FOR LARGE PHASE ARRAY ANTENNA MODULES” and filed October 7, 2024, assigned to the assignee hereof and hereby expressly incorporated by reference in its entirety.FIELD

[0002] This invention generally relates to beam forming integrated circuits (BFICs) and more particularly to phase offset reduction between BFIC channels.BACKGROUND

[0003] Large phase array antenna modules are used in wireless communication systems, satellite communications, and autonomous driving assistance systems. For example, massive Multiple Input Multiple Output (MIMO) antenna systems implemented on base stations (gNBs) facilitate large numbers of users in cellular systems where the massive MIMO antenna array may support hundreds of receiving and transmitting antenna elements. These MIMO systems utilize multiple beam-forming transceivers (TRX) connected to the antenna elements where the TRXs may be implemented with beam-forming integrated chips (BFICs). In some situations, a BFIC may support 8 transmitter (TX) channels and 8 receiver (RX) channels or 16 TX and 16 RX channels. The TX and RX channels are electronically controlled to steer a radio frequency (RF) beam. Commercial beam-forming transceivers are usually designed and implemented by using monolithic integrated semiconductor technologies for large volume fabrications and affordability.KWIC 00013 PC-2-SUMMARY

[0004] An apparatus includes a first coupler that couples a first portion of a test signal to a first input of first beam forming integrated circuit (BFIC) electronics and second portion of the test signal to second input of second BFIC electronics. A second coupler combines a first output signal from the first BFIC electronics and a second output signal from the second BFIC electronics. The collective phase offset due to the first coupler and the second coupler is 180 degrees. During a test mode, a controller eliminates, or at least reduces, a difference is phase between the first and second BFIC electronics by adjusting a phase shifter in at least one of the BFIC electronics. The BFIC electronics have the same phase offset when the power detected by a power detector at the second coupler output is a minimum level. The controller generates one or more control signals to control the adjust the phase offset during the test mode and applies the control signals during beam forming operation of the electronics.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 A is a block diagram of an example of a multiple BFIC module (apparatus) with inter-chip phase difference detection and compensation.

[0006] FIG. 1 B is a block diagram of an example of a single BFIC module (apparatus) including the first electronics and the second electronics with phase difference detection and compensation.

[0007] FIG. 2A is a schematic illustration of an example of a multiple BFIC module including a first BFIC, a second BFIC, a first coupler, and a second coupler, directional couplers and switch circuits.

[0008] FIG. 2B is a schematic illustration of an example of the multiple BFIC module in a receiver test mode where the first coupler is functioning as a combiner, the second coupler is functioning as a splitter and the switch circuits are configured in the receiver test mode.KWIC 00013 PC-3-

[0009] FIG. 3A is a schematic illustration of an example of a multiple BFIC module in a transmitter test mode where the first coupler is a Wilkinson divider, the second coupler is a rat race combiner.

[0010] FIG. 3B is a schematic illustration of an example of the multiple BFIC module in a receiver test mode where the Wilkison coupler is functioning as a Wilkinson combiner, the rat race coupler is functioning as a splitter, and the switch circuits, are configured in the receiver test mode.

[0011] FIG. 4A is a schematic illustration of an example of a multiple BFIC module in a transmitter test mode where the first coupler is a quadrature hybrid S coupler functioning a splitter and the second coupler is a quadrature hybrid C coupler functioning a combiner.

[0012] FIG. 4B is a schematic illustration of an example of the multiple BFIC module in a receiver test mode where the quadrature hybrid S coupler is functioning as a combiner, the quadrature hybrid C coupler is functioning as a splitter, and the switch circuits are configured in the receiver test mode.DETAILED DESCRIPTION

[0013] As discussed above, conventional systems employ beam-forming transceivers designed and implemented by using monolithic integrated semiconductor technologies for large volume fabrications and affordability. These BFICs, however, suffer from substantial process variations. Some fabrication techniques may have 20 degrees of standard deviation for transmitter and receiver characteristics when die-to- die, wafer-to-wafer and lot-to-lot variations are included. The total phase variation between modules may be more. In situations where multiple TRXs work together to server one particular user terminal, phase alignment among the TRXs becomes very critical to ensure proper data throughput. Traditional methods for TRX and antenna phase alignment rely on expensive and time-consuming over-the-air (OTA) measurements. For the examples discussed herein, however, circuitry implemented on a module with multiple BFICs with transceivers facilitates adjusting phase differenceKWIC 00013 PC-4- during test procedure and applying the derived phase adjustments during operation of the BFICs. Couplers separate a test signal applied to the input of two BFICs and combine the outputs in an out of phase manner such that phase difference between the two BFICs is detected by a power detector. By adjusting a phase shifter in one or both BFICs, the detected power is minimized. The phase adjustment settings used to minimize the detected power are then applied during operation of the BFICs such that the phase difference between the two BFICs is eliminated or at least reduced. The same techniques can be applied to a single BFIC that includes two or more transmitters, two or more receivers, or two or more transceivers.

[0014] FIG. 1 A is a block diagram of an example of a multiple BFIC module (apparatus) 100 with inter-chip phase difference detection and compensation. The various functions and operations of the blocks described with reference to the BFIC module 100 may be implemented in any number of devices, circuits, or elements. Two or more of the functional blocks may be integrated in a single device, and the functions described as performed in any single device may be implemented over several devices in some situations.

[0015] For the example of FIG. 1A, the module 100 is configured in the test mode. As discussed below, switches and directional couplers can be configured to place the module 100 in various test modes and in the operational mode. The operational mode may include transmitter beam forming operations and / or receiver beamforming operation. The multiple BFIC module (apparatus) 100 includes a first BFIC 102 and second BFIC 104. First electronics 106 in the first BFIC 102 and the second electronics 108 in the second BFIC 104 may both be final transmitter stages or may both be frontend receivers for the functions described with reference to FIG. 1A. Each BFIC 102, 104 typically includes electronics for both transmission and reception. The example of FIG. 1 A focuses on a test mode in a single direction (either the transmit or receive direction). In at least some of the examples discussed below, each BFIC includes both receiver and transmitter functionality and the techniques discussed with reference to FIG. 1 A are applied to detect and adjust the phase differences for both the transmitter and the receiver portions of the BFICs. In some situations, a component performing theKWIC 00013 PC-5- functions of a splitter in the transmitter test mode performs the functions of a combiner in the receiver test mode and vice versa. Accordingly, connection points referred to as input ports in the receiver test mode may be referred to as output ports in the transmitter test mode and vice versa.

[0016] For the example of FIG. 1A, the module (apparatus) 100 includes a first coupler 110 coupled to input ports 112, 114 of the BFICs 102, 104 and a second coupler 116 coupled to output ports 118, 120 of the BFICs 102, 104. During the test procedure (test mode), a test signal 122 is applied to a first coupler input 124 of the first coupler 110 which splits the signal into a first component (first portion) 126 and a second component (second portion) 128 where each signal component 126, 128 is coupled to one of the BFICs 102, 104. The second coupler 116 combines the output signals 130, 132 of the BFICs 102, 104 and applies the combined output signal 134 to a power detector 136 that is monitored by a controller 138. The collective phase difference due to phase shifts by the couplers is 180 degrees. In one example, one of the couplers has a phase shift of 180 degrees and the other has zero-degree phase shift. In another example, both couplers have a phase shift of 90 degrees. Other combinations can also be used where the collective phase shift is 180 degrees. Where no other phase offsets or phase errors act on the signals propagating through the two paths, power detected by the power detector 136 is at a minimum level. Where a phase offset difference between the two BFICs 102, 104 is not at a minimum, however, the power detector 136 indicates an increased power level since the signals through the two paths are not 180 degrees out of phase and the signals do not cancel. The power detector 136 generates a signal 137 based on the power level of the combined signal 134. Accordingly, if the first phase offset 140 of the first electronics 106 is not equal to the second phase offset 142 of the second electronics 108, the controller 138 receives a non-zero signal generated by the power detector 136 that is above the minimum level. The minimum level of the power detector output is zero if the power detector is calibrated for power differences due to different power levels due to characteristics of the paths other than phase differences. The controller 138 adjusts the phase difference between the two BFICs by controlling a phase shifter 144, 146 in at least one of BFICsKWIC 00013 PC-6-102, 104. As a result, the phase offset difference is adjusted to zero or at least minimized. In some situations, the controller 138 adjusts the first phase shifter 144 in the first electronics 106 and adjusts the second phase shifter 146 in the second electronics 108 to minimize the phase offset difference. The controller 138 stores the adjustment values of the control signals 148, 150 in memory 152 and applies the stored values to generate the phase adjustment control signals 148, 150 during the operational mode when the BFIC module 100 is used to transmit and / or receive signals through a connected antenna array. The phase adjustment control signals 148, 150 are illustrated with dashed lines in FIG. 1A to indicate that only one phase adjustment control signal may be applied to only one of the phase shifters and that the controlled phase shifter may be either one of the two phase shifters 144, 146. Each phase shifter 144, 146 is part of the electronics 106, 108 which each have a phase offset 140, 142. Accordingly, the overall phase shift through the first BFIC 102 from input 112 to output 118 is equal to the combination of the first phase offset (PO1 ) and the phase adjustment (PA1 ) of the first phase shifter 144. Similarly, the overall phase shift through the second BFIC 104 from input 114 to output 120 is equal to the combination of the second phase offset (PO2) and the phase adjustment (PA2) of the second phase shifter 146.

[0017] Therefore, for the example of FIG. A1 , the first coupler 110 functions as a splitter to split a test signal 122 received at the first coupler input 124 into a first component signal 126 at the first coupler primary output 154 and a second component signal 128 at the first coupler secondary output 156. The second component signal 128 has a phase that is offset by a first coupler phase shift (A) from the phase of the first component signal 126. The first component signal 126 is received at the first BFIC input 112 and the second component signal 128 is received at the second BFIC input port 114. The first component signal 126 is processed by the first electronics 106 where the phase of the first component signal 126 is shifted by the first phase offset (PO1 ) 140 that is inherent in the electronics 106 and by the first phase shift (PA1 ) of the first phase shifter 144. The resulting first BFIC output signal 130 is provided to the second coupler primary input 158 from the first BFIC output 118. The phase of the first BFIC output signal 130, therefore, is shifted by PA1 and PO1 relative to a reference phase (<t>) whichKWIC 00013 PC-7- can be expressed as <t> - PO1 + PA1. The second component signal 128 is processed by the second electronics 108 where the phase of the second component signal 128 is shifted by the second phase offset (PO2) 142 that is inherent in the electronics 108 and by the second phase shift (PA2) of the second phase shifter 146. The resulting second BFIC output signal 132 is provided to the second coupler secondary input 160 from the second BFIC output 120. The phase of the second BFIC output signal 132, therefore, is shifted by second coupler phase shift, A, PA2 and PO2 relative to the reference phase ( ) which can be expressed as <t> - A - PO2 + PA2. In some situations, one or more of the phase parameters may be positive, negative, or zero. The second coupler combines the first BFIC output signal 130 and a phase shifted version of the second BFIC output signal 132 to generate the second coupler output signal 134 at the second coupler output 162 of the second coupler 116. The second coupler 116 has a second coupler phase shift ([3) such that the signal that is combined with the first BFIC output signal 130 has a phase that can be expressed as - A - PO2 + PA2 - [3. As discussed above, the collective phase difference due to first coupler phase shift, A and the second coupler phase shift, (3, is 180 degrees (A + [3 = 180°). The controller 138, therefore, adjusts the first phase shifter 144, the second phase shifter 146, or both, such that PA1 + PA2 - PO1 - PO2 equals zero. In addition to situations where the phase difference between two BFICs is addressed, the techniques discussed herein may be applied to numerous other situations and configurations. As discussed below with reference to FIG. 1 B, the electronics 106, 108 may be implemented on the same BFIC. In another example, more than two BFICs, each with a set of electronics for a channel, are implemented in the same module. In such a situation, the phase difference between two sets of electronics are detected and adjusted (reduced or eliminated) before the phase between one of the adjusted sets of electronics and another set of electronics is detected and adjusted. The procedure may be applied to any number of sets of electronics, either in separate BFICs or in the same BFIC.

[0018] FIG. 1 B is a block diagram of an example of a single BFIC module (apparatus) 160 including the first electronics 106 and the second electronics 108 with phase difference detection and compensation. Accordingly, the apparatus of FIG. 1 B isKWIC 00013 PC-8- an example of the apparatus of FIG. 1 A where the electronics for two channels are implemented on the same BFIC and the difference in phase shifts 140, 142 between the two sets of electronics 106, 108 are detected and eliminated, or at least reduced. The operation and structure of the apparatus 160 is the same as the structure and operation of the example of FIG. 1 A except for differences related to the electronics 106, 108 being on same IC. Accordingly, the single BFIC 160 has two input ports 112, 114 where each is connected to one of the sets of electronics 106, 108 and has two output ports 118, 120 where each is connected to one of the sets of electronics 106, 108. The test signal 122 is split between by the first coupler and each portion of the test signal is coupled to one of the sets of electronics. Each test signal portion is processed by the electronics to generate an output signal that is combined by the second coupler.

[0019] FIG. 2A is a schematic illustration of an example of a multiple BFIC module 200 including a first BFIC 202, a second BFIC 204, a first coupler 206, and a second coupler 208, directional couplers 210, 212 and switch circuits 214, 216. For the example of FIG. 2A, the module 200 is in a transmitter test mode where the first coupler 206 is functioning as a splitter, the second coupler 208 is functioning as a combiner and the switch circuits 214, 216 are configured in a transmitter test mode. The BFIC module 200 of FIG. 2A and FIG. 2B is an example of the BFIC module 100 discussed with reference to FIG. 1A. Accordingly, BFICs 202, 204 discussed with reference to FIG. 2A and FIG. 2B are examples of the BFICs 102, 104 discussed with reference to FIG. 1A. The BFIC module 200 includes a first BFIC 202 and a second BFIC 204 where each BFIC 202, 204 includes a transmitter final stage 218, 220 and a frontend receiver 222, 224. The BFICs 202, 204, therefore, are examples of the BFICs 102, 104 where the electronics 106, 108 in each BFIC 202, 204 include electronics for receiver functions and electronics for transmitter functions. Each BFIC 202, 204 includes an antenna port 226, 228 configured to connected to one or more antenna elements of an antenna array. Each BFIC 202, 204 also includes a connection port 230, 232 facilitates connecting / coupling to a transmitter and receiver. In some situations, other devices, such as switches, may be included in the connections between the first coupler 206 and the BFIC connection ports 230, 232.KWIC 00013 PC-9-

[0020] For the example, each frontend receiver 222, 224 includes a multiple stage low noise amplifier (LNA) 234, 236, a phase shifter 238, 240, and a gain stage 242, 244. The frontend receivers 222, 224 may include other components in some situations. Each phase shifter 238, 240 allows for adjusting the overall phase shift of the frontend receiver 222, 224. The gain stage 242, 244 may be an additional gain stage provided to accommodate the phase shifter or may be part of the LNA and at least provides a consistent impedance at the frontend receiver output.

[0021] For the example, each transmitter final stage 218, 220 includes a multiple stage power amplifier (PA) 246, 248, a phase shifter 250, 252, and a gain stage 254, 256. The transmitter final stage may include other components in some situations. Each phase shifter allows for adjusting the overall phase shift of the transmitter final stage. The gain stage 254, 256 may be an additional gain stage or may be part of the PA and at least provides a consistent impedance at the transmitter final stage input.

[0022] Each BFIC 202, 204 includes a multiplexer 258, 260 to facilitate connections between the antenna port 226, 228 to the input of the receiver frontend and the output of the transmitter final stage. Examples of suitable multiplexers include multiplexers, TX / RX switches, and circulators. For the example, each BFIC 202, 204 also includes a switch 262, 264 connecting the connection port 230, 232 to the receiver frontend output and transmitter final stage input.

[0023] The module 200 includes directional couplers 210, 212 and switch circuits 214, 216 at the antenna side of the BFICs 202, 204. A first directional coupler 210 and first switch circuit 214 are connected to the first BFIC 202 are configured to direct a portion of the output signal during the transmission testing mode to the second coupler 208. The first directional coupler 210 and first switch circuit 214 are configured to minimize loss during normal operation. As a result, the level of the signal directed to the second coupler 208 during the test mode may be several decibels (dBs) lower than the signal that is directed to the antenna port 226 during operation. The first directional coupler 210 and switch circuit 214 allow for connecting the receiver frontend 222 to the coupler during the receive test mode and connecting the transmitter final stage 218 toKWIC 00013 PC-10- the second coupler 208 during the transmitter test mode, as well as connecting a matching load 266 that allows connection of the BFIC 202 to the antenna port 226 with minimal loss.

[0024] A second directional coupler 212 and second switch circuit 216 are connected to the second BFIC 204 and are configured to direct a portion of the output signal during the transmission testing mode to the second coupler 208. The second directional coupler 212 and second switch circuit 216 allow for connecting the second receiver frontend 224 to the second coupler 208 during the receive test mode and connecting the transmitter final stage 220 to the second coupler 208 during the transmitter test mode, as well as connecting a matching load 268 that allows connection of the second BFIC 204 to the antenna port 228 with minimal loss.

[0025] At the circuit end of module 200, each BFIC 202, 204 includes a switch 262, 264 that facilitates switching between the receiver frontend 22, 224 and the transmitter final stage 218, 220 of the BFIC 202, 204. For the example, the switches 262, 264 are implemented as part of the BFIC 202, 204. In some situations, the switches 262, 264 may be implemented outside the BFICs although still within the module 200. The directional couplers 210, 212 and switch circuits 214, 216 are part of the module 200 in the example but external to the BFICs 202, 204. In some situations, the directional coupler 210, 212 and / or switch circuit 214, 216 may be implemented within the BFIC. Therefore, components, circuits, elements, ports shown outside of the BFIC may be implemented within the BFIC and vice versa.

[0026] During the transmitter test mode, an external test signal is provided by a test signal generator 270 to a connection port 272 of the module 200 that is coupled to the first coupler 206 functioning as a splitter. The test signal generator 270 is illustrated with dashed lines to indicate that the test signal generator 270 is not part of the module 200 for the example. A power detector 274 detects the power at the output of the second coupler functioning as combiner. As discussed above with reference to FIG. 1A, the phase shifts of the couplers 206, 208 result in a 180-degree phase shift between the two paths due to the couplers. As a result, a minimal amount of power is detected whenKWIC 00013 PC-11- the BFICs have the same phase shift. A difference in phase between the two BFICs is detected by the power detector as an increase of power, since the signals through the two paths do not cancel out. A controller (not shown in FIG. 2A) adjusts the contributed phase of one or both of the phase shifters 250, 252 in the transmitter final stages 218, 220 to reduce or eliminate phase differences between the two transmitter final stages 218, 220 using the power detector output signal. Accordingly, the phase difference is minimized by adjusting one or both phase shifters 250, 252 to minimize the output of the power detector. The power detector 274 is illustrated with dashed lines to indicate that the power detector is external to the module 200 in the example. In some situations, however, the power detector 274 may be implemented in the module 200.

[0027] After adjusting the one or both phase shifters 250, 252 to eliminate, or at least reduce, phase differences, the controller stores the adjustment control values for the phase shifters in memory. During normal operation of the BFIC module 200, the controller applies the stored adjustment control values to the phase shifters.

[0028] FIG. 2B is a schematic illustration of an example of the multiple BFIC module 200 in a receiver test mode where the first coupler 206 is functioning as a combiner, the second coupler 208 is functioning as a splitter and the switch circuits 214, 216, 262, 264 are configured in the receiver test mode. For the example of FIG. 2B, the BFICs 202, 204 and module 200 include the same components as discussed above. For the example, therefore, the same couplers 206, 208 are used for receiver testing except that the first coupler 206 is configured as a combiner and the second coupler 208 is configured as a splitter. In other examples, additional devices (e.g., splitter, combiner) can be included in the module 200 to facilitate receiver testing.

[0029] During the receiver test mode, the switches 262, 264 are configured to connect the frontend receivers 222, 224 to the first coupler. The switching circuits 214, 216 are configured to connect the second coupler 208 to the BFICs 202, 204 through the directional couplers 210, 212. The test signal generator 270 is connected to the second coupler 108 and the test signal is split between the two BFICs 202, 204. The total phase shift due to the second coupler and the first coupler is 180 degrees.KWIC 00013 PC-12-Accordingly, the phase of the test signal portion coupled to the second BFIC 204 may be offset from the phase of the test signal portion coupled to the first BFIC 202 in some situations. Where the first coupler 206 combines the two output signals from the frontend receivers 222, 224 at a 180-degree phase shift, the second coupler 108 does not introduce a phase shift. Each test signal portion is processed by the frontend receiver 222, 224 and the resulting signal is combined by the first coupler 206. Any phase difference between the two frontend receivers 222, 224 is detected as a power increase above a minimum by the power detector 274. Based on the output signal for the power detector 274, the controller (not shown) adjusts one or both of the phase shifters 238, 240 in the frontend receivers 222, 224 to eliminate, or at least reduce, the phase difference between the two frontend receivers 222, 224. The adjust values for resulting in a minimum phase difference are stored and applied during normal receiver operation.

[0030] FIG. 3A is a schematic illustration of an example of a multiple BFIC module 300 in a transmitter test mode where the first coupler 206 is a Wilkinson divider 302, the second coupler 208 is a rat race combiner 304. For the example of FIG. 3A and FIG. 3B, the BFICs 202, 204 include the same components as discussed above. The operation of the module 300 is similar to the operation of the module 200 discussed above except for any differences due to the rat race coupler 304 and the Wilkinson divider 302. The switches 262, 264 and switching circuits 214, 216 are configured in the transmitter test mode as discussed above with reference to FIG. 2A. The test signal coupled to the transmitter final stages 218, 220 through the Wilkinson divider 302 and the switches 262, 264. The Wilkinson divider 302 splits the test signal without introducing a phase shift between the two output signal portions. Each test signal portion is processed by one of the transmitter final stages 218, 220 and the amplified output signals are coupled through the directional couplers 210, 212 to the rat race coupler 304. The rat race coupler 304 combines the signals at a 180-degree offset and the combined output signal is coupled to the power detector 274. The controller adjust one or both of the phase shifters 250, 252 to minimize the phase difference between theKWIC 00013 PC-13- two transmitter final stages 218, 222. The adjustment control values are stored in memory and applied during normal transmission operation of the BFICs 202, 204.

[0031] FIG. 3B is a schematic illustration of an example of the multiple BFIC module 300 in a receiver test mode where the Wilkison coupler 302 is functioning as a Wilkinson combiner 302, the rat race coupler 304 is functioning as a splitter, and the switch circuits 214, 216, 262, 264 are configured in the receiver test mode. For the example of FIG. 3B, the BFICs 202, 204 and module 200 include the same components as discussed above. For the example, therefore, the same rat race and Wilkinson devices are used for receiver testing except that the Wilkinson device functions as a combiner and the rat race device functions as a splitter. In other examples, additional devices (e.g., splitter, combiner) can be included in the module 300 to facilitate receiver testing.

[0032] During the receiver test mode, the switches 262, 264 are configured to connect the frontend receivers 222, 224 to the Wilkinson combiner 302. The switching circuits 214, 216 are configured to connect the rat race coupler (splitter) 304 to the BFICs 202, 204 through the directional couplers 210, 212. The test signal generator 270 is connected to the rat race coupler (splitter) 304 and the test signal is split between the two BFICs 202, 204. The phase shift between the outputs of the rat race coupler (splitter) 304 is 180 degrees. Each test signal portion is processed by the frontend receiver 222, 224 and the resulting signal is combined by the Wilkinson combiner 302. Any phase difference between the two frontend receivers 222, 224 is detected as a power increase above a minimum by the power detector 274. Based on the output signal for the power detector 274, the controller (not shown) adjusts one or both of the phase shifters 238, 240 in the frontend receivers 222, 224 to eliminate, or at least reduce, the phase difference between the two frontend receivers 222, 224. The adjustment values resulting in a minimum phase difference are stored and applied during normal receiver operation.

[0033] FIG. 4A is a schematic illustration of an example of a multiple BFIC module 400 in a transmitter test mode where the first coupler 206 is a quadrature hybrid SKWIC 00013 PC-14- coupler 402 functioning a splitter and the second coupler 208 is a quadrature hybrid C coupler 404 functioning a combiner. For the examples of FIG. 4A and FIG. 4B, the BFICs 202, 204 include the same components as discussed above. The operation of the module 400 is similar to the operation of the module 200 discussed above except for any differences due to the quadrature hybrid S coupler 402 and the quadrature hybrid C coupler 404. The switches 262, 264 and switching circuits 214, 216 are configured in the transmitter test mode as discussed above with reference to FIG. 2A. The test signal is coupled to the transmitter final stages 218, 220 through the quadrature hybrid S coupler 402 and the switches 262, 264. The quadrature hybrid S coupler 402 splits the test signal at a 90-degree phase shift between the two output signal portions. The quadrature hybrid S coupler 402 has a connection port 406, a through port 408, a coupled port 410, and an isolated port 412. When the quadrature hybrid S coupler 402 functions as a splitter, the signal from the connection port 406 is directed through the through port 408 and the coupled port 410 at a 3 dB attenuation. The output signal at the through port 408 is coupled to the first transmitter final stage 218 and has the same phase as the input signal at the connection port 406. The output signal at the coupled port 410 is coupled to the second transmitter final stage 220 and has a 90-degree phase offset from the signal at the first transmitter final state 218. The isolated port has a negligible power flow and acts as a termination port for reflections.

[0034] The input signal coupled to the connection port 406 of the quadrature hybrid S coupler 402, therefore, is received from the test signal generator 270 connected to the module connection port 272. The test signal is split into two portions where each test signal portion is processed by one of the transmitter final stages 218, 220 and the amplified output signals are coupled through the directional couplers 210, 212 to quadrature hybrid C coupler 404. The quadrature hybrid C coupler 404 combines the signals at a 90-degree offset and the combined output signal is coupled to the power detector 274. As a result, the aggregate phase shift due to the quadrature hybrid S coupler 402 and quadrature hybrid C coupler 404 is 180 degrees. More specifically, the output signal from the first transmitter final stage 218 is coupled through the directional coupler 210 and switch circuit 214 to a through port 412 of the quadrature hybrid CKWIC 00013 PC-15- coupler 404 and the output signal from the second transmitter final stage 220 is coupled through the directional coupler 212 and switch circuit 216 to a coupled port 414 of the quadrature hybrid C coupler 404. The quadrature hybrid C coupler 404 combines the signal at the coupled port 414 at a 90-degree phase shift with the signal at the through port 412 to generate the combined signal at a connection port 416. The power detector 274 provides a signal to the controller based on the power of the combined signal from the connection port 416. The controller adjust one or both of the phase shifters 250, 252 to minimize the phase difference between the two transmitter final stages 218, 222. The adjustment control values are stored in memory and applied during normal transmission operation of the BFICs 202, 204.

[0035] FIG. 4B is a schematic illustration of an example of the multiple BFIC module 400 in a receiver test mode where the quadrature hybrid S coupler 402 is functioning as a combiner, the quadrature hybrid C coupler 404 is functioning as a splitter, and the switch circuits 214, 216, 262, 264 are configured in the receiver test mode. For the example of FIG. 4B, the BFICs 202, 204 and module 200 include the same components as discussed above. For the example, therefore, the same quadrature hybrid S coupler 402 and quadrature hybrid C coupler 404 are used for receiver testing except that the quadrature hybrid S coupler 402 is functioning as a combiner and quadrature hybrid C coupler 404 functions as a splitter. In other examples, additional devices (e.g., splitter, combiner) can be included in the module 400 to facilitate receiver testing.

[0036] During the receiver test mode, the switches 262, 264 are configured to connect the frontend receivers 222, 224 to the quadrature hybrid S coupler 402. The switching circuits 214, 216 are configured to connect the quadrature hybrid C coupler (splitter) 404 to the BFICs 202, 204 through the directional couplers 210, 212. The test signal generator 270 is connected to the quadrature hybrid C coupler (splitter) 404 and the test signal is split between the two BFICs 202, 204. The phase shift between the signal at the coupled port 414 of the quadrature hybrid C coupler is offset by 90 degrees from the signal at the through port 412. Each test signal portion is processed by the frontend receiver 222, 224 and the resulting signal is combined by quadrature hybrid S coupler (combiner) 302. The quadrature hybrid S coupler 402 combines the signal atKWIC 00013 PC-16- the coupled port 410 at a 90-degree phase shift from the signal at the through port 408 to generate the combined signal at a connection port 406. The power detector 274 provides a signal to the controller based on the power of the combined signal from the connection port 406. Any phase difference between the two frontend receivers 222, 224 is detected as power increase above a minimum by the power detector 274. Based on the output signal for the power detector 274, the controller (not shown) adjusts one or both of the phase shifters 238, 240 in the frontend receivers 222, 224 to eliminate, or at least reduce, the phase difference between the two frontend receivers 222, 224. The adjustment values resulting in a minimum phase difference are stored and applied during normal receiver operation.

[0037] Although the examples of FIG. 2A, FIG. 2B, FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B include two BFICs, the techniques can be applied in situations where the two transmitter channels and the two receiver channels are in the same BFIC. Also, the techniques may be applied to minimizing the phase difference between more than two channels (sets of electronics). For example, the phase difference between two channels can be minimized before minimizing the phase difference between one of the two channels and a third channel and so on. The multiple channels may all be in a single BFIC, each in a separate BFIC, or distributed over a number of BFICs in any combination. As discussed above, the components of the BFIC, the module, or external to the module may implanted within different locations. For example, components such switches, directional couplers, and couplers may implemented in a BFIC, in the module external to the BFIC, or external to the module depending on size restrictions, signal isolation requirements, costs, manufacturing limitations, and other factors.

[0038] Clearly, other embodiments and modifications of this invention will occur readily to those of ordinary skill in the art in view of these teachings. The above description is illustrative and not restrictive. This invention is to be limited only by the following claims, which include all such embodiments and modifications when viewed in conjunction with the above specification and accompanying drawings. The scope of the invention should, therefore, be determined not with reference to the above description,KWIC 00013 PC-17- but instead should be determined with reference to the appended claims along with their full scope of equivalents.

Claims

KWIC 00013 PC-18-CLAIMS1 . An apparatus comprising: first beam forming integrated circuit (BFIC) electronics coupled between a first BFIC input and a first BFIC output, the first BFIC electronics having a first phase offset between the first BFIC input and the first BFIC output; second BFIC electronics coupled between a second BFIC input and a second BFIC output, the second BFIC electronics having a second phase offset between the second BFIC input and the second BFIC output; a first coupler having a first coupler input, a primary first coupler output coupled to the first BFIC input, and a secondary first coupler output coupled to the second BFIC input; a second coupler having a second coupler output and two second coupler inputs, each second coupler input coupled to one of the first BFIC output and the second BFIC output, the first coupler and the second coupler having a first collective phase shift between the primary first coupler output and the second coupler output that is 180 degrees out of phase with a second collective phase shift between the secondary first coupler output and the second coupler output; a power detector configured to generate a power level signal based on a power level of an output signal at the second coupler output when a test signal is applied to the first coupler input; and a controller configured to adjust at least one of the first phase offset or the second phase offset based on the power level signal to minimize the power level signal.

2. The apparatus of claim 1 , wherein the first BFIC electronics and the second BFIC electronics are implemented in a single BFIC.

3. The apparatus of claim 1 , wherein the first BFIC electronics are implemented in a first BFIC and the second BFIC electronics are implemented in a second BFIC.KWIC 00013 PC-19-4. The apparatus of claim 1 , further comprising memory configured to store one or more values applied by the controller to minimize the power level signal during a phase adjustment procedure, the controller configured to apply the one or more values during a beam forming operation.

5. The apparatus of claim 4, wherein the first BFIC electronics form a first transmitter final stage and the second BFIC electronics form a second transmitter final stage, and wherein, during the beam forming operation, the first BFIC output is coupled to a first antenna element set, the second BFIC output is coupled to a second antenna element set, and the first BFIC input and the second BFIC input are coupled to a transmitter.

6. The apparatus of claim 5, wherein the first coupler is a Wilkinson divider and the second coupler is a rat race coupler, the Wilkinson divider having a zero-degree phase shift between the primary first coupler output and the secondary first coupler output, the rat race coupler having a 180-degree phase offset between the two second coupler inputs.

7. The apparatus of claim 5, wherein the first coupler is a quadrature hybrid S coupler and the second coupler is a quadrature hybrid C coupler, the quadrature hybrid S coupler having a 90-degree phase shift between the primary first coupler output and the secondary first coupler output, the quadrature hybrid C coupler having a 90-degree phase offset between the two second coupler inputs.

8. The apparatus of claim 4, wherein the first BFIC electronics form a first frontend receiver and the second BFIC electronics form a second frontend receiver, and wherein, during the beam forming operation, the first BFIC output and the second BFIC output are coupled to a receiver.KWIC 00013 PC-20-9. The apparatus of claim 8, wherein the first coupler is a rat race coupler functioning as a splitter and the second coupler is a Wilkinson combiner, the rate race coupler having a 180-degree phase shift between the primary first coupler output and the secondary first coupler output, the Wilkinson combiner having a zero-degree phase offset between the two second coupler inputs.

10. The apparatus of claim 8, wherein the first coupler is a quadrature hybrid C coupler and the second coupler is a quadrature hybrid S coupler, the quadrature hybrid C coupler having a 90-degree phase shift between the primary first coupler output and the secondary first coupler output, the quadrature hybrid S coupler having a 90-degree phase offset between the two second coupler inputs.11 . The apparatus of claim 1 , wherein the first electronics comprise a first adjustable phase shifter configured to contribute, based on a first adjustment control signal received from the controller, a first phase adjustment to a total first phase offset of the first electronics including the first phase offset, and wherein the second electronics comprise a second adjustable phase shifter configured to contribute, based on a second adjustment control signal received from the controller, a second phase adjustment to a total second phase offset of the second electronics including the second phase offset.

12. A beam forming integrated circuit (BFIC) module comprising: a first final stage transmitter coupled between a first BFIC transmitter input and a first BFIC transmitter output, the first final stage transmitter comprising a first transmitter phase shifter and having a total first phase offset between the first BFIC transmitter input and the first BFIC transmitter output, the total first phase offset at least partially due to a first phase adjustment of the first transmitter phase shifter; a second final stage transmitter coupled between a second BFIC transmitter input and a second BFIC transmitter output, the second final stage transmitter comprising a second transmitter phase shifter and having a total second phase offset between the second BFIC transmitter input and the second transmitter BFIC output, theKWIC 00013 PC-21- total second phase offset at least partially due to a second phase adjustment of the second transmitter phase shifter; a first coupler having a first coupler input, a primary first coupler output coupled to the first BFIC transmitter input during a transmitter test mode, and a secondary first coupler output coupled to the second BFIC transmitter input during the transmitter test mode; a second coupler having a second coupler output and two second coupler inputs, each second coupler input coupled to one of the first BFIC transmitter output and the second BFIC transmitter output during the transmitter test mode, the first coupler and the second coupler having a first collective phase shift between the primary first couple output and the second coupler output that is 180 degrees out of phase with a second collective phase shift between the secondary first coupler output and the second coupler output, the second coupler configured to couple, during the transmitter test mode, a combined transmitter output signal at the second coupler output to a power detector configured to generate a power level signal based on a power level of the output signal when a test signal is applied to the first coupler input during the transmitter test mode; and a controller configured to: apply a transmitter control signal to at least one of the first transmitter phase shifter or the second transmitter phase shifter based on the power level signal to minimize the power level signal during the transmitter test mode, and apply the transmitter control signal to at least one of the first transmitter phase shifter or the second transmitter phase shifter during transmission of transmission signals through the first final stage transmitter and the second final stage transmitter.

13. The BFIC module of claim 12, further comprising: a first directional coupler coupled to the first BFIC transmitter output, a first switching circuit, the first switching circuit and the first directional coupler configured to couple, during the transmitter testing mode, a portion of the first transmitter output signal from first BFIC transmitter output to the second coupler;KWIC 00013 PC-22- a second directional coupler coupled to the second BFIC transmitter output; and a second switching circuit, the second switching circuit and the second directional coupler configured to couple, during the transmitter testing mode, a portion of the second transmitter output signal from second BFIC transmitter output to the second coupler.1 . The BFIC module of claim 13, wherein the first switching circuit and the first directional coupler are configured to couple, during the transmission of transmission signals through the first final stage transmitter and the second final stage transmitter, the first transmitter output signal from the first BFIC transmitter output to a first antenna port and wherein the second switching circuit and the second directional coupler are configured to couple, during the transmission of transmission signals through the first final stage transmitter and the second final stage transmitter, the second transmitter output signal from the second BFIC transmitter output to a second antenna port.

15. The BFIC module of claim 14, wherein the first coupler is a Wilkinson divider and the second coupler is a rat race coupler, the Wilkinson divider having a zero-degree phase shift between the primary first coupler output and the secondary first coupler output, the rat race coupler having a 180-degree phase offset between the two second coupler inputs.

16. The BFIC module of claim 14, wherein the first coupler is a quadrature hybrid S coupler and the second coupler is a quadrature hybrid C coupler, the quadrature hybrid S coupler having a 90-degree phase shift between the primary first coupler output and the secondary first coupler output, the quadrature hybrid C coupler having a 90-degree phase offset between the two second coupler inputs.

17. The BFIC module of claim 14, further comprising the power detector.KWIC 00013 PC-23-18. A beam forming integrated circuit (BFIC) module comprising: a first frontend receiver coupled between a first BFIC receiver input and a first BFIC receiver output, the first frontend receiver comprising a first receiver phase shifter and having a total first receiver phase offset between the first BFIC receiver input and the first BFIC receiver output, the total first receiver phase offset at least partially due to a first receiver phase adjustment of the first receiver phase shifter; a second frontend receiver coupled between a second BFIC receiver input and a second BFIC receiver output, the second frontend receiver comprising a second receiver phase shifter and having a total second receiver phase offset between the second BFIC receiver input and the second receiver BFIC output, the total second receiver phase offset at least partially due to a second receiver phase adjustment of the second receiver phase shifter; a first coupler having a first coupler output, and having a primary first coupler input coupled to the first BFIC receiver output during the receiver test mode, and a secondary first coupler input coupled to the second BFIC receiver output during the receiver test mode; a second coupler having a second coupler input, a primary second coupler output coupled to the first BFIC receiver input during the receiver test mode, and a secondary second coupler output coupled to the second BFIC receiver input during a receiver test mode, the first coupler and the second coupler having a first collective phase shift between the secondary second coupler input and the first coupler output that is 180 degrees out of phase with a second collective phase shift between the primary second coupler input and the first coupler output, the first coupler configured to couple an output signal at the first coupler output to a power detector configured to generate a power level signal based on a power level of the output signal when a test signal is applied to the second coupler input during the receiver test mode; and a controller configured to: apply a receiver control signal to at least one of the first receiver phase shifter or the second receiver phase shifter based on the power level signal to minimize the power level signal during the receiver test mode, andKWIC 00013 PC-24- apply the receiver control signal to at least one of the first receiver phase shifter or the second receiver phase shifter during reception of received signals through the first frontend receiver and the second frontend receiver.

19. The BFIC module of claim 18, further comprising: a first directional coupler coupled to the first BFIC receiver input; and a first switching circuit, the first switching circuit and the first directional coupler configured to couple, during the receiver test mode, a portion of the test signal at the primary second coupler output to the first BFIC receiver input; a second directional coupler coupled to the second BFIC transmitter output; and a second switching circuit, the second switching circuit and the second directional coupler configured to couple, during the receiver test mode, a portion of the test signal at the secondary second coupler output to the second BFIC receiver input.

20. The BFIC module of claim 19, wherein the first coupler is a rat race coupler functioning as a splitter and the second coupler is a Wilkinson combiner, the rate race coupler having a 180-degree phase shift between the primary first coupler output and the secondary first coupler output, the Wilkinson combiner having a zero-degree phase offset between the two second coupler inputs.21 . The BFIC module of claim 19, wherein the first coupler is a quadrature hybrid C coupler and the second coupler is a quadrature hybrid S coupler, the quadrature hybrid C coupler having a 90-degree phase shift between the primary first coupler output and the secondary first coupler output, the quadrature hybrid S coupler having a 90-degree phase offset between the two second coupler inputs.

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