Time-interleaved digital-to-analog converter and electronic device

Abstract

Provided are a time-interleaved digital-to-analog converter and an electronic device. The time-interleaved digital-to-analog converter comprises: a multi-channel sub-digital-to-analog converter, configured to provide outputs of multiple initial sampling rates; a mode control encoder, configured to generate a mode control code and send the mode control code to a multiplexer, so as to control a configuration mode of the multiplexer by means of the mode control code; and the multiplexer, connected to the multi-channel sub-digital-to-analog converter, and configured to determine, on the basis of the mode control code and the outputs of the multiple initial sampling rates, an output of a target sampling rate corresponding to the digital-to-analog converter, and determine an output path corresponding to the output of the target sampling rate, wherein the target sampling rate is greater than or equal to the initial sampling rates.

Description

Time-interleaved digital-to-analog converters and electronic devices

[0001] Cross-references to related applications

[0002] This disclosure is based on and claims priority to Chinese patent application CN202411768179.5, filed on December 3, 2024, entitled “Time-Interleaved Digital-to-Analog Converter and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of communications, and more specifically, to a time-interleaved digital-to-analog converter and an electronic device. Background Technology

[0004] Traditional time-interleaved digital-to-analog converters (TIDACs) have only a single output. To meet the highest requirements of various applications, the single output of a traditional TIDAC is often a high-speed sampling rate output. This results in excessive performance, power consumption, and area redundancy for low- and medium-speed applications. Therefore, to avoid wasting power and area when differentiating application scenarios, it is necessary to rationally and effectively switch the operating mode of the digital-to-analog converter (DAC) to match the application scenario, while improving the adaptability and versatility of high-speed DACs. Summary of the Invention

[0005] This disclosure provides a time-interleaved digital-to-analog converter and electronic device to at least address the problems of excessive performance, power consumption, and area redundancy in conventional TIDACs in the related art.

[0006] According to one embodiment of this disclosure, a time-interleaved digital-to-analog converter (DAC) is provided, comprising: a multi-channel sub-DAC configured to provide multiple initial sampling rate outputs; a mode control encoder configured to generate mode control codes and send them to a multiplexer to control the configuration mode of the multiplexer via the mode control codes; the multiplexer, connected to the multi-channel sub-DAC, configured to determine a target sampling rate output corresponding to the DAC based on the mode control codes and the multiple initial sampling rate outputs, and to determine an output path corresponding to the target sampling rate output; wherein the target sampling rate is greater than or equal to the initial sampling rate.

[0007] According to another embodiment of this disclosure, an electronic device is provided, including the time-interleaved digital-to-analog converter described in the above embodiments. Attached Figure Description

[0008] Figure 1 is a schematic diagram of the internal structure of a traditional time-interleaved digital-to-analog converter;

[0009] Figure 2 is a schematic diagram of the internal structure of a time-interleaved digital-to-analog converter according to an embodiment of the present disclosure;

[0010] Figure 3 is a schematic diagram of the internal structure of a dual-channel TIDAC according to an embodiment of the present disclosure;

[0011] Figure 4 is a schematic diagram of the mode control decoder structure according to an embodiment of the present disclosure;

[0012] Figure 5 is a schematic diagram of the mode table used in a digital-to-analog converter according to an embodiment of the present disclosure;

[0013] Figure 6 is a schematic diagram of a broadband output timing diagram according to an embodiment of the present disclosure;

[0014] Figure 7 is a schematic diagram of a narrowband output timing diagram according to an embodiment of the present disclosure;

[0015] Figure 8 is a schematic diagram of a narrowband output timing diagram according to another embodiment of the present disclosure;

[0016] Figure 9 is a schematic diagram of the internal structure of a capacitive digital-to-analog converter according to an embodiment of the present disclosure;

[0017] Figure 10 is a schematic diagram of the internal structure of a current-driven digital-to-analog converter according to an embodiment of the present disclosure. Detailed Implementation

[0018] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] A digital-to-analog converter (DAC) is a device that converts digital signals into analog signals. A time-interleaved digital-to-analog converter (TIDAC) is a high-speed DAC that uses interleaved clocks and time-division multiplexing to connect multiple low-sampling-rate sub-DACs in parallel, cyclically operating them to obtain a sampling rate several times higher than that of the sub-DACs. The number of parallel sub-DACs is also called the number of channels of the high-speed DAC. Figure 1 shows a schematic diagram of a traditional time-interleaved DAC. Its operating mode is fixed and singular. Its signal combination circuit—whether it is an adder used in non-return-to-zero interleaving, a multiplexer used in return-to-zero interleaving, or a combination of both algorithms—has only one output, and this output is a high-speed sampling rate output. Typically, the bandwidth of a combined high-speed DAC needs to meet the highest requirements of the converter's application scenario. However, in low- and medium-speed applications, the performance of a high-speed DAC is often excessive, resulting in excessive redundancy in power consumption and area. Therefore, when differentiating application scenarios, to avoid wasting power consumption and area, it is necessary to reasonably and effectively switch the DAC's operating mode to match the application scenario, while improving the DAC's adaptability and versatility.

[0021] This disclosure provides a time-interleaved digital-to-analog converter (DAC) suitable for multiple scenarios, with switchable bandwidth (i.e., adaptive bandwidth) and switchable channel count. It can combine multiple low-speed sub-DACs into a single low-, medium-, and high-speed universal wide-bandwidth DAC, depending on the application scenario. Specifically, a switch selection circuit is integrated into the signal combination circuit of this time-interleaved DAC. Simultaneously, through the combiner and with the aid of a decoder, it can maintain the single high-speed output found in a traditional time-interleaved DAC, select any output from multiple sub-DACs as the low-speed sampling rate output of the time-interleaved DAC, or combine the outputs of two or more sub-DACs into a medium-speed sampling rate output.

[0022] Figure 2 is a schematic diagram of the structure of a time-interleaved digital-to-analog converter according to an embodiment of the present disclosure. As shown in Figure 2, the time-interleaved digital-to-analog converter mainly consists of three major components: a multi-channel sub-digital-to-analog converter (multi-channel DAC), a mode control encoder, and a multiplexer.

[0023] A multi-channel digital-to-analog converter is configured to provide multiple initial sampling rate outputs. These multiple initial sampling rate outputs are connected to a multiplexer to select or select a portion of the initial sampling rate outputs and form a high-speed DAC in a time-division multiplexing manner.

[0024] The mode control encoder is configured to generate mode control codes and send them to the multiplexer to control the configuration mode of the multiplexer via the mode control codes.

[0025] The multiplexer, connected to the multi-channel sub-digital-to-analog converter, is configured to determine the output of the time-interleaved digital-to-analog converter corresponding to the target sampling rate based on the mode control code and the output of the multiple initial sampling rates, and to determine the output path corresponding to the output of the target sampling rate; wherein the target sampling rate is greater than or equal to the initial sampling rate.

[0026] In this embodiment, based on the sampling rate required for the actual application scenario and referring to the pre-configured operating mode table of the time-interleaved digital-to-analog converter (see Figure 5), an operating mode corresponding to the required sampling rate is determined. The selector in the time-interleaved digital-to-analog converter is then set according to this operating mode to ensure that the time-interleaved digital-to-analog converter operates at the corresponding sampling rate. Different operating modes allow the time-interleaved digital-to-analog converter to combine different sub-digital-to-analog converters, thereby obtaining digital-to-analog converters with different sampling rates.

[0027] Through the embodiments of this disclosure, digital-to-analog converters with different sampling rates can be set according to requirements. This allows for backward compatibility with lower sampling rates while maintaining high-speed sampling rate applications, thereby improving the bandwidth adjustability, adaptability, and versatility of time-interleaved digital-to-analog converters.

[0028] As shown in Figure 2, the multi-channel sub-digital-to-analog converter also includes N parallel sub-digital-to-analog converters, namely sub-DAC1 to sub-DAC1. N N is an integer greater than or equal to 2.

[0029] In this embodiment of the disclosure, the multiplexer is configured to select any one of the multi-channel sub-digital-to-analog converters to provide an output path for it individually, and to select all or some of the sub-digital-to-analog converters to combine them into a high-speed DAC in a time-division multiplexing manner.

[0030] In an exemplary embodiment, when the application scenario is a first sampling rate scenario, the multiplexer is further configured to determine the output of any initial sampling rate of any channel in the multi-channel sub-digital-to-analog converter as the output of the target sampling rate.

[0031] In an exemplary embodiment, when the application scenario is a second sampling rate scenario, the multiplexer is further configured to combine all or part of the initial sampling rate outputs of the multi-channel sub-digital-to-analog converters into a target sampling rate output using a time-division multiplexing method. The first sampling rate is less than the second sampling rate.

[0032] The following detailed examples illustrate how time-interleaved digital-to-analog converters can adapt to different application scenarios.

[0033] Figure 3 is a schematic diagram of the structure of a dual-channel TIDAC according to an embodiment of the present disclosure. As shown in Figure 3, the number of channels of the time-interleaved digital-to-analog converter is N = 2.

[0034] In this embodiment, the selector of the dual-channel time-interleaved digital-to-analog converter consists of four switches S1, S2, S3 and S4. The working state of the four switches, i.e., on or off, is controlled by the output of the mode control decoder.

[0035] The combiner of the dual-channel time-interleaved digital-to-analog converter consists of a multiple-input multiple-output structure composed of two dual-input single-output MUXs.

[0036] Figure 4 is a schematic diagram of the mode control decoder structure according to an embodiment of the present disclosure. As shown in Figure 4, the mode input control of the mode control decoder is two bits, namely mode <1> and mode <0> It is collectively referred to as mode<1:0>; it consists of 8 dual-channel selectors, which can decode the input mode<1:0> into 4-bit outputs to control the 4 switches S1, S2, S3 and S4 of the selector respectively.

[0037] In this embodiment, the operating modes of the dual-channel time-interleaved digital-to-analog converter with different bandwidths and channel numbers can be switched as follows: When OUT1 requires a low-speed output, the output control switch S1 of the mode control decoder is closed, and the switch S3 is open. The OUT1 output of the dual-channel time-interleaved digital-to-analog converter is equivalent to the single-channel output of the low-speed, narrow-bandwidth DAC core1. When OUT1 requires a high-speed output, the output control switches S1 and S3 of the mode control decoder are closed. The combiner uses an algorithm to integrate the outputs of DAC core1 and DAC core2. The OUT1 output of the dual-channel time-interleaved digital-to-analog converter is equivalent to the dual-channel interleaved output of the high-speed, high-bandwidth DAC core1 and DAC core2. The same mode control is not limited to single or dual channels and can be extended to multiple channels. The output is not limited to OUT1 and OUT2 and can be extended to multiple outputs. The entire time-interleaved digital-to-analog converter switches between different bandwidths and channel numbers based on specific application scenarios and requirements.

[0038] Figure 5 is a schematic diagram of the operating mode table used by the digital-to-analog converter according to an embodiment of the present disclosure. As shown in Figure 5, when mode<1:0>=00, S1 and S4 are closed, S2 and S3 are open, and OUT1 and OUT2 are connected to the outputs of DAC_core1 and DAC_core2, respectively; when mode<1:0>=01, S1 and S4 are open, S2 and S3 are closed, and OUT1 and OUT2 are connected to the outputs of DAC_core2 and DAC_core1, respectively; when mode<1:0>=10 or 11, S1 and S3 are closed, and OUT1 and OUT2 are connected to the combined output and dummy output of DAC_core1 and DAC_core2, respectively.

[0039] In this embodiment of the disclosure, the selector controls the output direction of the two sub-DACs within the dual-channel DAC through four switches S1, S2, S3 and S4, and also controls the output direction of the total DAC after passing through the combiner.

[0040] When the application scenario is high speed, set the working mode mode<1:0> to 10 or 11. At this time, the sub-DACs of the two channels are controlled to work simultaneously, and the multiplexer combines them into a high-speed signal with an equivalent sampling rate of f in a time-division multiplexing manner. The broadband output timing diagram in this working mode is shown in Figure 6.

[0041] When the application scenario is low speed, two working modes can be set. In the first working mode, mode<1:0> is 00. In this mode, the two sub-DAC channels are controlled to work simultaneously, but the outputs of the two sub-DACs are not combined by the combiner. OUT1 and OUT2 are connected to the outputs of DAC_core1 and DAC_core2 respectively, and output low-speed signals with a sampling rate of f / 2. The narrowband output timing diagram in this working mode is shown in Figure 7. In the second working mode, mode<1:0> is 01. In this mode, the two sub-DAC channels are controlled to work simultaneously, but the outputs of the two sub-DACs are not combined by the combiner. OUT1 and OUT2 are connected to the outputs of DAC_core2 and DAC_core1 respectively, and output low-speed signals with a sampling rate of f / 2. The narrowband output timing diagram in this working mode is shown in Figure 8.

[0042] As shown in Figure 2, the multiplexer also includes: a control decoder, configured to decode the received mode control code into a control signal and send the control signal to the selector, wherein the mode control code corresponds to the configuration mode; a selector, configured to split the outputs of multiple initial sampling rates into different combiners according to the received control signal; and a combiner, configured to combine the outputs of the input initial sampling rates into the output of the target sampling rate and determine the output path corresponding to the output of the target sampling rate.

[0043] In the embodiments disclosed herein, the selector (i.e., switch selection circuit), control decoder, and combiner are all means to achieve the selection, combination, and output of one or more sub-digital-to-analog converters. The selector, control decoder, and combiner in the implementation scheme do not necessarily have physical entities. For example, the function of the selector can be achieved by turning off useless sub-digital-to-analog converters; the function of the decoder can be replaced by a direct drive signal from outside the chip; the function of the combiner can be achieved by an adder, shifter, multiplexer, etc., or by direct coupling.

[0044] In one embodiment, the process of splitting the outputs of multiple initial sampling rates to different combiners according to the received control signal includes: selecting and splitting the outputs of multiple initial sampling rates, wherein the output of the selected initial sampling rate enters a designated combiner, and the outputs of the remaining initial sampling rates are split to other designated paths.

[0045] In one embodiment, the output of the initial sampling rate is the low sampling rate output, and the output of the target sampling rate is the high sampling rate output.

[0046] In one embodiment, the selector is controlled by a decoder located inside the chip or by a signal directly driven from outside the chip.

[0047] In one embodiment, the selector includes multiple switches, and the selector is further configured to control the closing of the multiple switches according to a control signal to split the outputs of multiple initial sampling rates into different combiners.

[0048] In one embodiment, the digital-to-analog converter includes outputs with one or more target sampling rates.

[0049] In one embodiment, the structure type of the time-interleaved digital-to-analog converter includes one of the following: resistive digital-to-analog converter, capacitive digital-to-analog converter, and current-driven digital-to-analog converter. For example, Figure 9 shows a capacitive digital-to-analog converter, and Figure 10 shows a current-driven digital-to-analog converter.

[0050] In one embodiment, the individual digital-to-analog converters in the time-interleaved circuit can have the same or different structural types.

[0051] In one embodiment, the mode control decoder implementation scheme includes, but is not limited to, digital circuit implementation, analog circuit implementation, or mixed-signal circuit implementation; the structure of the mode control decoder includes a combination of one or more logic circuits, such as buffers, NOT gates, AND gates, OR gates, XOR gates, latches, flip-flops, etc.

[0052] The time-interleaved digital-to-analog converter with flexibly switchable channel number and bandwidth provided in the embodiments of this disclosure, in addition to the above structure, also relates to wired and wireless communication, instrumentation, radar, electronic countermeasures and other equipment.

[0053] The time-interleaved digital-to-analog converter in the embodiments of this disclosure can also be other circuits or devices suitable for time-interleaving technology.

[0054] This disclosure also provides an electronic device including a time-interleaved digital-to-analog converter as described in any of the above embodiments.

[0055] Through the above embodiments, by setting a multiplexer, the output of the time-interleaved digital-to-analog converter can be determined according to different mode control codes and multiple initial sampling rates. This allows for different outputs based on different mode control codes, enabling appropriate sampling rates for different application scenarios and avoiding performance redundancy. Therefore, it solves the problems of excessive performance, power consumption, and area redundancy in traditional TIDACs, thereby improving the adaptability and versatility of TIDACs.

[0056] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solutions of this disclosure, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this disclosure.

[0057] It is obvious to those skilled in the art that the modules or steps of this disclosure described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this disclosure is not limited to any particular combination of hardware and software.

[0058] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A time-interleaved digital-to-analog converter, comprising: A multi-channel digital-to-analog converter configured to provide multiple outputs with multiple initial sampling rates; A mode control encoder is configured to generate mode control codes and send them to a multiplexer to control the configuration mode of the multiplexer via the mode control codes; The multiplexer, connected to the multi-channel sub-digital-to-analog converter, is configured to determine the output of the time-interleaved digital-to-analog converter corresponding to the target sampling rate based on the mode control code and the output of the multiple initial sampling rates, and to determine the output path corresponding to the output of the target sampling rate; wherein the target sampling rate is greater than or equal to the initial sampling rate.

2. The time-interleaved digital-to-analog converter according to claim 1, wherein, The multi-channel sub-digital-to-analog converter includes N sub-digital-to-analog converters connected in parallel, where N is an integer greater than or equal to 2.

3. The digital-to-analog converter according to claim 2, wherein, In the case of the first sampling rate scenario, the multiplexer is further configured to determine the output of any initial sampling rate of the multi-channel sub-digital-to-analog converter as the output of the target sampling rate.

4. The time-interleaved digital-to-analog converter according to claim 2, wherein, In the case of the second sampling rate scenario, the multiplexer is further configured to combine all or part of the initial sampling rate outputs of the multi-channel sub-digital-to-analog converter into the target sampling rate output in a time-division multiplexing manner.

5. The time-interleaved digital-to-analog converter according to claim 1, wherein, The multiplexer also includes: The control decoder is configured to decode the received mode control code into a control signal and send the control signal to the selector, wherein the mode control code corresponds to the configuration mode; The selector is configured to split the output of the multiple initial sampling rates to different combiners according to the received control signal; The combiner is configured to combine the output of the initial sampling rate into the output of the target sampling rate, and to determine the output path corresponding to the output of the target sampling rate.

6. The time-interleaved digital-to-analog converter according to claim 5, wherein, The selector is controlled by a decoder built into the chip or by a signal directly driven from outside the chip.

7. The time-interleaved digital-to-analog converter according to claim 5, wherein, The selector includes multiple switches, and the selector is further configured to control the closing of the multiple switches according to the control signal to split the output of the multiple initial sampling rates into different combiners.

8. The time-interleaved digital-to-analog converter according to claim 1, wherein, The digital-to-analog converter includes one or more outputs at the target sampling rate.

9. The time-interleaved digital-to-analog converter according to claim 1, wherein, The structure type of the digital-to-analog converter includes one of the following: resistive digital-to-analog converter, capacitive digital-to-analog converter, and current-driven digital-to-analog converter.

10. An electronic device comprising the time-interleaved digital-to-analog converter as described in any one of claims 1-9.

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