A digital-to-analog-converter and a method for detecting a timing error of the digital-to-analog-converter

Abstract

A method for detecting a timing error of a Digital-to-Analog-Converter (DAC). The DAC comprises: a digital control circuit configured to encode a digital input word into an encoded word, each bit of the encoded word having a corresponding bit weight, and further configured to encode each encoded word to a control word by mapping the bits of the encoded word to bits of the control word; clocked buffers comprising a first pair of clocked buffers and configured to sample the bits of the control word; analog weights, each weight associated with one of the bits in the control word; and summation circuitry configured to generate an analog sample by summing the sampled bits of the control word weighted by the respective associated analog weights. The method comprises: generating (901), a first pair of bits of the control word by periodically swapping a pair of mappings of bits of a first pair of bits of the encoded word having the same bit weight such that an error signal proportional to a timing error between a first clocked buffer and a second clocked buffer of the first pair of clocked buffers is generated; and detecting (902) the error signal.

Description

[0001] A DIGITAL-TO-ANALOG-CONVERTER AND A METHOD FOR DETECTING A TIMING

[0002] ERROR OF THE DIGITAL-TO-ANALOG-CONVERTER

[0003] TECHNICAL FIELD

[0004] The embodiments herein relate to a digital-to-analog-converter and a method for detecting a timing error of the digital-to-analog-converter. A corresponding computer program and a computer program carrier are also disclosed.

[0005] BACKGROUND

[0006] Digital-to-analog converters (DACs) are interface circuits between the digital and the analog domain and are used whenever a conversion from a digital signal representation to an analog signal representation is needed.

[0007] DACs are core components in a variety of equipment. High performance (high linearity and bandwidth, low power) DACs are crucial in wireless communication, be it in radio base-stations or various kinds of user devices (UE). For instance, in radio transmitters, a lot of the signal processing is typically done in the digital domain. However, the signal to be fed into the antenna typically uses an analog representation. Hence, a DAC is used somewhere in the signal chain leading up to the antenna.

[0008] A DAC may convert a sequence of digital words / numbers to a time-continuous signal where the digital number corresponds to a signal amplitude for a time-equidistant time series data. Figure 1 illustrates an example structure of a DAC. A digital input word [x1, x2, x3] (for example [1, 0, 0] representing the number 4) is transformed to a representation that is suitable for DAC conversion, in this example from binary encoding to thermometer encoding. A thermometer encoded word [q1..q7] is time synchronized (illustrated by a set of clocked buffers D1-D7, such as D-flip-flops) and multiplied with a set of weights w1-w7 and then the product is summed up to form an output signal. The time synchronization means that the update instants or windows of the bits of the encoded word are tightly aligned in time. That is, there is an explicit control (e.g. with the flip-flops) of the time the bits are updated. Errors in the time-synchronization and weight size contribute to an error in the summed output signal and that will contribute to a distorted output signal. Wireless communication is particularly challenging for DACs as all types of transmitters which include DACs should comply with stringent spectral emission requirements leading to e.g. high linearity and low spur level requirements of the DACs. In addition to this, the channel bandwidths to be supported continue to increase to meet the demand for continued increase in data rates. This in turn further exacerbate the challenge in designing DACs as it increases sampling rates and overall time accuracy in the DAC, especially if low power consumption is of utmost importance, as in battery-operated equipment or thermally limited equipment.

[0009] In the field of electronic circuits in general and for DACs in particular, there is a problem to accurately match certain properties to each other. One property that is required to be matched in DACs is the time instance where separate parts of a DAC, such as the clocked buffers, change from one sample of data to the next, herein called sampling time. For the majority of DAC types, the DAC output signal is constructed by summing up contributions from a number of DAC cells. This means that the equivalent sampling time is distributed and if there is misalignment between individual DAC cells, various forms of distortion will appear as the DAC output signal is formed by the summation of the outputs of the individual DAC cells. Normally, the timing mismatch is minimized by design, but for higher sampling and signal frequencies, the achievable level for the timing errors may contribute to unacceptable levels of distortion.

[0010] While matching may be improved to some extent by upscaling the dimensions of the constituting components of the DAC, it comes at the cost of a corresponding increase in power consumption. For power-limited equipment this is not acceptable and it is therefore important to pursue alternative routes to reach the level of matching required.

[0011] There are a number of existing solutions for minimizing DAC errors in general, and timing errors in particular. Some are described in prior art S. M. McDonnell, V. J. Patel, L. Duncan, B. Dupaix and W. Khalil, "Compensation and Calibration Techniques for Current- Steering DACs," in IEEE Circuits and Systems Magazine, vol. 17, no. 2, pp. 4-26, Second quarter 2017, doi: 10.1109 / MCAS.2017.2689518.

[0012] Some solutions rely on minimizing timing error by design. This is costly in terms of power and complexity and there is a limit to how accurate the timing mismatch can be made. Alternatively, the timing accuracy problem may be moved from the individual cells to a place later in the signal chain by sampling and holding the analog summed signal an extra time to settle before finally being outputted. This is often a feature of time- interleaved DAC structures. Though moving the time accuracy problem to a central, non- distributed, place may simplify timing accuracy problems, these types of structures introduce a new set of problems. For the interleaved DAC case, the amplitude mismatch between interleaved sub-DACs but also in general the problems of creating an accurate enough sample and hold / switching block are examples of such problems.

[0013] Dynamic element matching (DEM) techniques is a traditional set of methods to reduce the effect of timing mismatch. Here, timing mismatch errors are decorrelated from the input data, with the goal to spectrally distribute the distortion contributions from any timing mismatch. The problem with this is that it will increase noise floor and hence degrade the Signal-to-Noise Ratio (SNR). Alternative approaches to detect and compensate for timing errors rely on offline methods, i.e. they cannot be used during normal operation, or rely on switching in extra hardware, effectively putting the circuit into a different mode of operation and causing the measurement as such to influence the timing.

[0014] SUMMARY

[0015] If persistent time errors and weight errors can be detected and quantified, that gives the possibility to adjust the circuitry and mitigate the effects of these errors. Embodiments herein disclose a method to selectively identify timing-related errors by selective precoding and detect the errors of individual sets of DAC cells on the summed output signal.

[0016] Embodiments disclosed herein encode the data to sets of individual data contribution DAC cells in a way that particular timing errors give rise to measurable components of the output signal. Encoding individual data bits to give the total set of data- bits is the idea behind DEM but, in contrast to the prior art, the embodiments disclosed herein create an encoding scheme, not to spread out distortion components to noise, but to selectively impose a pattern that exercise errors from a particular set of sub cells to create a detectable signal in the summed up signal. This detected signal may in turn be used to quantify the timing errors introduced by just the selected DAC sub cells, and by trimming their individual timing, to calibrate the DAC.

[0017] According to a first aspect, the object is achieved by a method for detecting a timing error of a DAC. The DAC comprises an input port for receiving a sequence of digital input words, each representing a digital input sample. The DAC further comprises a digital control circuit configured to encode each digital input word into an encoded word. Each bit of the encoded word has a corresponding bit weight. The digital control circuit is further configured to encode each encoded word to a control word, representing the same digital input sample, by mapping the bits of the encoded word to bits of the control word. Each bit of the control word has the same bit weight as the corresponding bit of the encoded word.

[0018] The DAC further comprises a set of clocked buffers comprising a first pair of clocked buffers and configured to sample the bits of the control word at a common sampling frequency.

[0019] The DAC further comprises a set of analog weights. Each weight is associated with a unique one of the bits in the control word and proportional to the corresponding bit weight for a respective sample of the unique one of the bits of the control word.

[0020] The DAC further comprises summation circuitry configured to generate an analog sample corresponding to the digital input sample by summing the sampled bits of the control word weighted by the respective associated analog weights.

[0021] The DAC further comprises an output for outputting the analog sample.

[0022] The method comprises repeatedly generating (801), during a measurement period, for the first pair of clocked buffers and corresponding first pair of analog weights, a first pair of bits of the control word by periodically swapping a pair of mappings of bits of a first pair of bits of the encoded word having the same bit weight to the pair of bits of the control word such that an error signal proportional to a timing error between a first clocked buffer and a second clocked buffer of the first pair of clocked buffers is generated at the output during the measurement period corresponding to multiple swapping periods.

[0023] The method further comprises detecting (802) the error signal at the output.

[0024] According to a second aspect, the object is achieved by a DAC. The DAC is configured to perform the method of the first aspect.

[0025] According to a third aspect, the object is achieved by an electronic apparatus comprising the DAC according to the second aspect.

[0026] According to a fourth aspect, the object is achieved by an integrated circuit comprising the DAC according to the second aspect. According to a further aspect, the object is achieved by a computer program comprising instructions, which when executed by a processor of an electronic apparatus, causes the electronic apparatus to perform actions according to the first aspect.

[0027] According to a further aspect, the object is achieved by a carrier comprising the computer program of the aspect above, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0028] Since the first pair of bits of the control word is generated by periodically swapping the pair of mappings of bits of the first pair of bits of the encoded word having the same bit weight to the pair of bits of the control word the detected error signal, generated at the output during the measurement period corresponding to multiple swapping periods, is proportional to the timing error between the first clocked buffer and the second clocked buffer of the first pair of clocked buffers.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the figures, features that appear in some embodiments are indicated by dashed lines.

[0031] The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which:

[0032] Figure 1 schematically illustrates a DAC according to prior art,

[0033] Figure 2 schematically illustrates a communication environment in which embodiments disclosed herein may be implemented,

[0034] Figure 3 is a block diagram schematically illustrating a transceiver circuit according to some embodiments herein,

[0035] Figure 4 is a block diagram schematically illustrating a DAC according to some embodiments herein,

[0036] Figure 5 is a graph schematically illustrating different timing errors of a DAC and output from an ideal DAC,

[0037] Figure 6a schematically illustrates a DAC according to prior art,

[0038] Figure 6b schematically illustrates a DAC and a method of controlling the DAC,

[0039] Figure 7a schematically illustrates a DAC according to some embodiments herein, Figure 7b schematically illustrates a DAC according to some further embodiments herein,

[0040] Figure 8a schematically illustrates a DAC including a detection circuit according to some embodiments herein,

[0041] Figure 8b schematically illustrates a DAC including a detection circuit according to some further embodiments herein,

[0042] Figure 9 is a flowchart illustrating embodiments of a method for detecting a timing error of a DAC,

[0043] Figure 10 is a graph of amplitude of the detected error signal at the Nyquist frequency as function of delay time error and swap pair configuration setting,

[0044] Figure 11 is a graph of a first signal spectrum for a first delay time error and a first swap pair configuration setting,

[0045] Figure 12 is a graph of a second signal spectrum for a second delay time error and a second swap pair configuration setting,

[0046] Figure 13 is a graph of a third signal spectrum for a third delay time error and a third swap pair configuration setting,

[0047] Figure 14 is a graph of amplitude of the detected error signal at the clock frequency as function of duty cycle error and swap pair configuration setting,

[0048] Figure 15 is a graph of a first signal spectrum for a first duty cycle error and a first swap pair configuration setting,

[0049] Figure 16 is a graph of a second signal spectrum for a second duty cycle error and a second swap pair configuration setting,

[0050] Figure 17 is a graph of a third signal spectrum for a third duty cycle error and a third swap pair configuration setting,

[0051] Figure 18 is a graph of amplitude of the detected error signal at the Nyquist frequency as function of duty cycle error and swap pair configuration setting,

[0052] Figure 19 is a graph of a first signal spectrum for a first duty cycle error and a first swap pair configuration setting,

[0053] Figure 20 is a graph of a second signal spectrum for a second duty cycle error and a second swap pair configuration setting,

[0054] Figure 21 is a graph of a third signal spectrum for a third duty cycle error and a third swap pair configuration setting, Figure 22 is a graph of an injected delay time error and the amplitude of the error signal as function of cell number,

[0055] Figure 23 is a graph of an injected timing duty cycle error and the amplitude of the error signal as function of cell number,

[0056] Figure 24a is a graph of amplitude of the detected error signal at the Nyquist frequency as function of swap pair setting,

[0057] Figure 24b is a graph of amplitude of the detected error signal at the Nyquist frequency as function of swap pair setting,

[0058] Figure 25 is a block diagram illustrating an embodiment of a calibration circuit, Figure 26a is a graph of an electrical response of a calibration circuit,

[0059] Figure 26b is a zoom-in of the graph of the electrical response of the calibration circuit,

[0060] Figure 27 is a graph showing a timing retardation of the calibration circuit as function of a delay control word,

[0061] Figure 28 is a block diagram illustrating an embodiment of an integrated circuit comprising a DAC according to embodiments herein,

[0062] Figure 29 is a block diagram schematically illustrating an electronic device comprising a DAC according to embodiments herein.

[0063] Figure 30 is a block diagram schematically illustrating a wireless communication system.

[0064] DETAILED DESCRIPTION

[0065] Figure 2 illustrates a communication environment wherein embodiments disclosed herein may be employed. A wireless communication device 1, or wireless device 1 for short, of a cellular communications system is in wireless communication with a radio base station 2 of the cellular communications system. The wireless device 1 may be what is generally referred to as a user equipment (UE). The wireless devices 1 is depicted in Figure 2 as a mobile phone, but may be any kind of device with wireless, and in particular cellular, communication capabilities, such as a tablet or laptop computer, machine-type communication (MTC) device, or similar. Furthermore, a cellular communications system is used as an example throughout this disclosure. However, embodiments disclosed herein may be applicable in other types of wired or wireless communications systems as well, such as but not limited to WiFi systems. Further, embodiments may be implemented in any system (i.e. not limited to communication systems) employing a high-speed DAC, such as in any kind of instruments that require generation of linear high speed signals.

[0066] The radio base station 2 and wireless device 1 are examples of what in this disclosure is generically referred to as communication apparatuses. Embodiments are described below in the context of a communication apparatus in the form of the radio base station 2 or wireless device 1. However, other types of communication apparatuses may be considered as well, such as a WiFi access point or WiFi enabled device.

[0067] Figure 3 is a block diagram of an embodiment of a transceiver circuit 10, which may be comprised in a communication apparatus, such as the radio base station 2 or the wireless device 1. In the embodiment illustrated in Figure 3, the transceiver circuit 10 comprises a digital signal processing (DSP) circuit 15. The DSP circuit 15 may e g. be what is commonly referred to as baseband processor. The DSP circuit 15 may e.g. be configured to perform various digital signal processing tasks, such as one or more of coding, decoding, modulation, demodulation, fast Fourier transform (FFT), inverse FFT (IFFT), mapping, demapping, etc.

[0068] Furthermore, in the embodiment illustrated in Figure 3, the transceiver circuit 10 comprises a transmitter circuit 20. The transmitter circuit 20 comprises a DAC 25. The DAC 25 is connected to the DSP circuit 15 and configured to receive, as an input signal of the DAC 25, a digital representation of a signal to be transmitted from the DSP circuit 15. The DAC 25 is further configured to convert the signal to be transmitted to an analog representation, which is an output signal of the DAC 25. In some embodiments, the DAC 25 is a baseband DAC configured to generate the output signal in a baseband frequency range. In other embodiments, the DAC 25 is a radio-frequency (RF) DAC configured to generate the output signal in an RF range. In yet other embodiments, the DAC 25 is an intermediate-frequency (IF) DAC configured to generate the output signal in an IF range. The DSP circuit 15 may e.g. include a digital mixer or digital up-conversion in the transmit path, such that the input signal to the DAC is an RF or an IF signal, whichever the case may be. In any case, the input signal to the DAC 25 may be generated such that the intended output signal from the DAC 25 has zero signal content at DC, or 0 Hz (an ideal desired RF or IF signal has no spectral power (or amplitude) at DC. In practice there will be some residual contribution due to quantization and thermal noise as well as other error sources). The transmitter circuit 20 also comprises a transmitter (Tx) frontend (FE) circuit 30 connected between the DAC 25 and an antenna 35. The Tx FE circuit 30 is configured to transform the output signal from the DAC 25 to a format suitable for transmission via the antenna 35. This may include operations such as frequency up-conversion, filtering, and / or amplification. The Tx FE circuit 30 may comprise one or more mixers, filters, and / or amplifiers, such as power amplifiers (PAs), to perform such operations. The design of such Tx FE circuits is, per se, well known to a person skilled in the field of radio transceiver design, and is not discussed herein in any further detail.

[0069] Moreover, in the embodiment illustrated in Figure 3, the transceiver circuit 10 comprises a receiver circuit 40. The receiver circuit 40 comprises a receiver (Rx) FE circuit 45 connected to the antenna 35. Furthermore, the receiver circuit 40 comprises an ADC 50. The ADC 50 is connected between the Rx FE circuit 45 and the DSP circuit 15. The Rx FE circuit 45 is configured to transform a signal received via the antenna 35 to a format suitable to be input to the ADC 50. This may include operations such as frequency down-conversion, filtering, and / or amplification. The Rx FE circuit 45 may comprise one or more mixers, filters, and / or amplifiers, such as low-noise amplifiers (LNAs), to perform such operations. The design of such Rx FE circuits is, per se, well known to a person skilled in the field of radio transceiver design, and is not discussed herein in any further detail. The ADC 50 is configured to receive its (analog) input signal from the Rx FE circuit, and convert it to a digital representation to generate the digital output signal of the ADC 50. This digital output signal of the ADC 50 is input to the DSP circuit 15 for further digital signal processing.

[0070] Before going into more details of embodiments of the present disclosure, terminology used in the disclosure is first established. A digital signal is a sequence of samples, where the samples are numbers. These numbers can be represented in a variety of different number formats within a digital circuit. A word is used to represent a number in a given number format. The word consists of a number of bits. Each bit can adopt a low value and a high value. In this disclosure, the low value is considered to be -1, and the high value is considered to be +1 (or simply 1). It should be noted that this is merely an abstract convention that is used to provide a relatively simple mathematical description of the functionality of the embodiments disclosed herein, for instance in that the average of the low and the high value is 0. In a physical circuit, the high and low values are typically represented with different voltage levels. The same physical circuit could be described using another convention, for instance considering the low value to be 0 and the high value to be 1. This would slightly alter the mathematical description of the circuit, but would not alter the physical circuit or its functionality. Reference is made below to the time average of different sequences. This should be interpreted as the arithmetic average. That is, the time average of a given sequence during a time interval is the sum of the sample values of the given sequence in that time interval divided by the number of samples of the given sequence in that time interval.

[0071] Each bit has an associated bit weight given by the number format used. The number represented by the word is the sum, taken over all bits in the word, of the bit value multiplied with the bit weight. That is, if the number is denoted Z, the word is denoted z, the bits are denoted zt, i = 1,2, and the bit weights are denoted wi tthe number Z is given by

[0072] The DAC circuits considered in this disclosure are of the type that comprises a number of analog weights and selectively multiplies all of the analog weights by the corresponding bit value, and sums all of them, under control of a digital control word to form an analog output value. The number of weights is equal to the number of bits in the control word, while the number of discrete weight values may be smaller than the number of bits in the control word. Assume that the word z described above is used as the control word.

[0073] Further, let the analog weights be denoted atand the analog output value be denoted Y. Below, the notation T(t) is used in some places to indicate that the output value Y varies as a function of time t as a sequence of control words z[n] is applied. The analog output value Y is given by

[0074] Ideally, each analog weight atis proportional to the corresponding (digital) bit weight wt, i.e. at= Cwi, where C is a constant. In that case, the analog output value Y is also proportional to the number Z, i.e. Y = C ■ Z, which is the desired function of the DAC. However, due to factors such as manufacturing inaccuracies and temperature variations, there may be a mismatch between analog weights, which results in nonlinear distortion in the output of the DAC.

[0075] In implementations, the analog output T(t) is represented with a physical quantity, such as an electrical voltage or an electrical current. Figure 4 is a block diagram of the DAC 25 according to some embodiments disclosed herein. It comprises an input port 100 for receiving a sequence of digital input words x[n]. Each representing a digital input sample. The integer n is a sequence index indicating a given sample in the sequence.

[0076] Furthermore, the DAC comprises a digital control circuit 110 configured to encode each digital input word x[n] into an encoded word q[n]. Each bit qtof the encoded word q[n] having a corresponding bit weight Wj. The digital control circuit 110 is further configured to encode each encoded word q[n] to a control word z[n], representing the same digital input sample, by mapping the bits qt of the encoded word q[n] to bits z, of the control word z[n]. Each bit z, of the control word z[n] has the same bit weight wtas the corresponding bit qtof the encoded word q[n].

[0077] The control word z[n] also represents the same digital input sample. In some embodiments, such as when thermometer encoding is used for the encoded word, the first and second bit weights adopt values in {-1, 1}.

[0078] The DAC 25 further comprises clocked buffers 115, such as D-flip-flops. The clocked buffers comprises a first pair of clocked buffers D1 , D7 and are configured to sample the bits of the control word z_i at a common sampling frequency.

[0079] Moreover, the DAC 25 comprises a set 120 of analog weights, each weight associated with a unique one of the bits z, in the control word z[n] and proportional to the corresponding bit weight Wj for a respective sample of the unique one of the bits of the control word z,.

[0080] The DAC 25 further comprises a summation circuitry 130 configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word z, weighted by the respective associated analog weights, as mentioned above with reference to Eq. 2). The DAC 25 also comprises an output 140 for outputting the analog sample.

[0081] In some embodiments, there are multiple bits in the control word z[n] with the same bit weight. The analog weights associated with bits in the control word z[n] having the same bit weight are sometimes referred to below as analog weights with the same nominal weight. Conversely, analog weights associated with bits in the control word z[n] having different bit weight are sometimes referred to below as analog weights with different nominal weights.

[0082] The DAC 25 further comprises an error detection circuit 150 configured to detect an error signal at the output 140 of the DAC 25. More specifically, the error detection circuit 150 may be configured to detect an amplitude of the error signal. Furthermore, according to some embodiments, the DAC 25 comprises a calibration circuit 160 configured to adjust a sampling time of the clocked buffers 115 based on the detected error signal. Thereby, timing errors may be reduced.

[0083] Timing errors

[0084] Figure 5 illustrates two different timing errors that may arise in DACs and that may be reduced by embodiments disclosed herein. A first data signal A and a second data signal B represent two individual data signals, with the same weight and being time aligned. The signal A+B form the sum of the two data signals as illustrated in example 1 of Figure 5. Example 2 of Figure 5 illustrates a scenario where signal Bd corresponds to signal B but delayed. This may be referred to as a signal delay error. The sum A+Bd signal will exhibit undesired signal glitches due to the timing mismatch between A and Bd. Further, in example 3 the signal Bu corresponds to signal B but with a duty cycle shift from the ideal 50 / 50 high / low ratio. Given that delay and duty cycle errors may be expressed as both positive and negative, any timing error affecting the rising and falling edges of a cell signal may be expressed as a linear combination of the two above expressed errors.

[0085] Dynamic element matching

[0086] A well-established technique for mitigation of the effect of timing and amplitude errors in DACs is dynamic element matching DEM) and is illustrated in Figure 6a. Here, digital signals q1 - q7 are randomly permutated and mapped to different weight cells w1-w7, from one sample to another. The permutated mapping is illustrated with different types of arrows from each digital signal q1-q7 (solid line and different types of dashed lines). This means that signal content of each signal sent to the weight will be decorrelated from the signal in each digital signal q1-q7. That means that most signal frequency content present in a digital signal q, and that may create harmonic distortion when multiplied by a weight of a wrong size and / or at a wrong time, will be spread out to a noise like spectrum. This illustrates how a precoding scheme (the DEM randomization) may influence the content of the output signal.

[0087] Partial DEM

[0088] As discussed above, timing errors will only affect the output signal when the signal of a cell changes. It is the transitions of cell signals that triggers timing errors. Thus, the contribution of a signal cell may be minimized by minimizing the transition activity of a cell. Figure 6b illustrates a case where all input signal cells except a first input signal cell c1 (top) and a second input signal cell c2 (bottom) in a thermometer encoded word are scrambled with DEM. For a thermometer encoded word, the digital signal q1 is almost static at the code 0 and the digital signal q7 is almost static at code 1. This is true for almost all signals except full-swing signals. The full swing single sinewave signal may be a special case that is frequently used as a characterization signal, but for all other types of signals the statement that q1 is almost static 0 and q7 is almost static 1 hold. This means that any timing errors in the w1 and w7 paths will not show up as part of the output signal. Note that q1 may be arranged at the “bottom” of the thermometer ladder, and q7 may be “top”. Embodiments herein may give a more distinct detectable error signal the better a swapping activity is controlled. Embodiments herein may be applied for code words where q1 =1 and q7 = 0. q1 and q7 need to be different for the swapping to have an appreciable effect. Looking at the full range of codes (i.e. x1 , x2, x3) the outer most codes in the thermometer encoded word are the ones that will stay fixed for most codes. This is a reason to suggest to use q1 and q7 as the non-DEMed codes to be used for swapping. They are most likely to have different values and therefore generate an error signal when swapped. To have swapping at a certain frequency is also a mechanism that generates an error signal at a certain detectable frequency at the output. All relevant signals will very rarely utilize the full range of the codes. The peak-to-average-value of communication signals are high. A histogram of the input codes may e.g. be normal distribution-like. This is why q1 is almost static at code 0 and q7 is almost static at code 1. It is true static for all codes except the tails of the histogram. A single-tone full scale range signal will have a histogram of input codes that will look like a bath-tub. This is a special case where the condition that q1 and q7 are different are rarer. When q1 and q7 have the same value, the swapping will not create any switching and therefore not any error signal. The detectable error signal will be substantially smaller for the special case of a full-scale single-tone signal but it will still be present in the output signal.

[0089] With consideration of the partial DEM approach described above, embodiments disclosed herein provide a known activity on a particular set of weights. This is illustrated in Figure 7a. This may be done by letting a first swap control signal SA control swapping of a mapping of a particular set of encoded signals (bits) in a known manner. For example, the swap control signal may operate on encoded signals q1 and q7. The first swap control signal SA may be set to change every sample, which means that the encoded bits to w1 and w7 may change every clock period. A timing error between either w1 or w7 will then generate an error signal as shown in Figure 5, signal Ed. The error signal may be a pulse with opposite sign for each edge of the encoded data signal presented to w1 and w7.

[0090] The fundamental frequency component of this error signal is the same as the data swapping frequency, i.e. the frequency of the swap control signal. In some embodiments a swapping rate may be set to every data sample, i.e. the symbol rate. In such embodiments, this error signal which is induced by the signal delay error will have a lowest frequency component of half the clock frequency which is used to sample the control word at clocked buffers D1-D7 and a signal amplitude at half the clock frequency will then increase in proportion to a delay timing error between w1 and w7. Thus, embodiments herein may correct the delay timing error based on the measured amplitude of the output signal at half the clock frequency.

[0091] The sign (or phase) of the signal at half the clock frequency may depend on the relative direction of the delay between the sampled control signals of weight w1 and w7. Thus, embodiments disclosed herein may correct the timing error based on the measured phase of the error signal.

[0092] For the case of a duty cycle timing error between w1 and w7, the error signal may be a pulse with the same polarity at each swap event as indicated in Figure 2, signal Eu. With swapping of the encoded bits q1 and q7 at every sample, the fundamental frequency component of this error signal is the same as the clock frequency. By applying DEM to the signals for the other cells, the error signals due to timing errors of the other cells will be smeared out in frequency and not have a significant contribution to the signal content at the clock frequency or half the clock frequency.

[0093] For duty cycle error detection there may be an alternative way to excite the error signal. If the swap control signal in Figure 7a is adapted to provide a swap between two encoded bits, such as q1 and q7, every second sample instead of every sample, the error signal due to duty cycle errors will appear at half the clock frequency instead of at the clock frequency. If a block detecting the amplitude at the output at half the clock frequency is implemented, then it is possible to select which error property to detect depending on what swapping activity is applied to the pair of bits for which errors are to be detected.

[0094] Choose timing error source to excite In the previous example an error signal dependent on timing errors between weights w1 and w7 was induced. By selecting to which pair of weights the swap control signal is applied, and which weights are excluded from randomization with DEM, it is possible to arbitrarily choose between which cells the timing error is excited from. Figure 7b shows how to excite timing errors for cells w2 and w5 instead of w1 and w7 but the same method may be used to excite arbitrary pairs of weights by choosing to which cells the swap control signal is passed to, i.e. by controlling which cells are controlled by the swap control signal.

[0095] Detecting induced error signal at the DAC output

[0096] To mitigate effects of a timing error, the induced error signal first needs to be detected. Figure 8a illustrates the DAC 25 including the error detection circuit 150. The error detection circuit 150 may comprise a sampling circuit 851 , a low-pass filter 852 and an ADC 853. The ADC 853 facilitates further processing in digital domain as well as subsequent control / correction of delays.

[0097] As described above, it may be advantageous to implement the error signal at half the clock frequency. A method to detect the error signal at that frequency is to sample the output signal from the summation circuitry 130 with a period of half the clock frequency and low-pass filter the sampled signal, as indicated in Figure 8a.

[0098] The DAC sampling clock is available in the system that comprises the DAC 25 including the error detection circuit 150, and sampling at half that rate does not add much complexity. Please note that the setup of Figure 6a is generally available, that is it is a part of embodiments herein. This means that it is possible to measure an amplitude at half the clock rate without any emphasized error signal at the output of the summation circuit. This provides the ability to subtract any added signal due to error detection blocks. Note that the swap control signal (timing error stimulating signal (signal SA) may be different from a detection sampling signal SA’. For example, this may be the case for distinguishing error types as discussed above. Alternatively, this may be the case for a method to induce multiple swap control signals (error inducing signals) and use correlation as a method to distinguish between the induced errors as will be described further below.

[0099] In some embodiments there is also an optional buffer between the DAC output and the sampling function to isolate the DAC operation from the detection circuit but there may also be buffering functions between the constituent functions. Sampling and lowpass filtering as drawn in Figure 8a may also be viewed as mixing (aka frequency translation) with filtering, or a so called sampling mixer. This particular conceptual circuit implementation is advantageous as the low pass filter is effectively frequency translated by the sampling clock frequency to the input side of the sampling mixer and provides a high spectral selectivity of the DAC signal to only detect the frequency components of interest. The technique is well known and may be considered as a special case of the so-called N-path filter principle (for example as disclosed in E. A. M. Klumperink, H. J. Westerveld and B. Nauta, "N-path filters and mixer-first receivers: A review," 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2017, pp. 1-8, doi: 10.1109 / CICC.2017.7993643).

[0100] The detector technique proposed above may be extended to IQ sampling / mixing, in which case it is possible to also detect the phase of the frequency component, and not only the magnitude.

[0101] The above-described techniques for detecting the error from the output of the DAC 25 are examples. A person skilled in the art of electronic circuits and architectures may easily devise alternative techniques to detect the errors based on the swapping signal or knowledge of different aspects of the swapping signal, like frequency, phase, instants of swapping etc.

[0102] An alternative way to detect the timing-error-induced signal is to modulate the swap control signal SA as exemplified in Figure 8b. The swap control signal SA operates at some center frequency, e.g. swapping every or every second sample as exemplified above, or some other frequency. This swapping signal is in turn modulated or swapped with a second bit sequence C of much lower frequency than the frequency of the swap control signal SA, e.g. a pseudo-random bit sequence (PBRS) with a rate, say 1 / 10 or lower of the rate of the swap control signal SA. The same second bit sequence, now denoted C’ in Figure 8a, is also applied to the detected signal, before or after the ADC 853 by using an XOR block 854 (or other sign-switching function). This may be viewed as part of a correlation operation. A measurement indicative of the error to be detected may e.g. be obtained by integrating the output of the XOR block 854 (or other sign-switching function) over a period of time which should be long compared to the swapping period of the swap control signal. The benefits are:

[0103] 1. The information of interest may be seen as being coded, and decorrelated from the single-frequency of detection used above (e.g. the clock frequency or half the clock frequency). This is beneficial if there is e.g. a sampling clock leakage to the DAC output signal, thus potentially masking out information of interest.

[0104] 2. Using a low-frequency modulation will confine the spectral contributions when there are uncorrected errors, such that frequency planning is easier. Frequency planning refers to the planning of the frequency range consumed by the error such that is does not degrade the spectral performance of the DAC 25 for other frequency ranges having strict requirements. Signal SA’ in Figure 8b may to some extent couple to the input of the sampling circuit 851 of the detection circuit 150 and hence turn up at exactly the same frequency as the error to be detected. This coupling may vary with operating conditions and may thus limit the accuracy of the detection. Thus, by scrambling the swapping using signal SB, the swapping will no longer be periodic. The error will be spread in spectrum around say fs / 2 in proportion to the speed of the scrambling SB.

[0105] 3. Using a low-frequency modulation, the uncertainty of delay from the point of applying the modulation of the swapping of the encoded digital bits to the point where the low-frequency modulation is applied to the sign-switching function in XOR block 854, will not significantly affect the result.

[0106] 4. A higher frequency modulation may also be considered if the error of interest becomes enough spectrally distributed not to significantly degrade e.g. Signal to Noise and Distortion Ratio (SNDR) or SNR of the DAC output

[0107] Figure 9 illustrates a high-level flow chart for a method for detecting a timing error of the DAC 25. The method may be for selectively detecting timing errors between individual cells of the DAC 25. For example for detecting a timing error between a first pair of clocked buffers D1, D7 of the DAC 25. The clocked buffers D1-D7 mentioned above comprises the first pair of clocked buffers D1 , D7.

[0108] The method actions may be performed in any suitable order.

[0109] Action 901

[0110] The method comprises repeatedly generating, during a measurement period, for the first pair of clocked buffers D1, D7 and corresponding first pair of analog weights, a first pair of bits of the control word z[n] by periodically swapping a pair of mappings of bits of a first pair of bits of the encoded word q[n] having the same bit weight wtto the pair of bits of the control word z[n] such that an error signal proportional to a timing error between a first clocked buffer D1 and a second clocked buffer D7 of the first pair of clocked buffers D1 , D7 is generated at the output 140 during the measurement period corresponding to multiple swapping periods.

[0111] The digital control circuit 110 may be configured to repeatedly generate, during the measurement period, the first pair of bits of the control word z[n] as described above.

[0112] Swapping the pair of mappings of the bits of the first pair of bits of the encoded word q[n] may comprise, for a second digital input sample after a first digital input sample, swapping a first mapping of the first bit of the control word used for the first digital input sample with a second mapping of the second bit of the control word used for the first digital input sample. This swapping is performed such that for a first digital input sample, a first bit of the encoded word is mapped to a first bit of the control word and a second bit of the encoded word is mapped to a second bit of the control word, and then for a second digital input sample, the first bit of the encoded word is mapped to the second bit of the control word and the second bit of the encoded word is mapped to the first bit of the control word.

[0113] As mentioned above, embodiments herein may take advantage of DEM. In some embodiments disclosed herein for each sampling period during the measurement period, the DAC generates a first further bit of the control word z[n], which is different from the bits of the first pair of bits of the control word z[n], by randomly or pseudo-randomly, for example by a deterministic sequence that “looks random”, selecting a first further bit of the encoded word to be used as the first further bit of the control word z[n] and generating a second further bit of the control word z[n], which is different from the bits of the first pair of bits of the control word z[n], by randomly or pseudo-randomly selecting a second further bit of the encoded word to be used as the second further bit of the control word z[n]. The bit weights Wj of the selected first further bit and second further bit of the encoded word are equal.

[0114] The swapping frequency may equal the sampling frequency divided by an integer or by a fraction of the integer. The integer may be 1 or 2 for example. The sampling frequency and the Nyquist frequency are outside any signal frequencies, and they are easily available in the system. The integer may be positive.

[0115] In some embodiments the swapping frequency is modulated by a modulation signal. This may be beneficial if there is e.g. a sampling clock leakage to the DAC output signal.

[0116] Action 902

[0117] The method further comprises detecting the error signal at the output 140. Detecting 902 the error signal may comprise sampling the output signal and low-pass-filtering the sampled output signal. The error detection circuit 150 may be configured to detect the error signal at the output 140.

[0118] The error signal may be detected coherently with the swapping. For example, by sampling or mixing the error signal using a clock signal coherent with the swapping.

[0119] In some embodiments herein sampling the output signal comprises sampling the output signal at an integer multiple or integer fraction of the frequency of the periodic swapping of the bits of the first pair of bits of the encoded word q[n]. For example, the sampling may be done at the same rate as the swapping. An integer fraction (1 / N) may also be used but may render worse SNR as it effectively becomes subsampling.

[0120] In some embodiments herein detecting the error signal comprises mixing the output signal. Mixing may be done in combination with sampling and filtering. Mixing, filtering and sampling may also be done multiple times in a sequence to detect the error signal. In some embodiments herein the DAC comprises a mixer followed by a filter followed by a low frequency ADC (sampling) followed by a digital filter.

[0121] Detecting the error signal may further comprise time-averaging the sampled and low-pass filtered output signal over the measurement period.

[0122] In some embodiments herein detecting the error signal further comprises detecting a sign of the time-averaged sampled and low-pass filtered output signal.

[0123] Detecting the error signal may comprise detecting an amplitude or a phase of the error signal or both.

[0124] In some embodiments herein detecting the error signal comprises correlating the output signal with the modulation signal.

[0125] The measurement period may be chosen such that the detected error signal is larger than the noise floor of the detection measurement, preferably at least 3 dB larger, more preferably at least 6 dB larger, even more preferably at least 10 dB larger.

[0126] The measurement period may correspond to more than a hundred swapping periods, preferably between one thousand and one hundred million swapping periods, more preferably between ten thousand and ten million swapping periods, even more preferably between a hundred thousand and one million swapping periods.

[0127] In some embodiments herein during the measurement period the first pairs of bits of the control word z[n] is generated only from the first pair of bits of the encoded word q[n]. By generating the first pairs of bits of the control word z[n] only from the first pair of bits of the encoded word q[n] it is ensured that only the timing error between the first pair of cells is detected with the error signal. When a measurement period is over, a new pair of cells may be selected for swapping of the mapping of the bits of the encoded word.

[0128] Action 903

[0129] The method may further comprise adjusting a sampling time of at least the first clocked buffer D1 based on the detected error signal. The calibration circuit 160 may be configured to adjust the sampling time of at least the first clocked buffer D1 of the first pair of clocked buffers D1 , D7 based on the detected error signal. The calibration circuit 160 may be arranged within the at least first clocked buffer D1.

[0130] In some embodiments herein adjusting the at least first sampling circuit D1 is based on the time-averaged error signal.

[0131] Adjusting the at least first sampling circuit D1 may further be based on the sign of the time-averaged sampled and low-pass filtered output signal.

[0132] In some embodiments herein adjusting the sampling time of the at least first clocked buffer D1 based on the detected error signal comprises adjusting a propagation delay, for example a clock-to-Q delay, of the at least first clocked buffer D1.

[0133] Verification of embodiments herein by simulation

[0134] This section presents simulation results from a MATLAB model of the DAC 25 verifying the functionality of the suggested method. The MATLAB model models amplitude, time-delay and duty-cycle errors in the DAC 25 with different DAC segmentations. The model is fed with digital signal data and the DAC output is created in an oversampled, sum of a set of individual contributing cells. Timing errors significantly smaller than steps given by the oversampling ratio used is created by sine-based interpolation. The method has been verified with several different DAC segmentations with 4 to 9 thermometer encoded Most Significant Bit (MSB) bits connected to 0 to 8 binary encoded bits providing the finer resolution range of the DAC 25. The total number of bits have been 4 to 16.

[0135] In a first simulation example a segmentation with 4 thermometer encoded bits and 8 binary encoded bits, together forming a 12-bit DAC, has been used.

[0136] In a second simulation example for validating a timing error detection of binary encoded bits, a segmentation of a one level decomposed DAC, where 4 MSB bits in each sub-DAC have been thermometer encoded, has been used. Remaining 7 bits per sub- DAC have been binary encoded and it is an excitation of selected binary bits that are described in this simulation example.

[0137] The simulations generating the disclosed results have been made with 4000 samples, giving that the pace at which an individual error were detected is 1 / 4000 of the sample rate. Note that the error detection is done in the background while sending valid data so the rate of detecting error is a measure of error-change-tracking-speed. Detection time may then affect how frequent it is possible to detect an error. If a timing error changes over time due to for instance temperature or supply voltage variations, then the time it takes to detect an error will affect how rapid error changes it is possible to compensate for.

[0138] In the simulations a signal emulating the normal transmitted data is present. The signal is a two-tone signal at full-scale amplitude range with a random frequency for each 4000 sample simulation. Note the ratio between sample rate and detection time of 4000 samples is an example of a feasible ratio.

[0139] Isolated delay time error identification example

[0140] Figure 10 shows the detected signal amplitude at the Nyquist frequency on the vertical axis for a set of simulations with different time delay errors per cell (with different data markers as indicated in the legend) and for different encoding settings (what pair to excite) on the horizontal axis.

[0141] Each of the curves represent simulations with a fixed delay time error for a certain cell, as described in the legend. Note that there are peaks in the signal spectrum at the Nyquist frequency for the swap pair configurations that reflects the cell where time delay errors have been injected. Also note that the height of the peak reflects the size of the delay time error.

[0142] Figure 11, Figure 12 and Figure 13 show the signal spectrum for a few of the simulation-points shown in Figure 10. The points with the corresponding spectrums are marked S1 , S2 and S3 in Figure 10. Note that for these simulations, two-tone signals at random frequencies have been used for each simulation point in Figure 10, to further demonstrate the robustness. Note that the spectrum S2 of Figure 12 shows the case where cell 2 and 7 have a delay time error but the encoding of the digital control circuit 110 is set for detecting the error for the cells 1 and 3. Thus, Figure 12 illustrates that a delay error on a cell that is subject to random DEM swapping will not create an error signal at the Nyquist frequency and that delay errors in cells that are not driven by the selected swapping scheme will have a significantly smaller contribution to the signal amplitude at the Nyquist frequency. The highest peaks in the spectrum originate from the payload signals which are input to the DAC 25.

[0143] Isolated duty cycle time error identification example

[0144] Figure 14 shows the detected signal amplitude at the clock frequency on the vertical axis for a set of simulations with different duty cycle errors per cell (as described in the legend) and different encoding settings (what pair to excite) on the horizontal axis. Each of the curves represent simulations with fixed duty cycle error. Figure 15, Figure 16, and Figure 17 each shows the signal spectrum for a few of the simulation-points shown in Figure 14. The points with the corresponding spectrums are marked S1, S2 and S3 in Figure 14.

[0145] Isolated duty cycle time error identification, selected swap rate example

[0146] Figure 18 shows the detected amplitude at the Nyquist frequency on the vertical axis for a set of simulations with different duty cycle errors per cell (as described by the legend) and different encoding settings (what pair to excite) on the horizontal axis. Each of the curves represent simulations with fixed duty cycle error. Note that there are peaks in the amplitude at the Nyquist frequency for the swap pair configurations that reflects the cell where timing errors have been injected. Also note that the height of the peak reflects the size of the duty cycle error.

[0147] Figure 19, Figure 20, and Figure 21 show the signal spectrum for a few of the simulation-points shown in Figure 18. The points with the corresponding spectrums are marked S1 , S2 and S3 in Figure 18.

[0148] The results in Figures 18-21 are obtained with a swapping frequency of half the sampling frequency. This places the error signal due to duty cycle errors at the Nyquist frequency. This is in contrast to the results in Figures 14-17, where the error signal is due to timing delays, and the swapping frequency is at the clock frequency. Thus, it is possible to select which type of timing error (delay- or duty-cycle error) that will induce the error signal at the Nyquist frequency based on the frequency of the swapping.

[0149] Orthogonality and simultaneous errors

[0150] The simulations for estimating delay and duty cycle timing errors presented above have been conducted by injecting one type of error at the time. It was shown that a single error may be detected when a particular encoding is used. Below it will be explained how it is possible to detect and identify a particular error with other errors present. The dotted lines of Figure 22 and Figure 23 respectively show delay time errors and duty cycle errors injected for a particular cell number shown on the horizontal axis. The errors have been set to the same for each simulation point. The solid curve in Figure 22 shows the detected signal amplitude at the Nyquist frequency when the encoding is adapted to detect the delay timing error, as described above, for a particular unit cell. In the same way, the solid curve of Figure 23 shows the detected signal amplitude at the Nyquist frequency when the encoding is adapted to excite a duty cycle error for a particular cell. This illustrates that method embodiments disclosed herein may be used to detect delay and duty cycle errors within a pair of cells while timing errors of the same magnitude exist in relation to other unit cells and that duty cycle and delay errors may be independently detected by changing encoding of the encoded word to generate the control word and measure the amplitude at Nyquist frequency. Note, in this simulation, the errors have intentionally been set to only positive values for all cells. That has been done only to simplify the presentation of the error. For negative cell timing errors, the phase of the detected signal at Nyquist will change and the error signal may comprise of a combination of the amplitude and phase information. The fact that the phase changes with the sign of the error has been verified by simulation but is not shown here. An illustration when the phase is taken into account is shown in the next section.

[0151] The simulations presented above have been performed to detect timing errors on DACs with equally weighted thermometer encoded bits. This a very common way of partitioning, especially for the most significant bits of a DAC. As the number of unit cells grows with a factor of two for each bit added to a DAC, it is very common to partition parts of a DAC with non-equal weights, typically binary weighted. To have the possibility to affect the activity of a DAC cell according to embodiments disclosed herein, multiple ways to create the same summed output signal is required. Thus, some kind of redundant coding is required. This is native for a thermometer encoded DAC as all cells will have the same weight but for a binary scaled DAC or DAC part that is not natively the case. One way to create redundant coding is decomposition of the encoded word. An example of one level decomposition encoding is illustrated in Table 1 below. It shows the mapping of a 4-bit word to two decomposed 3-bit words, and an extra LSB bit. The logic needed to implement this is well-known. After decomposition, a portion of the bits (typically the most significant bits) may be converted to thermometer encoding giving the ability to create any hybrid version of thermometer encoding and redundant binary encoding of choice.

[0152] Table 1. One level decomposition encoding of a 4-bit word

[0153] With the decomposed encoding of binary bits it is possible to identify that for each bit weight there are at least two cells with the same weight. It is also possible to identify that for each bit weight (1 , 2 or 4) there is one cell (x1 b, x2b, or x4b) that is constant positive for half of the input range (Dec: 9-15) and one cell (x1a, x2a, or x4a) that is constant negative for the other half of the input range (Dec: 0-8). It is further possible to identify that for the half part of Table 1 where a bit is not constant, the number of positive and negative values are equal. For any signal with reasonable oversampling ratio, that means that making a swap of data for a pair of equally weighted bits (e.g. the pair x1a and x1 b, the pair x2a and x2b, or the pair x4a and x4b) with a fixed frequency increases the data swapping activity for that pair of equally weighted bits. In particular, it increases the amplitude of the swapping-induced error signal at the Nyquist frequency. This in turn means that the frequency of data activity for a weight pair may be controlled by encoding the encoded word into the control word in the same way as described above. The amplitude level at the Nyquist frequency is less due to that there is less chance to have a data swap event (1 to -1 , or -1 to 1) for every data sample. Still the change of activity between swapping at a constant pace and not doing it is significant enough so that error sources may be isolated by the encoding. Figure 24a shows the detected error signal when introducing a duty cycle error in one of the pair of LSB / 2*LSB / .... weighted cells for the one-level decomposed DAC of Table 1. Figure 24b is an alternative way of illustrating the detected error signal. Figure 24b shows the detected error signal when introducing a timing error in individual cells. The swap pair setting is the same for the same label on the horizontal axis. The timing error has been introduced to one cell at a time (Each timing error for an individual cell has its own data point symbol as illustrated by the legend.), and the legend further indicates whether the sign of the error signal is positive or negative (i.e. detected phase >0 or detected phase <0 using the terminology in the legend). Figure 24b shows that the detected error signal is considerably stronger when swapping is performed for a pair for which the timing error is present. The lower data points are more or less overlapped and represent the cases where swapping is performed for a pair for which the timing error is not present.

[0154] Figure 24b shows an injected error in the first (e.g. x1a, x2a, or x4a in table 1 corresponding to LSBa cell in the legend of Figure 24b) of the pair of equally weighted bits will result in an error signal with a different sign than if an error is injected in the second (e.g. x1b, x2b, or x4b in table 1 corresponding to LSBb cell in the legend of Figure 24b) of the pair of equally weighted bits. This shows that it is possible to detect the relation between errors with the same weight and then know what direction a timing needs to be adjusted to reduce the error in an equally weighted pair.

[0155] Note the swap pair axis indicates which pair of equally weighted cells corresponds to columns x[4 / 2 / 1]a and x[4 / 2 / 1]b in Table 1. The phase of the detected signal derivable from Figure 24b shows that it is possible to identify the relationship between the errors in a pair. The phase of the detected error signal will depend on the relationship of the phase of the swap control signal and the phase of the sampling signal in the error detection circuit 150. Though this relationship is potentially nontrivial to set up, the phase relationship between these signals may be kept static. This means that it is possible to detect the direction of an error by a method like: measure the error for a particular pair, adjust the delay for one of the cells in the pair measured. Measure the error again. If the measured error is bigger than before, then the adjustment was in the wrong direction. Then change adjustment direction. The property that the phase of the error signal depends on the relationship between the phase of the swap control signal and the phase of the sampling signal is present for the thermometer-encoded configurations, whose simulations are shown above. Note that the weight of the cell influences the amplitude of the detected error signal at the Nyquist frequency, which makes the detection of the errors of the lower significance cells more challenging since lower significance cells produce smaller amplitude of the error signal. However, it also means that a timing error in a lower significance cell contributes less to distortion in the overall signal, which means that a larger timing error may typically be tolerated.

[0156] In the simulations above the error signals have been detected through peak amplitude (and phase) of the spectrum of the simulated output signal. In sampling circuit implementations calculating a full spectrum is expensive. An alternative detection method is to sample and average the signal as described above.

[0157] Timing trimming in the DAC cells

[0158] Once the timing errors are measured, they may be corrected inside the individual DAC cells. This may be achieved by suitably trimming the propagation delay of the digital cells processing the DAC bit streams. For example, by adjusting the clock-to-Q delay of the clocked buffers 115. For DACs operating close to the Nyquist frequency at a few tens of giga-samples-per-second it is necessary to achieve timing matching of a few tens of femtoseconds. In a 7-nm CMOS process the native timing spread is within a few hundred femtoseconds. Therefore, any practical trimming circuit must provide a granularity of a few tens of femtoseconds and a range of a few hundred femtoseconds.

[0159] For a CMOS circuit, a well-known method for adjusting the propagation delay is to connect / disconnect capacitance to appropriate nodes. However, this conventional method has two major drawbacks making it unfeasible for timing correction of high-speed DACs: 1) It requires additional switches to be connected to timing critical nodes, slowing down the maximum achievable operating speed and increasing the power consumption; 2) The parasitic capacitance of even just the switches is large enough to make the practically achievable trimming granularity too coarse.

[0160] Therefore, to demonstrate the practicality of the DAC timing trimming, a technique may be employed for adjusting the load capacitance used to trim the propagation delay of an inverter. This method provides very fine-grained adjustment, and a relatively small additional capacitive load requiring very little additional power. Instead of connecting / disconnecting additional capacitance, a non-linear gate capacitance of permanently connected MOS transistors may be used. Due to the non-linear nature of the gate capacitance, it’s possible to change it by connecting a drain or source terminals or both to either high or low voltage potential, as shown in Figure 25. Since the change of the gate capacitance is relatively small a fine-grained trimming can be achieved. Furthermore, since the absolute gate capacitance is also small (relative to the drain / source junction capacitance of switches for example) the additional load due to the trimming circuit can be reasonably accommodated by the design. The two inverters in the upper part of Error! Reference source not found., represent a chain of CMOS digital circuits, as are commonly found in D-flip-flops, and the node vPulse_mid is the one to be slowed down.

[0161] Figure 26a shows a simulation result when a single data pulse is fed through the chain of inverters and a value of a delay control word, acting as a control signal to the timing calibration circuit 160, is swept from 0 to 8. The effect on timing is barely noticeable despite the pulse being rather short (corresponding to 20 Gsps). A zoom in to the rising edge is shown in Figure 26b where the timing retardation for various values of the control word is more visible. Shown also, is the circuit response for a completely disconnected calibration circuit, this is the native response. As can be seen the parasitic delay due to the calibration circuit is about 450 fs. This is a relatively small value compared to the typical delay of about 6 ps of a single inverter, and about 20 ps of a D-flip-flop.

[0162] The relative timing retardation measured at the mid-point of the rising and falling edges separately is shown in Figure 27 for all values of the delay control word. It is interesting to note that the rising edge is delayed more relative to the falling edge. This is because of the asymmetric sizing of the inverters. With the example sizing, the calibration granularity is ~19 fs and ~9 fs for the rising and falling edges respectively. With a 3-bit delay control word the corresponding calibration ranges (maximum adjustment of the delay) are -130 fs and -60 fs.

[0163] In the example above, both rising and falling edges are trimmed (i.e. calibrated) with a single control word, which may be undesirable since, as it became evident above, it may be necessary to correct duty-cycle errors too. In order to achieve this the D-flip-flop may be implemented such that each edge is handled by a single-edge-latch on a dedicated node, making it possible to adjust each edge and transition separately. This may be implemented according to the disclosure in document WO2023110111 A1.

[0164] Closing the loop and mitigating errors

[0165] The embodiments described above enable the possibility to trigger and detect a particular timing error for a chosen pair of unit cells of the DAC. This may be done during normal operation and do not interfere with the normal operation of the DAC. For thermometer encoded parts, the pair of cells from which the timing error shall be triggered may be selected arbitrarily by the described encoding. To correct the timing errors, there is a variety of possible algorithms that may be considered. As the detection may be performed in the background during normal operation, there is a great degree of freedom when it comes to convergence speed and noise robustness when choosing correction algorithm used to correct timing errors based on detected error signals. One algorithm that may be considered is outlined below but there are a variety of possible solutions that are enabled by the timing error detection method disclosed herein.

[0166] 1. Choose one cell instance as reference.

[0167] 2. Choose a second cell instance as target for correction.

[0168] 3. Setup encoding according to the embodiments above so that a timing error for the cells chosen in action 1 and 2, 7 or 8 triggers an error signal at the Nyquist frequency.

[0169] Measure the error signal.

[0170] 4. If the error signal is smaller than a predefined value go to action 7 otherwise go to action 5.

[0171] 5. Adjust the timing of the cell chosen in action 2, either with a value proportional to the obtained error signal in action 3 or with a fixed small step only depending on the phase (sign) of the error signal obtained in action 3. For delay errors both edges (rising and falling) are trimmed in the same direction, while for duty cycle errors they are moved in the opposite direction.

[0172] 6. Go to action 3.

[0173] 7. If all cells have been adjusted choose the original cell in action 2 (i.e. a new round of calibration is started, the original cell can be any cell) and go to action 3. Alternatively stop the adjusting algorithm and flag the calibration as done. Else do action 8.

[0174] 8. Choose a different cell that has not been selected previously in action 2 and go to action 3.

[0175] A detection method according to embodiments disclosed herein may be summarized as follows:

[0176] Embodiments herein may comprise controlling the swapping activity for a first cell or first set of cells so that the timing errors in relation to at least one other cell are emphasized on either a particular frequency or with a known pattern.

[0177] Optionally, at the same time, the activity of other cells may be influenced so that timing errors on those cells do not create significant amplitude on the frequency or pattern that are emphasized for the first set of cells. This may for example be accomplished by spectrally spreading out the error power of the other cells to noise (DEM).

[0178] Embodiments of the DAC 25 are suitable for integration on an integrated circuit. This is illustrated in Figure 28, schematically showing an integrated circuit 500 comprising the DAC 25.

[0179] Figure 29 schematically illustrates an electronic apparatus 1400, such as a communication apparatus. The communication apparatus may be the network node 2 for a wireless communications network 170 illustrated in Figure 30, or the wireless communications device 1 for the wireless communications network. The electronic apparatus comprises the DAC 25.

[0180] The DAC 25 or the electronic apparatus 1400 or both may be configured to perform the method actions of Figure 9 above. For example, the DAC 25 or the electronic apparatus 1400 may be configured to generate the first further bit of the control word by randomly or pseudo-randomly selecting the first further bit of the encoded word to be used as the first further bit of the control word z[n] and to generate the second further bit of the control word z[n], by randomly or pseudo-randomly selecting the second further bit of the encoded word to be used as the second further bit of the control word z[n].

[0181] In some embodiments the DAC 25 or the electronic apparatus 1400 is configured to detect the error signal by being configured to sample the output signal and low-pass-filter the sampled output signal.

[0182] The DAC 25 or the electronic apparatus 1400 may be configured to sample the output signal at an integer multiple or integer fraction of the frequency of the periodic swapping of the bits of the first pair of bits of the encoded word q[n]. For instance, the DAC 25 or the electronic apparatus 1400 may comprise circuitry, such as the error detection circuit 150, configured to sample the output signal.

[0183] In some embodiments the DAC 25 or the electronic apparatus 1400 is configured to detect the error signal by being configured to time-average the sampled and low-pass filtered output signal over the measurement period, and to adjust the at least first sampling circuit D1 based on the time-averaged error signal. The DAC 25 or the electronic apparatus 1400 may be configured to detect the error signal further by being configured to detect the sign of the time-averaged sampled and low-pass filtered output signal, and to adjust the at least first sampling circuit D1 further based on the sign of the time-averaged sampled and low-pass filtered output signal.

[0184] In some embodiments the DAC 25 or the electronic apparatus 1400 is configured to modulate the swapping frequency by a modulation signal, and to detect the error signal by being configured to correlate the output signal with the modulation signal.

[0185] The DAC 25 or the electronic apparatus 1400 may be configured to detect the error signal by being configured to detect the amplitude or the phase of the error signal or both.

[0186] In some embodiments the DAC 25 or the electronic apparatus 1400 is configured to adjust the sampling time of the at least first clocked buffer D1 based on the detected error signal by being configured to adjust a propagation delay of the at least first clocked buffer D1.

[0187] The DAC 25 or the electronic apparatus 1400 may be further configured to choose the measurement period such that the detected error signal is larger than the noise floor of the detection measurement, preferably at least 3 dB larger, more preferably at least 6 dB larger, even more preferably at least 10 dB larger.

[0188] In some embodiments the DAC 25 or the electronic apparatus 1400 is configured to generate during the measurement period the first pairs of bits of the control word z[n] only from the first pair of bits of the encoded word q[n].

[0189] The DAC 25 or the electronic apparatus 1400 may be further configured to detect the error signal by being configured to mix the output signal.

[0190] Figure 29 illustrates further optional details of the electronic apparatus 1400. The electronic apparatus 1400 may be configured to perform the method actions of Figure 9 above.

[0191] The embodiments herein may be implemented through a processor or one or more processors, such as the processor 1404, of a processing circuitry in the electronic apparatus 1400, and depicted in Figure 14 together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product, for instance in the form of a data carrier carrying computer program code for performing the embodiments herein when being loaded into the electronic apparatus 1400. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server and downloaded to the electronic apparatus 1400.

[0192] The electronic apparatus 1400 may further comprise a memory 1402 comprising one or more memory units. The memory comprises instructions executable by the processor in the electronic apparatus 1400.

[0193] The memory 1402 is arranged to be used to store e.g. information, data, configurations, and applications to perform the methods herein when being executed in the electronic apparatus 1400.

[0194] In some embodiments, a computer program 1403 comprises instructions, which when executed by the at least one processor, cause the at least one processor of the electronic apparatus 1400 to perform the actions above.

[0195] In some embodiments, a carrier 1405 comprises the computer program, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer- readable storage medium.

[0196] The electronic apparatus 1400 may further comprise an input and output interface, I / O, 1406 configured to communicate with other devices. The input and output interface 1406 may comprise a receiver, such as a wireless receiver, not shown) and a transmitter, such as a wireless transmitter, (not shown).

[0197] Those skilled in the art will also appreciate that the units described above may refer to a combination of analog and digital circuits, and / or one or more processors configured with software and / or firmware, e.g. stored in the electronic apparatus 1400, that when executed by the respective one or more processors such as the processors described above. One or more of these processors, as well as the other digital hardware, may be included in a single Application-Specific Integrated Circuitry (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).

[0198] Figure 31 illustrates a wireless communications network 170 in which embodiments herein may be implemented.

[0199] The wireless communications network 170 may use a number of different technologies, such as Wi-Fi, Long Term Evolution (LTE), LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile communications / enhanced Data rate for GSM Evolution (GSM / EDGE), Worldwide Interoperability for Microwave Access (WiMax), or Ultra Mobile Broadband (UMB), just to mention a few possible implementations. Embodiments herein relate to recent technology trends that are of particular interest in a 5G context. However, embodiments are also applicable in further development of other existing wireless communication systems such as e.g. WCDMA and LTE and in future wireless communication systems, such as 6G systems.

[0200] Network nodes operate in the wireless communications network 170 such as the network node 2. The network node 2 provides radio coverage over a geographical area, a service area referred to as a cell 15, which may also be referred to as a beam or a beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi or similar. There may be more than one cell. For example, there may be a second cell 16 as well. The network node 2 may be a NR-RAN node, transmission and reception point e.g. a base station, a radio access node such as a Wireless Local Area Network (WLAN) access point or an Access Point Station (AP STA), an access controller, a base station, e.g. a radio base station such as a NodeB, an evolved Node B (eNB, eNode B), a gNB, a base transceiver station, a radio remote unit, an Access Point Base Station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point or any other network unit capable of communicating with a wireless communications device within the service area depending e.g. on the radio access technology and terminology used. The respective network node 2 may be referred to as a serving radio access node and communicates with a UE with Downlink (DL) transmissions to the UE and Uplink (UL) transmissions from the UE. A number of wireless communications devices operate in the wireless communication network 10, such as the wireless communications device 1.

[0201] The wireless communications device 1 may be a mobile station, a non-access point (non-AP) STA, a STA, a user equipment and / or a wireless terminal, that communicate via one or more Access Networks (AN), e.g. RAN, e.g. via the network node 2 to one or more core networks (CN) e.g. comprising a CN node 13, for example comprising an Access Management Function (AMF). It should be understood by the skilled in the art that “UE” is a non-limiting term which means any terminal, wireless communication terminal, user equipment, Machine Type Communication (MTC) device, Device to Device (D2D) terminal, or node e.g. smart phone, laptop, mobile phone, sensor, relay, mobile tablets or even a small base station communicating within a cell.

[0202] When using the word "comprise" or “comprising” it shall be interpreted as non- limiting, i.e. meaning "consist at least of".

[0203] The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used.

Claims

CLAIMS1 . A method for detecting a timing error of a Digital-to-Analog-Converter, DAC, (25), comprising: an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample; a digital control circuit (110) configured to encode each digital input word (%[n]) into an encoded word (q[n]), each bit (Q;) of the encoded word (q[n]) having a corresponding bit weight (wi), wherein the digital control circuit (110) is further configured to encode each encoded word (q[n]) to a control word (z[n]), representing the same digital input sample, by mapping the bits (Q;) of the encoded word (q[n]) to bits (Z;) of the control word (z[n]), each bit (z of the control word (z[n]) having the same bit weight (w;) as the corresponding bit (q^) of the encoded word (q[n]); a set of clocked buffers (D1-D7) comprising a first pair of clocked buffers (D1 , D7) and configured to sample the bits of the control word (z;) at a common sampling frequency; a set (120) of analog weights, each weight associated with a unique one of the bits (Z;) in the control word (z[n]) and proportional to the corresponding bit weight (wi) for a respective sample of the unique one of the bits of the control word (zf); summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the sampled bits of the control word (Z;) weighted by the respective associated analog weights; and an output (140) for outputting the analog sample; the method comprising: repeatedly generating (901), during a measurement period, for the first pair of clocked buffers (D1 , D7) and corresponding first pair of analog weights, a first pair of bits of the control word (z[n]) by periodically swapping a pair of mappings of bits of a first pair of bits of the encoded word (q[n]) having the same bit weight (nq) to the pair of bits of the control word (z[n]) such that an error signal proportional to a timing error between a first clocked buffer (D1) and a second clocked buffer (D7) of the first pair of clocked buffers (D1 , D7) is generated at the output (140) during the measurement period corresponding to multiple swapping periods; and detecting (902) the error signal at the output (140).

2. The method according to claim 1 , wherein swapping the pair of mappings of the bits of the first pair of bits of the encoded word (q[n]) comprises: for a second digital inputsample after a first digital input sample, swapping a first mapping of the first bit of the control word used for the first digital input sample with a second mapping of the second bit of the control word used for the first digital input sample.

3. The method according to claim 1 or 2, further comprising: adjusting (903) a sampling time of at least the first clocked buffer (D1) based on the detected error signal.

4. The method according to any of the claims 1-3, further comprising, for each sampling period during the measurement period, generating a first further bit of the control word (z[n]), which is different from the bits of the first pair of bits of the control word (z[n]), by randomly or pseudo-randomly selecting a first further bit of the encoded word to be used as the first further bit of the control word (z[n]) and generating a second further bit of the control word (z[n]), which is different from the bits of the first pair of bits of the control word (z[n]), by randomly or pseudo-randomly selecting a second further bit of the encoded word to be used as the second further bit of the control word (z[n]), wherein the bit weights (wi) of the selected first further bit and second further bit of the encoded word are equal.

5. The method according to any of the claims 1-4, wherein detecting (902) the error signal comprises sampling the output signal and low-pass-filtering the sampled output signal.

6. The method according to claim 5, wherein sampling the output signal comprises sampling the output signal at an integer multiple or integer fraction of the frequency of the periodic swapping of the bits of the first pair of bits of the encoded word (q[n]).

7. The method according to claim 5 or 6, wherein detecting (902) the error signal further comprises time-averaging the sampled and low-pass filtered output signal over the measurement period, and wherein adjusting (903) the at least first sampling circuit (D1) is based on the time-averaged error signal.

8. The method according to claim 7 in combination with claim 3, wherein detecting (902) the error signal further comprises detecting a sign of the time-averaged sampled and low-pass filtered output signal, and wherein adjusting (903) the at least first samplingcircuit (D1) is further based on the sign of the time-averaged sampled and low-pass filtered output signal.

9. The method according to any of the claims 1-8, wherein the swapping frequency is modulated by a modulation signal, and wherein detecting (902) the error signal comprises correlating the output signal with the modulation signal.

10. The method according to any of the claims 1-9, wherein detecting (902) the error signal comprises detecting an amplitude or a phase of the error signal or both.

11. The method according to any of the claims 1-10, wherein the swapping frequency equals the sampling frequency divided by an integer or by a fraction of the integer.

12. The method according to any of the claims 3-11 , wherein adjusting (903) the sampling time of the at least first clocked buffer (D1) based on the detected error signal comprises adjusting a propagation delay of the at least first clocked buffer (D1).

13. The method according to any of the claims 1-12, wherein the measurement period is chosen such that the detected error signal is larger than the noise floor of the detection measurement, preferably at least 3 dB larger, more preferably at least 6 dB larger, even more preferably at least 10 dB larger.

14. The method according to any of the claims 1-13, wherein the measurement period corresponds to more than a hundred swapping periods, preferably between one thousand and one hundred million swapping periods, more preferably between ten thousand and ten million swapping periods, even more preferably between a hundred thousand and one million swapping periods.

15. The method according to any of the claims 1-14, wherein during the measurement period the first pairs of bits of the control word (z[n]) is generated only from the first pair of bits of the encoded word (q[n]) .

16. The method according to any of the claims 1-15, wherein detecting (902) the error signal comprises mixing the output signal.

17. A Digital-to-Analog-Converter, DAC, (25), comprising:an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample; a digital control circuit (110) configured to encode each digital input word (%[n]) into an encoded word (q[n]), each bit (Q;) of the encoded word (q[n]) having a corresponding bit weight (wi), wherein the digital control circuit (110) is further configured to encode each encoded word (q[n]) to a control word (z[n]), representing the same digital input sample, by mapping the bits (Q;) of the encoded word (q[n]) to bits (Z;) of the control word (z[n]), each bit (z of the control word (z[n]) having the same bit weight (w;) as the corresponding bit (q^) of the encoded word (q[n]); a set of clocked buffers (D1-D7) comprising a first pair of clocked buffers (D1, D7) and configured to sample the bits of the control word (z;) at a common sampling frequency; a set (120) of analog weights, each weight associated with a unique one of the bits (Z;) in the control word (z[n]) and proportional to the corresponding bit weight (wi) for a respective sample of the unique one of the bits of the control word (zf); summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the sampled bits of the control word (Z;) weighted by the respective associated analog weights; and an output (140) for outputting the analog sample; wherein the digital control circuit (110), is configured to: repeatedly generate, during a measurement period, for the first pair of clocked buffers (D1 , D7) and corresponding first pair of analog weights, a first pair of bits of the control word (z[n]) by being configured to periodically swap a pair of mappings of bits of a first pair of bits of the encoded word (q[n]) having the same bit weight (nq) to the pair of bits of the control word (z[n]) such that an error signal proportional to a timing error between a first clocked buffer (D1) and a second clocked buffer (D7) of the first pair of clocked buffers (D1, D7) is generated at the output (140) during the measurement period corresponding to multiple swapping periods; and wherein the DAC (25) further comprises an error detection circuit (150) configured to detect the error signal at the output (140).

18. The DAC (25) according to claim 15 or 16, wherein the DAC (25) is further configured to perform the method of any of the claims 2-16.

19. The DAC (25) according to claim 17 or 18, further comprising a calibration circuit (160) configured to: adjust a sampling time of at least a first clocked buffer (D1) of the first pair of clocked buffers (D1, D7) based on the detected error signal.

20. The DAC (25) according to claim 19, wherein the calibration circuit (160) is arranged within the at least first clocked buffer (D1).

21. An electronic apparatus (1 , 2) comprising the DAC (25) according to any one of the claims 17 - 19.

22. The electronic apparatus (1 , 2) of claim 21 , wherein the electronic apparatus is a communication apparatus.

23. The electronic apparatus (1) of claim 22, wherein the communication apparatus is a wireless communications device (1) for a wireless communications network.

24. The electronic apparatus (2) of claim 22, wherein the communication apparatus is a base station (2) for a wireless communications network.

25. An integrated circuit (500), such as a transceiver circuit (10), comprising the DAC (25) according to any one of the claims 17-20.

26. A computer program (1403, 1503), comprising computer readable code units which when executed on a processor of an electronic apparatus (1 , 2) according any one of claims 21-24, causes the electronic apparatus (1 , 2) to perform the method according to any one of claims 1-16.

27. A carrier (1405, 1505) comprising the computer program according to the preceding claim, wherein the carrier (1405, 1505) is one of an electronic signal, an optical signal, a radio signal and a computer readable medium.

Images