Digital-to-analog converter and its purely digital domain calibration method
By employing a segmented digital-to-analog converter architecture and a pure digital domain calibration method, and adjusting unit device parameters and calibration coefficients, the process mismatch and packaging drift issues of high-precision DACs are resolved, resulting in improved accuracy and linearity. This approach is applicable to resistor, capacitor, and current source DACs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU CORPRO TECH CO LTD
- Filing Date
- 2026-04-07
- Publication Date
- 2026-06-23
AI Technical Summary
Under high-precision requirements, existing digital-to-analog converters (DACs) are affected by process fluctuations, making it difficult to ensure device matching accuracy through analog circuit layout design. Traditional adjustment methods are costly and cannot eliminate parameter drift during the packaging process. Digital calibration algorithms are complex, resulting in insufficient DAC accuracy and linearity.
A segmented digital-to-analog converter architecture is adopted. Redundancy is introduced by adjusting the physical parameters of the unit device. Combined with a pure digital domain calibration algorithm, the calibration coefficient register and decoder split the digital input code value, measure and calculate the calibration coefficient, so as to add redundancy without increasing circuit complexity.
It improves the accuracy and linearity of DACs, effectively eliminates the effects of process mismatch and packaging stress, is suitable for resistor, capacitor and current source DACs, simplifies hardware requirements and reduces costs.
Smart Images
Figure CN122026909B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of mixed-signal integrated circuit technology, and more specifically, relates to digital-to-analog converters and their pure digital domain calibration methods. Background Technology
[0002] In modern electronic systems, digital-to-analog converters (DACs) are crucial interface circuits connecting the digital and analog worlds, widely used in wireless communication, medical imaging, precision instruments, audio processing, and industrial control. With the continuous miniaturization of semiconductor manufacturing processes and the rapid improvement of digital signal processing capabilities, systems are placing increasingly stringent demands on DAC performance indicators, particularly resolution, accuracy, linearity, and conversion speed.
[0003] Ideally, the output voltage of a DAC should increase in a perfectly linear, stepwise manner as the input digital code increases. However, in actual integrated circuit manufacturing, due to random process fluctuations such as photolithography precision, etching rate, doping concentration gradient, and oxide layer thickness variations, the analog devices constituting the core array of the DAC (such as resistors, capacitors, and current source transistors) inevitably suffer from parameter mismatch. This causes the DAC's transfer function to deviate from the ideal straight line, resulting in integral and differential nonlinear errors.
[0004] When a DAC resolution of 14 bits or higher is required, relying solely on matching techniques in analog circuit layout design (such as common centroid placement and virtual device addition) is insufficient to guarantee that the inherent matching accuracy of the devices meets the design requirements. For example, under standard CMOS processes, the unadjusted device matching accuracy typically only supports about 10 to 12 bits of linearity. To achieve higher accuracy, adjustment or calibration methods are usually employed.
[0005] Traditional laser trimming is commonly used in resistive DACs, adjusting the resistance value by physically changing the geometry of the resistive material. However, trimming methods have significant drawbacks: firstly, they are costly, increasing testing time and equipment investment; secondly, trimming is usually performed during the wafer testing stage, which cannot eliminate parameter drift introduced by mechanical stress during subsequent packaging, thus limiting its accuracy to around 16 bits.
[0006] Digital calibration corrects the nonlinearity of the main DAC by compensating for parameter mismatch in the digital domain. For the digital calibration algorithm to work effectively, especially for calibrating large transition errors caused by high-bit switching, the DAC architecture must have redundancy capabilities. This ensures that the DAC's transfer function covers the entire output range without gaps, meaning that the analog output of the DAC has overlapping coverage between adjacent input code values. Existing methods for adding DAC redundancy typically employ non-binary weights, splitting binary weights, and inserting additional redundant bits. While effective, these methods often lead to extremely complex digital logic and increase the number of control lines in the analog array and the chip area.
[0007] Therefore, there is an urgent need for a solution that can effectively provide the redundancy required for calibration without significantly increasing circuit complexity and chip area, as well as an efficient pure digital domain calibration algorithm that works well with this architecture. Summary of the Invention
[0008] To address the aforementioned technical problems, this invention provides a digital-to-analog converter and a pure digital domain calibration method thereof.
[0009] In a first aspect, the present invention provides a digital-to-analog converter, comprising:
[0010] The calibration coefficient register is used to store calibration coefficients;
[0011] The decoder receives the binary code value of the digital input and splits the binary code value into a thermometer code value, a first binary code value, and a second binary code value according to the calibration coefficient in the calibration coefficient register.
[0012] A digital-to-analog converter array, coupled to a decoder, is used to generate an analog output voltage based on the thermometer code value, a first binary code value, and a second binary code value.
[0013] The digital-to-analog converter array adopts a segmented architecture, including:
[0014] The first segment of the thermometer code DAC array includes a first type of unit device, which generates a first output component under the control of the thermometer code value;
[0015] The second binary code DAC array includes a first type of unit device, which generates a second output component under the control of the first binary code value;
[0016] The third binary code DAC array, including the second type of unit device, generates the third output component under the control of the second binary code value;
[0017] By adjusting the physical parameters of the first type of unit device or the second type of unit device, the sum of the total weights of the third binary code DAC array is made greater than the weight of the least significant bit of the second binary code DAC array. The third binary code DAC array provides redundancy for the least significant bit of the second binary code DAC array and the first thermometer code DAC array.
[0018] Secondly, the present invention provides a pure digital domain calibration method based on a digital-to-analog converter, comprising:
[0019] The calibration coefficient register enters calibration mode, and the control signal skips the decoder and directly controls the bit switching switch of the digital-to-analog converter;
[0020] Determine the calibration start position;
[0021] Measure the reference state output voltage: Set all bit switches to the reference potential and measure the first output voltage of the digital-to-analog converter at this time;
[0022] Measure the actual weight bit by bit: switch the bit switching switch corresponding to the bit to be calibrated from the reference potential to the positive reference potential, and measure the second output voltage after stabilization;
[0023] Calculate and store calibration coefficients: Calculate the actual weight of the bit to be calibrated based on the difference between the second output voltage and the first output voltage, calculate the calibration coefficients based on the actual weights, and store them in the calibration coefficient register.
[0024] Based on the above technical solution, the present invention can be further improved as follows.
[0025] Furthermore, the physical parameters of the first type of unit device are adjusted by increasing the resistance, decreasing the capacitance, or decreasing the current source; the physical parameters of the second type of unit device are adjusted by decreasing the resistance, increasing the capacitance, or increasing the current source.
[0026] Furthermore, the digital-to-analog converter is a resistive digital-to-analog converter; the first type of unit device is a resistor with a first resistance value; the second type of unit device is a resistor with a second resistance value; the first resistance value is greater than the second resistance value, so that the sum of the voltage weights generated by the third binary code DAC array is greater than the least significant bit weight of the second binary code DAC array.
[0027] Furthermore, the first type of unit device is a capacitor with a first capacitance value; the second type of unit device is a capacitor with a second capacitance value; the first capacitance value and the second capacitance value are not equal, and the first type of unit device and the second type of unit device are configured such that the total capacitance weight coverage of the third segment binary code DAC array exceeds one least effective bit step of the second segment binary code DAC array.
[0028] Furthermore, the digital-to-analog converter is a current-source type digital-to-analog converter; the first type unit device is the current source of the first output current; the second type unit device is the current source of the second output current; the first output current and the second output current are not equal; the first type unit device and the second type unit device are configured such that the total current output range of the first segment thermometer code DAC array is greater than the least significant bit current step of the second segment binary code DAC array.
[0029] Furthermore, the decoder re-encodes the binary code value of the digital input based on the calibration coefficients stored in the calibration coefficient register.
[0030] Furthermore, the measurement process for the same calibrated position is repeated a set number of times, and the average of the differences between the second output voltage and the first output voltage obtained from all measurements is calculated as the actual weight of the calibrated position.
[0031] Furthermore, the calibration coefficient is calculated based on the actual weights, including: assuming the calibration coefficient is... , For calibration, the first Position weight For the ideal first Position weight are positive integers and , Let the number of bit weights in the digital-to-analog converter be:
[0032] .
[0033] The beneficial effects of this invention are as follows: Compared to traditional non-binary architectures, this invention does not require changes to the basic connection topology of the DAC, nor does it require complex hardware multipliers or dividers for radix conversion, resulting in good accuracy and linearity for the digital-to-analog converter. Redundancy is introduced simply by adjusting the size of the unit device, without adding additional DAC branches, thus improving the overall weight of the DAC and providing redundancy. This redundancy addition method, combined with a pure digital domain calibration algorithm, can effectively improve the accuracy and linearity of the DAC. The pure digital domain calibration method used in this invention can effectively eliminate the effects of process mismatch and packaging stress. This method is applicable to resistor, capacitor, and current source DACs, and has wide applicability. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of the digital-to-analog converter provided in Embodiment 1 of the present invention;
[0035] Figure 2 This is a circuit diagram of a resistive DAC array;
[0036] Figure 3 This is a circuit diagram of a capacitor-type DAC array;
[0037] Figure 4 This is a circuit diagram of a current-source DAC array;
[0038] Figure 5 This is a schematic diagram of the pure digital domain calibration method based on a digital-to-analog converter provided in Embodiment 2 of the present invention;
[0039] Figure 6 This is a flowchart illustrating the pure digital domain calibration algorithm of the present invention. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0041] Example 1
[0042] As an example, see the attached document. Figure 1 As shown, to solve the above-mentioned technical problems, this embodiment provides a digital-to-analog converter, including:
[0043] The calibration coefficient register is used to store calibration coefficients;
[0044] The decoder receives the binary code value of the digital input and, based on the calibration coefficients in the calibration coefficient register, splits the binary code value into a thermometer code value, a first binary code value, and a second binary code value. It receives an N-bit binary code value as digital input and, based on the KCal bit calibration weighting coefficients, splits the N-bit binary code value into an H-bit thermometer code value, an M-bit, and an L-bit binary code value. Typically, because the resolution of the DAC architecture is greater than the target resolution of the final output to achieve better DAC output performance, the resolution of the decoded code value is greater than the resolution of the input code value.
[0045] A digital-to-analog converter array, coupled to a decoder, is used to generate an analog output voltage based on the thermometer code value, a first binary code value, and a second binary code value.
[0046] The digital-to-analog converter array adopts a segmented architecture, including:
[0047] The first segment of the thermometer code DAC array includes a first type of unit device, which generates a first output component under the control of the thermometer code value;
[0048] The second binary code DAC array includes a first type of unit device, which generates a second output component under the control of the first binary code value;
[0049] The third binary code DAC array, including the second type of unit device, generates the third output component under the control of the second binary code value; the third binary code DAC array, under the control of the L-bit binary code, divides the reference voltages VREFP and VREFN to generate a voltage to supply to the second binary code DAC array; the second binary code DAC array, under the control of the M-bit binary code, divides VREFP, VREFN, and VML to fine-tune the output voltage VOUT; the first thermometer code DAC array, under the control of the H-bit thermometer code, divides the reference voltages VREFP and VREFN to coarsely adjust the output voltage VOUT.
[0050] By adjusting the physical parameters of the first type of unit device or the second type of unit device, the sum of the total weights of the third binary code DAC array is made greater than the weight of the least significant bit of the second binary code DAC array. The third binary code DAC array provides redundancy for the least significant bit of the second binary code DAC array and the first thermometer code DAC array.
[0051] This invention breaks the strict binary ratio by fine-tuning the unit components of the DAC at the physical level, thereby introducing redundancy without increasing additional circuit nodes and complexity. Combined with a pure digital domain calibration algorithm, it effectively corrects process errors and improves the effective number of bits and linearity of the DAC.
[0052] The full-scale range of the third binary code DAC array exceeds the minimum step size of the second binary code DAC array, thus creating redundancy in both the second binary code DAC array and the first thermometer code DAC array. This redundancy can be achieved simply by fine-tuning the layout size without adding additional DAC channels; meanwhile, the first thermometer code DAC array inherently possesses monotonicity and redundancy characteristics due to the use of thermometer code itself.
[0053] Compared to traditional non-binary architectures, this invention does not require changes to the basic connection topology of the DAC, nor does it require complex hardware multipliers or dividers for radix conversion; the redundancy is introduced only by adjusting the size of the third-segment binary code DAC array device, without adding additional DAC branches.
[0054] As an optional implementation, the physical parameters of the first type of unit device are adjusted by increasing the resistance, decreasing the capacitance, or decreasing the current source; the physical parameters of the second type of unit device are adjusted by decreasing the resistance, increasing the capacitance, or increasing the current source.
[0055] Typically, DAC arrays use only one type of unit component (resistor, capacitor, or current source). To better match performance and facilitate layout, the DAC array in this invention consists of two types of unit components. The first segment of the thermometer code DAC array and the second segment of the binary code DAC array use the same unit components. The unit components used in the third segment of the binary code DAC array are artificially adjusted based on the unit components of the first segment of the thermometer code DAC array. This adjustment can be achieved by simply changing the length, width, and number of components without increasing the complexity of the circuit and layout routing. By changing the unit components used in the third segment of the binary code DAC array, the overall weight of the third segment of the binary code DAC array can be improved. After the modification, the weight of the third segment of the binary code DAC array is still a binary weight, but the sum of the weights of the third segment of the binary code DAC array is greater than the least significant bit weight of the second segment of the binary code DAC, providing redundancy for the least significant bit of the second segment of the binary code DAC array and the first segment of the thermometer code DAC array. The inherent redundancy characteristics of the thermometer code provide redundancy from the most significant bit to the second least significant bit of the first segment of the thermometer code DAC array.
[0056] As an optional implementation, the digital-to-analog converter is a resistive digital-to-analog converter; the first type of unit device is a resistor with a first resistance value; the second type of unit device is a resistor with a second resistance value; the first resistance value is greater than the second resistance value, so that the sum of the voltage weights generated by the third binary code DAC array is greater than the least significant bit weight of the second binary code DAC array.
[0057] In a resistive DAC (such as an R-2R architecture or a voltage divider series architecture), the first segment of the thermometer code array consists of H unit resistors connected in series or parallel. The second segment of the binary code DAC array consists of a standard R-2R network, with the unit resistor set to R1. The third segment of the binary code DAC array also uses an R-2R structure, with the unit resistor set to R0, and R0 is set to be less than R1.
[0058] In a voltage-mode R-2R ladder network, reducing the resistance at the end of the ladder network increases the proportion of current flowing through that section, or increases the voltage contribution weight at the voltage divider node. Specifically, by reducing R0, the maximum voltage change that the third binary code segment can generate is greater than the voltage value corresponding to the least significant bit of the second binary code DAC array.
[0059] The degree to which R0 is smaller than R1 depends on the magnitude of the process resistor mismatch. Its value must be chosen such that the redundancy covers the worst-case process mismatch, ensuring continuous output voltage across any input code and thus avoiding gaps in the DAC transfer function. (See attached image) Figure 2The schematic diagram of the resistive DAC array circuit shown shows that R0 is less than R1, which can provide redundancy for the first segment of the thermometer code DAC array and the second segment of the binary code DAC array. The use of binary encoding saves space, while the thermometer encoding can ensure monotonicity and provide redundancy.
[0060] As an optional implementation, the first type of unit device is a capacitor with a first capacitance value; the second type of unit device is a capacitor with a second capacitance value; the first capacitance value and the second capacitance value are not equal, and the first type of unit device and the second type of unit device are configured such that the total capacitance weight coverage of the third segment binary code DAC array exceeds one least significant bit step of the second segment binary code DAC array.
[0061] In a capacitive DAC, the first segment of the thermometer code DAC array consists of H unit capacitors, where each unit capacitor is [value missing]. C1, connected in parallel The second binary code DAC array consists of M capacitors, with a unit capacitance of [missing information]. C1, connected in parallel The third binary code DAC array consists of L capacitors, with a unit capacitance of C0. (See attached image.) Figure 3 The circuit diagram of the capacitor-type DAC array shown is similar to... Figure 2 Similarly, the resistive DAC array shown is designed so that C0 is greater than C1 to provide redundancy. This design makes the total capacitance of the third capacitor array exceed the capacitance value corresponding to the smallest capacitor bit of the second binary code DAC array, providing redundancy for the second binary code DAC array and the first thermometer code DAC array. This redundancy is used to correct the gaps caused by the increased capacitance of the capacitors in the second binary code DAC array and the first thermometer code DAC array due to process deviations.
[0062] As an optional implementation, the digital-to-analog converter is a current-source type digital-to-analog converter; the first type unit device is the current source of the first output current; the second type unit device is the current source of the second output current; the first output current and the second output current are not equal; the first type unit device and the second type unit device are configured such that the total current output range of the third binary code DAC array is greater than the least significant bit current step of the second binary code DAC array.
[0063] As attached Figure 4 The circuit diagram shown is of a current source DAC array. The first segment of the thermometer code DAC array consists of... It consists of several unit current sources, and each unit current source is... Through parallel indivual To achieve this; the second binary code DAC array is composed of It consists of several current sources, with each current source being [number]. Through parallel indivual To achieve this; the third binary code DAC array is composed of It consists of several current sources, with each current source being [number]. .and Figure 2 Similarly, the resistive DAC array shown is artificially made to have a unit current source. Value greater than To provide redundancy.
[0064] As an alternative implementation, the decoder re-encodes the binary code value of the digital input based on the calibration coefficients stored in the calibration coefficient register to compensate for nonlinearity caused by process errors.
[0065] Example 2
[0066] Based on the same principle as the method shown in Embodiment 1 of the present invention, as illustrated in the appendix. Figure 5 As shown, embodiments of the present invention also provide a pure digital domain calibration method based on a digital-to-analog converter, including:
[0067] Determine the calibration start position;
[0068] The calibration coefficient register enters calibration mode, and the control signal skips the decoder and directly controls the bit switching switch of the digital-to-analog converter;
[0069] Measure the reference state output voltage: Set all bit switches to the reference potential and measure the first output voltage of the digital-to-analog converter at this time;
[0070] Measure the actual weight bit by bit: switch the bit switching switch corresponding to the bit to be calibrated from the reference potential to the positive reference potential, and measure the second output voltage after stabilization;
[0071] Calculate and store calibration coefficients: Calculate the actual weight to be calibrated based on the difference between the second output voltage and the first output voltage, calculate the calibration coefficients based on the actual weights, and store them in the calibration coefficient register.
[0072] The pure digital domain calibration method used in this invention can effectively eliminate the effects of process mismatch and packaging stress. This method is applicable to resistor, capacitor and current source DACs and has wide applicability.
[0073] As an optional implementation, the calibration coefficient is calculated based on the actual weights, including: setting the calibration coefficient as... , For calibration, the first Position weight For the ideal first Position weight are positive integers and , Let the number of bit weights in the digital-to-analog converter be:
[0074] .
[0075] Taking a resistive DAC array as an example, such as Figure 6 The flowchart below shows the pure digital domain calibration algorithm of this invention. The detailed calibration steps are as follows:
[0076] (1) Determine the calibration start position: Since the nonlinear error caused by the low-weight mismatch is very small and has little impact on accuracy, the low-weight (assuming the low-weight is from the 1st to the 2nd) should be determined. (The first bit) generally does not require calibration; calibration can begin from the second bit. Starting with bit weights It is a positive integer;
[0077] (2) Initialize the calibration count, set the iteration count, and measure the actual weight: In calibration mode, the input can skip the decoder and directly control the DAC bit switching switch, connecting the potential switching switches of all resistors to the reference potential. After the output stabilizes, measure the output voltage of the DAC at this time and record it as . Subsequently, the lower plate of the bit switching switch for the calibrated bit resistor switches from the reference potential to the positive reference potential, while the other bit switching switches remain unchanged. After the output stabilizes, the DAC output voltage will change due to the switching of the calibrated bit. , Indicates the first The weight of the bit;
[0078] (3) Let For the number of calibrations, One calibrated bit The weight is Repeat step (2). Next, get One calibrated bit The weight is set to , ,average This is to eliminate the influence of noise, let:
[0079] ;
[0080] (4) Repeat steps (2) and (3) until all bits to be calibrated are calibrated;
[0081] (5) Assume the ideal position weight is Based on the bit weights obtained from calibration Calculate calibration coefficients ,in:
[0082] ; ;
[0083] ;
[0084] ;
[0085] (6) Store the calibration coefficients in the calibration coefficient register to compensate for the mismatch caused by process error.
[0086] Optionally, the measurement process for the same calibrated bit can be repeated a set number of times, and the average of the differences between the second output voltage and the first output voltage obtained from all measurements can be calculated as the actual weight of the calibrated bit.
[0087] By using a multiple averaging algorithm, the noise variance was reduced. This significantly improves the accuracy of the calibration coefficients.
[0088] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A digital-to-analog converter, characterized in that, include: The calibration coefficient register is used to store calibration coefficients; The decoder receives the binary code value of the digital input and splits the binary code value into a thermometer code value, a first binary code value, and a second binary code value according to the calibration coefficient in the calibration coefficient register. A digital-to-analog converter array, coupled to a decoder, is used to generate an analog output voltage based on the thermometer code value, a first binary code value, and a second binary code value. The digital-to-analog converter array adopts a segmented architecture, including: The first segment of the thermometer code DAC array includes a first type of unit device, which generates a first output component under the control of the thermometer code value; The second binary code DAC array includes a first type of unit device, which generates a second output component under the control of the first binary code value; The third binary code DAC array, including the second type of unit device, generates the third output component under the control of the second binary code value; By adjusting the physical parameters of the first type of unit device or the second type of unit device, the sum of the total weights of the third binary code DAC array is made greater than the weight of the least significant bit of the second binary code DAC array. The third binary code DAC array provides redundancy for the least significant bit of the second binary code DAC array and the first thermometer code DAC array.
2. The digital-to-analog converter according to claim 1, characterized in that, The physical parameters of the first type of unit device are adjusted by increasing the resistance, decreasing the capacitance, or decreasing the current source; the physical parameters of the second type of unit device are adjusted by decreasing the resistance, increasing the capacitance, or increasing the current source.
3. The digital-to-analog converter according to claim 1, characterized in that, The digital-to-analog converter is a resistive digital-to-analog converter; the first type of unit device is a resistor with a first resistance value; the second type of unit device is a resistor with a second resistance value; the first resistance value is greater than the second resistance value, so that the sum of the voltage weights generated by the third binary code DAC array is greater than the least significant bit weight of the second binary code DAC array.
4. The digital-to-analog converter according to claim 1, characterized in that, The digital-to-analog converter is a capacitive digital-to-analog converter; The first type of unit device is a capacitor with a first capacitance value; the second type of unit device is a capacitor with a second capacitance value; the first capacitance value and the second capacitance value are not equal, and the first type of unit device and the second type of unit device are configured such that the total capacitance weight coverage of the third segment binary code DAC array exceeds one least significant bit step of the second segment binary code DAC array.
5. The digital-to-analog converter according to claim 1, characterized in that, The digital-to-analog converter is a current-source type. The first type of unit device is a current source for the first output current; the second type of unit device is a current source for the second output current; the first output current and the second output current are not equal; The first type of unit device and the second type of unit device are configured such that the total current output range of the third binary code DAC array is greater than the least significant bit current step of the second binary code DAC array.
6. The digital-to-analog converter according to claim 1, characterized in that, The decoder re-encodes the binary code value of the digital input based on the calibration coefficients stored in the calibration coefficient register.
7. A pure digital domain calibration method based on the digital-to-analog converter according to any one of claims 1-6, characterized in that, include: The calibration coefficient register enters calibration mode, and the control signal skips the decoder and directly controls the bit switching switch of the digital-to-analog converter; Determine the calibration start position; Measure the reference state output voltage: Set all bit switches to the reference potential and measure the first output voltage of the digital-to-analog converter at this time; Measure the actual weight bit by bit: switch the bit switching switch corresponding to the bit to be calibrated from the reference potential to the positive reference potential, and measure the second output voltage after stabilization; Calculate and store calibration coefficients: Calculate the actual weight to be calibrated based on the difference between the second output voltage and the first output voltage, calculate the calibration coefficients based on the actual weights, and store them in the calibration coefficient register.
8. The pure digital domain calibration method for the digital-to-analog converter based on claim 7, characterized in that, The measurement process for the same calibrated position is repeated a set number of times, and the average of the differences between the second output voltage and the first output voltage obtained from all measurements is calculated as the actual weight of the calibrated position.
9. The pure digital domain calibration method for the digital-to-analog converter based on claim 7, characterized in that, The calibration coefficient is calculated based on the actual weights, including: assuming the calibration coefficient is... , For calibration, the first Position weight For the ideal first Position weight are positive integers and , Let the number of bit weights in the digital-to-analog converter be: 。