Directional deposition of inhibiting layer for area selective deposition

Abstract

Directional deposition methods for depositing an inhibiting film on a patterned structure are described. A patterned structure on a substrate is simultaneously exposed to a precursor and a plasma at an angle in a range of from 0° to 60°. The patterned structure includes a top surface and at least one opening having at least one sidewall surface and a bottom surface, to form the inhibiting layer on the top surface and the bottom surface. A metal layer may then be selectively formed on the sidewall surface of the patterned structure.

Description

Docket No. 44024680W001 PATENTDIRECTIONAL DEPOSITION OF INHIBITING LAYER FOR AREA SELECTIVE DEPOSITIONTECHNICAL FIELD

[0001] Embodiments of the disclosure pertain to the field of semiconductor devices and semiconductor device manufacturing. More particularly, embodiments of the disclosure are directed to methods to control the selective deposition of a metal film on a patterned structure.BACKGROUND

[0002] Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. There are two major types of random-access memory cells, dynamic and static, which are well-suited for use in electronic devices. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values but require periodic reprogramming or "refreshing" to maintain this voltage for more than very short periods of time. Static random-access memories (SRAM) are so named because they do not require periodic refreshing.

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004] The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cellDocket No. 44024680W001 PATENT2 capacitor, and the compatibility of array devices with non-array devices.

[0005] To maintain the cadence of device miniaturization, selective deposition has shown promise, as it has the potential to remove costly lithographic steps and simplify integration schemes. Area selective deposition (ASD) offers the potential to simplify process schemes by depositing a thermal ALD film on a selected area without a lithographic step. This involves exploiting different surface reactivities from a prepatterned structure composed of different materials or through the inhibition of a surface through the use of inhibitor chemistry. On non-planar patterned structures, ASD has been used to deposit a film selectively on side walls or on the top and bottom of a trench. The ability to control where a film is selectively deposited on the side wall of a patterned structure, however, is needed. There is an ongoing need in the art, therefore, for methods to improve deposition selectivity and to avoid the problems encountered during ASD.SUMMARY

[0006] One or more embodiments of the disclosure are directed to methods of forming a film on a semiconductor device. In some embodiments, the method comprises: forming an inhibiting layer on a patterned structure on a substrate by a directional deposition process, the patterned structure including a top surface and at least one opening having at least one sidewall surface and a bottom surface; and selectively forming the film on the at least one sidewall surface of the patterned structure, the film comprising a metal layer or a dielectric layer.

[0007] Another aspect of the disclosure is directed to methods of forming an inhibiting layer on a semiconductor structure. In one or more embodiments, the method comprises: simultaneously exposing a patterned structure on a substrate to a precursor and a plasma at an angle in a range of from 0° to 60°, the patterned structure including a top surface and at least one opening having at least one sidewall surface and a bottom surface, to form the inhibiting layer on the top surface and the bottom surface.BRIEF DESCRIPTION OF THE DRAWINGSDocket No. 44024680W001 PATENT

[0008] So that the manner in which the above recited features of the disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0009] FIG. 1 illustrates a process flow diagram of a method in accordance with one or more embodiments of the disclosure;

[0010] FIG. 2A is a cross-section view of a device according to one or more embodiments;

[0011] FIG. 2B is a cross-section view of a device according to one or more embodiments;

[0012] FIG. 2C is a cross-section view of a device according to one or more embodiments;

[0013] FIG. 2D is a cross-section view of a device according to one or more embodiments;

[0014] FIG. 2E is a cross-section view of a device according to one or more embodiments;

[0015] FIG. 3A is a cross-section view of a device according to one or more embodiments;

[0016] FIG. 3B is a cross-section view of a device according to one or more embodiments;

[0017] FIG. 3C is a cross-section view of a device according to one or more embodiments;

[0018] FIG. 3D is a cross-section view of a device according to one or more embodiments;

[0019] FIG. 3E is a cross-section view of a device according to one or more embodiments;

[0020] FIG. 3F is a cross-section view of a device according to one or more embodiments;

[0021] FIG. 3G is a cross-section view of a device according to one or moreDocket No. 44024680W001 PATENT embodiments;

[0022] FIG. 4 illustrates a cluster tool according to one or more embodiments; and

[0023] FIG. 5 illustrates a deposition system according to one or more embodiments.

[0024] Example embodiments are described herein with reference to cross- sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing.DETAILED DESCRIPTION

[0025] Before describing several exemplary embodiments of the invention, it is to be understood that the invention is not limited to the details of construction or process steps set forth in the following description. The invention is capable of other embodiments and of being practiced or being carried out in various ways.

[0026] As used in this specification and the appended claims, the term "substrate" refers to a surface, or portion of a surface, upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can also refer to only a portion of the substrate unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0027] A "substrate" as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, silicon carbide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize,Docket No. 44024680W001 PATENT hydroxylate, anneal, UV cure, e-beam cure and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates.

[0028] According to one or more embodiments, the term "on", with respect to a film or a layer of a film, includes the film or layer being directly on a surface, for example, a substrate surface, as well as there being one or more underlayers between the film or layer and the surface, for example the substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlayers. In other embodiments, the phrase "directly on" refers to a layer or a film that is in contact with a surface, for example, a substrate surface, with no intervening layers. Thus, the phrase "a layer directly on the substrate surface" refers to a layer in direct contact with the substrate surface with no layers in between.

[0029] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas" and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0030] "Atomic layer deposition" or "cyclical deposition" as used herein refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or portion of the substrate, is exposed separately to the two or more reactive compounds which are introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. It is noted, as recognized by one of skill in the art, that excess unreacted atoms / molecules of the reactive compound are purged and what has reacted or adhered to the substrate remains reacted / adhered. These reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface, or material on the substrate surface, are exposed simultaneously to the two or more reactive compounds so that any given point on the substrate is substantially not exposed to more than one reactive compound simultaneously. As used in this specification and the appended claims, the termDocket No. 44024680W001 PATENT6"substantially" used in this respect means, as will be understood by those skilled in the art, that there is the possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and that the simultaneous exposure is unintended.

[0031] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidant) is pulsed into the reaction zone followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compound or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process so that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive compounds are alternatively pulsed until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B and purge gas is a cycle. A cycle can start with either compound A or compound B and continue the respective order of the cycle until achieving a film with the predetermined thickness.

[0032] In an embodiment of a spatial ALD process, a first reactive gas and second reactive gas (e.g., nitrogen gas) are delivered simultaneously to the reaction zone but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first reactive gas and then subsequently to the second reactive gas.

[0033] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or where there is overlap for a majority of exposures of the precursors.

[0034] As used herein throughout the specification, "substantially simultaneously" means that most of the duration of the first reactive compound exposure overlaps with the second reactive compound exposure.

[0035] As used herein, the term "purging" includes any suitable purge process that removes unreacted precursor, reaction products and by-products from the processDocket No. 44024680W001 PATENT region. One suitable purge process includes moving the substrate through a gas curtain to a portion or sector of the processing region that contains none or substantially none of the reactant. In one or more embodiments, purging the processing chamber comprises applying a vacuum. In some embodiments, purging the processing region comprises flowing a purge gas over the substrate. In some embodiments, the purge process comprises flowing an inert gas over the substrate. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, the purging the substrate surface or the reaction chamber may occur for a time duration in a range of from 0.2 seconds to 30 seconds, from 0.2 seconds to 10 seconds, from 0.2 seconds to 5 seconds, from 0.5 seconds to 30 seconds, from 0.5 seconds to 10 seconds, from 0.5 seconds to 5 seconds, from 1 seconds to 30 seconds, from 1 seconds to 10 seconds, from 1 seconds to 5 seconds, from 5 seconds to 30 seconds, from 5 seconds to 10 seconds or from 10 seconds to 30 seconds.

[0036] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a datum bit by storing a packet of charge (i.e., a binary one), or no charge (i.e., a binary zero) on a capacitor. The charge is gated onto the capacitor via an access transistor and sensed by turning on the same transistor and measuring the voltage perturbation created by dumping the charge packet on the interconnect line on the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. The DRAM device is formed of an array of DRAM cells. The rows on access transistors are linked by word lines, and the transistor inputs / outputs are linked by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-substrate plate capacitors to 3D structures which have diverged into "stack" capacitors with both plates above the substrate, and "trench" capacitors using an etched cavity in the substrate as the common plate.

[0037] Traditionally, DRAM cells have recessed high work-function metal structures in buried word line structures. In a DRAM device, a bit line is formed in a metal level situated above the substrate, while the word line is formed at the polysilicon gate level at the surface of the substrate. In a buried word line (bWL) device, a word line is buried below the surface of a semiconductor substrate using a metal as a gate electrode.Docket No. 44024680W001 PATENT8

[0038] Unlike the traditional 2D DRAM, which only uses the horizontal plane, 4F2DRAM, or 3D DRAM, is a cell array structure where transistors are stacked vertically. In the 4F2DRAM structure, various device parts, including the source, gate, drain, and capacitor are stacked from bottom to top. The word line connects to the gate, and the bit line connects to the source. Memory cell sizes are measured using an nF2formula where 'n' is a constant derived from the cell design and 'F' is the feature size of the process technology. Thus, for example, in a 130 nm process node, F = 0.13 micron, and therefore 4F2= 4 x 0.13 x 013 = 0.0676 square micron. For the same feature size, as the cell size becomes smaller, memory capacity increases.

[0039] The selection of what metal is used as a gate can greatly impact the performance of the device. Deposition of metal layers on trench sidewalls for 4F2DRAM memory devices require complex process schemes. Existing process flows to deposit metal on the dielectric fin require multiple steps including conformal depositions and etch backs. There are additional challenges in multistep processing in removing deposition at the base of the trench. In one or more embodiments, area selective deposition (ASD) can advantageously simplify process schemes by reducing / removing process steps, replacing them with a self-aligned method of depositing a material. In one or more embodiments, a 4F2DRAM device would benefit from an ASD method with the requirement to be able to inhibit deposition on the top of high aspect ratio features and the bottom of the trench.

[0040] In one or more embodiments, an inhibiting layer is deposited by directional plasma enhanced chemical vapor deposition (PECVD) on a patterned structure. Area selective deposition (ASD) of a metal film on a sidewall surface of the patterned structure is then performed. In some embodiments, an isotropic etch is used to remove any excess inhibiting layer prior to the area selective deposition.

[0041] As used in this specification and the appended claims, the phrase "selectively over," or similar phrases, means that the subject material is deposited on the stated surface to a greater extent than on another surface. In some embodiments, "selectively" means that the subject material forms on the selective surface at a rate greater than or equal to about 10x, 15x, 20x, 25x, 30x, 35x, 40x, 45x or 50x the rate of formation on the non-selected surface. Accordingly, in one or more embodiments, a selectively deposited layer forms selectively on the sidewall surface of the patternedDocket No. 44024680W001 PATENT9 structure at a rate greater than or equal to about 10x, 15x, 20x, 25x, 30x, 35x, 40x, 45x or 50x the rate of formation on the non-selected surface (i.e. , the top surface or the bottom surface).

[0042] In one or more embodiments, the metal film is deposited using a metal precursor and a reactant pulsed to form the metal film. The number of cycles is ideally one but can be in a range of from 1 to 10 cycles or from 2 to 5 cycles or from 2 to 100 cycles.

[0043] The embodiments of the disclosure are described by way of the Figures, which illustrate devices (e.g., 4F2DRAM) and processes for forming semiconductor structures in accordance with one or more embodiments of the disclosure. The processes shown are merely illustrative possible uses for the disclosed processes, and the skilled artisan will recognize that the disclosed processes are not limited to the illustrated applications.

[0044] FIG. 1 illustrates a process flow diagram of a method according to one or more embodiments of the present disclosure. FIGS. 2A through 2E are cross- sectional views illustrating a device 100 in various stages of processing according to one or more embodiments. FIGS. 3A through 3G are cross-sectional views illustrating a device 100 in various stages of processing according to one or more embodiments.

[0045] Referring to FIGS. 1 and 2A, in one or more embodiments, at operation 12, a substrate 101 is provided. As used in this specification and the appended claims, the term "provided" means that the substrate 101 is made available for processing (e.g., positioned in a processing chamber).

[0046] With reference to FIG. 2, in one or more embodiments, the substrate 101 can be any suitable material known to the skilled artisan. As used in this specification and the appended claims, the term "substrate" refers to a surface, or portion of a surface, upon which a process acts, as described herein.

[0047] Referring to FIG. 1 and FIG. 2A, in one or more embodiments, the substrate 101 may include a patterned structure 102. In one or more embodiments, the patterned structure 102 includes at least one opening 106. In one or more embodiments, the patterned structure 102 includes at least one opening 106 and at least one fin 105 having a top surface 112, such that the at least one opening 106 is located adjacent to at least one fin 105. In other embodiments, the at least oneDocket No. 44024680W001 PATENT10 opening 106 may be located between two adjacent fins 105. The opening 106 may be characterized by any shape or configuration according to the present technology. In some embodiments, the opening 106 may be or include a trench structure, a via structure, or an aperture formed within the patterned structure 102. In one or more embodiments, the patterned structure 102 comprises a plurality of fins 105 of a memory device, and the plurality of openings 106 are gate openings.

[0048] Although the opening 106 may be characterized by any shape or size, in some embodiments the opening 106 may be characterized by a high aspect ratio, or a ratio of the depth of the feature to the width across the opening 106. For example, in some embodiments opening 106 may be characterized by an aspect ratio greater than or equal to 5:1 , and may be characterized by an aspect ratio greater than or equal to 10:1 , greater than or equal to 15:1 , greater than or equal to 20:1 , greater than or equal to 25:1 , greater than or equal to 30:1 , greater than or equal to 40:1 , greater than or equal to 50:1 , or greater. In one or more embodiments, the opening 106 has an aspect ratio in a range of from 1 :1 to 1000:1.

[0049] Additionally, the opening 106 may be characterized by a narrow width or diameter across the feature including between two sidewalls 110, such as a critical dimension in a range of from 5 nm to 500 nm, or in a range of from 10 nm to 200 nm, or in a range of from 20 nm to 100 nm. The opening 106 may include at least one sidewall 110 and a bottom surface 108. In one or more embodiments, the at least one sidewall 110 also forms the sidewall of the at least one fin 105. The at least one fin 105 may have a top surface 112.

[0050] In one or more embodiments, a film 104 or liner forms substantially conformally on the patterned structure 102. As used herein, a layer which is "substantially conformal" refers to a layer where the thickness is about the same throughout (e.g., on the top, middle and bottom of sidewalls and on the bottom of the opening 106). A layer which is substantially conformal varies in thickness by less than or equal to about 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1 %, or 0.5%. The film 104 may comprise any suitable material known to the skilled artisan. In one or more embodiments, the patterned structure 102 comprises a plurality of fins of a memory device, the opening 106 is a gate opening, and the film 104 comprises an oxide material that is formed on the fins, which may comprise silicon (Si).Docket No. 44024680W001 PATENT11

[0051] Referring to FIG. 1 and FIG. 2B, at operation 14, in one or more embodiments, the device 100 is exposed to a precursor and a reactant to form an inhibiting layer 114 on the patterned structure 102. The inhibiting layer 114 may comprise any suitable material known to the skilled artisan. In some embodiments, the inhibiting layer 114 comprises one or more of a halogenated carbon film, a fluorocarbon film, a chlorocarbon film, a bromocarbon film, an amorphous carbon film, an oxygen containing carbon film, or a nitrogen containing carbon film.

[0052] In one or more embodiments, the inhibiting layer 114 is deposited by a directional deposition process. In one or more embodiments, the directional deposition process is plasma enhanced chemical vapor deposition (PECVD). Without intending to be bound by theory, it is thought that this deposition method relies upon surface topography to deactivate a surface with an inhibiting layer and therefore can be broadly used in area selective deposition schemes in depositing dielectric on dielectric, dielectric on metal, metal on dielectric or any combination thereof.

[0053] As used herein, the term "directional" means that the angle of the deposition of the inhibiting film can be controlled. In one or more embodiments, the hardware and / or process variables of the angled deposition system is what sets the angle, and then the shadowing of the features / line of sight sets the extent to which that deposition ends up on the sidewalls of the trench features. In one or more embodiments, the inhibiting layer 114 is deposited on the patterned structure at an angle in a range of from 0° to 60°, or in a range of from 0° to 50°, or in a range of from 0° to 45°, or in a range of from greater than 0° to 50°, or in a range of from greater than 0° to 45°, or in a range of from 1 ° to 50°, or in a range of from 1 ° to 45°, or a range of from 5° to 60°, or in a range of from 5° to 45°, or in a range of from 10° to 60°, or in a range of from 10° to 45°.

[0054] In one or more embodiments, any suitable deposition system known to the skilled artisan may be used. For example, referring to FIG. 5, a deposition system 500, more specifically a selective deposition system that may be used is provided. The deposition system 500 includes a process chamber 501 , wherein the process chamber 501 may house a substrate 520. The substrate 520 may be any suitable substrate and may have a three-dimensional shape, as illustrated. The deposition system 500 may include an angled deposition source 202, wherein the depositionDocket No. 44024680W001 PATENT12 source 502 is disposed adjacent the process chamber 501 . In other embodiments, the deposition source 502 may be disposed within the process chamber 501. The deposition source 502 may be arranged to generate a deposition beam 512, as a depositing species. In one or more embodiments, the deposition source 502 may be coupled to a source 508, where the source 508 represents a liquid vapor source, a single gas source, multiple gas sources, a gas manifold, and the like. The source 508 is couples to the deposition source 502. The deposition source 502 may be a chemical vapor deposition source in some embodiments, or may be an ion source, such as any suitable ion source known in the art. The deposition source 502 may be a plasma source, generating a plasma therein. In one or more embodiments, the deposition beam 512 may include ions, neutrals, excited species, where the species of deposition beam 512 may be directed along a given direction to the substrate 520. In some embodiments, the deposition beam 512 may be a collimated beam and an angled deposition beam, wherein the depositing species are directed along a trajectory defining a non-zero angle of incidence (shown as 0i) with respect to a perpendicular to a substrate plane. The beam 512 can be in a ribbon shape and have an adjustable angle.

[0055] The deposition system may include a substrate stage 506 configured to scan the substrate 520. In some embodiments, the substrate stage 506 may be configured to scan the substrate along at least one direction, such as along the y-axis of the Cartestian coordinate system shown. The substrate stage 506 may scan the substrate over a target range, such as between a first position, P1 , adjacent the deposition source 502, and a second position, P2.

[0056] The plasma enhanced chemical vapor deposition (PECVD) process of some embodiments comprises substantially simultaneous exposures to a precursor and a reactant. In some embodiments, the inhibiting film 114 is deposited by a PECVD process using one or more of a remote plasma or a direct plasma. In one or more embodiments, the plasma may be generated remotely or within the processing chamber. In some embodiments, the inhibiting film 114 is deposited by a PECVD process using a capacitively coupled plasma (CCP). In some embodiments, the inhibiting film 114 is deposited by a PECVD process using in inductively coupled plasma (ICP). In other embodiments, the plasma is a microwave plasma.Docket No. 44024680W001 PATENT13

[0057] In one or more embodiments, the plasma comprises one or more of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), carbon monoxide (CO), carbon dioxide (CO2), methane (CH4), ammonia (NH3), krypton (Kr), oxygen (O2), and ozone (O3).

[0058] Any suitable power can be used depending on, for example, the reactants, or the other process conditions. In some embodiments, the plasma is generated with a plasma power in the range of about 10 W to about 3000 W. In some embodiments, the plasma is generated with a plasma power less than or equal to about 3000 W, less than or equal to about 2000 W, less than or equal to about 1000 W, less than or equal to about 500 W, or less than or equal to about 250 W.

[0059] The PECVD process of some embodiments comprises exposing the patterned structure 102 to a reactive gas. In some embodiments, the reactive gas comprises a plurality of reactants. In these embodiments, the reactants are exposed to the substrate surface simultaneously. For example, the reactants may comprise a fluorine-containing precursor and a plasma gas. In some embodiments, the reactants may comprise a carbon-containing precursor and a plasma gas. The plasma gas can be any suitable gas that can be ignited to form a plasma and / or can act as a carrier or diluent for the precursor. In some embodiments, one or more of the reactants are flowed together into the processing chamber. In some embodiments, the reactants are flowed into the processing chamber separately.

[0060] In one or more embodiments, the fluorine-containing precursor may comprise any suitable precursor known to the skilled artisan. In one or more embodiments, the fluorine containing precursor comprises one or more of carbon tetrafluoride (CF4), trifluoromethane (CHF3), and vinyl fluoride (C2H3F), 2- (trifluoromethyl)acrylic acid, 1 ,1 ,1 ,3,3,3-Hexafluoroisopropyl acrylate, glycidyl 2, 2,3,3- tetrafluoropropyl ether, ammonium trifluoroacetate, and the like.

[0061] In one or more embodiments, the carbon-containing precursor may comprise any suitable precursor known to the skilled artisan. In one or more embodiments, the carbon-containing precursor comprises one or more of acetylene, methane, propylene, butylene, cyclobutylene, norbornene, and the like.Docket No. 44024680W001 PATENT14

[0062] The process of some embodiments switches the plasma on and off during processing. Stated differently, the plasma of some embodiments is ignited at a regular interval.

[0063] In one or more embodiments, the plasma is generated or ignited within the processing chamber (e.g., a direct plasma) by igniting the plasma gas to form a plasma. As mentioned previously, the plasma may be ignited at a regular interval. A "regular" interval means that the time of plasma ignitions is about equally spaced. In some embodiments, a regular interval means that the times that the plasma is ignited for is about the same. In some embodiments, regular intervals means that the plasma is ignited for about the same amount of time and the time difference between the ignitions is about the same. Stated differently, during processing, the plasma source will be switched on to generate the plasma and off to allow the plasma gas to remain unaffected by the plasma.

[0064] In one or more embodiments, the cycling of the plasma can occur over any time frame. For example, the plasma may be on for one second and off for one second before the cycle repeats or the plasma may be on for 50 ms and off for 50 ms before the cycle repeats.

[0065] Similarly, in one or more embodiments, the active and inactive periods of the plasma cycle may be uneven. For example, the plasma may be on for 400 ms and off for 100 ms, or vice versa. The percentage of a cycle in which the plasma is active is referred to as the duty cycle of the plasma. For example, the 400 ms active and 100 ms inactive would be a duty cycle of about 80 %.

[0066] In some embodiments, the regular interval has a duty cycle in a range of about 5% to about 90%. In some embodiments, the regular interval has a duty cycle that is less than or equal to about 90%, less than or equal to about 80%, less than or equal to about 70%, less than or equal to about 60%, less than or equal to about 50%, less than or equal to about 40%, less than or equal to about 30%, less than or equal to about 25%, less than or equal to about 20%, less than or equal to about 15%, or less than or equal to about 10%.

[0067] The plasma power, in one or more embodiments, can be maintained at any suitable power. In some embodiments, the plasma power is in a range of about 10 W to about 200 W. In some embodiments, the plasma power is less than or equal toDocket No. 44024680W001 PATENT15 about 200 W, less than or equal to about 150 W, less than or equal to about 100 W, less than or equal to about 50 W, less than or equal to about 25 W or less than or equal to about 20W.

[0068] The plasma frequency may be any suitable frequency. In some embodiments, the plasma has a frequency in a range of about 10 Hz to about 10 kHz. In some embodiments, the plasma frequency is less than or equal to about 10 kHz, less than or equal to about 5 kHz, less than or equal to about 2 kHz, less than or equal to about 1 kHz, less than or equal to about 500 Hz, less than or equal to about 200 Hz, less than or equal to about 100 Hz, less than or equal to about 50 Hz, or less than or equal to about 20 Hz. In some embodiments, the plasma frequency is greater than or equal to about 10 Hz, greater than or equal to about 20 Hz, greater than or equal to about 50 Hz, greater than or equal to about 100 Hz, greater than or equal to about 200 Hz, greater than or equal to about 500 Hz, greater than or equal to about 1 kHz, greater than or equal to about 2 kHz, or greater than or equal to about 5 kHz.

[0069] The parameters of the plasma can be controlled to provide a predetermined deposition rate. Each of the plasma parameters discussed above may be expected to have an effect on the deposition rate of the inhibiting film 114.

[0070] In one or more embodiments, the deposition rate of the inhibiting film 114 is provided as a given thickness of the deposited film in a given unit of time. For example, for a film with a deposition rate of 100 A / min, 50 A will be deposited in 30 seconds on a flat surface.

[0071] In some embodiments, the inhibiting film 114 is deposited at a rate in a range of about 300 A / min to about 900 A / min. In some embodiments, the inhibiting film 114 is deposited at a rate of less than or equal to about 750 A / min, less than or equal to about 600 A / min, less than or equal to about 500 A / min, less than or equal to about 450 A / min, less than or equal to about 400 A / min, less than or equal to about 350 A / min, less than or equal to about 300 A / min, or less than or equal to about 250 A / min.

[0072] In addition to controlling the parameters of the plasma exposure, additional process parameters can also be controlled. Specifically, the deposition temperature, the processing pressure, the spacing between plasma and wafer, the selection of theDocket No. 44024680W001 PATENT16 precursor and the ratio between the precursor and any diluent in the reactive gas can be tailored to maintain the flowability of the deposited flowable film.

[0073] The inhibiting film 114 can be deposited at any suitable temperature. In some embodiments, the inhibiting film 114 is deposited at a temperature in the range of about greater than 0 °C to about 500 °C, including in a range of from about 20 °C to about 500 °C, or in a range of from about 20 °C to about 450 °C. The temperature can be kept low to preserve the thermal budget of the device being formed and limit reactions when the plasma is inactive. In some embodiments, depositing the inhibiting film 114 occurs at a temperature less than about 500 °C.

[0074] In one or more embodiments, the inhibiting film 114 can be deposited at any suitable chamber pressure. In some embodiments, the inhibiting film 114 is deposited at a pressure in the range of about 1 Torr to about 10 Torr. In some embodiments, the pressure is greater than or equal to about 1 Torr, greater than or equal to about 2 Torr, greater than or equal to about 3 Torr, greater than or equal to about 5 Torr, greater than or equal to about 7 Torr, or greater than or equal to about 9 Torr. In some embodiments, the pressure is less than or equal to about 10 Torr, less than or equal to about 9 Torr, less than or equal to about 8 Torr, less than or equal to about 7 Torr, less than or equal to about 5 Torr, or less than or equal to about 3 Torr.

[0075] In one or more embodiments, with reference to FIG. 2B, the inhibiting layer 114 can have any suitable thickness. In some embodiments, the thickness of the inhibiting layer 114 is in a range of from greater than 0 nm to about 20 nm, including in a range of from about 1 nm to about 15 nm, or in range of from about 2 nm to about 11 nm. Without intending to be bound by theory, it is thought that the directional PECVD deposition results in the formation of a thicker film on a top surface 112 and on a bottom surface 108 of the patterned structure 102 than forms on the sidewall surface 110. In one or more embodiments, the thickness of the inhibiting layer 114 is thinnest on the middle portion of the sidewall surface 110 and thickness on the top surface 112 of the fin 105 and on the bottom surface 108 of the opening 106. In some embodiments, the sidewall surface 110 of the patterned structure 102 may be substantially free of the inhibiting layer 114.

[0076] With reference to FIG. 1 and FIG. 2C, at operation 16, in one or more embodiments, any inhibiting layer 114 that formed on the sidewall surface 110 of theDocket No. 44024680W001 PATENT17 patterned structure 102, the excess inhibiting layer 114, may be removed from the sidewall surface to leave a sidewall surface 116 that is substantially free of the inhibiting layer 114. The inhibiting layer 114 may be removed from the sidewall surface by any suitable means known to the skilled artisan including any suitable dry etching process, any suitable wet etching process, any suitable isotropic etching process, or other suitable etching techniques. In some embodiments, the inhibiting layer 114 is removed by isotropic etching or by dry etching or by etching. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SFe, CH2F2, CHF3, and / or C2F6), a chlorine-containing (e.g., CI2, CHCI3, CCI4, and / or BCI3), a bromine-containing gas (e.g., HBr and / or CHBrs), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. In one or more embodiments, the wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant(s).

[0077] Referring to FIG. 1 and FIG. 2D, at operation 18, a film 118 is formed selectively on the sidewall surface 116 of the patterned structure 102. The film 118 may be formed by any suitable deposition process including atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the film 118 is a metal layer. In other embodiments, the film 118 is a dielectric layer.

[0078] In one or more embodiments, the film 118 may have any suitable thickness. In some embodiments, the thickness of the film 118 is in a range of from greater than 0 nm to about 20 nm, including in a range of from about 1 nm to about 15 nm, or in range of from about 2 nm to about 11 nm.

[0079] The atomic layer deposition process of some embodiments comprises sequential exposures to a precursor and a reactant to form the film 118. The chemical vapor deposition process of some embodiments comprises simultaneous exposures to a precursor and a reactant to form the film 118. In specific embodiments, the atomic layer deposition process comprises sequential exposures to a precursor and a reactant to form a metal layer. In other specific embodiments, the chemical vapor deposition process of comprises simultaneous exposures to a precursor and a reactant to form the metal layer.Docket No. 44024680W001 PATENT18

[0080] The film 118 may comprise any suitable material known to the skilled artisan. In one or more embodiments, the film 118 is a metal layer that includes a metal comprising one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In some embodiment, the metal layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or molybdenum (Mo).

[0081] In other embodiments, the film 118 is a dielectric layer and comprises any suitable dielectric material. As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the film 118 comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN).

[0082] In some embodiments, forming the film 118 includes exposing the patterned structure 102 to a precursor and reactant at a temperature in a range of from 350 °C to 550 °C, from 400 °C to 550 °C, from 450 °C to 550 °C, 500 °C to 550 °C, from 350 °C to 500 °C, from 400 °C to 500 °C, from 450 °C to 500 °C, from 350 °C to 450 °C, from 400 °C to 450 °C or from 350 °C to 400 °C.

[0083] In some embodiments, forming the film 118 includes exposing the patterned structure 102 to a precursor for a duration of time in a range of from 5 seconds to 60 minutes, from 1 minutes to 60 minutes, from 5 minutes to 60 minutes, from 10 minutes to 60 minutes, from 20 minutes to 60 minutes, from 40 minutes to 60 minutes, from 5 seconds to 40 minutes, from 1 minutes to 40 minutes, from 5 minutes to 40 minutes, from 10 minutes to 40 minutes, from 20 minutes to 40 minutes, from 5 seconds to 20 minutes, from 1 minutes to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 5 seconds to 10 minutes, from 1 minutes to 10 minutes or from 5 minutes to 10 min.

[0084] In some embodiments, forming the film 118 includes exposing the patterned structure 102 to a reactant for a duration of time in a range of from 5 seconds to 60 minutes, from 1 minutes to 60 minutes, from 5 minutes to 60 minutes, from 10 minutes to 60 minutes, from 20 minutes to 60 minutes, from 40 minutes to 60 minutes, from 5 seconds to 40 minutes, from 1 minutes to 40 minutes, from 5 minutes to 40 minutes,Docket No. 44024680W001 PATENT19 from 10 minutes to 40 minutes, from 20 minutes to 40 minutes, from 5 seconds to 20 minutes, from 1 minutes to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 5 seconds to 10 minutes, from 1 minutes to 10 minutes or from 5 minutes to 10 min.

[0085] In some embodiments, forming the film 118 includes exposing the patterned structure 102 to a precursor at a dose in a range of from 100 seem to 7000 seem, from 500 seem to 7000 seem, from 1000 seem to 7000 seem, from 3000 seem to 7000 seem, from 5000 seem to 7000 seem, from 100 seem to 5000 seem, from 500 seem to 5000 seem, from 1000 seem to 5000 seem, from 3000 seem to 5000 seem, from 100 seem to 3000 seem, from 500 seem to 3000 seem, from 1000 seem to 3000 seem, from 100 seem to 1000 seem, from 500 seem to 1000 seem or from 100 seem to 500 seem.

[0086] In some embodiments, forming the film 118 includes exposing the patterned structure 102 to a reactant at a dose in a range of from 100 seem to 7000 seem, from 500 seem to 7000 seem, from 1000 seem to 7000 seem, from 3000 seem to 7000 seem, from 5000 seem to 7000 seem, from 100 seem to 5000 seem, from 500 seem to 5000 seem, from 1000 seem to 5000 seem, from 3000 seem to 5000 seem, from 100 seem to 3000 seem, from 500 seem to 3000 seem, from 1000 seem to 3000 seem, from 100 seem to 1000 seem, from 500 seem to 1000 seem or from 100 seem to 500 seem.

[0087] In some embodiments, forming the film 118 includes exposing the patterned structure 102 to a precursor and reactant at a pressure in a range of from 5 Torr to 50 Torr, from 10 Torr to 50 Torr, from 25 Torr to 50 Torr, from 5 Torr to 25 Torr, from 10 T orr to 25 T orr or from 5 Torr to 10 T orr.

[0088] In one or more embodiments, the processing chamber may be optionally purged to remove unreacted precursor, unreacted reactant, reaction products, and byproducts. In one or more embodiments, the purge gas is selected from one or more of argon (Ar), nitrogen (N2), hydrogen (H2), and helium (He).

[0089] With reference to FIG. 2E, in one or more embodiments, any remaining inhibiting layer 114 is then removed from the top surface 112 and the bottom surface 108. The inhibiting layer 114 may be removed from the top surface 112 and the bottom surface 108 by any suitable means known to the skilled artisan including anyDocket No. 44024680W001 PATENT20 suitable dry etching process, any suitable wet etching process, any suitable isotropic etching process, or other suitable etching techniques. In some embodiments, the inhibiting layer 114 is removed from the top surface 112 and the bottom surface 108 by isotropic etching. For example, a dry etching process may implement an oxygencontaining gas, a fluorine-containing gas (e.g., CF4, SFe, CH2F2, CHF3, and / or C2F6), a chlorine-containing (e.g., CI2, CHCb, CCI4, and / or BCI3), a bromine-containing gas (e.g., HBr and / or CHBrs), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. In one or more embodiments, the wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant(s).

[0090] Referring to FIGS. 1 and 3A, in one or more embodiments, at operation 12, a substrate 201 is provided. As used in this specification and the appended claims, the term "provided" means that the substrate 201 is made available for processing (e.g., positioned in a processing chamber).

[0091] With reference to FIG. 3A, in one or more embodiments, the substrate 201 can be any suitable material known to the skilled artisan and as described herein.

[0092] Referring to FIG. 1 and FIG. 3A, in one or more embodiments, the substrate 201 may include a patterned structure 202. In one or more embodiments, the patterned structure 202 includes at least one opening 206 and at least one fin 205, such that the at least one opening 206 is located between two adjacent fins 205. The opening 206 may be characterized by any shape or configuration according to the present technology. In some embodiments, the opening 206 may be or include a trench structure, a via structure, or aperture formed within the patterned structure 202. In one or more embodiments, the patterned structure 202 comprises a plurality of fins 205 of a memory device, and the plurality of features 206 are gate openings.

[0093] Although the opening 206 may be characterized by any shape or size, in some embodiments the opening 206 may be characterized by a high aspect ratio, or a ratio of a depth of the feature to a width across the opening 206. For example, in some embodiments opening 206 may be characterized by an aspect ratio greater than or equal to 5:1 , and may be characterized by an aspect ratio greater than or equal to 10:1 , greater than or equal to 15:1 , greater than or equal to 20:1 , greater than or equalDocket No. 44024680W001 PATENT21 to 25:1 , greater than or equal to 30:1 , greater than or equal to 40:1 , greater than or equal to 50:1 , or greater. In one or more embodiments, the opening 206 has an aspect ratio in a range of from 1 :1 to 1000:1.

[0094] Additionally, the opening 206 may be characterized by a narrow width or diameter across the feature including between two sidewalls 210a, 210b, such as a critical dimension in a range of from 5 nm to 500 nm, or in a range of from 10 nm to 200 nm, or in a range of from 20 nm to 100 nm. The opening 206 may include at least one sidewall 210a, 210b and a bottom surface 208. In one or more embodiments, the at least one sidewall 210a,210b also forms the sidewall of the at least one fin 205. The at least one fin 205 may have a top surface 212.

[0095] In one or more embodiments, a film 204 or liner forms substantially conformally on the patterned structure 202. As used herein, a layer which is "substantially conformal" refers to a layer where the thickness is about the same throughout (e.g., on the top, middle and bottom of sidewalls and on the bottom of the opening 206). A layer which is substantially conformal varies in thickness by less than or equal to about 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1 %, or 0.5%. The film 204 may comprise any suitable material known to the skilled artisan. In one or more embodiments, the patterned structure 202 comprises a plurality of fins 205 of a memory device, the plurality of openings 206 are gate openings, and the film 204 comprises an oxide material that is formed on the fins 205, which may comprise silicon (Si).

[0096] Referring to FIG. 1 and FIG. 3B, at operation 14, in one or more embodiments, the device 200 is exposed to a precursor and a reactant to form an inhibiting layer 214 on the patterned structure 202. The inhibiting layer 214 may comprise any suitable material known to the skilled artisan. In some embodiments, the inhibiting layer 214 comprises one or more of a halogenated carbon film, a fluorocarbon film, a chlorocarbon film, a bromocarbon film, an amorphous carbon film, an oxygen containing carbon film, or a nitrogen containing carbon film.

[0097] In one or more embodiments, the inhibiting layer 214 is deposited by directional plasma enhanced chemical vapor deposition (PECVD) as described herein with respect to the inhibiting layer 114. Without intending to be bound by theory, it is thought that this deposition method relies upon surface topography to deactivate aDocket No. 44024680W001 PATENT22 surface with inhibiting layer and therefore can be broadly used in area selective deposition schemes in depositing dielectric on dielectric, dielectric on metal, metal on dielectric or any combination thereof.

[0098] In one or more embodiments, the angle of the deposition is with respect to the vertical patterned structure 202. In one or more embodiments, the hardware and / or process variables of the angled deposition system is what sets the angle, and then the shadowing of the features / line of sight sets the extent to which that deposition ends up on the sidewalls of the trench features. In one or more embodiments, the inhibiting layer 214 is deposited on the patterned structure at an angle in a range of from 0° to 60°, or in a range of from 0° to 50°, or in a range of from 0° to 45°, or in a range of from greater than 0° to 60°, or in a range of from greater than 0° to 45°, or in a range of from 1 ° to 50°, or in a range of from 1 ° to 45°, or a range of from 5° to 60°, or in a range of from 5° to 45°, or in a range of from 10° to 50°, or in a range of from 10° to 45°.

[0099] In one or more embodiments, the fluorine-containing precursor of the PECVD process may comprise any suitable precursor known to the skilled artisan. In one or more embodiments, the fluorine containing precursor comprises one or more of carbon tetrafluoride (CF4), trifluoromethane (CHF3), and vinyl fluoride (C2H3F), 2- (Trifluoromethyl)acrylic acid, 1 ,1 ,1 ,3,3,3-Hexafluoroisopropyl acrylate, Glycidyl 2, 2,3,3- tetrafluoropropyl ether, Ammonium trifluoroacetate, and the like.

[0100] In one or more embodiments, the carbon-containing precursor of the PECVD process may comprise any suitable precursor known to the skilled artisan. In one or more embodiments, the carbon-containing precursor comprises one or more of acetylene, methane, propylene, butylene, cyclobutylene, norbornene, and the like.

[0101] In one or more embodiments, with reference to FIG. 3B, the inhibiting layer 214 can have any suitable thickness. In some embodiments, the thickness of the inhibiting layer 214 is in a range of from greater than 0 nm to about 20 nm, including in a range of from about 1 nm to about 15 nm, or in range of from about 2 nm to about 11 nm. Without intending to be bound by theory, it is thought that the directional PECVD deposition results in the formation of a thicker film on a top surface 212 and on a bottom surface 208 of the patterned structure 202 than forms on the sidewall surface 210a, 210b. In some embodiments, the sidewall surface 210a, 210b of theDocket No. 44024680W001 PATENT23 patterned structure 202 is substantially free of the inhibiting layer 214. In one or more embodiments, depending upon the angle of the direction PECVD deposition, the inhibiting layer 214 may form to a greater extent on one sidewall 210a of the opening 206 and substantially not on the opposing sidewall 210b of the opening 206. Without intending to be bound by theory, such deposition permits the formation of different metal layers on each sidewall of the opening 206.

[0102] With reference to FIG. 1 and FIG. 3B, at operation 16, in one or more embodiments, any inhibiting layer 214 formed on the sidewall surface 210b of the patterned structure 202, the excess inhibiting layer 214, may be removed from the sidewall surface 210b to leave a sidewall surface 210b that is substantially free of the inhibiting layer 214. The inhibiting layer 214 may be removed from the sidewall surface 210b by any suitable means known to the skilled artisan including any suitable dry etching process, any suitable wet etching process, any suitable isotropic etching process, or other suitable etching techniques. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SFe, CH2F2, CHF3, and / or C2F6), a chlorine-containing (e.g., CI2, CHCI3, CCI4, and / or BCb), a bromine-containing gas (e.g., HBr and / or CHBrs), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. In one or more embodiments, the wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant(s).

[0103] Referring to FIG. 1 and FIG. 3C, at operation 18, a film 218 is formed selectively on the sidewall surface 210b of the patterned structure 202. The film 218 may be formed by any suitable deposition process including atomic layer deposition (ALD) or chemical vapor deposition (CVD) as described herein with respect to film 118. In some embodiments, the film 218 is a metal layer. In other embodiments, the film 218 is a dielectric layer.

[0104] In one or more embodiments, the film 218 may have any suitable thickness. In some embodiments, the thickness of the film 218 is in a range of from greater than 0 nm to about 20 nm, including in a range of from about 1 nm to about 15 nm, or in range of from about 2 nm to about 11 nm.Docket No. 44024680W001 PATENT24

[0105] The atomic layer deposition process of some embodiments comprises sequential exposures to a precursor and a reactant to form the film 218. The chemical vapor deposition process of some embodiments comprises simultaneous exposures to a precursor and a reactant to form the film 218. In specific embodiments, the atomic layer deposition process comprises sequential exposures to a precursor and a reactant to form a metal layer. In other specific embodiments, the chemical vapor deposition process of comprises simultaneous exposures to a precursor and a reactant to form the metal layer.

[0106] The film 218 may comprise any suitable material known to the skilled artisan. In one or more embodiments, the film 218 is a metal layer including a metal comprising one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In some embodiments, the metal layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or molybdenum (Mo).

[0107] In other embodiments, the film 218 is a dielectric layer and comprises any suitable dielectric material. In one or more embodiments, the film 218 comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN).

[0108] With reference to FIG. 3D, in one or more embodiments, the inhibiting layer 214 is then removed from the top surface 212, the bottom surface 208, and the at least one sidewall surface 210a to leave an exposed surface 216. The inhibiting layer 214 may be removed from the top surface 212, the bottom surface 208, and the at least one sidewall surface 210a by any suitable means known to the skilled artisan including any suitable dry etching process, any suitable wet etching process, any suitable isotropic etching process, or other suitable etching techniques. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SFe, CH2F2, CHF3, and / or C2F6), a chlorine-containing (e.g., CI2, CHCI3, CCI4, and / or BCI3), a bromine-containing gas (e.g., HBr and / or CHBrs), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. In one or more embodiments, the wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; aDocket No. 44024680W001 PATENT25 solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant(s).

[0109] With reference to FIG. 1, in one or more embodiments of the method 10 there is a determination / decision point 20 of whether a target thickness or placement of the metal layer on the sidewall surface of the patterned structure has been achieved following one or more cycles of forming the metal layer. If a target thickness or the placement of the as-deposited metal layer has not been achieved, another cycle of forming an inhibiting layer followed by forming the metal layer is performed. If a target thickness or the target placement of the as-deposited metal layer has been achieved, another cycle to form another metal layer is not started. Exemplary numbers of cycles for the formation of metal layers may include 1 cycle to 2000 cycles. Additional exemplary ranges for the number of cycles may include 50 cycles to 1000 cycles, and 100 cycles to 750 cycles, among other exemplary ranges.

[0110] Referring to FIG. 1 and FIG. 3E, at operation 14, in one or more embodiments, the device 200 is exposed to a precursor and a reactant to form a second inhibiting layer 220 on the patterned structure 202 and on the film 218. The inhibiting layer 220 may comprise any suitable material known to the skilled artisan. In some embodiments, the inhibiting layer 220 comprises one or more of a fluorocarbon film, or an amorphous carbon film. The second inhibiting layer 220 may comprise the same material as the inhibiting layer 214 or may comprise a different material.

[0111] In one or more embodiments, the second inhibiting layer 220 is deposited by directional plasma enhanced chemical vapor deposition (PECVD) as described herein with respect to the inhibiting layer 114 and inhibiting layer 214. Without intending to be bound by theory, it is thought that this deposition method relies upon surface topography to deactivate a surface with inhibiting layer and therefore can be broadly used in area selective deposition schemes in depositing dielectric on dielectric, dielectric on metal, metal on dielectric or any combination thereof.

[0112] In one or more embodiments, the angle of the deposition is with respect to the vertical patterned structure 202. In one or more embodiments, the hardware and / or process variables of the angled deposition system is what sets the angle, and then the shadowing of the features / line of sight sets the extent to which that deposition ends up on the sidewalls of the trench features. In one or more embodiments, theDocket No. 44024680W001 PATENT26 second inhibiting layer 220 is deposited on the patterned structure and on the film 218 at an angle in a range of from 0° to 50°, or in a range of from 0° to 45°, or in a range of from greater than 0° to 50°, or in a range of from greater than 0° to 45°, or in a range of from 1 ° to 50°, or in a range of from 1 ° to 45°, or a range of from 5° to 50°, or in a range of from 5° to 45°, or in a range of from 10° to 50°, or in a range of from 10° to 45°.

[0113] In one or more embodiments, the fluorine-containing precursor may comprise any suitable precursor known to the skilled artisan. In one or more embodiments, the fluorine containing precursor comprises one or more of carbon tetrafluoride (CF4), trifluoromethane (CHF3), and vinyl fluoride (C2H3F), 2- (Trifluoromethyl)acrylic acid, 1 ,1 ,1 ,3,3,3-Hexafluoroisopropyl acrylate, Glycidyl 2, 2,3,3- tetrafluoropropyl ether, Ammonium trifluoroacetate, and the like.

[0114] In one or more embodiments, the carbon-containing precursor may comprise any suitable precursor known to the skilled artisan. In one or more embodiments, the carbon-containing precursor comprises one or more of acetylene, methane, propylene, butylene, cyclobutylene, norbornene, and the like.

[0115] In one or more embodiments, with reference to FIG. 3E, the second inhibiting layer 220 can have any suitable thickness. In some embodiments, the thickness of the second inhibiting layer 220 is in a range of from greater than 0 nm to about 20 nm, including in a range of from about 1 nm to about 15 nm, or in range of from about 2 nm to about 11 nm. Without intending to be bound by theory, it is thought that the directional PECVD deposition results in the formation of a thicker film on a top surface 212 and on a bottom surface 208 of the patterned structure 202 than forms on the sidewall surface 216. In some embodiments, the sidewall surface 216 of the patterned structure 202 is substantially free of the second inhibiting layer 220. In one or more embodiments, depending upon the angle of the direction PECVD deposition, the second inhibiting layer 220 may form to a greater extent on the film 218 and substantially not on the opposing sidewall 216 of the opening 206. Without intending to be bound by theory, such deposition permits the formation of different metal layers on each sidewall of the opening 206.

[0116] With reference to FIG. 1 and FIG. 3E, at operation 16, in one or more embodiments, any second inhibiting layer 220 formed on the exposed sidewall surfaceDocket No. 44024680W001 PATENT27216 of the patterned structure 202 and on the film 218, the excess second inhibiting layer 220, may be removed from the exposed sidewall surface 216 to leave the sidewall surface 216 substantially free of the second inhibiting layer 220. The second inhibiting layer 220 may be removed from the sidewall surface by any suitable means known to the skilled artisan including any suitable dry etching process, any suitable wet etching process, any suitable isotropic etching process, or other suitable etching techniques. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SFe, CH2F2, CHF3, and / or C2F6), a chlorine- containing (e.g., CI2, CHCI3, CCI4, and / or BCI3), a bromine-containing gas (e.g., HBr and / or CHBrs), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. In one or more embodiments, the wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant(s).

[0117] Referring to FIG. 1 and FIG. 3F, at operation 18, a second film 222 is formed selectively on the exposed sidewall surface 216 of the patterned structure 202. The second film 222 may be formed by any suitable deposition process including atomic layer deposition (ALD) or chemical vapor deposition (CVD) as described herein with respect to film 118 and film 218. In some embodiments, the film 222 is a metal layer. In other embodiments, the film 222 is a dielectric layer.

[0118] The atomic layer deposition process of some embodiments comprises sequential exposures to a precursor and a reactant to form the second film 222. The chemical vapor deposition process of some embodiments comprises simultaneous exposures to a precursor and a reactant to form the second film 222. In specific embodiments, the atomic layer deposition process comprises sequential exposures to a precursor and a reactant to form a second metal layer. In other specific embodiments, the chemical vapor deposition process of comprises simultaneous exposures to a precursor and a reactant to form the second metal layer.

[0119] The second film 222 may comprise any suitable material known to the skilled artisan. In one or more embodiments, the second film 222 is a metal layer including a metal comprising one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalumDocket No. 44024680W001 PATENT28(Ta), titanium (Ti), or rhodium (Rh). In some embodiments, the second film 222 comprises the same material as the film 218. In other embodiments, the second film 222 comprises a different material than the film 218. In some embodiments, the second metal layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or molybdenum (Mo).

[0120] With reference to FIG. 3G, in one or more embodiments, the remaining second inhibiting layer 220 is then removed from the top surface 212, the bottom surface 208, and the at least one sidewall surface 216. The second inhibiting layer 220 may be removed from the top surface 212, the bottom surface 208, and the at least one sidewall surface 216 by any suitable means known to the skilled artisan including any suitable dry etching process, any suitable wet etching process, any suitable isotropic etching process, or other suitable etching techniques. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SFe, CH2F2, CHF3, and / or C2F6), a chlorine-containing (e.g., CI2, CHCI3, CCI4, and / or BCI3), a bromine-containing gas (e.g., HBr and / or CHBrs), an iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. In one or more embodiments, the wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant(s).

[0121] According to one or more embodiments, the substrate may be subjected to processing prior to and / or after forming the metal layer. This processing can be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is moved from the first chamber to a separate, second chamber for further processing. The substrate can be moved directly from the first chamber to the separate processing chamber, or it can be moved from the first chamber to one or more transfer chambers, and then moved to the separate processing chamber. Accordingly, the processing apparatus may comprise multiple chambers in communication with a transfer station. An apparatus of this sort may be referred to as a "cluster tool" or "clustered system," and the like.

[0122] Generally, a cluster tool is a modular system comprising multiple chambers which perform various functions including substrate center-finding and orientation,Docket No. 44024680W001 PATENT29 degassing, annealing, deposition and / or etching. Additional embodiments of the disclosure are directed to processing tools 900 for the formation of the memory devices and methods described, as shown in FIG. 4. The cluster tool 900 includes at least one central transfer station 921 , 931 with a plurality of sides. A robot 925, 935 is positioned within the central transfer station 921 , 931 and is configured to move a robot blade and a wafer to each of the plurality of sides.

[0123] The cluster tool 900 comprises a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to the central transfer station. The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chamber can be any suitable chamber including, but not limited to, a preclean chamber, a buffer chamber, transfer space(s), a wafer orienter / degas chamber, a cryo cooling chamber, a deposition chamber, annealing chamber, etching chamber, a selective etching chamber, and the like. The particular arrangement of process chambers and components can be varied depending on the cluster tool and should not be taken as limiting the scope of the disclosure.

[0124] In the embodiment shown in FIG. 4, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on a front 951 of the factory interface 950. While the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this is merely representative of one possible configuration.

[0125] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrates being processed in the cluster tool 900. In the embodiment shown, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette with a plurality of wafers positioned within the cassette.

[0126] A robot 952 is within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. The robot 952 is capable of transferring a wafer from a cassette in the loading chamber 954 through the factory interface 950 to load lock chamber 960. The robot 952 is also capable of transferring a wafer from the load lock chamber 962 through the factory interface 950 to a cassetteDocket No. 44024680W001 PATENT30 in the unloading chamber 956. As will be understood by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0127] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 positioned therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 comprises more than one robotic wafer transfer mechanism. The robot 925 in first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921. Individual wafers are carried upon a wafer transport blade that is located at a distal end of the first robotic mechanism.

[0128] After processing a wafer in the first section 920, the wafer can be passed to the second section 930 through a pass-through chamber. For example, chambers 922, 924 can be uni-directional or bi-directional pass-through chambers. The pass- through chambers 922, 924 can be used, for example, to cryo cool the wafer before processing in the second section 930 or allow wafer cooling or post-processing before moving back to the first section 920.

[0129] A system controller 990 is in communication with the first robot 925, second robot 935, first plurality of processing chambers 902, 904, 916, 918 and second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component that can control the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit (CPU), memory, suitable circuits, and storage.

[0130] Processes may generally be stored in the memory of the system controller 990 as a software routine that, when executed by the processor, causes the processDocket No. 44024680W001 PATENT31 chamber to perform processes of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware such as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor, transforms the general-purpose computer into a specific-purpose computer (controller) that controls the chamber operation such that the processes are performed.

[0131] Spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below,” or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0132] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the materials and methods andDocket No. 44024680W001 PATENT32 does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0133] Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0134] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure includes modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

Docket No. 44024680W001 PATENT33What is claimed is:

1. A method of forming a film on a semiconductor structure, the method comprising: forming an inhibiting layer on a patterned structure on a substrate by a directional deposition process, the patterned structure including a top surface and at least one opening having at least one sidewall surface and a bottom surface; and selectively forming the film on the at least one sidewall surface of the patterned structure, the film comprising a metal layer or a dielectric layer.

2. The method of claim 1 , wherein the at least one sidewall surface of the at least one opening comprises a first sidewall surface and a second sidewall surface, the inhibiting layer is formed on the top surface and the bottom surface, and the film is selectively deposited on the first sidewall surface and the second sidewall surface via a deposition process that is selective between the inhibiting layer and the first sidewall surface and the second sidewall surface.

3. The method of claim 1 , wherein the at least one sidewall surface of the at least one feature comprises a first sidewall surface and a second sidewall surface, the inhibiting layer is formed on the first sidewall surface, and the film is selectively deposited on the second sidewall surface via a deposition process that is selective between the inhibiting layer and the second sidewall surface.

4. The method of claim 1 , wherein the film is formed by one or more of atomic layer deposition (ALD) or chemical vapor deposition (CVD).

5. The method of claim 1 , wherein the directional deposition process is a plasma enhanced chemical vapor deposition (PECVD) process comprising simultaneously exposing the patterned structure to a precursor and a plasma.

6. The method of claim 1 , wherein the directional deposition process comprises deposition of the inhibiting layer at an angle in the range of from 0° to 60°.Docket No. 44024680W001 PATENT347. The method of claim 6, wherein the directional deposition process comprises deposition of the inhibiting layer at an angle in the range of from 5° to 60°.

8. The method of claim 5, wherein the directional deposition process comprises exposing the patterned structure to an angled deposition beam.

9. The method of claim 5, wherein the precursor comprises one or more of a fluorine-containing precursor or a carbon-containing precursor.

10. The method of claim 9, wherein the fluorine-containing precursor comprises one or more of carbon tetrafluoride (CF4), trifluoromethane (CHF3), and vinyl fluoride (C2H3F), 2-(Trifluoromethyl)acrylic acid, 1 ,1 ,1 ,3,3,3-Hexafluoroisopropyl acrylate, Glycidyl 2,2,3,3-tetrafluoropropyl ether, and ammonium trifluoroacetate and wherein the carbon-containing precursor comprises one or more of acetylene, methane, propylene, butylene, cyclobutylene, and norbornene.

11. The method of claim 5, wherein the plasma comprises one or more of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), carbon monoxide (CO), carbon dioxide (CO2), methane (CH4), ammonia (NH3), krypton (Kr), oxygen (O2), and ozone (O3).

12. The method of claim 1 , wherein the metal layer includes a metal comprising one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

13. The method of claim 1 , wherein the at least one feature has an aspect in a range of from 1 :1 to 1000:1.Docket No. 44024680W001 PATENT3514. The method of claim 1 , further comprising removing the inhibiting layer from the at least one sidewall surface prior to forming the film.

15. The method of claim 1 , further comprising: forming a second inhibiting layer on the patterned structure and on the film by a directional deposition process; and selectively forming a second film on the at least one sidewall surface of the patterned structure.

16. A method of forming an inhibiting layer on a semiconductor structure, the method comprising: simultaneously exposing a patterned structure on a substrate to a precursor and a plasma at an angle in a range of from 0° to 60°, the patterned structure including a top surface and at least one opening having at least one sidewall surface and a bottom surface, to form the inhibiting layer on the top surface and the bottom surface.

17. The method of claim 16, wherein the angle is in the range of from 5° to 60°.

18. The method of claim 16, wherein the method comprises a directional deposition process including exposing the patterned structure to an angled deposition beam.

19. The method of claim 16, wherein the precursor comprises one or more of a fluorine-containing precursor or a carbon-containing precursor.

20. The method of claim 19, wherein the fluorine-containing precursor comprises one or more of carbon tetrafluoride (CF4), trifluoromethane (CHF3), and vinyl fluoride (C2H3F), 2-(Trifluoromethyl)acrylic acid, 1 ,1 ,1 ,3,3,3-Hexafluoroisopropyl acrylate, Glycidyl 2,2,3,3-tetrafluoropropyl ether, and ammonium trifluoroacetate, and wherein the carbon-containing precursor comprises one orDocket No. 44024680W001 PATENT36 more of acetylene, methane, propylene, butylene, cyclobutylene, and norbornene.

21. The method of claim 16, wherein the plasma comprises one or more of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), carbon monoxide (CO), carbon dioxide (CO2), methane (CH4), ammonia (NH3), krypton (Kr), oxygen (O2), and ozone (O3).

22. The method of claim 16, further comprising removing the inhibiting layer from the at least one sidewall surface.

23. The method of claim 16, wherein the inhibiting layer comprises one or more of a halogenated carbon film, an amorphous carbon film, an oxygen containing carbon film, or a nitrogen containing carbon film.

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