Multiple threshold modulator and method for current source converters

Abstract

Method for modulating an n-phase current source converter, comprising the steps: a) obtaining duty ratio values, which are identified by using the following four sub-steps: i. obtaining initial duty ratio values, which are used to determine required output currents, from the ratio of AC output current reference values and a DC supply current value, ii. determining excess duty ratio values, which are used to compensate a missing duty ratio value, wherein the missing duty ratio value results from the subtraction between 1 and a sum of the initial upper or initial lower duty ratio values, wherein the sum of initial upper duty ratio values equals the sum of initial lower duty ratio values, iii. splitting the missing duty ratio value among converter legs that results in final duty ratio values and iv. obtaining cumulative sums of the initial or final duty ratio values, which are supplied to the comparator array as thresholds, b) comparing multiple thresholds through the comparison of the cumulative sums of the initial duty ratio values or final duty ratio values to a piecewise linear carrier signal, which results in n-1 digital signals obtained from n-1 comparators, wherein the comparing of multiple thresholds is performed by a first multiple threshold modulator for the upper switches and a second multiple threshold modulator for the lower switches, and c) processing of the digital signals from the multiple threshold comparator to obtain gating signals by using a digital combinatorial logic.

Description

[0001] MULTIPLE THRESHOLD MODULATOR AND METHOD FOR CURRENT

[0002] SOURCE CONVERTERS

[0003] The present invention relates to a method and apparatus or modulator for controlling the gate signals of current source converters, such as current source inverters or rectifiers.

[0004] BACKGROUND OF THE INVENTION

[0005] A current source converter modulator can be implemented by hardware, discrete circuits, integrated circuits, or software. The modulator generates gate signals from duty ratio signals, which are calculated based on desired output currents for a current source inverter or input currents for a current source rectifier and a DC link current. Furthermore, the modulator controls the gate signals of the current source converter in such a way that the desired output currents for a current source inverter or input currents for a current source rectifier are achieved. Gate signals, which are digital signals with high and low states, ensure that switches of a current source converter are on or off at a specific time. The process of generating these duty ratio signals or duty ratio signals is known as a modulation technique.

[0006] A solution for the commutation problem of current source converters is presented in publication N. Burany “Safe control of four-quadrant switches”, Conference Record of the IEEE Industry Applications Society Annual Meeting, San Diego, USA, 1989, pp. 1190-1194 vol.l, doi: 10.1109 / IAS.1989.96794. It shows that the switching of conduction paths must be done in a well-defined four-stepped switching order. Furthermore, it describes the importance of providing an overlap time for current source converters, which is comparable in value to the dead time or blanking time in voltage source inverters.

[0007] In the publication “Novel Three-Phase Two-Third-PWM Buck-Boost Current Source Inverter System Employing Dual-Gate Monolithic Bidirectional GaN e-FETs” by M. Guacci et al. (IEEE 10th International Symposium on Power Electronics for Distributed Generation Systems (PEDG), Xi'an, China, 2019, pp. 674-683, doi: 10.1109 / PEDG.2019.8807580) a three-phase current source inverter using gallium nitride transistors is disclosed. The transistors are monolithic bidirectional GaN enhancement-mode field effect transistors, which allow a controlled bidirectional current flow and can be used to increase the performance of current source inverters. This monolithic bidirectional switch resolves the traditional challenge of requiring a four-quadrant switch for current source converters. The publication also describesa two-thirds pulse-width modulation. An analogue current source converter with corresponding signal diagrams is also disclosed in US 2023 / 138129 Al.

[0008] Space vector modulation analysis, which was developed for voltage source inverters, is also applicable to current source inverters. This subject matter is shown in the publication “Current source inverter modulation” by G. Ledwich (IEEE Transactions on Power Electronics, vol. 6, no. 4, pp. 618-623, Oct. 1991, doi: 10.1109 / 63.97760). Moreover, this publication shows that pulse width modulation also applies to current source inverters.

[0009] A novel carrier-based pulse width modulation for a three phase current source converter is described in the publication “A novel carrier based PWM for current source converter” by N. S. Choi et al. (Proceedings of The 7th International Power Electronics and Motion Control Conference, 3, 1945-1950, 2012). The proposed pulse width modulation needs a special selector to assign proper gate signals.

[0010] In the publication “Algebraic Modulation Scheme for Current Source Converter” by W. Xiong et al. (IEEE Transactions on Power Electronics, vol. 38, no. 11, pp. 13770-13780, 2023, doi: 10.1109 / TPEL.2023.3304020) a modulation scheme for a three-phase current source converter is presented. The method is based on the solution of non-homogenous equations of converter current synthesis and provides two degrees of freedom. One degree of freedom is the free parameters in the duty ratio calculation and another degree of freedom is the switching sequence arrangement. Through this approach the three modulation strategies simple algebraic modulation, algebraic modulation with reduced common-mode voltage and algebraic modulation with reduced DC-link current ripple can be extended to multiphase CSCs.

[0011] In the publication “Current-Source Converter On-Line Pattern Generator Switching Frequency Minimization” by J. R. Espinoza and G. Joos (IEEE Transactions on Industrial Electronics, vol. 44, no. 2, pp. 198-206, 1997, doi: 10.1109 / 41.564158) two on-line pulse-width modulation pattern generators for three-phase current-source rectifiers and inverters are described. One of the two techniques is best suited for analogue control schemes, and it uses three dead-band modulating and a sawtooth carrier signal. The other technique is based on space vectors and thus best suited for digital control schemes.In the publication “Carrier-based Discontinuous PWM Modulation for Current Source Converters” by O. Ojo and S. Vanaparthy (Conference Record of the 2004 IEEE Industry Applications Conference, 2004. 39th IAS Annual Meeting. , Seattle, WA, USA, 2004, pp. 2224-2231 vol.4, doi: 10.1109 / IAS.2004.1348785) two different methods for the modulation of three-phase current source converters are presented. The two methods focus on the direct generalized discontinuous modulation of three-phase current source converters. The first method uses an approach similar to the classical space vector implementation, while the second method uses an approach based on the carrier based generalized discontinuous pulse-width modulation scheme for voltage source converters.

[0012] Summarizing, the previous modulation techniques for current source converters (CSCs) are based on space vector modulation (SVM) or pulse-width modulation (PWM). However, SVM is cumbersome and difficult to implement because it requires sector detections and calculation of vector dwell times. In addition, it averages CSC quantities at the level of the switching period, which prevents us from seeing and using all the degrees of freedom in the CSC. Furthermore, SVM is mainly limited to three-phase systems, as the complexity of the modulation increases with an increasing number of phases. The limitation to three-phase systems also applies to the above PWMs. In addition, these PWMs are still related to SVM due to sector identification requirement they impose.

[0013] SHORT DESCRIPTION OF THE INVENTION

[0014] In view of the above description of the background, the objective task of the invention is to provide an easy and simple method and modulator for controlling the on and off times or states of switches, also known as modulation, of a CSC. This invention also provides a modulator for current source converter, which is usable for each phase regardless of the total number of phases.

[0015] A solution is provided by a method for modulating an n-phase current source converter, comprising the steps:

[0016] a) obtaining duty ratio values, which are identified by using the following four substeps:

[0017] i. obtaining initial duty ratio values, which are used to determine required output currents, from the ratio of AC output current reference values and a DC supply current value,ii. determining excess duty ratio values, which are used to compensate a missing duty ratio value, wherein the missing duty ratio value results from the subtraction between 1 and a sum of the initial upper or initial lower duty ratio values, wherein the sum of initial upper duty ratio values equals the sum of initial lower duty ratio values,

[0018] iii. splitting the missing duty ratio value among converter legs that results in final duty ratio values and

[0019] iv. obtaining cumulative sums of the initial or final duty ratio values, which are supplied to a comparator array as thresholds,

[0020] b) comparing multiple thresholds through the comparison of the cumulative sums of the initial duty ratio values or final duty ratio values to a piecewise linear carrier signal, which results in n-1 digital signals obtained from n-1 comparators, wherein the comparing of multiple thresholds is performed by a first multiple threshold modulator for the upper switches and a second multiple threshold modulator for the lower switches, and

[0021] c) processing of the digital signals from a multiple threshold comparator to obtain gating signals by using a digital combinatorial logic.

[0022] The inventive method allows simple modulation of current source converters, such as current source inverters (CSI) or current source rectifiers (CSR). Furthermore, this method is not limited to three-phase systems. Also, the method is applicable in any system which requires a current provided by a current source to be directed to more than one of the output branches, such as in matrix converters.

[0023] The positive part of the ratio of AC output current reference values and the DC supply current value can apply as initial duty ratio value for the corresponding upper switch, while the negative part can apply as initial duty ratio value for the corresponding lower switch. This applies to all output currents and to the corresponding upper and lower switches.

[0024] The term switch refers to a device, which can lock voltage and current in both directions like a four-quadrant switch. Such switches are realized by using two metal-oxide-semiconductor field-effect transistors (MOSFETs) in series or by using one monolithic bidirectional switch.It is possible that both carrier signals have different shapes, phase shifts and even frequencies, as the proposed method to calculate initial duty ratio values allows to completely decouple piecewise linear carrier signals. Therefore, piecewise linear carrier signals can be the same within step b), although they might have different waveforms and frequencies. Besides that, the piecewise linear carrier signal for the upper switches can be different from the piecewise linear carrier signal for the lower switches, it is also possible that the same waveform can be used.

[0025] There are n-1 degrees of freedom split the missing duty ratio value among the converter legs, and therefore a plurality of methods can be used to share the missing duty ratio value.

[0026] Furthermore, the cumulative addition of the duty ratio values ensures that always only one of the switches in a group of upper or lower switches is switched on. Also, the n-1 values of the cumulative sums of the duty ratio values are independent, wherein the last value equals one.

[0027] The cumulative addition of the duty ratio values also ensure that the switches are activated and deactivated in a sequence. Thus, the switches are not on simultaneously, except during short commutation intervals. This sequential switching is crucial for the correct operation of the current source converter.

[0028] A multiple threshold comparator array makes a multiple threshold modulator (MTM).

[0029] In a preferred embodiment the first and second multiple threshold modulator are built identically. This allows a simplified process.

[0030] The digital combinatorial logic can be realized in hardware and / or software.

[0031] In some embodiments n is greater or equal 2 (n >= 2). This enables, for example, control of single-phase, three-phase, four-phase, five-phase or any higher-phase current source converters. Thus, the method is not limited to three-phase systems.

[0032] To provide the flow of the DC supply current through the upper switches, at any time point, one of the switches should be on. This result in a constraint for the duty ratio values of the upper switches. In this case the sum of the cumulative addition of the n duty ratio values for the upperswitches has to be equal to 1. The same condition for providing the flow of the DC supply current through the lower switches must be met.

[0033] To ensure the constraint where the duty ratio values add up to 1, the calculation of duty ratio values according to the claimed method is structured into two parts. The first part is the required part, based on the ratio of the converter output current reference and the converter DC supply current, where we obtain the so-called initial duty ratio values. While this ratio is positive, its value represents the upper switch duty ratio value for the corresponding phase, and the corresponding lower switch duty ratio value equals zero. On the other hand, while the ratio is negative, its negative value is duty ratio value for the corresponding lower switch, while the duty ratio value for the corresponding upper switch is zero. By multiplying the initial duty ratio values of the lower switches with -1, an overall positive number is obtained for the duty ratio value for the lower switches. In this manner, the initial duty ratio values for all upper switches and for all lower switches are obtained. The sum of these initial duty ratio values is not guaranteed to be equal to one. Since this sum should be equal to one, we need to deal with excess duty ratio values. Therefore, the excess duty ratio value for the upper or lower switches is added to the respective initial duty ratio values.

[0034] Since the converter DC supply current is required to flow at any time, the sum of upper switch duty ratio values, as well as the sum of all lower switch duty ratio values should be equal to 1. In the case the sum is greater than one, the converter cannot provide output currents specified by the reference values, and it saturates, operating in an overmodulation mode. In the other case, when the sum is lower than one, the duty ratio values should be increased such that they add up to one. The missing duty ratio value we define as one minus the sum of the initial upper duty ratio values, which is the same as one minus the sum of the initial lower duty ratio values. In order not to affect the converter output current waveforms, initial duty ratio values for upper switches should be increased by the same amount as for the corresponding initial duty ratio values for the lower switches. In this manner, this leaves n-1 degrees of freedom to share the missing duty ratio value between the inverter legs, comprising of n upper switches and the corresponding n lower switches. There are many ways to share the missing duty ratio value among the inverter legs. For example, an excess duty ratio dividing block can take excess duty ratio value as scalar input and produce a vector with the length of n-1. With this vector all the excess duty ratio values for different phases are given. One method is to share the missing duty ratio value among the converter legs equally. Another method is to assign the missing duty ratiovalue to only one inverter leg, the last one would be the simplest to achieve the lowest hardware or data processing requirements, while any inverter leg could be used for such purposes. Furthermore, the missing duty ratio value can be randomly distributed among the inverter legs, to spread the generated current high frequency spectrum in order to reduce electromagnetic interference. Also, the missing (excess) duty ratio can be spread in such a way that one final duty ratio value is equal to 1, while all other final duty ratio values are equal to 0. This spread reduces or minimize the switching losses. Within this context duty ratio values of 0 correspond to switches, which are permanently off, while duty ratio values of 1 correspond to switches, which are permanently on. Once the switch is on or off permanently, switching losses are zero. Overall, the n-1 degrees of freedom of sharing the missing duty ratio value may be used to optimize the inverter performance according to an optimization criterion.

[0035] To summarize, to generate duty ratio values both for upper and lower switches, the first step is to generate initial duty ratio values according to the converter de supply current and the output current reference values. To make the final duty ratio values for upper switches, as well as for the lower switches to add up to one, the missing duty ratio value is computed and shared among the duty ratio values assigning the additional duty ratio value to each converter leg, having the same value for the upper and the lower switch. The result are duty ratio values for upper switches and for lower switches, the total of 2n variables, n for upper switches, and n for lower switches. For both groups of the switches, upper and lower, the sum of the duty ratio values equals one. Thus, only n-1 duty ratio values in each group carry information, the last value in each group is required to add up to one. From this moment onward, processing of upper switches and lower switches is separated, although the methods of their processing are the same.

[0036] After the final duty ratio values are obtained, to control the converter according to the obtained final duty ratio values, gating signals for the switches should be generated. This process is performed by a multiple threshold modulator according to the invention. The nature of the commutation process is that in each time point one of the upper switches is conducting, as well as one of the lower switches. For each group of the switches, the conducting process is organized like a relay race where the conducting switch transfers its conducting state to the next switch. This is performed by applying a multiple threshold modulator in which each threshold corresponds to transfer of conduction from a conducting switch to the next one. The thresholds are obtained as cumulative sums of duty ratio values. Two such modulators are required, one that controls upper switches, and another one that controls lower switches. The modulators canshare the same piecewise linear carrier waveforms. However, the carrier waveforms might have different waveforms and even different frequency, which can be utilized to optimize the high frequency spectrum of generated currents in order to reduce the electromagnetic interference or to reduce the switching losses.

[0037] The digital signal obtained comparing the threshold values to the carrier waveform changes their value from 1 to 0 when the switch they apply to should be switched off. To generate gating signals that cover both turning on a switch and turning off the switch, a combinatorial logic processing is required. The process involves n-1 NOT logic circuits / operations and n-2 two input AND logic circuits / operations per group of switches, upper and lower.

[0038] A multiple threshold modulator, which performs the modulation process for an n-phase current source converter, comprises (n-1) Operational Amplifiers, which perform Compare operations, (n-1) Not Circuits, which perform NOT operations, and (n-2) And Circuits, which perform AND operations, wherein the multiple threshold modulator is configured in such a way that it receives n final duty ratio values or cumulative sums of final duty ratio values as input, as well as piecewise linear carrier signal as an additional input and processes the input signals into n digital gate signals as output, wherein states of upper switches of the current source converter are controllable with the digital gate signals from a first multiple threshold modulator, while states of lower switches of the current source converter are controllable with the digital gate signals from a second multiple threshold modulator. The second multiple threshold modulator is preferably identical to the first multiple threshold modulator.

[0039] The multiple threshold modulator can be implemented as analog, or as digital. In a digital implementation, the components can be realized using digital logic circuits, Field Programmable Gate Away (FPGA), application-specific integrated circuit (ASIC), or microcontrollers, for example.

[0040] According to Kirchhoff’s circuit laws the converter output currents must sum to zero, which leads to remaining n-1 degrees of freedom to choose values of the currents. Correspondingly, n-1 duty ratio values are used as input into the multiple threshold modulator, while the remaining duty ratio value, which is referred to as last duty ratio value or excess duty ratio value, is assigned to a last switch gate signal for the respective upper or lower switches. Thus, the last switches can be turned on for a longer duration, which ensures that all duty ratio valuescollectively sum to 1. Specifically, the modulator receives duty ratio values for the switches 1 to n-1 and calculates the last duty ratio value. The calculation is the same for the upper and lower switches. For the last duty ratio value for the upper switches, for example, you get 1 minus sum of n-1 duty ratio values of the upper switches. The multiple threshold modulator can edit the last duty ratio value for the upper or lower switches in such a way, that the sum of the n duty ratio values adds up to 1 automatically. This makes the proposed modulator robust to the provided duty ratio values. Alternatively, instead of assigning the excess duty ratio value solely to the last switch gate signal n, the excess duty ratio value can be distributed equally among all the duty ratio values. This approach enables the equalization of the conduction times of the switches and prevents the last switch from remaining continuously on at low duty ratio values.

[0041] If we only consider the average value of output current for the calculation of duty ratio values, it can happen that duty ratio values do not add up to 1. That remaining leftover is known as excess duty ratio value.

[0042] In a preferred embodiment, the excess duty ratio values are determined in the following way. First, for each phase k = 1...n, initial duty ratio values for the upper switches and for the lower switches are obtained from the ratio of the AC output current reference values and the DC supply current value, as already described. The sum of the initial upper duty ratio values is denoted Su0=

[0043]

[0044] and the sum of the initial lower duty ratio values is denoted S(o= Zk=n

[0045] k=lulOk-

[0046] Under normal operating conditions Su0and S(oare equal and less than or equal to 1. A missing duty ratio value dmissis then defined as dmiss= 1 — Su0= 1 — S(o.

[0047] The missing duty ratio value dmissis decomposed into phase-specific excess duty ratio values dexk which satisfy idexk= dmiss.

[0048] The final duty ratio values dukand dikare then obtained by adding the corresponding excess duty ratio values to the initial duty ratio values according to

[0049] dUk = duQk+ dexkfor the upper switches and

[0050] dik = di0k+ dexkfor the lower switches.In this way, the difference xy remains unchanged for each phase - and thus the average phase current resulting from the initial duty cycles (duk— dtk) while at the same time ensuring that the sum of the final duty cycles in each switch group is exactly equal to 1, i.e.,

[0051]

[0052] In some embodiments the n-1 degrees of freedom can be utilized to distribute the duty ratio values across phases. In this case, the duty ratio values are assigned according to any optimization criteria, which can enhance the high-frequency performance of current source converters. In order to spread the high-frequency spectrum and reduce the potential for electromagnetic interference, this distribution can be randomized, for example.

[0053] In a preferred embodiment an excess duty ratio handler is used to obtain n-1 cumulative sums of final duty ratios by distributing the excess duty ratio value and cumulative addition of n initial duty ratio values with the distributed excess duty ratio value.

[0054] To enable a kind of minimal modulation, the n-1 initial duty ratio values can be added cumulative through (n-2) Adders and afterwards given directly to the multiple threshold modulator. As there is no division of the excess duty ratio value, the whole excess duty ratio value is assigned to the last phase, for both the upper and lower switches.

[0055] In some embodiments a comparator is used to compare the cumulated final duty ratio values with the piecewise linear carrier signal. The resulting comparator outputs are used to generate the gate signals. For example, the previous and the subsequent comparator values are combined, wherein the previous comparator values are negated.

[0056] The AND gates in the excess duty ratio handler or the Adders are used for processing the input signals and ensuring the generated gate signals are proportional to the duty ratio values. Furthermore, the AND gate or Adder ensures an appropriate connection within a single switching period. Since this approach to modulation align with the operational requirements of sequential switching, it is particularly intuitive and natural for current source converters.DETAILED DESCRIPTION OF THE INVENTION

[0057] The foregoing and other objects, features and advantages of the invention will become more apparent from the following detailed description, which proceeds with reference to the accompanying figures.

[0058] Fig. 1 shows the method and two multiple threshold modulators according to the invention, wherein a first modulator modulates the upper switches, and a second modulator modulates the lower switches.

[0059] Fig. 2 illustrates an example of how the modulator operates using a sawtooth carrier signal.

[0060] Fig. 3 shows the implementation of excess duty ratio handler and multiple threshold modulators according to the invention, which uses time domain waveforms in Fig. 2 for piecewise linear carriers, and if equal share of the excess duty ratio value is used, ensures the waveforms like in Fig. 6.

[0061] Fig. 4 shows a minimal modulation where initial duty ratio values are fed directly to the multiple threshold modulator, leading to excess duty ratio value among all duty ratio values being assigned to the last phase.

[0062] Fig. 5 shows a triangular or sawtooth shaped carrier signal.

[0063] Fig. 6 resulting waveforms for the initial and final duty ratio values for equal distribution of excess duty ratio value across phases.

[0064] Fig. 7 resulting waveforms for initial and final duty ratio values where the excess duty ratio value is assigned to the last phase (minimal modulation).

[0065] Fig. 8 digital circuit realization of an ‘overlap circuit’ that ensures delay of the falling edge.

[0066] In Fig. 1 the inventive method for modulating an n-phase current source converter and an excess duty ratio Ad handler and a multiple threshold modulator are illustrated. The terms excess duty ratio and excess duty ratio value are used equally. AC output current reference values

[0067]

[0068] to

[0069]

[0070] and a DC supply current value Idcare used to calculate 2n initial duty ratio values - n initial duty ratio values for upper switches du0= (du01, duOn) and n duty ratio values for lower switches d(0= (dJ01, ...,d(On). Before being sent to the excess duty ratio handler, duty ratio vectors du0and d(0are split (Unbundling Point) into 2n individual signal lines. A ‘Upper Ad Handler’ receives n initial duty ratio values for the upper switches and a ‘Lower Ad Handler’ receives the n initial duty ratio values for the lower switches. Details on the implementation ofboth handlers are illustrated in Fig. 3. It is extremely important to notice an excess duty ratio vector Ad coupling between the upper and lower handlers. This coupling is necessary when the excess duty ratio values are handled, since per phase, the same excess duty ratio value must be applied for the upper and lower switches. The coupling excess duty ratio vector is n — 1 length and it contains info about n — 1 excess duty ratio values, i.e., Ad = (Ad1;...,Adn-1). The output of the upper Ad handler are n — 1 cumulative sums of the upper final duty ratio values, i.e., dul, dul+ du2, and so on up to Sfc i-1dufc, and these are fed to a first multiple threshold modulator. The output of the lower Ad handler are n — 1 cumulative sums of the lower final duty ratio values, i.e., d(1, d(1+ d;2, and so on up to Sfc i-1difc, and these are fed to a second multiple threshold modulator. Therefore, the first multiple threshold modulator receives the n-1 cumulative sums of the final duty ratio values for the upper switches as input and a piecewise linear carrier signal for the upper switches’ cuas an additional input. The second multiple threshold modulator receives the n-1 cumulative sums of the final duty ratio values for the lower switches as input and piecewise linear carrier signal for the lower switches ci as an additional input. The piecewise linear carrier signal for the upper switches is completely decoupled from the piecewise linear carrier signal for the lower switches. This means they are independent from each other, which can result in different shapes, phase shifts and even frequencies of carrier signals. A possible triangular or sawtooth shaped carrier signal is shown in Fig. 5. Because of the independence of both carrier signals, the upper and lower switches can operate at a different switching frequency. This enables a degree of freedom, which is not achievable with SVM and can be leveraged to optimize the high-frequency operation of the current source converter. Both multiple threshold modulators are processing the respective carrier signal and the respective n-1 cumulative sums of final duty ratio values into first n gate signals Suito Sunand second n gate signals Sn to Sin. The second index in the gate signals is a number between 1 and n, which represents the phase number. The first n gate signals can control the upper switches of a current source converter, while the second n gate signals control the lower switches of a current source converter.

[0071] These first n gate signals Suito Sunand second n gate signals Sn to Sin are digital signals that denote on and off states of the MOSFETs in the power stage of the CSI. In practice, these signals need to have their falling edges delayed ensuring so called ‘overlap time’ so that a proper commutation occurs in the CSI. These are called ‘commutation sequences’ and were not discussed yet, as they are known and considered trivial to implement by people skilled in the art. In the power stage, for simplicity reasons, only MOSFET with the diode in series is shown.There are embodiments where two MOSFETs in anti-series can be used, or monolithic bidirectional switches can be used. Both of these options can leverage the provided first n gate signals Suito Sunand second n gate signals Sn to Sin, the user only needs to take care of a proper commutation sequence, which is trivial for persons skilled in art and therefore, here considered prior art.

[0072] Fig. 2 shows an example of how the modulator for the upper switches operates using a sawtooth carrier signal for the upper switches. Such a process can be identical for modulator for the lower switches and a carrier signal for the lower switches. The figure shows the use of sequentially added the duty ratio values for the upper switches. These cumulative signals are necessary for comparators. Through the cumulative addition of the duty ratio values, it is ensured that the switches are activated and deactivated in sequence, which is decisive for the operation of the current source converter. Final additional logic processing after the comparators ensures that the switches do not turn on simultaneously, except for the overlap time during commutation. However, the commutation handling corresponds to the prior art.

[0073] Details on handling the excess duty ratio Ad and forming the cumulative sums of final duty ratio values and comparing them to a sawtooth carrier signal is shown in Fig. 3. The ‘Handling Ad’ part in Fig. 3 ensures the time domain waveforms from Fig. 2 for the upper switches according to the invention, and for the lower switches the same waveforms are ensured. The ‘Handling Ad’ part in Fig. 3 takes n initial duty ratio values, distributes the excess duty ratio Ad according to the invention, adds them cumulatively and finally obtains n-1 cumulative sums of final duty ratio values for the ‘Modulation’ part. Afterwards in the ‘Modulation’ part of Fig.

[0074] 3, n-1 comparators compare the cumulated final duty ratio values with the carrier signal for the upper and lower switches. This results in the comparator outputs, which are used to generate gate signals for the upper and lower switches. Previous comparator output values are negated by using a Not gate. Subsequently, the previous comparator values and subsequent comparator values are combined and processed through an AND gate. The AND gate automatically ensures that the duty ratio values are properly connected, and the generated gate signals are proportional to the duty ratio values.

[0075] Instead of dealing with division of the excess duty ratio Ad, we can have ‘Minimal Modulation’ like shown in Fig. 4, where n-1 initial duty ratio values are cumulatively added up and given to the multiple threshold modulator directly, without previous division of the excess duty ratio. Inthis case, where no prior division of the excess duty ratios is done, according to the invention of the MTM, MTM will assign all of the excess duty ratios Ad to the last phase, for the lower and for the upper switches. Therefore, the excess duty ratio of the last phase is An= Ad = 1 —

[0076]

[0077] d-iok- According to the invention, the sums for the upper and lower initial duty ratio values are equal:

[0078]

[0079] diok- The waveforms guaranteed by this operation are shown in Fig. 7.

[0080] The following describes how the initial or final duty ratio values are used in the comparator array. In a first group of embodiments, the multiple threshold modulator receives cumulative sums of the final duty ratio values dukand dikas thresholds in step b). Since the missing duty ratio value dmisshas already been distributed among the phases as explained above, the sum of all final duty ratio values for each group of switches (upper and lower) is equal to 1. Therefore, the constraint that at any time exactly one upper switch and exactly one lower switch conduct the DC supply current is fulfilled.

[0081] In an alternative set of embodiments, which may also be referred to as “minimal modulation,” cumulative sums of at most k-1 initial duty cycles are used as threshold values in step b). In this case, the multiple-threshold modulator is designed to internally calculate at least one final duty cycle value as the remainder to 1. For the upper switch group, this can be done, for example, according to

[0082]

[0083] while for the lower switch group

[0084]

[0085] applies. The final duty ratio value determined in this way corresponds to an excess duty ratio value that is completely assigned to the last phase. This ensures that even if initial duty ratios are used in step b), the totality of the duty ratios effectively used by the modulator circuit in each switch group is always normalized to 1.

[0086] Fig. 5 shows a triangular or sawtooth shaped carrier signal, wherein carrier signals for the upper switches cuand lower switches ci of current source converter pulse width modulation are piecewise linear and can be different. Fig. 5 also indicates that each final duty ratio value from the n final duty ratio values is ranging from 0 to 1.Fig. 7 shows example waveforms for a three phase CSI in case of the equal distribution of the excess duty ratio. Graph (a) in Fig. 7 shows DC supply current Idcand the waveforms for current references i15i2, and i3. These are inputs for the modulation method, like depicted in Fig. 1. In the graphs (b) and (c) of Fig. 6, resultant initial duty ratio values are shown, obtained according to the invention by the block ‘Obtaining Initial Duty Ratios’ from Fig. 1. In Fig. 6 graph (d) the waveforms of the resultant excess duty ratio Ad and the excess duty ratios per phase Ad1,Ad2, Ad3are shown. Equal share of the excess duty ratio is exemplified in this

[0087]

[0088] figure, therefore: Adx= Ad2= Ad3= In Fig. 6 graph (e) and (f), final duty ratio values

[0089]

[0090] for the upper and lower switches, obtained according to the invention for the equal share of the excess duty ratio value, are shown. The final duty ratio values for the upper switches are calculated as: dul= du01+ Adx, du2=du02 + d2, and du3= du03+ Ad3, whereas for the lower switches they are: d(1= d(01+ Adx, d2= d(02+ Ad2, and d(3= d(03+ Ad3. It should be noted that according to the invention, the same excess duty ratio value per phase is used for the upper and the lower switches. Also, according to the invention, the final duty ratio values for the upper and for the lower switches add up to 1.

[0091] In Fig. 7, resultant waveforms for the final duty ratio values in case of the assigning the whole excess duty ratio value to the last phase are shown, called ‘Minimal Modulation’ in Fig. 4. Note that waveforms in the graphs (a), (b) and (c) of Fig. 7 are identical to the ones in the graphs (a), (b) and (c) of Fig. 6. In Fig. 7 graph (d) we see that the whole excess duty ratio value is assigned to the last phase: Ad3= Ad. Therefore, the excess duty ratio values for the first two phases are zero, i.e., Adx= Ad2= 0. The resultant final duty ratio values for the upper and the lower switches are depicted in Fig. 7 graph (e) and (f). It should be noted that in this case duty ratio values have moments when they are equal to zero - for the first two phases dul, du2, dtand d2in total 180° each. In moments when final duty ratio values are equal to zero, there is no switching in the converter, i.e., the corresponding gate signals in these moments are off or in digital terms Tow’ state. For example, when dul= 0 -> SU1= 'off . From here we can see that distribution of excess duty ratio Ad has significant impact on the converter performance (e.g. switching losses), and it can be used to optimize the converter operation according to the application requirements. There are numerous ways to distribute the excess duty ratio across the phases. Accordingly, the abovementioned can be considered as an example embodiment of a distribution of the excess duty ratio. The converter according to the invention and the method according to the invention are applicable to any distribution of the excess duty ratio.Fig. 8 shows digital realization of an ‘overlap circuit’ that ensures delay of the falling edge of obtained gate signals, which can be applied to ensure overlap during for the commutation of the current source converter.

Claims

CLAIMS1. Method for modulating an n-phase current source converter, comprising the steps: a) obtaining duty ratio values, which are identified by using the following four substeps:i. obtaining initial duty ratio values, which are used to determine required output currents, from the ratio of AC output current reference values and a DC supply current value,ii. determining excess duty ratio values, which are used to compensate a missing duty ratio value, wherein the missing duty ratio value results from the subtraction between 1 and a sum of the initial upper or initial lower duty ratio values, wherein the sum of initial upper duty ratio values equals the sum of initial lower duty ratio values,iii. splitting the missing duty ratio value among converter legs that results in final duty ratio values andiv. obtaining cumulative sums of the initial or final duty ratio values, which are supplied to a comparator array as thresholds,b) comparing multiple thresholds through the comparison of the cumulative sums of the initial duty ratio values or final duty ratios to a piecewise linear carrier signal, which results in n-1 digital signals obtained from n-1 comparators, wherein the comparing of multiple thresholds is performed by a first multiple threshold modulator for the upper switches and a second multiple threshold modulator for the lower switches, andc) processing of the digital signals from a multiple threshold comparator to obtain gating signals by using a digital combinatorial logic.

2. Method according to claim 1, wherein n is greater or equal to 2.

3. Method according to claim 1 or 2, wherein the first and second multiple threshold modulator are built identically.

4. Method according to any of the claims 1 to 3, wherein the missing duty ratio value is shared equally or distributed randomly among the inverter legs.

5. Method according to any of the claims 1 to 3, wherein the missing duty ratio value is assigned to one converter leg, preferably the last inverter leg.

6. Method according to any of the claims 1 to 3, wherein the missing duty ratio value is spread in such a way that one final duty ratio value is equal to 1, while all other final duty ratio values are equal to 0.

7. Method according to any of the claims 1 to 6, wherein the combinatorial logic is realized in hardware and / or software.

8. Multiple threshold modulator, which performs the modulation process for an n-phase current source converter, comprises(n-1) Operational Amplifiers, which perform Compare operations,(n-1) Not Circuits, which perform NOT operations, and(n-2) And Circuits, which perform AND operations,wherein the multiple threshold modulator is configured in such a way that it receives n final duty ratio values or cumulative sums of final duty ratio values as input, as well as piecewise linear carrier signal as an additional input and processes the input signals into n digital gate signals as output, wherein states of upper switches of the current source converter are controllable with the digital gate signals from a first multiple threshold modulator, while states of lower switches of the current source converter are controllable with the digital gate signals from a second multiple threshold modulator.

9. Multiple threshold modulator according to claim 8, wherein the first and second multiple threshold modulator are built identically.

10. Multiple threshold modulator according to claim 8 or 9, wherein the multiple threshold modulator is implemented as analog.

11. Multiple threshold modulator according to claim 8 or 9, wherein the multiple threshold modulator is implemented as digital.

12. Multiple threshold modulator according to claim 11, wherein a digital implementation of the multiple threshold modulator is realized by using digital logic circuits, FPGA, ASIC or microcontrollers.

13. Multiple threshold modulator according to any of the claims 8 to 12, wherein an excess duty ratio handler is used to obtain n-1 cumulative sums of final duty ratio values.

14. Multiple threshold modulator according to any of the claims 8 to 12, wherein the n-1 initial duty ratio values are added cumulative through (n-2) Adders and afterwards given directly to the multiple threshold modulator.

15. Multiple threshold modulator according to any of the claims 8 to 14, wherein a comparator is used to compare the cumulated final duty ratio values with the piecewise linear carrier signal.

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