A dynamic voltage adjustment system and adjustment method

Abstract

The present invention discloses a dynamic voltage adjustment system and adjustment method, the system includes a main controller, a power management chip and at least one computing chip, the computing chip is used to detect that the error rate of the computing result exceeds the preset threshold value, and then send the computing error information to the main controller; the main controller is used to send a power adjustment command to the power management chip according to the computing error information to adjust the power supply voltage of the computing chip. Under the condition of fixed frequency, the present invention controls the chip power consumption by reducing the voltage, can effectively and maximally reduce the chip power supply voltage, and through hardware detection, can greatly shorten the voltage detection and adjustment time, and improve the power efficiency of the chip and the system.

Description

Technical Field

[0001] The present invention relates to a dynamic voltage adjustment technology, and in particular to a dynamic voltage adjustment system and adjustment method for controlling power consumption by dynamically reducing voltage. Background Art

[0002] With the development of integrated circuit technology, the scale of chips is getting larger and larger, and power consumption has become an increasingly important issue in integrated circuit design. Dynamic Voltage Frequency Scaling (DVFS) technology is a dynamic voltage frequency adjustment technology currently widely used in the semiconductor field. DVFS technology specifically dynamically adjusts the operating frequency and voltage of the chip to achieve the purpose of energy saving. This technology is currently being increasingly used in high-performance computing (HPC) systems, such as multi-core central processing units (CPUs) and tensor processing units (TPUs).

[0003] There are two main solutions for dynamically adjusting the voltage and frequency of existing chips. One is software processing, but software processing requires many clock cycles to complete data analysis and adjustment, and is mostly based on judging the idle time of the CPU. For example, the patent application publication number CN103345296A discloses a technology named "Dynamic Voltage and Frequency Adjustment Triggering Device and Method", and its main principle is: when the timing period ends, the idle rate calculator and the DVFS interrupt generator are triggered by the timer; the idle rate calculator calculates the processor idle rate within the timing period that ends based on the trigger; the DVFS interrupt generator determines whether the processor idle rate within the timing period that ends based on the trigger exceeds the upper or lower limit of the current processor power consumption level, and if it exceeds the upper or lower limit of the current processor power consumption level, an interrupt signal is issued. The second is to use the digital logic time margin to adjust the chip's operating voltage or frequency. For example, the patent application publication number CN103426453A discloses a technology called "Dynamic Voltage Frequency Adjustment Method and System". Its main principle is: real-time monitoring of the memory's operating voltage, calculation to determine the memory's current required operating frequency, and the target voltage corresponding to the frequency, respectively comparing the target voltage, the current voltage, and the memory's lowest voltage preset value, and determining the target value of the read operation reserved gap value based on the target voltage, so that when the memory is at the target voltage, the memory's read operation reserved time gap is sufficient. Therefore, on the basis of ensuring the accuracy of the memory read operation, the memory's operating voltage can be adjusted to be lower than the preset lowest operating voltage to reduce the memory's operating energy consumption.

[0004] However, both of the above solutions have the problem that the detection and adjustment time is long to a certain extent and the implementation is relatively complicated.

[0005] In existing large digital chips, such as CPU, TPU, DSP (Digital Signal Processing) and GPU (Graphics Processing Unit), the relationship between power consumption, voltage and frequency is shown in the following formula:

[0006] P=aCFV 2 ;

[0007] Among them, P is the workload (power), a is a constant, C is the load capacitance, F is the frequency, and V is the power supply voltage of the digital part of the chip. From the above formula, it can be seen that the power consumption and voltage are in a square relationship, so reducing the voltage has the greatest benefit on power consumption control. Summary of the invention

[0008] The object of the present invention is to overcome the defects of the prior art and provide a dynamic voltage adjustment system and adjustment method which can effectively reduce the voltage and shorten the adjustment time.

[0009] To achieve the above object, the present invention proposes the following technical solution: A dynamic voltage adjustment system comprises: a main controller, a power management chip and at least one computing chip, wherein:

[0010] At least one of the computing chips is in communication with the main controller, and is used to detect its computing error rate, and send computing error information to the main controller after the error rate exceeds a preset threshold value;

[0011] The main controller is in communication connection with the power management chip, and is used for collecting the operation error information reported by the operation chip, and issuing a power adjustment command to the power management chip according to the operation error information;

[0012] The power management chip is connected to the computing chip, and is used for receiving the power adjustment command of the main controller and providing the computing chip with a corresponding power supply voltage.

[0013] Preferably, there are multiple computing chips, and the multiple computing chips are powered in series or in parallel.

[0014] Preferably, the computing chip includes a replication computing core and a statistical judgment unit, wherein:

[0015] The copy operation core is used to receive preset operands, calculate corresponding operation results through algorithms and output them to the statistical judgment unit;

[0016] The statistical judgment unit is used to judge whether the calculation result is correct, and to count the number of calculation errors within a set time, calculate the calculation error rate according to the ratio of the number of calculation errors to the total number of execution operations, and send the calculation error information to the main controller after the error rate exceeds a preset threshold value.

[0017] Preferably, the statistical judgment unit is preset with a reference result for detecting whether the calculation result output by the copy calculation core is correct. The statistical judgment unit is used to compare the calculation result it receives with the reference result. If the two are consistent, the calculation result is judged to be correct; if they are inconsistent, the calculation result is judged to be wrong.

[0018] Preferably, a preset threshold value is also preset in the statistical judgment unit, and the statistical judgment unit is used to compare the calculated operation error rate with the preset threshold value. If the error rate exceeds the preset threshold value, the operation error information is sent to the main controller.

[0019] Preferably, the main controller simultaneously receives error information reported by multiple computing chips, and determines whether to issue a power adjustment command to the power management chip based on at least the power supply voltage value, power consumption, and computing power of the computing chip to control the power management chip to adjust the power supply voltage of the computing chip.

[0020] Preferably, the computing chip further includes at least one computing core, and the structure of the computing core is the same as or similar to that of the duplicate computing core.

[0021] Preferably, the computing chip is communicatively connected to the main controller via a bus.

[0022] Preferably, a power MOSFET tube for controlling power is installed inside or outside the power management chip, and the power management chip controls the MOSFET tube to provide power supply voltage to the computing chip.

[0023] Preferably, the power management chip may at least be a HIP630x chip or a TL494 chip.

[0024] Preferably, the main controller may at least adopt FPGA or an embedded processor with integrated ARM core.

[0025] The present invention also proposes another technical solution: a dynamic voltage adjustment method, comprising:

[0026] S1, at least one computing chip detects its computing error rate, and after the error rate exceeds a preset threshold value, sends computing error information to a main controller;

[0027] S2, the main controller collects the operation error information reported by the operation chip, and sends a power adjustment command to the power management chip according to the operation error information;

[0028] S3, the power management chip receives the power adjustment command from the main controller and provides a corresponding power supply voltage to the computing chip.

[0029] Preferably, the S1 includes:

[0030] S11, the replica operation core receives a preset operand, calculates a corresponding operation result through an algorithm and outputs it to the statistical judgment unit;

[0031] S12, the statistical judgment unit determines whether the calculation result is correct, and counts the number of calculation errors within a set time, calculates the calculation error rate according to the ratio of the number of calculation errors to the total number of execution operations, and sends the calculation error information to the main controller after the error rate exceeds the preset threshold value.

[0032] Preferably, in S12, the statistical judgment unit judging whether the calculation result is correct specifically includes: the statistical judgment unit compares the calculation result it receives with its built-in reference result, and if the two are consistent, the calculation result is judged to be correct; if they are inconsistent, the calculation result is judged to be wrong.

[0033] Preferably, in S12, after the error rate exceeds the preset threshold value, sending the operation error information to the main controller specifically includes: a statistical judgment unit is used to compare the calculated operation error rate with the built-in preset threshold value, and if the error rate exceeds the preset threshold value, sending the operation error information to the main controller.

[0034] The beneficial effects of the present invention are:

[0035] 1. A dynamic voltage adjustment system and adjustment method are proposed to control the chip power consumption by reducing the voltage under the condition of fixed frequency, which can effectively and maximally reduce the power supply voltage of the digital part of the chip.

[0036] 2. Through hardware detection, the voltage detection and adjustment time can be greatly shortened, and the power efficiency of computing chips and high-performance computing systems can be improved.

[0037] 3. The application advantages are more obvious in multi-computing chip systems with series power supply and parallel power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a structural schematic diagram of a dynamic voltage adjustment system for series power supply of the present invention;

[0039] Figure 2 It is a structural schematic diagram of a dynamic voltage adjustment system for parallel power supply of the present invention;

[0040] Figure 3 It is a schematic diagram of the structure inside the computing chip of the present invention;

[0041] Figure 4 It is a schematic flow diagram of the method of the present invention;

[0042] Figure 5 It is a flowchart of a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The technical solutions of the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention.

[0044] The present invention discloses a dynamic voltage adjustment system and adjustment method, which can achieve a better effect of reducing chip working energy consumption by reducing the voltage to the maximum extent under the condition of fixed frequency.

[0045] Combination Figure 1 and Figure 2 As shown, a dynamic voltage adjustment system disclosed in an embodiment of the present invention is a high performance computing system (HPC system), which includes: a main controller, a power management chip and at least one computing chip, wherein the computing chip is the core part of the HPC system and is used for data calculation, such as tensor operation, encryption operation, etc. Figure 3 As shown, a computing chip is generally a chip including at least one built-in computing core (ie, an arithmetic logic unit). When there are multiple computing cores, such as dozens or even hundreds, the structures and functions of these computing chips are the same or similar.

[0046] Different from the structure of the existing computing chip, the embodiment of the present invention adds a replica computing core and a statistical judgment unit in the computing chip, wherein the structure of the replica computing core is the same or similar to the structure of the existing computing core in the computing chip, and can perform the same function as the existing computing core without performing the detection function of the present invention. In the embodiment of the present invention, the replica computing core is mainly used to receive preset operands to its own algorithm unit, such as the tensor algorithm or encryption algorithm, etc. After the encryption algorithm is performed on the operand, the algorithm unit will output a fixed operation result to the statistical judgment unit accordingly.

[0047] In this embodiment, a reference result is preset in the statistical judgment unit for detecting whether the calculation result output by the copy operation core is correct. The statistical judgment unit is mainly used to compare the calculation result output by the copy operation core it receives with the reference result in itself. If the two are consistent, it means that the calculation result of the copy operation core is correct. If they are inconsistent, it means that the calculation result is wrong. Regardless of whether the calculation result determined by the statistical judgment unit is correct or not, the copy operation core continues to perform the algorithm calculation of the next operand after the statistical judgment unit determines the result. When the statistical judgment unit determines that the calculation result is wrong, it will count the number of calculation errors of the copy operation core within a set time, such as by a certain time counter.

[0048] Furthermore, after the statistical judgment unit counts the number of operation errors of the copied operation core within the set time, it is also used to calculate the operation error rate of the operation chip based on the ratio of the number of operation errors to the total number of operations performed within the set time. For example, the total number of operations performed within the set 1s time is 10,000 times, and the number of operation errors counted within the 1s is 5 times, then the calculated operation error rate is 0.0005.

[0049] In this embodiment, a preset threshold value is also preset in the statistical judgment unit, and the threshold value is configurable. The statistical judgment unit compares the above-calculated operation error rate with the preset threshold value. If the error rate exceeds the preset threshold value, the operation error information is sent to the main controller. The operation chip is connected to the main controller through a bus.

[0050] In this embodiment, combined with Figure 1 and Figure 2 As shown, the computing chips can be connected in series or in parallel, and can be used in multiple computing chip systems with series power supply and parallel power supply. In series connection, if 20 computing chips are connected in series, and the power supply voltage required for each computing chip is 1V, then the total power supply voltage required for the 20 series computing chips is 20V; in parallel connection, if 20 computing chips are connected in parallel, and the power supply voltage required for each computing chip is 1V, then the total power supply voltage required for the 20 parallel computing chips is 1V.

[0051] In addition, the present invention detects the computing performance by duplicating the computing core and the statistical judgment unit in the computing chip. The duplicating the computing core and the statistical judgment unit here can detect the computing performance by hardware time. Compared with the existing software processing, the hardware detection can shorten the detection and adjustment time.

[0052] The main controller is connected to the computing chip in a two-way communication manner through a digital interface such as a bus. In this embodiment, the main controller is mainly used to collect the computing error information reported by the computing chip, and issue a power adjustment command to the power management chip based on the computing error information. Specifically, when there are multiple computing chips, the main controller receives the error information reported by multiple computing chips at the same time or almost at the same time, and based on this information and the actual working power supply voltage value of the computing chip (i.e., P=aCFV in the power consumption formula), the main controller can adjust the power supply voltage of the computing chip to adjust the power supply voltage of the computing chip. 2 The value of parameter V in the power consumption formula (i.e., P = aCFV 2 The value of the parameter P in the calculation chip), computing power and other factors are used to determine whether to issue a power adjustment command to the power management chip to control the power management chip to adjust the supply voltage of the computing chip.

[0053] Take a parallel system consisting of 100 computing chips as an example. When the main controller receives a report from a computing chip that the error rate exceeds the threshold value, the main controller will query the firmware (the firmware here refers to the driver program stored inside the main controller) to make a corresponding judgment on whether to set the power consumption priority or the computing power priority principle. If the computing power is prioritized, the main controller will issue a power adjustment command to increase the voltage, which is used to increase the power supply voltage of the computing chip so that the error rate of this computing chip is reduced below the threshold value. If the firmware sets power consumption priority, the main controller will further compare the percentage of increased power consumption caused by increasing the power supply voltage to restore the computing chip to normal operation and the percentage of computing power of this computing chip in the entire HPC system of this application. If the percentage of computing power occupied by this computing chip is lower than the percentage of increased power consumption caused by increasing the power supply voltage to restore this computing chip to normal operation, the main controller will not issue a power adjustment command to increase the voltage. Otherwise, it will issue a power adjustment command to increase the voltage.

[0054] During implementation, the main controller may be a Field-Programmable Gate Array (FPGA), an embedded processor with an integrated ARM core, or the like.

[0055] The power management (Voltage Regulator Module, VRM) chip is connected to the main controller and the computing chip. On the one hand, it is used to receive the power adjustment command of the main controller and generate the corresponding power supply voltage to power the computing chip according to the power adjustment command; on the other hand, the computing chip sends the computing error information to the main controller. Specifically, the power management chip has a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Chinese full name Metal-Oxide Semiconductor Field Effect Transistor) tube for controlling the power supply. The power management chip controls the MOSFET tube to provide the power supply voltage to the computing chip, and the specific power supply voltage value provided is controlled by the main controller. During implementation, the power management chip can be used, such as HIP630x chip, TL494 chip, etc.

[0056] Based on the above dynamic voltage adjustment system, such as Figure 4 As shown, the embodiment of the present invention also discloses a dynamic voltage adjustment method, including:

[0057] S1, at least one computing chip detects its computing error rate, and after the error rate exceeds a preset threshold value, sends computing error information to a main controller.

[0058] Specifically, combined Figure 5 As shown, the duplicate computing core in the computing chip receives preset operands to its own algorithm unit, and the algorithm unit outputs a fixed computing result to the statistical judgment unit. The statistical judgment unit compares the computing result output by the duplicate computing core it receives with the reference result within itself. If the two are consistent, it means that the computing result of the duplicate computing core is correct. If they are inconsistent, it means that the computing result is wrong. When the statistical judgment unit determines that the computing result is wrong, it will count the number of computing errors of the duplicate computing core within the set time, and calculate the computing error rate of the computing chip according to the ratio of the number of computing errors and the total number of computing operations performed within the set time. The statistical judgment unit compares the above-calculated computing error rate with the preset threshold value. If the error rate exceeds the preset threshold value, the computing error information is sent to the main controller.

[0059] S2, the main controller collects the operation error information reported by the operation chip, and sends a power adjustment command to the power management chip according to the operation error information.

[0060] Specifically, when there are multiple computing chips, the main controller receives error information reported by multiple computing chips simultaneously or almost simultaneously, and based on this information and in combination with various factors such as the actual working power supply voltage value, power consumption, and computing power of the computing chip, determines whether to issue a power adjustment command to the power management chip to control the power management chip to adjust the power supply voltage of the computing chip.

[0061] S3, the power management chip receives the power adjustment command from the main controller and provides the corresponding power supply voltage to the computing chip.

[0062] Specifically, the power management chip has a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) tube for controlling the power supply. The power management chip controls the MOSFET tube to provide power supply voltage to the computing chip, and the specific power supply voltage value provided is controlled by the main controller.

[0063] The present invention can minimize the power supply voltage of the computing chip and the working power consumption of the entire system by dynamically adjusting the voltage based on the error rate judgment of the computing chip in combination with the other information mentioned above, thereby achieving better power consumption control results than the existing calculation of idle time and time margin and shortening the detection and adjustment time.

[0064] The technical contents and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention and are covered by the claims of this patent application.

Claims

1. A dynamic voltage adjustment system, characterized in that: include: A main controller, a power management chip and at least one computing chip, wherein: At least one of the computing chips is in communication with the main controller, and is used to detect its computing error rate, and send computing error information to the main controller after the error rate exceeds a preset threshold value, wherein the computing chip includes a replica computing core and a statistical judgment unit, wherein: The copy operation core is used to receive preset operands, calculate corresponding operation results through algorithms and output them to the statistical judgment unit; The statistical judgment unit is used to judge whether the operation result is correct, and to count the number of operation errors within a set time, calculate the operation error rate according to the ratio of the number of operation errors to the total number of execution operations, and send the operation error information to the main controller after the error rate exceeds a preset threshold value; The main controller is in communication connection with the power management chip, and is used for collecting the operation error information reported by the operation chip, and issuing a power adjustment command to the power management chip according to the operation error information; The power management chip is connected to the computing chip and is used to receive the power adjustment command of the main controller and provide the computing chip with a corresponding power supply voltage, wherein: The main controller sends a power adjustment command to the power management chip according to the operation error information, including: Query the firmware and determine whether to set power consumption priority; In response to the power consumption priority, the percentage of increased power consumption caused by increasing the power supply voltage to restore the computing chip to normal operation and the percentage of computing power of the computing chip in the entire HPC system are compared; In response to a percentage lower than the computing power percentage of the computing chip in the entire HPC system, no power adjustment command is issued. In response to a percentage higher than the computing power percentage of the computing chip in the entire HPC system, a power adjustment command to increase the voltage is issued.

2. The dynamic voltage adjustment system according to claim 1, characterized in that: There are multiple computing chips, and the multiple computing chips are connected in series or in parallel for power supply.

3. The dynamic voltage adjustment system according to claim 1, characterized in that: The statistical judgment unit is preset with a reference result for detecting whether the calculation result output by the copy calculation core is correct. The statistical judgment unit is used to compare the calculation result it receives with the reference result. If the two are consistent, the calculation result is judged to be correct; if they are inconsistent, the calculation result is judged to be wrong.

4. The dynamic voltage adjustment system according to claim 1, characterized in that: The statistical judgment unit is also preset with a preset threshold value, and is used to compare the calculated operation error rate with the preset threshold value. If the error rate exceeds the preset threshold value, the operation error information is sent to the main controller.

5. The dynamic voltage adjustment system according to claim 1, characterized in that: The main controller simultaneously receives error information reported by multiple computing chips, and determines whether to issue a power adjustment command to the power management chip based on at least the power supply voltage value, power consumption, and computing power of the computing chip to control the power management chip to adjust the power supply voltage of the computing chip.

6. The dynamic voltage adjustment system according to claim 1, characterized in that: The computing chip further includes at least one computing core, and the structure of the computing core is the same as or similar to that of the duplicate computing core.

7. A dynamic voltage adjustment method based on the dynamic voltage adjustment system according to any one of claims 1 and 3 to 6, characterized in that: include: S1, at least one computing chip detects its computing error rate, and after the error rate exceeds a preset threshold value, sends computing error information to a main controller; S2, the main controller collects the operation error information reported by the operation chip, and sends a power adjustment command to the power management chip according to the operation error information; S3, the power management chip receives the power adjustment command from the main controller and provides a corresponding power supply voltage to the computing chip.

8. The dynamic voltage adjustment method according to claim 7, characterized in that: The S1 includes: S11, the replica operation core receives a preset operand, calculates a corresponding operation result through an algorithm and outputs it to the statistical judgment unit; S12, the statistical judgment unit determines whether the calculation result is correct, and counts the number of calculation errors within a set time, calculates the calculation error rate according to the ratio of the number of calculation errors to the total number of execution operations, and sends the calculation error information to the main controller after the error rate exceeds the preset threshold value.

9. The dynamic voltage adjustment method according to claim 8, characterized in that: In S12, the statistical judgment unit judges whether the calculation result is correct specifically includes: the statistical judgment unit compares the received calculation result with its built-in reference result, if the two are consistent, the calculation result is judged to be correct, if not, the calculation result is judged to be wrong.

10. The dynamic voltage adjustment method according to claim 8, characterized in that: In S12, after the error rate exceeds the preset threshold value, sending the operation error information to the main controller specifically includes: a statistical judgment unit is used to compare the calculated operation error rate with the built-in preset threshold value, and if the error rate exceeds the preset threshold value, the operation error information is sent to the main controller.

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