Semiconductor device

Abstract

The present invention relates to a semiconductor device, which improves the reliability of the semiconductor device. A wiring (M2a) is formed on a semiconductor substrate with an interlayer insulating film therebetween, an interlayer insulating film (IL3) is formed on the interlayer insulating film so as to cover the wiring (M2a), and a pad (PD1) is formed on the interlayer insulating film (IL3). A stacked film (LM) having an opening (OP3) exposing the pad (PD1) is formed on the interlayer insulating film (IL3), and a rewiring (RW) electrically connected to the pad (PD1) is formed on the stacked film (LM) including above the pad (PD1) exposed from the opening (OP3). An end portion of the wiring (M2a) is located below a connection region (CN) between the pad (PD1) and the rewiring (RW). A plurality of openings (SL) are formed in the wiring (M2a), and at least a part of the plurality of openings (SL) overlaps with the connection region (CN) in a plan view.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device that can be suitably used for a semiconductor device having a redistribution formed after forming a pad. Background Art

[0002] There is a technique for manufacturing a semiconductor device by forming a redistribution after forming a bonding pad.

[0003] Japanese Patent Application Laid-Open No. 2003-264256 (Patent Document 1) describes a technique for a semiconductor device having a Cu wiring 10 formed after forming a bonding pad BP. Japanese Patent Application Laid-Open No. 2000-183214 (Patent Document 2) and Japanese Patent Application Laid-Open No. 6-53211 (Patent Document 3) describe a technique for providing a slit in a wiring layer.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-264256

[0005] Patent Document 2: Japanese Patent Application Laid-Open No. 2000-183214

[0006] Patent Document 3: Japanese Patent Application Laid-Open No. 6-53211 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] In a semiconductor device having a redistribution formed after forming a pad, it is desired to improve reliability.

[0009] Other problems and new features will become apparent from the description of the present specification and the accompanying drawings.

[0010] Solutions to the Problems

[0011] According to one embodiment, a semiconductor device includes: a first wiring formed on a semiconductor substrate with a first interlayer insulating film interposed therebetween; a second interlayer insulating film formed on the first interlayer insulating film so as to cover the first wiring; and a first pad formed on the second interlayer insulating film. The semiconductor device further includes: a first insulating film formed on the second interlayer insulating film and having a first opening exposing the first pad; a second wiring formed on the first insulating film including above the first pad exposed from the first opening and electrically connected to the first pad; and a second pad formed on the first insulating film and integrally connected to the second wiring. An end portion of the first wiring is located below a connection region between the first pad and the second wiring, and a plurality of second openings are formed in the first wiring. In a plan view, at least a part of the plurality of openings overlaps with the connection region.

[0012] Effects of the Invention

[0013] According to one embodiment, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional view of a main part of a semiconductor device according to one embodiment.

[0015] Figure 2 is a cross-sectional view of a main part of a semiconductor device according to one embodiment.

[0016] Figure 3 is a top view of a semiconductor device according to one embodiment.

[0017] Figure 4 is a perspective plan view of a semiconductor device according to one embodiment.

[0018] Figure 5 is a cross-sectional view of a main part in a manufacturing process of a semiconductor device according to one embodiment.

[0019] Figure 6 is next Figure 5 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0020] Figure 7 is next Figure 6 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0021] Figure 8 is next Figure 7 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0022] Figure 9 is next Figure 8 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0023] Figure 10 is next Figure 9 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0024] Figure 11 is next Figure 10 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0025] Figure 12 is the same as Figure 11 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0026] Figure 13 is next Figure 11 a cross-sectional view of a main part in a manufacturing process of the semiconductor device.

[0027] Figure 14 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that is the same as Figure 13 .

[0028] Figure 15 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that follows Figure 13 .

[0029] Figure 16 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that is the same as Figure 15 .

[0030] Figure 17 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that follows Figure 15 .

[0031] Figure 18 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that is the same as Figure 17 .

[0032] Figure 19 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that follows Figure 17 .

[0033] Figure 20 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that is the same as Figure 19 .

[0034] Figure 21 is a cross-sectional view of a main part in the manufacturing process of a semiconductor device that follows Figure 20 .

[0035] Figure 22 is a cross-sectional view of a semiconductor package of an embodiment.

[0036] Figure 23 is a cross-sectional view of a main part of a semiconductor device of an embodiment.

[0037] Figure 24 is a top view of a main part of a semiconductor device of an embodiment.

[0038] Figure 25 is a top view of a main part of a semiconductor device of an embodiment.

[0039] Figure 26 is a top view of a main part of a semiconductor device of an embodiment.

[0040] Figure 27 is a top view of a main part of a semiconductor device of an embodiment.

[0041] Figure 28Cross-sectional view of the main part of the semiconductor device in the research example mode.

[0042] Figure 29 Top view of the main part of the semiconductor device in the research example mode.

[0043] Figure 30 Top view of the main part of the semiconductor device in the research example mode.

[0044] Figure 31 Top view of the main part of the semiconductor device in one embodiment.

[0045] Figure 32 Top view of the main part of the semiconductor device in one embodiment.

[0046] Figure 33 Top view of the main part of the semiconductor device in one embodiment.

[0047] Figure 34 Cross-sectional view of the main part of the semiconductor device in the first modified example mode.

[0048] Figure 35 Top view of the main part of the semiconductor device in the first modified example.

[0049] Figure 36 Top view of the main part of the semiconductor device in the first modified example.

[0050] Figure 37 Top view of the main part of the semiconductor device in the second modified example.

[0051] Figure 38 Top view of the main part of the semiconductor device in the second modified example.

[0052] Figure 39 Top view of the main part of the semiconductor device in the second modified example.

[0053] Figure 40 Top view of the main part of the semiconductor device in the second modified example.

[0054] Figure 41 Top view of the main part of the semiconductor device in the third modified example.

[0055] Figure 42 Top view of the main part of the semiconductor device in the third modified example.

[0056] Figure 43 Top view of the main part of the semiconductor device in the third modified example.

[0057] Figure 44 Top view of the main part of the semiconductor device in the third modified example.

[0058] (Symbol Explanation)

[0059] CN: Connection region; IL1, IL2, IL3: Interlayer insulating film; LF: Insulating film; LM: Stacked film; M1, M2, M2a, M2b, M2c, M3, M102a, M102b, M102c: Wiring; OP1, OP2, OP3, OP4, SL: Opening; PD1, PD2: Pad; PA: Protective film; PL1: Resin film; RG1, RG2: Opening formation region; RW: Rewiring; SB: Semiconductor substrate. Detailed Embodiment

[0060] In the following embodiments, when necessary for ease of explanation, the description is divided into multiple parts or embodiments. However, unless otherwise specifically stated, they are not unrelated to each other. One is a variant, detailed description, supplementary explanation, etc. of a part or all of the other. Additionally, in the following embodiments, when referring to the quantity of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specifically stated and in cases where it is clearly limited to a specific quantity in principle, it is not limited to that specific quantity and can be more than the specific quantity or less than the specific quantity. Also, in the following embodiments, the structural elements (including element steps, etc.) are not necessarily required unless otherwise specifically stated and in cases where it is clearly considered necessary in principle, which goes without saying. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the structural elements, unless otherwise specifically stated and in cases where it is clearly considered not to be the case in principle, it includes substantially similar or analogous things to that shape, etc. This also applies to the above-mentioned numerical values and ranges.

[0061] Next, the embodiments will be described in detail based on the drawings. In addition, in all the drawings used to illustrate the embodiments, the same symbols are attached to the components having the same functions, and the repeated description thereof is omitted. Also, in the following embodiments, unless otherwise particularly necessary, the description of the same or similar parts is not repeated in principle.

[0062] In addition, in the drawings used in the embodiments, there are cases where even in cross-sectional views, shading is omitted for ease of observing the drawings. There are also cases where even in top views, shading is added for ease of observing the drawings.

[0063] (Embodiment)

[0064] <Regarding the Structure of the Semiconductor Device>

[0065] Figure 1 and Figure 2 are the main partial cross-sectional views showing the cross-sectional structure of the semiconductor device of the present embodiment.Figure 1 and Figure 2 Cross-sectional views at different positions in the semiconductor device corresponding to this embodiment, in Figure 1 shows a cross-section cutting across the pad PD1, and in Figure 2 shows a cross-section cutting across the pad PD2. In addition, in Figure 2 for simplicity of the drawing, the illustration of the interlayer insulating film IL2 and the structure below it is omitted, but actually, below the cross-sectional structure of Figure 2 there is also a structure similar to the interlayer insulating film IL2 and the structure below it shown in Figure 1 .

[0066] The semiconductor device of this embodiment is a semiconductor device (semiconductor chip) manufactured using a semiconductor substrate SB made of single crystal silicon or the like.

[0067] On the semiconductor substrate SB made of single crystal silicon or the like that constitutes the semiconductor device (semiconductor chip) of this embodiment, various elements (semiconductor elements) are formed as needed. As the elements formed on the semiconductor substrate SB, transistor elements such as MISFETs (Metal Insulator Semiconductor Field Effect Transistors), memory elements, capacitor elements, or resistor elements can be exemplified. In Figure 1 as an example, a case where a capacitor element CT is formed on the semiconductor substrate SB is shown, but in an unillustrated area, transistor elements such as MISFETs are also formed on the semiconductor substrate SB. The capacitor element CT is, for example, a capacitor element used for power supply stabilization.

[0068] The capacitor element CT is, for example, a PIP (Polysilicon Insulator Polysilicon) type capacitor element, but it can also be a MIM (Metal Insulator Metal) type capacitor element. When the capacitor element CT is of the PIP type, the capacitor element CT has a polysilicon film PS1 as the lower electrode, a polysilicon film PS2 as the upper electrode, and an insulating film YZ as the capacitor insulating film (dielectric film). In Figure 1 this case, a polysilicon film PS1 is formed on the element isolation region ST formed in the semiconductor substrate SB using the STI (Shallow Trench Isolation) method or the like, and a polysilicon film PS2 is formed on the polysilicon film PS1 with the insulating film YZ interposed therebetween.

[0069] In addition, here, a single-crystalline silicon substrate is cited as the semiconductor substrate SB for description. However, as another method, an SOI (Silicon On Insulator) substrate or the like can also be used as the semiconductor substrate SB.

[0070] On the semiconductor substrate SB, a multilayer wiring structure is formed by a plurality of interlayer insulating films and a plurality of wiring layers. That is, a plurality of interlayer insulating films IL1, IL2, and IL3 are formed on the semiconductor substrate SB, and plugs V1, via holes V2 and V3, and wirings M1, M2, and M3 are formed in the plurality of interlayer insulating films IL1, IL2, and IL3.

[0071] Specifically, on the semiconductor substrate SB, an interlayer insulating film IL1 is formed as an insulating film so as to cover the elements formed on the semiconductor substrate SB, and a wiring M1 is formed on the interlayer insulating film IL1. The wiring M1 is a wiring of the first wiring layer (the lowermost wiring layer). On the interlayer insulating film IL1, an interlayer insulating film IL2 is formed as an insulating film so as to cover the wiring M1, and a wiring M2 is formed on the interlayer insulating film IL2. The wiring M2 is a wiring of the second wiring layer which is the wiring layer above the first wiring layer. On the interlayer insulating film IL2, an interlayer insulating film IL3 is formed as an insulating film so as to cover the wiring M2, and a wiring M3 is formed on the interlayer insulating film IL3. The wiring M3 is a wiring of the third wiring layer which is the wiring layer above the second wiring layer.

[0072] The plug V1 is made of a conductor and is formed below the wiring M1, that is, formed in the interlayer insulating film IL1 so as to penetrate the interlayer insulating film IL1. The upper surface of the plug V1 is in contact with the lower surface of the wiring M1, thereby being electrically connected to the wiring M1. In addition, the bottom of the plug V1 is connected to the element. For example, the bottom of the plug V1 is connected to the polysilicon film PS1 or polysilicon film PS2 constituting the capacitor element CT, or the gate electrode or source / drain region of a MISFET (not shown). Thus, the wiring M1 is electrically connected to various elements formed on the semiconductor substrate SB via the plug V1.

[0073] The via hole V2 is made of a conductor and is formed between the wiring M2 and the wiring M1, that is, formed in the interlayer insulating film IL2 to connect the wiring M2 and the wiring M1. The via hole V2 can also be formed integrally with the wiring M2. In addition, the via hole V3 is made of a conductor and is formed between the wiring M3 and the wiring M2, that is, formed in the interlayer insulating film IL3 to connect the wiring M3 and the wiring M2. The via hole V3 can also be formed integrally with the wiring M3.

[0074] In the semiconductor device of the present embodiment, the third wiring layer, i.e., wiring M3, is the uppermost wiring layer. That is, the desired wiring of the elements formed on the semiconductor substrate SB is performed through the first wiring layer (wiring M1), the second wiring layer (wiring M2), and the third wiring layer (wiring M3), so that the desired operation can be performed.

[0075] The pad (pad region, pad electrode, bonding pad) PD1 is formed through the third wiring layer which is the uppermost wiring layer. That is, the pad PD1 and the wiring M3 are formed on the same layer. That is to say, the wiring M3 and the pad PD1 are formed through the same conductive layer in the same process. Therefore, the pad PD1 is formed on the interlayer insulating film IL3. The pad PD1 can also be regarded as a part of the wiring M3, but the entire wiring M3 is covered by the insulating film LF, while at least a part of the pad PD1 is exposed from the opening OP1 of the insulating film LF.

[0076] Among them, a part of the pad PD1 is covered by the insulating film LF. That is, the pad PD1 is exposed from the opening OP1 of the insulating film LF, but the part of the pad PD1 that does not overlap with the opening OP1 when viewed from above is covered by the insulating film LF. Specifically, the central portion of the upper surface of the pad PD1 is not covered by the insulating film LF, and the outer peripheral portion and the side surface of the upper surface of the pad PD1 are covered by the insulating film LF. Before forming the rewiring RW, the pad PD1 can also be used to test whether the semiconductor device performs the desired operation (probe test described later).

[0077] In addition, "viewed from above" means the case of observing on a plane substantially parallel to the main surface of the semiconductor substrate SB.

[0078] Preferably, the pad PD1 is made of a conductive material (a conductive material showing metal conduction) mainly composed of aluminum. Examples of preferred materials for the pad PD1 include compounds or alloys of Al (aluminum) and Si (silicon), or compounds or alloys of Al (aluminum) and Cu (copper), or compounds or alloys of Al (aluminum), Si (silicon), and Cu (copper). Among the materials (conductive materials mainly composed of aluminum) constituting the pad PD1, preferably, the composition ratio of Al (aluminum) is greater than 50 atomic percent (i.e., rich in Al), and more preferably 97 atomic percent or more. In addition, Figure 1 One pad PD1 is shown, but in fact, one or more pads PD1 are formed, and preferably, a plurality of pads PD1 are formed.

[0079] The pad PD1 is connected to a wiring M3 formed integrally with the pad PD1. The wiring M3 formed integrally with the pad PD1 is connected to the wiring M2 via a via hole portion V3 provided directly below the wiring M3, whereby the pad PD1 can be electrically connected to the wiring M2. As another method, a via hole portion V3 can also be provided directly below the pad PD1, and the pad PD1 can be electrically connected to the wiring M2 via the via hole portion V3.

[0080] In addition, Figure 1 shows a case where the number of wiring layers (excluding the rewiring RW) formed on the semiconductor substrate SB is 3 layers (a case of a total of 3 layers of wirings M1, M2, and M3), but the number of wiring layers is not limited to 3 layers, and various changes can be made as long as there are 2 or more layers (i.e., a plurality of layers). However, if the number of wiring layers (excluding the rewiring RW) is 3 or more layers, it is easier to perform the layout design of the wirings, so it is more preferable.

[0081] As Figure 1 and Figure 2 shown, on the interlayer insulating film IL3, an insulating film (laminated insulating film) LF is formed so as to cover the wiring M3. A resin film PL1 is formed on the insulating film LF, and a rewiring (reconfigured wiring) RW is formed on the resin film PL1. That is, on the interlayer insulating film IL3, a laminated film of the insulating film LF and the resin film PL1 on the insulating film LF is formed so as to cover the wiring M3, and the rewiring RW is formed on the laminated film.

[0082] The insulating film LF is an insulating film that functions as a passivation film. Here, it is composed of a laminated film of a silicon oxide film LF1 and a silicon oxynitride film LF2 on the silicon oxide film LF1. A silicon nitride film can also be used instead of the silicon oxynitride film LF2. The silicon oxynitride film and the silicon nitride film are excellent as insulating films for passivation films. Therefore, by including the silicon oxynitride film or the silicon nitride film in the insulating film LF, the insulating film LF can function properly as a passivation film.

[0083] Preferably, the resin film PL1 is a polyimide film (polyimide resin film). The polyimide film is a polymer containing imide bonds as repeating units and is a kind of organic insulating film. Polyimide-based resins are organic resins suitably used for devices requiring high heat resistance of 200 °C or more. As the resin film PL1, other organic insulating films such as epoxy-based, PBO-based, acrylic-based, and WRP-based resins can also be used in addition to the polyimide film. When the insulating film LF is composed of a laminated film of a silicon oxide film LF1 and a silicon oxynitride film LF2 on the silicon oxide film LF1, the resin film PL1 is formed on the silicon oxynitride film LF2.

[0084] The insulating film LF has an opening OP1 that exposes at least a part of the pad PD1, and the resin film PL1 has an opening OP2 that includes the opening OP1 of the insulating film LF therein. That is, when viewed from above, the opening OP1 of the insulating film LF is included inside the pad PD1 and is also included inside the opening OP2 of the resin film PL1. Therefore, the planar dimension (planar area) of the opening OP1 is smaller than that of the pad PD1, and the planar dimension of the opening OP2 is larger than that of the opening OP1. Accordingly, the part of the pad PD1 exposed from the opening OP1 of the insulating film LF is not covered by the resin film PL1 and is exposed from the opening OP2 of the resin film PL1.

[0085] After forming a stacked film of a silicon oxide film LF1 and a silicon oxynitride film LF2 on the silicon oxide film LF1 (i.e., the insulating film LF), photolithography technology and etching technology are used to form the opening OP1 in this stacked film. Therefore, the opening (OP1) of the silicon oxynitride film LF2 matches (is continuous with) the opening (OP1) of the silicon oxide film LF1. That is, the opening OP1 of the insulating film LF is composed of the opening (OP1) of the silicon oxynitride film LF2 and the opening (OP1) of the silicon oxide film LF1, and the planar shape and planar dimension of the opening (OP1) of the silicon oxynitride film LF2 are substantially the same as those of the opening (OP1) of the silicon oxide film LF1, and their planar positions are substantially aligned.

[0086] On the other hand, the resin film PL1 is formed after the opening OP1 is formed in the stacked film of the silicon oxide film LF1 and the silicon oxynitride film LF2 (the insulating film LF). Therefore, the planar dimension of the opening OP2 of the resin film PL1 can be made different from the planar dimension of the opening OP1 of the insulating film LF. In the present embodiment, the planar dimension of the opening OP2 of the resin film PL1 is larger than that of the opening OP1 of the insulating film LF. When viewed from above, the opening OP2 of the resin film PL1 is included inside the opening OP1 of the insulating film LF.

[0087] Accordingly, at least a part of the pad PD1 is exposed from the opening OP1 of the insulating film LF, the part of the pad PD1 exposed from the opening OP1 of the insulating film LF is exposed from the opening OP2 of the resin film PL1, and the insulating film LF constituting the peripheral portion of the opening OP1 is also exposed.

[0088] The pad PD1 is exposed from the opening OP1 of the insulating film LF, and a rewiring RW is also formed on the pad PD1 exposed from the opening OP1. In addition, a rewiring RW is also formed on the insulating film LF of the part exposed from the opening OP2 of the resin film PL1. That is, the rewiring RW is formed on the resin film PL1 including above the pad PD1 exposed from the opening OP1 and above the insulating film LF exposed from the opening OP2, and is electrically connected to the pad PD1.

[0089] When viewed from above, the opening OP1 is included inside the opening OP2, and the opening OP2 is included inside the rewiring RW. Therefore, the upper surface of the pad PD1 that forms the bottom surface of the opening OP1 (i.e., the upper surface of the pad PD1 of the portion exposed from the opening OP1), the side surface of the insulating film LF that forms the side wall of the opening OP1, the upper surface of the insulating film LF exposed from the opening OP2, and the side surface of the resin film PL1 that forms the side wall of the opening OP2 are covered by the rewiring RW.

[0090] The rewiring RW is a wiring that leads out the pad PD1, which is a part of the uppermost wiring layer (here, the third wiring layer), to a desired area (pad PD2) of the semiconductor chip. That is, the rewiring RW is formed in such a manner that it extends on the resin film PL1 from the pad PD1 exposed from the opening OP1 of the insulating film LF to the pad PD2 on the resin film PL1.

[0091] The pad (pad area, pad electrode, bonding pad) PD2 and the rewiring RW are formed on the same layer by the same process through the same conductive layer. Therefore, the pad PD2 is also formed on the resin film PL1. The pad PD2 is formed integrally with the rewiring RW and is electrically connected, and is electrically connected to the pad PD1 via the rewiring RW. In addition, Figure 2 only one pad PD2 is shown, but in fact, one or more pads PD2 are formed in the semiconductor device, and preferably, a plurality of pads PD2 are formed. In addition, Figure 1 and Figure 2 for ease of observing the drawings, regarding the rewiring RW and the pad PD2, the copper film CF and the seed film SE, which will be described later, are shown integrally without being separated.

[0092] On the resin film PL1, an insulating protective film PA is formed so as to cover the rewiring RW. Since the protective film PA is an insulating film, it can also be regarded as a protective insulating film. The rewiring RW is covered and protected by the protective film PA. As the protective film PA, a resin film is preferred, and for example, a polyimide film (polyimide resin film) can be appropriately used. The protective film PA becomes the outermost film of the semiconductor device (semiconductor chip). By using a resin film such as a polyimide film as the protective film PA, advantages such as improved reliability and easy handling of the semiconductor device can be obtained.

[0093] The pad PD2 is exposed from the opening OP4 of the protective film PA. That is, an opening OP4 is provided in the pad PD2, whereby the pad PD2 is exposed from the opening OP4 of the protective film PA. The planar shapes of the pad PD2 and the opening OP4 can each be set to a circular shape, for example. A bump electrode BP is formed on the pad PD2 exposed from the opening OP4 of the protective film PA. When viewed from above, the opening OP4 of the protective film PA is included inside the pad PD2. In addition, Figure 2 shows a case where the bump electrode BP is formed on the pad PD2 with a base metal film UM interposed therebetween. Regarding the base metal film UM, its formation can also be omitted, but it is more preferably formed.

[0094] Figure 3 is a top view (overall top view) of the semiconductor device (semiconductor chip) CP of the present embodiment, showing the arrangement of the bump electrodes BP in the semiconductor device CP. In addition, the bump electrode BP is formed on the pad PD2 as described above Figure 2 shown, so the arrangement of the pads PD2 in the semiconductor device CP is the same as the Figure 3 arrangement of the bump electrodes BP therein. Figure 4 is a plan perspective view of the semiconductor device CP of the present embodiment, showing the arrangement of the pads PD1 in the semiconductor device CP. In addition, the above Figure 1 corresponds to a cross-section cutting across the pad PD1 in the semiconductor device CP, and the above Figure 2 corresponds to a cross-section cutting across the pad PD2 and the bump electrode BP thereon in the semiconductor device CP. When viewed from above, the pad PD1 is separated from the pad PD2, and the redistribution wiring RW extends in such a way as to connect a plurality of pads PD1 and a plurality of pads PD2 respectively, which is not shown in Figure 3 and Figure 4 .

[0095] The redistribution wiring RW is a wiring that electrically connects the pads PD1 in each chip region of the semiconductor wafer (semiconductor substrate) to the mounting electrodes (corresponding to the pad PD2 and the bump electrode BP thereon in the present embodiment), and the mounting electrodes are used to mount the semiconductor chips (CP) obtained by singulating the semiconductor wafer into each chip region on a predetermined wiring substrate. The redistribution wiring RW has a function of making the pads PD1 restricted by the dimensions of the wafer process and the mounting electrodes restricted by the dimensions of the package process match in size.

[0096] That is, the dimensions of the above-described mounting electrodes (the dimensions of the electrodes themselves and the adjacent intervals, pitches, etc.) are restricted by the dimensions on the wiring substrate side, and thus require dimensions relatively larger than the dimensions of the pads PD1 (the dimensions of the pads themselves and the adjacent intervals, pitches, etc.). Therefore, instead of directly using the fine pads PD1 that are restricted by the wafer process for the mounting electrodes, the pads PD1 are led out to a free area with a relatively large area on the main surface of the chip region through the rewiring RW, and mounting electrodes (here, the pads PD2 and the bump electrodes BP thereon) with relatively large dimensions and pitches are arranged in this area. The planar dimensions and arrangement pitches of the pads PD2 can be made larger than those of the pads PD1, and on the upper surface of the semiconductor device CP, the pads PD2 and the bump electrodes BP thereon can be arranged (aligned) in, for example, an array form. Thereby, the semiconductor device CP can be easily and accurately mounted on the wiring substrate.

[0097] <Regarding the manufacturing process of the semiconductor device>

[0098] Next, the manufacturing process of the semiconductor device of the present embodiment will be described. The above-described Figures 1 to 4 semiconductor device is manufactured through the following manufacturing process.

[0099] Figures 5 to 21 is a main part cross-sectional view in the manufacturing process of the semiconductor device of the present embodiment. In Figures 5 to 21 In, in Figures 5 to 11 , Figure 13 , Figure 15 , Figure 17 and Figure 19 the cross-sectional views of the regions corresponding to the above-described Figure 1 are shown, and in Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 and Figure 21 the cross-sectional views of the regions corresponding to the above-described Figure 2 are shown. In addition, in order to simplify the drawings, in Figures 9 to 21 the illustration of the interlayer insulating film IL2 and the structure thereunder is omitted.

[0100] First, as Figure 5 shown, a semiconductor substrate (semiconductor wafer) SB made of, for example, p-type single crystal silicon having a resistivity of about 1 to 10 Ωcm is prepared (preliminarily).

[0101] Next, on the main surface of the semiconductor substrate SB, element isolation regions ST are formed, for example, by using the STI (Shallow Trench Isolation) method or the like.

[0102] Next, in the semiconductor substrate SB, elements (semiconductor elements) such as MISFETs (not shown) are formed in the active regions defined (delimited) by the element isolation regions ST. In addition, a capacitor element CT can also be formed on the element isolation region ST. For example, after forming a polysilicon film, patterning is performed thereon, whereby a polysilicon film PS1 is formed on the element isolation region ST, an insulating film and a polysilicon film are formed so as to cover the polysilicon film PS1, and then patterning is performed on them, whereby an insulating film YZ and a polysilicon film PS2 are formed, and thus a capacitor element CT can be formed.

[0103] Next, as Figure 6 shown, an interlayer insulating film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SB. The interlayer insulating film IL1 is formed so as to cover various elements formed in the semiconductor substrate SB. Therefore, when a MISFET (not shown) is formed in the active region of the semiconductor substrate SB, the MISFET is also covered by the interlayer insulating film IL1. In addition, when a capacitor element CT is formed on the element isolation region ST, the capacitor element CT is also covered by the interlayer insulating film IL1. The interlayer insulating film IL1 is composed of, for example, a single film of a silicon oxide film, or a stacked film of a silicon nitride film and a silicon oxide film thereon. After the formation of the interlayer insulating film IL1, if necessary, the upper surface of the interlayer insulating film IL1 is polished by a CMP (Chemical Mechanical Polishing) method or the like to planarize the upper surface of the interlayer insulating film IL1.

[0104] Next, a photoresist layer (not shown) formed on the interlayer insulating film IL1 using photolithography technology is used as an etching mask to dry-etch the interlayer insulating film IL1, thereby forming a contact hole in the interlayer insulating film IL1. Thereafter, a conductive film is buried in the contact hole, thereby forming a conductive plug (connection conductor portion) V1 as Figure 6 shown.

[0105] To form the plug V1, for example, a barrier conductor film (such as a titanium film, a titanium nitride film, or a stacked film thereof) is formed on the interlayer insulating film IL1 including the bottom surface and side walls of the contact hole by a sputtering method or a plasma CVD method or the like. Thereafter, a main conductor film composed of a tungsten film or the like is formed on the barrier conductor film so as to fill the contact hole by a CVD method or the like. Thereafter, unnecessary main conductor film and barrier conductor film outside the contact hole are removed by a CMP method or an etch-back method or the like. As a result, the upper surface of the interlayer insulating film IL1 is exposed, and the plug V1 is formed by the barrier conductor film and the main conductor film remaining after being buried in the contact hole of the interlayer insulating film IL1.

[0106] Next, as Figure 7As shown, a wiring M1 of the first wiring layer as the lowest wiring layer is formed on the interlayer insulating film IL1 in which the plug V1 is buried. In order to form the wiring M1, first, a conductive film for the first wiring layer is formed on the interlayer insulating film IL1 in which the plug V1 is buried. The conductive film is composed of, for example, a barrier conductor film, an aluminum film, and a stacked film of a barrier conductor film in this order from the bottom, and can be formed using a sputtering method or the like. The aluminum film in the conductive film can be regarded as an aluminum film for forming the wiring M1. As the barrier conductor film, for example, a titanium film, a titanium nitride film, or a stacked film thereof can be used. Thereafter, the conductive film is patterned using a photolithography technique and an etching technique, thereby forming the wiring M1. The plug V1 is electrically connected to the wiring M1 by contacting the wiring M1 with its upper surface.

[0107] The aluminum film used to form the wiring M1 is not limited to a pure aluminum film, and a conductive material film with aluminum as the main component can be used (however, a conductive material film that exhibits metal conduction). For example, a compound film or alloy film of Al (aluminum) and Si (silicon), or a compound film or alloy film of Al (aluminum) and Cu (copper), or a compound film or alloy film of Al (aluminum), Si (silicon) and Cu (copper) can be preferably used as the aluminum film used to form the wiring M1. In addition, it is preferred that the composition ratio of Al (aluminum) in the aluminum film is greater than 50 atomic percent (i.e., rich in Al), and it is more preferred if it is 97 atomic percent or more. This applies not only to the aluminum film used to form the wiring M1, but also to the aluminum film used to form the wiring M2, and the aluminum film used to form the wiring M3 and the pad PD1. Therefore, the wirings M1, M2, and M3 are all aluminum wirings with aluminum (Al) as the main component, and the pad PD1 is an aluminum pad with aluminum as the main component.

[0108] Then, if Figure 7 As shown, on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the interlayer insulating film IL1, an interlayer insulating film IL2 is formed so as to cover the wiring M1. The interlayer insulating film IL2 is composed of a silicon oxide film or the like, and can be formed using a CVD method or the like. After the interlayer insulating film IL2 is formed, the upper surface of the interlayer insulating film IL2 can be polished using a CMP method or the like as needed to improve the flatness of the upper surface of the interlayer insulating film IL2.

[0109] Next, a photoresist layer (not shown) formed on the interlayer insulating film IL2 using a photolithography technique is used as an etching mask to dry-etch the interlayer insulating film IL2, thereby forming a through hole in the interlayer insulating film IL2. Thereafter, a conductive film is embedded in the through hole, thereby forming a conductive through hole portion (connecting conductor portion) V2. The through hole portion V2 can also be regarded as a conductive plug. The through hole portion V2 can be formed using the same method as the plug V1, but the material of the conductive film of the through hole portion V2 can also be different from that of the plug V1. For example, it can also be set as follows: the plug V1 is mainly composed of a tungsten film, and the through hole portion V2 is mainly composed of an aluminum film.

[0110] Then, if Figure 8 As shown, a wiring M2 of the second wiring layer is formed on the interlayer insulating film IL2 in which the through hole portion V2 is embedded. In order to form the wiring M2, first, a conductive film for the second wiring layer is formed on the interlayer insulating film IL2 in which the through hole portion V2 is embedded. The conductive film is composed of, for example, a barrier conductor film, an aluminum film, and a laminated film of a barrier conductor film in order from the bottom, and can be formed using a sputtering method or the like. The aluminum film in the conductive film can be regarded as an aluminum film for forming the wiring M2. As the barrier conductor film, for example, a titanium film, a titanium nitride film, or a laminated film thereof can be used. Thereafter, the conductive film is patterned using a photolithography technique and an etching technique, thereby forming the wiring M2. The through hole portion V2 is electrically connected to the wiring M1 by connecting to the wiring M1 on its lower surface, and is electrically connected to the wiring M2 by connecting to the wiring M2 on its upper surface. That is, the through hole portion V2 electrically connects the wiring M1 to the wiring M2. The wiring M2 includes wirings M2a, M2b, and M2c described later.

[0111] In addition, the case where the through-hole portion V2 and the wiring M2 are formed by different processes is described here. As another method, the through-hole portion V2 and the wiring M2 can also be formed by the same process. In this case, the through-hole portion V2 and the wiring M2 are formed integrally. In this case, after a through hole for the through-hole portion V2 is formed in the interlayer insulating film IL2, a conductive film (conductive film for the second wiring layer) is formed on the interlayer insulating film IL2 in a manner to fill the through hole, and then the conductive film is patterned using photolithography technology and etching technology, thereby forming the wiring M2. Thus, the wiring M2 is formed, and the through-hole portion V2 formed integrally with the wiring M2 is also formed.

[0112] Then, if Figure 8As shown, on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the interlayer insulating film IL2, an interlayer insulating film IL3 is formed so as to cover the wiring M2. The interlayer insulating film IL3 is composed of a silicon oxide film or the like, and can be formed using a CVD method or the like. After the interlayer insulating film IL3 is formed, the upper surface of the interlayer insulating film IL3 can be polished using a CMP method or the like as needed to improve the flatness of the upper surface of the interlayer insulating film IL3.

[0113] Next, a photoresist layer (not shown) formed on the interlayer insulating film IL3 using photolithography technology is used as an etching mask to dry-etch the interlayer insulating film IL3, thereby forming a through hole in the interlayer insulating film IL3. Thereafter, a conductive film is embedded in the through hole, thereby forming a conductive through hole portion (connecting conductor portion) V3. The through hole portion V3 can also be regarded as a conductive plug. The through hole portion V3 can be formed using the same conductive material and the same method as the through hole portion V2. In addition, regarding the through hole portion V3, not shown in FIG. Figure 8 As shown in the above Figure 2 Shown in.

[0114] Then, if Figure 9 As shown in FIG. 1 , on the interlayer insulating film IL3 in which the via portion V3 is embedded, the wiring M3 of the third wiring layer and the pad PD1 are formed. Figure 2 In addition, as mentioned above, Figure 9 In order to simplify the drawings, the interlayer insulating film IL2 and the structure thereunder are omitted from the drawings. However, in fact, Figure 9 There is also a cross-sectional structure Figure 8 The interlayer insulating film IL2 and the structure thereunder are shown.

[0115] In order to form the wiring M3 and the pad PD1, first, a conductive film for the third wiring layer is formed on the interlayer insulating film IL3 in which the through hole portion V3 is buried. The conductive film CD2 is composed of, for example, a barrier conductor film, an aluminum film, and a stacked film of a barrier conductor film in order from the bottom, and can be formed using a sputtering method or the like. The conductive film is a conductive film for the third wiring layer, but also serves as a conductive film for forming the pad PD1. The aluminum film in the conductive film can be regarded as an aluminum film for forming the wiring M3 and the pad PD1. As the barrier conductor film, for example, a titanium film, a titanium nitride film, or a stacked film thereof can be used. Thereafter, the conductive film is patterned using a photolithography technique and an etching technique, thereby forming the wiring M3 and the pad PD1. The through hole portion V3 is electrically connected to the wiring M2 by connecting to the wiring M2 on its lower surface, and is electrically connected to the wiring M3 or the pad PD1 by connecting to the wiring M3 or the pad PD1 on its upper surface. That is, the via portion V3 electrically connects the wiring M2 and the wiring M3 or electrically connects the wiring M2 and the pad PD1. The planar shape of the pad PD1 can be, for example, a substantially rectangular planar shape having sides larger than the wiring width of the wiring M3.

[0116] In addition, the case where the through-hole portion V3 and the wiring M3 are formed by different processes is described here. As another method, the through-hole portion V3, the wiring M3, and the pad PD1 can also be formed by the same process. In this case, the through-hole portion V3 is formed integrally with the wiring M3 or the pad PD1. In this case, after a through hole for the through-hole portion V3 is formed in the interlayer insulating film IL3, a conductive film (conductive film for the second wiring layer) is formed on the interlayer insulating film IL3 in a manner to fill the through hole, and then the conductive film is patterned using photolithography technology and etching technology, thereby forming the wiring M3 and the pad PD1. Thus, the wiring M3 and the pad PD1 are formed, and the through-hole portion V3 formed integrally with the wiring M3 or the pad PD1 is also formed.

[0117] Then, if Figure 10 As shown, on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the interlayer insulating film IL3, a silicon oxide film LF1 is formed in a manner covering the wiring M3 and the pad PD1. The silicon oxide film LF1 can be formed by a CVD method or the like. As a film forming method for the silicon oxide film LF1, a particularly preferred method is the HDP (High Density Plasma: high-density plasma)-CVD method. The thickness of the silicon oxide film LF1 (formed film thickness) can be set to, for example, about 0.5 to 0.6 μm. At the stage before the silicon oxide film LF1 is formed, the wiring M3 and the pad PD1 are exposed, but when the silicon oxide film LF1 is formed, the wiring M3 and the pad PD1 are covered by the silicon oxide film LF1 and are therefore not exposed.

[0118] Next, a silicon nitride oxide film LF2 is formed on the main surface (the entire main surface) of the semiconductor substrate SB, that is, on the silicon oxide film LF1. The silicon nitride oxide film LF2 can be formed by a CVD method or the like. As a film forming method of the silicon nitride oxide film LF2, a plasma CVD method is particularly preferred. The thickness (formed film thickness) of the silicon nitride oxide film LF2 can be set to about 0.9 to 1.1 μm, for example. As another embodiment, a silicon nitride film can be used instead of the silicon nitride oxide film LF2.

[0119] By forming the silicon oxide film LF1 and the silicon oxynitride film LF2, an insulating film LF composed of a stacked film of the silicon oxide film LF1 and the silicon oxynitride film LF2 on the silicon oxide film LF1 is formed on the interlayer insulating film IL3 to cover the wiring M3 and the pad PD1.

[0120] Next, an opening OP1 is formed in the insulating film LF. The opening OP1 is formed by selectively removing the insulating film LF on the pad PD1. The opening OP1 is formed so as to be included in the pad PD1 in a plan view.

[0121] Specifically, the opening OP1 can be formed in the following manner. That is, after the silicon oxide film LF1 and the silicon oxynitride film LF2 are formed in sequence, a photoresist pattern (not shown) is formed on the silicon oxynitride film LF2 using a photolithography technique. Then, the photoresist pattern is used as an etching mask to sequentially etch the silicon oxynitride film LF2 and the silicon oxide film LF1 (dry etching), thereby forming the opening OP1 in the insulating film LF. Then, the photoresist pattern is removed, and the silicon oxynitride film LF2 and the silicon oxide film LF1 are sequentially etched (dry etching). Figure 10 This stage is shown in . The opening OP1 is formed to penetrate the insulating film LF (ie, the stacked film of the silicon oxide film LF1 and the silicon oxynitride film LF2), and at least a part of the pad PD1 is exposed from the opening OP1.

[0122] When the opening OP1 is formed in the insulating film LF, the pad PD1 is exposed from the opening OP1 of the insulating film LF, but it is preferred that at this time, at least a portion of the upper surface of the pad PD1 is exposed from the opening OP1 of the insulating film LF, and the side surface (side wall) of the pad PD1 is covered by the insulating film LF and is not exposed from the opening OP1 of the insulating film LF. In other words, it is preferred that the opening OP1 of the insulating film LF overlaps with the pad PD1 when viewed from above, but is contained inside the pad PD1, that is, the periphery of the opening OP1 of the insulating film LF is inside the periphery of the pad PD1 when viewed from above.

[0123] In addition, when the opening OP1 is formed in the insulating film LF, the pad PD1 is exposed from the opening OP1 of the insulating film LF, but the wiring M3 other than the pad PD1 remains covered by the insulating film LF and is not exposed. The wiring M3 other than the pad PD1 also remains covered by the insulating film LF thereafter and is not exposed.

[0124] Then, if Figure 11 and Figure 12 As shown in FIG. 1 , a resin film PL1 is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the insulating film LF so as to cover the pad PD1 .

[0125] As the resin film PL1, a polyimide film or the like can be preferably used. The resin film PL1 can be formed, for example, by a coating method. Specifically, a polyimide precursor liquid is coated on the main surface of the semiconductor substrate SB while the semiconductor substrate SB is rotated by a so-called spin coating method, and then the polyimide film as the resin film PL1 can be formed. The thickness (formed film thickness) of the resin film PL1 can be set to about 3 to 5 μm, for example.

[0126] The resin film PL1 is formed on the insulating film LF and on the pad PD1 exposed from the opening OP1 of the insulating film LF. In the stage before the resin film PL1 is formed, the pad PD1 is exposed from the opening OP1 of the insulating film LF, but when the resin film PL1 is formed, the pad PD1 exposed from the opening OP1 of the insulating film LF is covered by the resin film PL1 and thus becomes non-exposed.

[0127] Next, an opening OP2 is formed in the resin film PL1. Figure 11 and Figure 12 FIG. 4 shows a stage in which an opening OP2 is formed in the resin film PL1. Figure 11 is a cross section of the openings OP1 and OP2, and Figure 12 The cross section does not cross the openings OP1 and OP2, so with respect to the openings OP1 and OP2, Figure 11 In Figure 12 The opening OP2 can be formed, for example, in the following manner.

[0128] That is, the resin film PL1 is formed as a photosensitive resin film in advance, and the resin film PL1 composed of the photosensitive resin is exposed and developed, thereby selectively removing the resin film PL1 that becomes the opening OP2, thereby forming the opening OP2 in the resin film PL1. Thereafter, a heat treatment is performed to cure the resin film PL1. The opening OP2 is formed so as to penetrate the resin film PL1, and at least a part of the pad PD1 is exposed from the opening OP2.

[0129] In another embodiment, the resin film PL1 may be dry-etched using a photoresist pattern formed on the resin film PL1 using a photolithography technique as an etching mask to form the opening OP2 in the resin film PL1. In this case, the resin film PL1 may not be a photosensitive resin film.

[0130] The opening OP2 is formed so as to include the opening OP1 inside when viewed from above. That is, the plane size (plane area) of the opening OP2 of the resin film PL1 is larger than the plane size of the opening OP1 of the insulating film LF, and the opening OP2 of the resin film PL1 includes the opening OP1 of the insulating film LF inside when viewed from above. That is, the outer periphery of the opening OP2 of the resin film PL1 is located outside the outer periphery of the opening OP1 of the insulating film LF when viewed from above.

[0131] Therefore, in the stage of forming the resin film PL1, the upper surface of the pad PD1 constituting the bottom surface of the opening OP1 and the inner wall of the opening OP1 of the insulating film LF are covered by the resin film PL1, but when the opening OP2 is subsequently formed in the resin film PL1, the upper surface of the pad PD1 constituting the bottom surface of the opening OP1 and the inner wall of the opening OP1 of the insulating film LF are not covered by the resin film PL1 and are exposed.

[0132] In this way, an insulating film LF and a resin film PL1 having openings OP1 and OP2 that expose at least a portion of the pad PD1 are formed. Here, the opening OP2 of the resin film PL1 and the opening OP1 of the insulating film LF are collectively referred to as an opening OP3. In addition, a laminated film of the insulating film LF and the resin film PL1 on the insulating film LF is referred to as a laminated film LM. The laminated film LM is a laminated insulating film, and therefore the laminated film LM as a whole can also be regarded as an insulating film. The opening OP3 corresponds to the opening of the laminated film LM of the insulating film LF and the resin film PL1 on the insulating film LF, and is formed by the opening OP2 of the resin film PL1 and the opening OP1 of the insulating film LF. Specifically, the inner wall of the opening OP3 is formed by the inner wall of the opening OP2 of the resin film PL1, the inner wall of the opening OP1 of the insulating film LF, and the upper surface of the insulating film LF that is located between the inner wall of the opening OP2 and the inner wall of the opening OP1 and is not covered by the resin film PL1. At this stage ( Figure 11 and Figure 12 ), the stacked film LM having the opening portion OP3 exposing at least a portion of the pad PD1 is formed on the interlayer insulating film IL3 in a manner covering the wiring M3.

[0133] In this way, Figures 5 to 12In this way, the semiconductor substrate SB is subjected to wafer processing. Wafer processing is also called pre-process. Here, wafer processing generally refers to the process until the following state is reached: various elements, wiring layers (here wiring M1, M2, M3) and pad electrodes (here pad PD1) are formed on the main surface of the semiconductor wafer (semiconductor substrate SB), and after the surface protection film (here laminated film LM) is formed, electrical tests can be performed on each of the multiple chip areas formed on the semiconductor wafer using a probe or the like. Each chip area of ​​the semiconductor wafer corresponds to an area in the semiconductor wafer from which one semiconductor chip is obtained.

[0134] Therefore, the laminated film LM becomes the uppermost layer in the semiconductor wafer subjected to the wafer process as a surface protection film. That is, in the semiconductor wafer subjected to the wafer process, the resin film PL1 in the laminated film LM becomes the uppermost film. In the semiconductor wafer subjected to the wafer process, by setting the uppermost film to a resin film (organic insulating film) such as a polyimide film, the semiconductor wafer can be easily handled. In addition, the wiring M3 of the third wiring layer becomes the uppermost wiring, and the pad PD1 is formed by the third wiring layer.

[0135] By performing a probe test (wafer test) using the pad PD1 exposed from the opening OP3 of the laminated film LM, it is also possible to perform an electrical test on each chip area of ​​the semiconductor wafer. Specifically, the probe (probe needle, probe) used for the test can be brought into contact with the pad PD1 exposed from the opening OP3 of the laminated film LM in each chip area of ​​the semiconductor wafer to perform an electrical test on each chip area. Based on the results of the probe test, it is possible to select whether each chip area of ​​the semiconductor wafer is a qualified product or a defective product, or by feeding back the data of the measurement results of the probe test to each manufacturing process, it can help improve the yield and reliability. Therefore, although the probe test can also be omitted, it is more preferred to perform the probe test.

[0136] After the wafer process (pre-processing) steps described above are performed, the above Figure 11 and Figure 12 After the construction, the probe test is performed as required, and then Figure 13 and Figure 14 As shown, a seed film (seed layer) SE is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the laminate film LM including the pad PD1 exposed from the opening OP3 of the laminate film LM. The seed film SE is a film that functions as a seed layer (power supply layer) for electrolytic plating later.

[0137] The seed film SE is composed of, for example, a laminated film of a chromium (Cr) film and a copper (Cu) film on the chromium (Cr) film, and can be formed by, for example, a sputtering method. Thus, the seed film SE is formed on the laminated film LM including the pad PD1 exposed at the bottom of the opening OP3 and the inner wall of the opening OP3. The surface of the laminated film LM except the opening OP3 is the resin film PL1, so the seed film SE is formed on the resin film PL1 in a manner that is in contact with the resin film PL1.

[0138] The film thickness of the seed film SE can be set to, for example, about 75 nm for a chromium (Cr) film and about 250 nm for a copper (Cu) film. In addition, the chromium (Cr) film on the lower layer side of the seed film SE can function as a barrier conductor film, for example, it has a function of preventing the diffusion of copper and a function of improving adhesion with the resin film PL1, but is not limited to a chromium (Cr) film, and for example, a titanium (Ti) film, a titanium tungsten (TiW) film, a titanium nitride (TiN) film, or a tungsten (W) film can be used.

[0139] Next, a photoresist pattern PR1 is formed on the seed film SE using a photolithography technique. The photoresist pattern PR1 is formed in a region other than the region where the rewiring RW and the pad PD2 are to be formed, and the seed film SE is exposed in the region where the rewiring RW is planned to be formed and the region where the pad PD2 is planned to be formed. That is, the photoresist pattern PR1 has an opening (groove) in the region where the rewiring RW is planned to be formed and the region where the pad PD2 is planned to be formed.

[0140] Next, a copper (Cu) film CF is formed on the seed film SE exposed from the opening of the photoresist pattern PR1 by electrolytic plating. Thus, the copper film CF is selectively formed on the seed film SE in the area not covered by the photoresist pattern PR1. The film thickness of the copper film CF can be set to about 5 to 6 μm, for example. The copper film CF is formed in the area where the rewiring RW is planned to be formed and the area where the pad PD2 is planned to be formed. Figure 13 and Figure 14 , a stage in which a copper film CF is formed is shown.

[0141] Then, if Figure 15 and Figure 16 As shown, on the photoresist pattern PR1 including on the copper film CF, another photoresist pattern PR2 is formed using a photolithography technique. The photoresist pattern PR2 is formed in a region other than a region where the base metal film UM in the pad PD2 is to be formed, and the copper film CF is exposed in the region where the base metal film UM is planned to be formed. That is, the photoresist pattern PR2 has an opening in the region where the base metal film UM is planned to be formed.

[0142] Next, a base metal film UM is formed on the copper film CF exposed from the opening of the photoresist pattern PR2 by electrolytic plating. Thus, the base metal film UM is formed on the copper film CF in the area not covered by the photoresist pattern PR2. The base metal film UM is formed on the copper film CF that becomes the pad PD2. The base metal film UM is composed of, for example, a laminated film of a nickel (Ni) film and a gold (Au) film on the nickel (Ni) film. The film thickness of the base metal film UM can be set to, for example, about 2 to 3 μm. Figure 15 and Figure 16 , a stage where the base metal film UM is formed is shown.

[0143] Then, if Figure 17 and Figure 18 As shown, the photoresist pattern PR2 and the photoresist pattern PR1 are removed. Thus, the copper film CF is exposed, and the portion of the seed film SE not covered by the copper film CF is also exposed.

[0144] In addition, in the present embodiment, the following case is described: after forming the copper film CF, the photoresist pattern PR2 is formed without removing the photoresist pattern PR1, then the base metal film UM is formed, and then the photoresist patterns PR2 and PR1 are removed. As another embodiment, after forming the copper film CF, the photoresist pattern PR1 is removed, then the photoresist pattern PR2 is formed, then the base metal film UM is formed, and then the photoresist pattern PR2 is removed.

[0145] Then, if Figure 17 and Figure 18 As shown, the seed film SE of the portion not covered by the copper film CF is removed by etching. At this time, the seed film SE of the portion covered by the copper film CF, that is, the seed film SE located under the copper film CF is not removed but remains. The etching at this time is preferably set to an etching level that removes the seed film SE of the portion not covered by the copper film CF, but does not excessively etch the copper film CF and the base metal film UM.

[0146] In this way, the rewiring RW and the pad PD2 composed of the seed film SE and the copper film CF are formed. That is, the rewiring RW and the pad PD2 are respectively composed of the stacked film of the seed film SE and the copper film CF on the seed film SE. Therefore, the rewiring RW can also be regarded as a copper wiring mainly composed of copper (Cu), and the pad PD2 can also be regarded as a copper pad mainly composed of copper (Cu).

[0147] The rewiring RW and the pad PD2 are formed on the resin film PL1 of the laminated film LM. Among them, the rewiring RW is formed on the laminated film LM including the pad PD1 exposed from the opening OP3, and is electrically connected to the pad PD1. The rewiring RW is also connected to the pad PD2, and specifically, the pad PD2 is formed integrally with the rewiring RW. Therefore, the pad PD1 is electrically connected to the pad PD2 via the rewiring RW. In addition, a base metal film UM is formed on the copper film CF constituting the pad PD2, and the base metal film UM can also be regarded as a part of the pad PD2.

[0148] Then, if Figure 19 and Figure 20 As shown in FIG. 1 , an insulating protective film PA is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the laminated film LM, so as to cover the rewiring RW and the pad PD2. As the protective film PA, a resin film is preferably used, for example, a polyimide film is preferably used. Figure 19 and Figure 20 In order to facilitate the understanding of the drawings, the copper film CF and the seed film SE are not separated but shown as one with respect to the rewiring RW and the pad PD2. The protective film PA can be formed by, for example, a coating method, for example, by the same method as the above-mentioned resin film PL1.

[0149] Next, an opening OP4 is formed in the protective film PA. Figure 19 and Figure 20 FIG. 4 shows a stage in which an opening OP4 is formed in the protective film PA. Figure 20 is a cross section across the opening O4, and Figure 19 The cross section does not cross the opening OP4, so with respect to the opening OP4, Figure 20 In Figure 19 Not shown.

[0150] For example, the opening OP4 can be formed in the following manner. That is, the protective film PA is formed as a photosensitive resin film in advance, and the protective film PA composed of the photosensitive resin is exposed and developed, thereby selectively removing the protective film PA that becomes the opening OP4, thereby forming the opening OP4 in the protective film PA. After that, a heat treatment is performed to cure the protective film PA. The opening OP4 is formed in a manner that penetrates the protective film PA, and at least a portion of the pad PD2 is exposed from the opening OP4. In the case where a base metal film UM is formed on the pad PD2, the base metal film UM on the pad PD2 is exposed from the opening OP2.

[0151] In another embodiment, the protective film PA may be dry-etched using a photoresist pattern formed on the protective film PA using a photolithography technique as an etching mask to form the opening OP4 in the protective film PA. In this case, the protective film PA may not be a photosensitive resin film.

[0152] The pad PD2 (or the base metal film UM on the pad PD2) is exposed from the opening OP2 of the protective film PA, but the rewiring RW is covered and protected by the protective film PA. By making the topmost protective film PA a resin film (organic insulating film) such as a polyimide film, the relatively soft resin film (organic insulating film) can be used as the topmost layer to facilitate the handling of the semiconductor device.

[0153] Then, if Figure 21 As shown, a bump electrode BP is formed on the base metal film UM on the pad PD2 exposed from the opening OP4. The bump electrode BP is composed of, for example, a solder bump or the like. For example, the solder bump (bump electrode BP) can be formed in the following manner: after supplying solder paste to the base metal film UM on the pad PD2 exposed from the opening OP4 using a printing method, a heat treatment (solder reflow treatment) is performed, thereby forming a spherical solder bump (bump electrode BP) on the base metal film UM. The base metal film UM can also be regarded as a part of the bump electrode BP. As another method, it is also possible to configure (supply) a spherical solder ball on the base metal film UM on the pad PD2 exposed from the opening OP4 and then perform a heat treatment (solder reflow treatment), thereby forming a spherical solder bump (bump electrode BP) on the base metal film UM. In addition, as another method, the bump electrode BP can also be formed using a plating method.

[0154] After that, a dicing process is performed to cut (cut) the semiconductor substrate SB to separate (singulate) it into a plurality of semiconductor chips. That is, the semiconductor substrate SB is cut along the scribe line region. Thus, semiconductor chips are obtained from each chip region of the semiconductor substrate SB (semiconductor wafer). Each semiconductor chip corresponds to the above Figure 3 and Figure 4 In addition, the back surface of the semiconductor substrate SB may be ground before dicing to reduce the thickness of the semiconductor substrate SB.

[0155] <Structure of semiconductor package>

[0156] Next, regarding an example of a semiconductor package (semiconductor device) PKG using the semiconductor device (semiconductor chip) of this embodiment, refer to Figure 22 To explain. Figure 22 It is a cross-sectional view of the semiconductor package PKG according to the present embodiment.

[0157] like Figure 22 As shown, the semiconductor package PKG includes a wiring substrate PB, a semiconductor chip CP1 mounted on the upper surface of the wiring substrate PB, a resin portion (bottom filling resin) UFR filling the space between the semiconductor chip CP1 and the wiring substrate PB, and a plurality of solder balls HB disposed on the lower surface of the wiring substrate PB. The semiconductor chip CP1 corresponds to the above Figures 1 to 4 The semiconductor device (CP) shown in FIG. Therefore, the semiconductor chip CP1 has a plurality of bump electrodes BP.

[0158] The semiconductor chip CP1 is mounted on the upper surface of the wiring substrate PB in a flip-chip manner. That is, the semiconductor chip CP1 is mounted on the upper surface of the wiring substrate PB through a plurality of bump electrodes BP in a manner such that the back side of the semiconductor chip CP1 faces upward and the surface of the semiconductor chip CP1 (the main surface on one side where the bump electrode BP is formed) faces a direction opposite to the upper surface of the wiring substrate PB. Therefore, the semiconductor chip CP1 is soldered upside down on the upper surface of the wiring substrate PB. The plurality of bump electrodes BP of the semiconductor chip CP1 are respectively bonded to and electrically connected with the plurality of connection pads (terminals, substrate-side terminals, electrodes, and conductive connection pad portions) LA on the upper surface of the wiring substrate PB. That is, the plurality of pads PD2 of the semiconductor chip CP1 are respectively electrically connected to the plurality of connection pads LA on the upper surface of the wiring substrate PB via the bump electrodes BP.

[0159] A resin portion UFR as an underfill resin is filled between the semiconductor chip CP1 and the upper surface of the wiring board PB. The resin portion UFR is made of a resin material (eg, a thermosetting resin material) such as epoxy resin or silicone resin, and may further contain a filler (eg, silicon dioxide).

[0160] The planar shape of the wiring substrate (package substrate) PB intersecting with its thickness is rectangular, and has an upper surface as a main surface on one side and a lower surface as a main surface on the side opposite to the upper surface. In the chip mounting area (the area where the semiconductor chip CP1 is mounted) on the upper surface of the wiring substrate PB, a plurality of connection pads LA are arranged in an arrangement corresponding to the arrangement of the bump electrodes BP on the surface of the semiconductor chip CP1. Thus, the semiconductor chip CP1 can be mounted on the upper surface of the wiring substrate PB in a flip-chip manner to respectively connect the plurality of bump electrodes BP of the semiconductor chip CP1 to the plurality of connection pads LA on the upper surface of the wiring substrate PB. In the case where the plurality of bump electrodes BP on the surface of the semiconductor chip CP1 are arranged in an array, the plurality of connection pads LA are arranged in an array in the chip mounting area on the upper surface of the wiring substrate PB.

[0161] A plurality of terminals (external connection terminals, electrodes, pads, conductive pad portions) TE are formed on the lower surface of the wiring substrate PB. A plurality of pads LA on the upper surface of the wiring substrate PB are electrically connected to the plurality of terminals TE on the lower surface of the wiring substrate PB via wirings, via wiring portions, etc. provided in the wiring substrate PB. On the lower surface of the wiring substrate PB, the plurality of terminals TE are arranged in an array, for example, and solder balls (ball electrodes, protruding electrodes, protruding-shaped electrodes) HB are connected to the respective terminals TE. The solder balls HB can function as external terminals (external connection terminals) of the semiconductor package PKG.

[0162] <Regarding the wiring structure under the pad PD1>

[0163] Figure 23 is a cross-sectional view of the main part of the semiconductor device of the present embodiment, showing the same cross-section as the above Figure 1 However, in Figure 23 , for simplifying the drawing, the illustration of the interlayer insulating film IL2 and the structure thereunder is omitted, but actually, under the cross-sectional structure of Figure 23 there also exists Figure 1 the interlayer insulating film IL2 and the structure thereunder shown in Figure 24 and Figure 25 are top views of the main part of the semiconductor device of the present embodiment. The same planar region is shown in Figure 24 and Figure 25 , but different layers are shown. The pad PD1 is shown in Figure 24 , and the wiring M2 which is one layer lower than the pad PD1 is shown in Figure 25 . Figure 24 is a top view, but for facilitating the observation of the drawing, shading is added to the pad PD1 and the wiring M3, and in addition, Figure 25 is a top view, but for facilitating the observation of the drawing, shading is added to the wiring M2. Figure 24 and Figure 25 The cross-sectional views at the position of the A - A line roughly correspond to the above Figure 1 and Figure 23 . Figure 26 and Figure 27 are also top views of the main part of the semiconductor device of the present embodiment, showing the same planar region as Figure 25 and the same layer as Figure 25 . In addition, Figure 26 is a diagram prepared in such a way that the positional relationship between the openings OP1, OP2 and the Figure 25 shown wiring M2 is clear. The diagram in Figure 25 where shading is omitted and the positions of the openings OP1, OP2 are added corresponds to Figure 26 . In addition, Figure 27This is a diagram prepared in such a way that the later-described opening formation regions RG1 and RG2 are clear. In Figure 25 the diagram corresponding to adding a dashed line indicating the opening formation region RG1 and a dashed line indicating the opening formation region RG2 in Figure 27 . In Figure 24 and Figure 26 the position (planar position) of the opening OP1 of the insulating film LF is indicated by a double-dashed line, and the position (planar position) of the opening OP2 of the resin film PL1 is indicated by a dashed line.

[0164] From Figure 23 and Figure 24 it can also be seen that in a top view, the opening OP1 is included inside the opening OP2, and the opening OP2 is included inside the pad PD1. In Figure 24 the case, the planar shapes of the opening OP1, the opening OP2, and the pad PD1 are all rectangular shapes, more precisely, rectangles having sides in the X direction and sides in the Y direction. In addition, the X direction and the Y direction shown in each top view are directions substantially parallel to the main surface of the semiconductor substrate SB. Also, the X direction and the Y direction are orthogonal directions to each other.

[0165] From Figures 23 to 27 it can also be seen that a wiring M2 extends under the pad PD1. When performing wiring design, if, different from this embodiment, the region under the pad PD1 is set as a region where the wiring M2 is prohibited from being arranged in order to avoid the region under the pad PD1 and the wiring M2 is arranged, the degree of freedom in wiring design becomes low and it is difficult to perform wiring design. In addition, it may lead to an increase in the planar size of the semiconductor device. Therefore, in this embodiment, the region under the pad PD1 is set as a region where the wiring M2 can be arranged. Therefore, a wiring M2 extends under the pad PD1, and in Figures 23 to 27 the case, the wirings M2a, M2b, and M2c extending in the X direction pass through the region under the pad PD1.

[0166] The wirings M2a, M2b, and M2c are all wirings M2 of the wiring layer (here, the second wiring layer) one layer below the wiring layer (here, the third wiring layer) where the pad PD1 is formed. Therefore, the wirings M2a, M2b, and M2c are wirings of the same layer. Since the wirings M2a, M2b, and M2c each extend under the pad PD1, they have a part overlapping with the pad PD1 in a top view. That is, in a top view, at least a part of each of the wirings M2a, M2b, and M2c overlaps with the pad PD1.

[0167] Among wirings M2a, M2b, and M2c, each of wirings M2a and M2b has a plurality of openings SL below pad PD1. Wiring M2c among wirings M2a, M2b, and M2c does not have an opening (SL) below pad PD1. In Figures 23 to 27 the case of, in each of wirings M2a and M2b, each opening SL is a slit-shaped opening extending along the extending direction (here, the X direction) of the wiring.

[0168] If the width W1a of wiring M2a assuming that no plurality of openings SL are formed in wiring M2a, the width W1b of wiring M2b assuming that no plurality of openings SL are formed in wiring M2b, and the width W1c of wiring M2c are compared, the widths W1a and W1b are each greater than the width W1c, the width W1a is greater than the width W1b, and W1a > W1b > W1c holds. That is, wirings M2a and M2b correspond to wirings in which a plurality of openings SL are provided in a wide wiring, and wiring M2c corresponds to a narrow wiring in which no opening (SL) is provided. Further, the "width of the wiring" corresponds to the dimension (width) in the direction substantially perpendicular to the current direction (the direction in which current flows) of the wiring. In Figure 26 this, the current direction in each of wirings M2a, M2b, and M2c is the X direction, and thus the widths W1a, W1b, and W1b are all dimensions in the Y direction.

[0169] From Figure 25 and Figure 26 it can be seen that, when viewed from above, at least a part of wiring M2a overlaps with opening OP1, and thus overlaps with connection region CN between pad PD1 and rewiring RW. The end (side surface) of wiring M2a is located below connection region CN between pad PD1 and rewiring RW.

[0170] Here, the connection region CN between pad PD1 and rewiring RW refers to the region where pad PD1 and rewiring RW are connected. Since rewiring RW is formed on pad PD1 exposed from opening OP1 of insulating film LF, the upper surface of pad PD1 exposed from opening OP1 of insulating film LF corresponds to connection region CN between pad PD1 and rewiring RW. Thus, when viewed from above, connection region CN between pad PD1 and rewiring RW substantially coincides with opening OP1 of insulating film LF.

[0171] Further, from

[0172] and Figure 25 and Figure 26As can be seen, when viewed from above, at least a part of the wiring M2b overlaps with the opening OP2, but the wiring M2b does not overlap with the opening OP1. Therefore, the wiring M2b does not overlap with the connection region CN between the pad PD1 and the rewiring RW. The end (side surface) of the wiring M2b is located below the opening OP2, but the end (side surface) of the wiring M2b is not located below the connection region CN.

[0173] In addition, from Figure 25 and Figure 26 it can be seen that three wirings M2c pass under the pad PD1, and at least a part of two of the wirings M2c (the two wirings M2c closer to the wiring M2a) overlaps with the opening OP1 when viewed from above. Therefore, it overlaps with the connection region CN between the pad PD1 and the rewiring RW. The ends (side surfaces) of these two wirings M2c are located below the connection region CN. In addition, the number of the wirings M2c is not limited to three.

[0174] In addition, from Figure 25 and Figure 26 it can be seen that at least a part of one of the three wirings M2c (one wiring M2c closer to the wiring M2b) passing under the pad PD1 overlaps with the opening OP2, but does not overlap with the opening OP1 and does not overlap with the connection region CN. The end (side surface) of this one wiring M2c is located below the opening OP2, but is not located below the connection region CN.

[0175] Therefore, the wiring M2a and the two wirings M2c are wirings whose ends (the ends of the wirings M2a and M2c) are located below the opening OP1 and thus below the connection region CN. In addition, the wiring M2b and one wiring M2c are wirings whose ends (the ends of the wirings M2b and M2c) are not located below the opening OP1, but the ends (the ends of the wirings M2b and M2c) are located below the opening OP2.

[0176] In the present embodiment, in order to suppress or prevent cracks from occurring in the interlayer insulating film IL3 sandwiched between the wirings M2a, M2b and the pad PD1, a plurality of openings SL are provided in each of the wirings M2a, M2b, and details will be described later. On the other hand, the width (W1c) of the wiring M2c is small. Therefore, even if no opening (SL) is formed in the wiring M2c, there is little concern about cracks occurring in the interlayer insulating film IL3 sandwiched between the wiring M2c and the pad PD1. Therefore, no opening (SL) is formed in the wiring M2c to reduce the resistance of the wiring M2c. The reason for forming the opening SL and where to form the opening SL will be described in the following section of "Process of Research" and the section of "Regarding Main Features and Effects".

[0177] <Regarding the Process of Research>

[0178] The present inventor has studied a semiconductor device in which rewiring is formed after forming pads. From the study by the present inventor, it has been found that in such a semiconductor device, cracks may be generated in the interlayer insulating film (IL3) under the pad (PD1) due to the pressure (stress) applied to the pad (PD1) through the rewiring (RW). Hereinafter, a specific description will be given with reference to Figures 28 to 30 as follows.

[0179] Figure 28 is a cross-sectional view of a main part of a semiconductor device as a research example studied by the present inventor, corresponding to the above Figure 23 . Similar to the above Figure 23 , in Figure 28 , the illustration of the above interlayer insulating film IL2 and the structure thereunder is also omitted. In addition, Figure 29 and Figure 30 are top views of a main part of a semiconductor device as a research example studied by the present inventor, corresponding to the above Figure 24 and Figure 25 respectively. The pad PD1 is shown in Figure 29 , and the wiring M2 below the pad PD1 is shown in Figure 30 . For easy viewing of the drawings, the pad PD1 and the wiring M3 in Figure 29 and the wiring M2 in Figure 30 are shaded. Figure 29 and Figure 30 The cross-sectional view at the position of the line B - B corresponds to Figure 29 . In addition, in Figure 29 and Figure 30 , the position of the opening OP1 of the above insulating film LF is indicated by a double-dot dash line, and the position of the opening OP2 of the above resin film PL1 is indicated by a dot dash line.

[0180] In the research example of Figures 28 to 30 , the wiring M102a corresponds to the above wiring M2a, the wiring M102b corresponds to the above wiring M2b, and the wiring M102c corresponds to the above wiring M2c. However, different from the above wirings M2a and M2b, no opening SL is formed in the wirings M102a and M102b. That is, the case where no opening SL is formed in the wirings M2a and M2b in the above Figures 23 to 27 corresponds to the research example of Figures 28 to 30 . The wiring M102a is the same as the above wiring M2a except that it does not have the opening SL, the wiring M102b is the same as the above wiring M2b except that it does not have the opening SL, and the wiring M102c is the same wiring as the above wiring M2a.

[0181] In Figures 28 to 30In the case of the research example, cracks CR are likely to occur in the interlayer insulating film IL3 between the pad PD1 and the wiring M2. The reasons are as follows.

[0182] A rewiring RW is formed on the pad PD1, so pressure (stress) is applied to the pad PD1 through the rewiring RW. This is because when the semiconductor device (CP) is mounted on a wiring substrate (PB) or the like, the bump electrode BP of the semiconductor device is connected to the terminal (landing pad LA) of the wiring substrate (PB), and the stress generated by the thermal shrinkage of the wiring substrate (PB) is applied to the rewiring RW through the bump electrode BP, and further applied to the pad PD1 through this rewiring RW. In addition, since the thermal expansion coefficient of the metal material is larger than that of the insulating material and the thickness of the rewiring RW is very thick, the pressure (stress) due to the rewiring RW is easily applied to the pad PD1.

[0183] When pressure (stress) is applied to the pad PD1 through the rewiring RW, cracks CR sometimes occur in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M2. According to the research of the present inventor, cracks CR occur in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M2 when the following two factors (the first factor and the second factor) are satisfied.

[0184] The first factor is that the end of the wiring M2 (here the wiring M102a) exists below the connection region CN between the pad PD1 and the rewiring RW, and the second factor is that the width (wiring width) of the wiring M2 (here the wiring M102a) is large.

[0185] In the pad PD1, the region where the pressure (stress) applied through the rewiring RW is large is the connection region CN and the region below it. This is because pressure (stress) is transmitted from the rewiring RW to the pad PD1 through the connection region CN between the pad PD1 and the rewiring RW. That is, in the pad PD1, in the connection region CN and the region below it, a large pressure (stress) is directly transmitted from the rewiring RW.

[0186] The end of the wiring M102a (the end of the wiring M102a) exists below the connection region CN. When the end of the wiring M2 (here the end of the wiring M102a) exists below the connection region CN, it is possible for cracks CR to occur starting from the corner of the end of the wiring M102a (the corner formed by the upper surface and the side surface of the wiring) in the interlayer insulating film IL3 sandwiched between the corner of the end of the wiring M102a and the pad PD1. This is because the pressure (stress) applied to the pad PD1 through the rewiring RW is applied to the interlayer insulating film IL3 below the connection region CN; the stress applied to the interlayer insulating film IL3 due to the wiring M102a is concentrated at the corner of the end of the wiring M102a.

[0187] The stress applied to the interlayer insulating film IL3 due to the wiring M2 may be generated due to thermal shrinkage of the wiring M2 or the like, and the magnitude of this stress tends to increase as the width of the wiring M2 increases. That is, when comparing a wide-width wiring M2 with a narrow-width wiring M2, the thermal shrinkage amount of the wide-width wiring M2 is larger than that of the narrow-width wiring M2. Therefore, the stress applied to the interlayer insulating film IL3 due to the wiring M2 is greater for the wide-width wiring M2 than for the narrow-width wiring M2. Therefore, the possibility of generating a crack CR in the interlayer insulating film IL3 starting from the corner portion forming the end of the wiring M2 increases as the stress applied to the interlayer insulating film IL3 due to this wiring M2 increases, and thus increases as the width of this wiring M2 increases.

[0188] Therefore, if the end of the wiring M2 exists below the connection region CN, there is a possibility of generating a crack CR starting from the corner portion forming the end of the wiring M2 in the interlayer insulating film IL3 sandwiched between this wiring M2 and the pad PD1. If the width of this wiring M2 is small, the possibility is low, but if the width of this wiring M2 is wide, the possibility becomes high. That is, if the end of the wide-width wiring M102a exists below the connection region CN, a large stress is applied to the interlayer insulating film IL3 sandwiched between the corner portion forming the end of the wiring M102a and the pad PD1, and it is easy to generate a crack CR starting from the corner of the wiring M102a. Generating a crack CR in the interlayer insulating film IL3 reduces the reliability of the semiconductor device. Therefore, in order to improve the reliability of the semiconductor device, it is desirable to suppress or prevent the generation of a crack CR in the interlayer insulating film IL3.

[0189] Therefore, as a method for suppressing or preventing the generation of a crack CR in the interlayer insulating film IL3, the following first method and second method can be considered.

[0190] The first method is to avoid the end of the wiring M2 existing below the connection region CN between the pad PD1 and the rewiring RW. In this case, the end (corner) of the wiring M2 that may become the starting point of the crack CR does not exist in the region (the region below the connection region CN) that is likely to be transmitted the pressure from the rewiring RW, so that the generation of a crack CR in the interlayer insulating film IL3 can be suppressed or prevented.

[0191] However, in the case of adopting the first method, the entire region below the connection region CN becomes a region where the end of the wiring M2 is prohibited from being arranged, so that the degree of freedom of the layout of the wiring M2 becomes low, and the wiring design of the semiconductor device becomes difficult. In addition, if the wiring M2 is arranged so as to avoid the region below the connection region CN in order to adopt the first method, it is not conducive to the miniaturization of the semiconductor device, resulting in an increase in the planar size of the semiconductor device.

[0192] The second method is to dispose only narrow-width signal wirings below the connection region CN without disposing wide-width ground wirings or the like. In this case, although the end portion (corner portion) of the wiring M2 exists in the region (the region below the connection region CN) where the pressure from the rewiring RW is likely to be transmitted, since the width of the wiring M2 is small, the possibility of generating a crack CR starting from the end portion (corner portion) of the wiring M2 is low, and generation of the crack CR in the interlayer insulating film IL3 can be suppressed or prevented.

[0193] However, in the case of adopting the second method, the entire region below the connection region CN becomes a region where the end portions of wide-width wirings M2 such as ground wirings are prohibited from being disposed, so the degree of freedom in the layout of the wiring M2 becomes low, and the wiring design of the semiconductor device becomes difficult. In addition, if it is desired to dispose wide-width wirings M2 such as ground wirings while avoiding the region below the connection region CN in order to adopt the second method, it is not advantageous for miniaturization of the semiconductor device, resulting in an increase in the planar size of the semiconductor device.

[0194] Therefore, it is desirable to provide a technique capable of suppressing or preventing generation of the crack CR in the interlayer insulating film IL3 and improving the degree of freedom in the layout of the wiring M2 below the pad PD1.

[0195] <Regarding main features and effects>

[0196] The semiconductor device of the present embodiment includes: a semiconductor substrate SB; a wiring M2a (first wiring) formed on the semiconductor substrate SB with an interlayer insulating film IL2 (first interlayer insulating film) therebetween; an interlayer insulating film IL3 (second interlayer insulating film) formed on the interlayer insulating film IL2 so as to cover the wiring M2a; and a pad PD1 (first pad) formed on the interlayer insulating film IL3. The semiconductor device of the present embodiment further includes a stacked film LM (first insulating film) formed on the interlayer insulating film IL3 and having an opening OP3 (first opening) exposing the pad PD1. The semiconductor device of the present embodiment further includes: a rewiring RW (second wiring) formed on the stacked film LM including above the pad PD1 exposed from the opening OP3 and electrically connected to the pad PD1; and a pad PD2 (second pad) formed on the stacked film LM and integrally connected to the rewiring RW.

[0197] One of the main features of the present embodiment is that, when viewed from above, at least a part of the wiring M2a (first wiring) overlaps with the pad PD1, and the end of the wiring M2a is located below the connection region CN between the pad PD1 and the rewiring RW. Another main feature of the present embodiment is that a plurality of openings SL (second openings) are formed in the opening formation region RG1 (first region) in the wiring M2a, and at least a part of the opening formation region RG1 overlaps with the connection region CN between the pad PD1 and the rewiring RW when viewed from above.

[0198] In addition, the opening formation region RG1 corresponds to the region in the wiring M2a where a plurality of openings SL are formed, and the opening formation region RG2 corresponds to the region in the wiring M2b where a plurality of openings SL are formed. Specifically, as Figure 27 shown, the opening formation region RG1 substantially corresponds to the region combining the plurality of openings SL formed in the wiring M2a and the region between these openings SL (the wiring portion between adjacent openings SL), and the opening formation region RG2 substantially corresponds to the region combining the plurality of openings SL formed in the wiring M2b and the region between these openings SL (the wiring portion between adjacent openings SL).

[0199] In the present embodiment, when viewed from above, at least a part of the wiring M2a overlaps with the pad PD1, and the end of the wiring M2a is located below the connection region CN between the pad PD1 and the rewiring RW (see Figures 23 to 27 ). In the case where the opening SL is not formed in the wiring M2a differently from the present embodiment, as described in connection with the above Figures 28 to 30 research example, when pressure (stress) is applied to the pad PD1 by the rewiring RW, cracks CR may be generated in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M102a. The reason for this is, as described in connection with the above research example, that the end of the wiring M102a exists below the connection region CN; and the width of this wiring M102a is large.

[0200] In contrast, in the present embodiment, although the end of the wiring M2a (the end of the wiring M2a) exists below the connection region CN, a plurality of openings SL are formed in the opening formation region RG1 in this wiring M2a, and at least a part of the opening formation region RG1 overlaps with the connection region CN when viewed from above. Thus, even when at least a part of the wiring M2a overlaps with the pad PD1 when viewed from above and the end of the wiring M2a is located below the connection region CN, it is possible to suppress or prevent the generation of something equivalent to the above cracks CR in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M2a. The reason therefor will be described below.

[0201] As described in connection with the above research example, if the end of the wide-width wiring M2 exists below the connection region CN between the pad PD1 and the rewiring RW, a large stress is applied to the interlayer insulating film IL3 sandwiched between the corner of the end of the wiring M2 and the pad PD1, and a crack CR is likely to occur starting from the end (corner) of the wiring M2. This is because the pressure (stress) applied to the pad PD1 through the rewiring RW is applied to the interlayer insulating film IL3 below the connection region CN; the stress applied to the interlayer insulating film IL3 due to the wiring M2 is concentrated at the corner of the end of the wiring M2. The magnitude of the stress applied to the interlayer insulating film IL3 due to the wiring M2 tends to be larger as the width of the wiring M2 is larger and smaller as the width of the wiring M2 is smaller. Regarding the possibility of a crack CR occurring in the interlayer insulating film IL3 starting from the end (corner) of the wiring M2 when the end of the wiring M2 exists below the connection region CN, if the stress applied to the interlayer insulating film IL3 due to the wiring M2 is reduced, the possibility is reduced. Therefore, if the effective width of the wiring M2 is reduced, the possibility is reduced.

[0202] Forming an opening SL in the wiring M2 corresponds to reducing the effective wiring width of the wiring M2. Therefore, forming an opening SL in the wiring M2 serves to reduce the effective wiring width of the wiring M2 and reduce the stress applied to the interlayer insulating film IL3 due to the wiring M2. In addition, if an opening SL is formed in the wiring M2, the interlayer insulating film IL3 is also filled in the opening SL, and the interlayer insulating film IL3 filled in the opening SL can act to suppress the deformation of the wiring M2, which also acts to reduce the stress applied to the interlayer insulating film IL3 due to the wiring M2. Therefore, if an opening SL is formed in the wiring M2, the stress applied to the interlayer insulating film IL3 due to the wiring M2 can be reduced compared to the case where no opening SL is formed in the wiring M2. Thus, regarding the possibility of a crack CR occurring in the interlayer insulating film IL3 starting from the end (corner) of the wiring M2 when the end of the wiring M2 exists below the connection region CN, the possibility can be reduced by forming an opening SL in the wiring M2. Therefore, compared with the Figures 28 to 30 research example above, Figures 23 to 27 in the present embodiment, since a plurality of openings SL are formed in the wiring M2a, it is possible to further suppress or prevent a crack from occurring in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M2a (M102a). Thus, the reliability of the semiconductor device can be improved.

[0203] In addition, in the present embodiment, it is not necessary to set the area under the pad PD1 as an area where the wiring M2 is prohibited from being disposed, and the wiring M2 can be freely disposed under the pad PD1. Therefore, the degree of freedom in the layout of the wiring M2 can be improved. In addition, it is beneficial to miniaturize the semiconductor device.

[0204] In addition, in the present embodiment, an opening SL is provided in the wiring M2, and it is extremely important in what area the opening SL is provided. The area in which the opening SL should be provided will be described below.

[0205] As described above, in the interlayer insulating film IL3, the area directly below the connection area CN (vertically below) is likely to transmit the pressure (stress) transmitted from the rewiring RW to the pad PD1. Therefore, in order to prevent cracks (CR) from occurring in the interlayer insulating film IL3, it is effective to reduce the stress applied to the interlayer insulating film IL3 due to the wiring M2 in the area directly below the connection area CN. In order to reduce the stress applied to the interlayer insulating film IL3 due to the wiring M2 below the connection area CN, it is effective to provide an opening (SL) in the wiring M2 below the connection area CN.

[0206] Therefore, in the present embodiment, as a first condition, in a plan view, at least a part of the opening formation region RG1, which is a region where a plurality of openings SL are formed, in the wiring M2a whose end (the end of the wiring M2a) exists below the connection area CN overlaps with the connection area CN.

[0207] In addition, the fact that at least a part of the opening formation region RG1 overlaps with the connection area CN in a plan view implies that at least a part of the plurality of openings SL formed in the wiring M2a overlaps with the connection area CN in a plan view. From another point of view, the fact that at least a part of the opening formation region RG1 overlaps with the connection area CN in a plan view implies that at least a part of the opening formation region RG1 is below the connection area CN, and thus at least a part of the plurality of openings SL formed in the wiring M2a is below the connection area CN.

[0208] If the first condition is satisfied, an opening SL is provided in the wiring M2a below the connection area CN, thereby obtaining the effect of reducing the stress applied to the interlayer insulating film IL3 due to the wiring M2a. Therefore, it is possible to suppress or prevent cracks from occurring in the interlayer insulating film IL3 that is likely to transmit pressure (stress) from the rewiring RW through the pad PD1.

[0209] In addition, in the present embodiment, preferably, as a second condition, in a plan view, the overlapping area of the wiring M2a and the connection area CN is included in the opening formation region RG1.

[0210] The overlapping region of the wiring M2a and the connection region CN when viewed from above corresponds to Figure 31 the region with shading added. Herein, Figure 31 is a top view of the main part of the semiconductor device of the present embodiment, and is a view obtained by removing the dotted line indicating the position of the opening OP2 and adding shading to the overlapping region of the wiring M2a and the connection region CN when viewed from above. Figure 26

[0211] The overlapping region of the wiring M2a and the connection region CN when viewed from above corresponds to the region of the wiring M2a that overlaps with the connection region CN when viewed from above. In addition, the fact that the overlapping region of the wiring M2a and the connection region CN when viewed from above is included in the opening formation region RG1 implies that the entire region of the wiring M2a that overlaps with the connection region CN when viewed from above is included in the opening formation region RG1. Thus, it is implied that a plurality of openings SL are arranged in the entire region of the wiring M2a that overlaps with the connection region CN when viewed from above. From another perspective, the fact that the overlapping region of the wiring M2a and the connection region CN when viewed from above is included in the opening formation region RG1 implies that the entire region of the wiring M2a located below the connection region CN is included in the opening formation region RG1. Thus, it is implied that a plurality of openings SL are arranged in the entire region of the wiring M2a located below the connection region CN.

[0212] If the second condition is satisfied, then a plurality of openings SL are arranged in substantially the entire region of the wiring M2a located below the connection region CN, and it is possible to suppress or prevent the generation of a portion with a wide wiring width. Therefore, below the connection region CN, openings SL are provided in the wiring M2a, whereby the effect of reducing the stress applied to the interlayer insulating film IL3 due to the wiring M2a can be obtained more accurately. Thus, it is possible to more accurately suppress or prevent cracks from occurring in the interlayer insulating film IL3 where pressure (stress) is easily transmitted from the rewiring RW through the pad PD1.

[0213] That is to say, even when only a part of the overlapping region of the wiring M2a and the connection region CN is included in the opening formation region RG1 when viewed from above, the effect of suppressing or preventing cracks from occurring in the interlayer insulating film IL3 can be obtained. However, it is more preferable that the entire overlapping region of the wiring M2a and the connection region CN is included in the opening formation region RG1 when viewed from above. That is, it is more preferable that the second condition is satisfied. Thereby, below the connection region CN, the stress applied to the interlayer insulating film IL3 due to the wiring M2a can be made smaller more accurately, and it is possible to more accurately suppress or prevent cracks from occurring in the interlayer insulating film IL3. In addition, if the second condition is satisfied, the above-mentioned first condition is necessarily satisfied.​

[0214] Further, in the present embodiment, preferably, as a third condition, below the connection region CN between the pad PD1 and the rewiring RW, a plurality of openings SL are formed in the opening formation region RG1 of the wiring M2a such that a portion having a width (width of the wiring portion) of 0.6 μm or more is not generated in the wiring M2a. Further, the width of the wiring (M2, M2a) corresponds to the dimension (width) of the wiring (M2, M2a) in a direction substantially perpendicular to the current direction (direction in which current flows). For example, preferably, in Figure 26 the width W2a (here, the dimension in the Y direction) of the wiring portion sandwiched by the openings SL adjacent in the Y direction in the wiring M2a is less than 0.6 μm.

[0215] As a premise of the third condition, it is assumed that the width W1a of the wiring M2a when a plurality of openings SL are not formed in the wiring M2a is 0.6 μm or more. Further, it is assumed that the width W1a of the wiring M2a when a plurality of openings SL are not formed in the wiring M2a corresponds to the width of the above-mentioned wiring M102a, and the width of the above-mentioned wiring M102a is 0.6 μm or more.

[0216] As described above, compared with the wiring M2 having a narrow width, the stress applied to the interlayer insulating film IL3 due to the wiring M2 is greater for the wiring M2 having a wide width. Therefore, in the present embodiment, below the connection region CN, a plurality of openings SL are formed in the wiring M2a in order to reduce the effective width of the wiring M2a, whereby the stress applied to the interlayer insulating film IL3 due to the wiring M2a is reduced. Therefore, preferably, below the connection region CN, a plurality of openings SL are formed such that a portion having a large (wide) width is not generated in the wiring M2a. Specifically, preferably, a plurality of openings SL are formed in the wiring M2a such that a portion having a width (width of the wiring portion) of 0.6 μm or more is not generated in the wiring M2a.

[0217] As described above, compared with the wiring M2 having a narrow width, the stress applied to the interlayer insulating film IL3 due to the wiring M2 is greater for the wiring M2 having a wide width. From the research of the present inventors, it is known that in the above Figures 28 to 30 research example, if the width of the wiring M102a is 0.6 μm or more, the possibility of generating a crack CR starting from the end portion (corner portion) of the wiring M102a in the interlayer insulating film IL3 sandwiched by the wiring M102a and the pad PD1 increases.

[0218] Therefore, in the present embodiment, in the wiring M2a having a width W1a of 0.6 μm or more, assuming that the plurality of openings SL are not formed, the plurality of openings SL are formed to avoid the generation of a portion having a width (width of the wiring portion) of 0.6 μm or more in the wiring M2a below the connection region CN between the pad PD1 and the rewiring RW. Thus, below the connection region CN, the stress applied to the interlayer insulating film IL3 due to the wiring M2a can be more accurately reduced, and the generation of cracks in the interlayer insulating film IL3 sandwiched between the wiring M2a and the pad PD1 can be more accurately suppressed or prevented.

[0219] In addition, in the present embodiment, a laminated film LM (first insulating film) having an opening OP3 exposing the pad PD1 is formed on the interlayer insulating film IL3, and a rewiring RW electrically connected to the pad PD1 is formed on the laminated film LM including on the pad PD1 exposed from the opening OP3. The laminated film LM (first insulating film) is composed of a laminated film of an insulating film LF (second insulating film) and a resin film PL1 (third insulating film) on the insulating film LF, and the opening OP3 (first opening) of the laminated film LM is formed by the opening OP1 (third opening) of the insulating film LF and the opening OP2 (fourth opening) of the resin film PL1. When viewed from above, the opening OP1 of the insulating film LF is included in the opening OP2 of the resin film PL1, and the rewiring RW is connected to the pad PD1 exposed from the opening OP1 of the insulating film LF.

[0220] In this case, when viewed from above, the connection area CN between the pad PD1 and the rewiring RW is roughly consistent with the opening OP1 of the insulating film LF. Therefore, the above-mentioned second condition is that, when viewed from above, the overlapping area between the wiring M2a and the connection area CN is included in the opening forming area RG1, which can be said to be that, when viewed from above, the overlapping area between the wiring M2a and the opening OP1 is included in the opening forming area RG1, which is referred to as the fourth condition. That is, the fourth condition is that, when viewed from above, the overlapping area between the wiring M2a and the opening OP1 is included in the opening forming area RG1. In addition, the overlapping area between the wiring M2a and the opening OP1 when viewed from above corresponds to the area of ​​the wiring M2a that overlaps with the opening OP1 when viewed from above. The overlapping area between the wiring M2a and the opening OP1 when viewed from above is substantially consistent with the overlapping area between the wiring M2a and the connection area CN when viewed from above, and both correspond to Figure 31 The area with shadow added.

[0221] If the overlapping region of the wiring M2a and the opening OP1 when viewed from above satisfies the fourth condition and is included in the opening formation region RG1, then in the region below the opening OP1 (i.e., below the connection region CN), a plurality of openings SL are disposed substantially over the entire region, and a portion with a wide wiring width can be suppressed or prevented from being generated. Therefore, below the opening OP1 (i.e., below the connection region CN), an opening SL is provided in the wiring M2a, whereby the effect of reducing the stress applied to the interlayer insulating film IL3 due to the wiring M2a can be obtained more accurately. As a result, the effect of suppressing or preventing the generation of cracks CR in the interlayer insulating film IL3 where pressure (stress) is easily transmitted from the rewiring RW through the pad PD1 can be obtained more accurately.

[0222] In addition, in the present embodiment, it is preferable that, as a fifth condition, when viewed from above, the overlapping region of the wiring M2a and the opening OP2 is included in the opening formation region RG1.

[0223] The overlapping region of the wiring M2a and the opening OP2 when viewed from above corresponds to Figure 32 the shaded region in the wiring M2a. Here, Figure 32 is a top view of the main part of the semiconductor device of the present embodiment, and is a view obtained by removing the double-dot chain line indicating the position of the opening OP1 and adding shading to the overlapping region of the wiring M2a and the opening OP2 and the overlapping region of the wiring M2b and the opening OP2 when viewed from above. Figure 26

[0224] In addition, the overlapping region of the wiring M2a and the opening OP2 when viewed from above corresponds to the region of the wiring M2a that overlaps with the opening OP2 when viewed from above. Further, the fact that the overlapping region of the wiring M2a and the opening OP2 when viewed from above is included in the opening formation region RG1 implies that the entire region of the wiring M2a that overlaps with the opening OP2 when viewed from above is included in the opening formation region RG1, and thus implies that a plurality of openings SL are disposed over the entire region of the wiring M2a that overlaps with the opening OP2 when viewed from above. From another perspective, the fact that the overlapping region of the wiring M2a and the opening OP2 when viewed from above is included in the opening formation region RG1 implies that the entire region of the wiring M2a below the opening OP2 is included in the opening formation region RG1, and thus implies that a plurality of openings SL are disposed over the entire region of the wiring M2a below the opening OP2.

[0225] ​In the region below the connection region CN, that is, the region below the opening OP1, the pressure (stress) applied from the pad PD1 to the interlayer insulating film IL3 is extremely large. This is because the rewiring RW is formed in contact with the pad PD1 exposed from the opening OP1, and no insulating film is interposed between the rewiring RW and the pad PD1 exposed from the opening OP1. Therefore, pressure (stress) is directly applied from the rewiring RW to the pad PD1 exposed from the opening OP1, and this pressure is transmitted to the interlayer insulating film IL3 below the connection region CN (that is, below the opening OP1).

[0226] On the other hand, when viewed from above, the opening OP2 is included inside the opening OP1. Therefore, in the region outside the opening OP1 and inside the opening OP2 when viewed from above, an insulating film LF is interposed between the rewiring RW and the pad PD1, but no resin film PL1 is interposed. Therefore, in the region outside the opening OP1 and inside the opening OP2 when viewed from above, there is no resin film PL1. Correspondingly, the pressure (stress) from the rewiring RW is transmitted to the pad PD1 to some extent via the insulating film LF and further applied to the underlying interlayer insulating film IL3. That is, the pressure (stress) applied from the pad PD1 to the interlayer insulating film IL3 in the region outside the opening OP1 and inside the opening OP2 when viewed from above is smaller than the pressure (stress) applied from the pad PD1 to the interlayer insulating film IL3 in the region inside the opening OP1 when viewed from above. Even so, it is still of a certain magnitude. Therefore, although it does not reach the level of the region inside the opening OP2 when viewed from above, there is also a certain possibility of generating something equivalent to the above crack CR in the interlayer insulating film IL3 in the region outside the opening OP1 and inside the opening OP2 when viewed from above. Therefore, in order to minimize the possibility of generating something equivalent to the above crack CR in the interlayer insulating film IL3, it is desirable to reduce the stress applied to the interlayer insulating film IL3 due to the wiring M2 not only in the region inside the opening OP1 when viewed from above but also in the region outside the opening OP1 and inside the opening OP2 when viewed from above.

[0227] Therefore, in the present embodiment, preferably, as the fifth condition, in a plan view, the overlapping region of the wiring M2a and the opening OP2 is included in the opening formation region RG1. If the fifth condition is satisfied, then not only in the region inside the opening OP2 in a plan view, but also in the region outside the opening OP1 and inside the opening OP2 in a plan view, a plurality of openings SL are formed in the wiring M2a. Thus, not only in the region inside the opening OP2 in a plan view, but also in the region outside the opening OP1 and inside the opening OP2 in a plan view, the stress applied to the interlayer insulating film IL3 due to the wiring M2a can be reduced, and thus the generation of cracks in the interlayer insulating film IL3 can be more accurately suppressed or prevented. In addition, if the fifth condition is satisfied, the above-mentioned fourth condition is necessarily satisfied.

[0228] In addition, Figures 23 to 27 (In the case of the present embodiment), the end of the wiring M2a and Figures 28 to 30 the end of the wiring M102a in the research example are present below the connection region CN of the pad PD1 and the rewiring RW, that is, at a position overlapping the opening OP1 in a plan view. Therefore, in Figures 28 to 30 the research example, there is a concern that cracks CR may be generated in the interlayer insulating film IL3 starting from the end (corner) of the wiring M102a. Therefore, in Figures 23 to 27 (the present embodiment), a plurality of openings SL are provided in the wiring M2a to suppress or prevent the generation of cracks CR in the interlayer insulating film IL3 starting from the end (corner) of the wiring M2a. On the other hand, Figures 23 to 27 (In the case of the present embodiment), the end of the wiring M2b and Figures 28 to 30 the end of the wiring M102b in the research example are not present below the connection region CN of the pad PD1 and the rewiring RW, that is, at a position not overlapping the opening OP1 in a plan view, but at a position overlapping the opening OP2 in a plan view. As described above, although it does not reach the extent of the region inside the opening OP2 in a plan view, there is also a certain possibility that something equivalent to the above-mentioned crack CR may be generated in the interlayer insulating film IL3 in the region outside the opening OP1 and inside the opening OP2 in a plan view. Therefore, in Figures 28 to 30 the research example, although it does not reach the length of the wiring M102a, the wiring M102b may also cause cracks in the interlayer insulating film IL3. That is, there is also a certain possibility that cracks CR may be generated starting from the end (corner) of the wiring M102b in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M102b.

[0229] Therefore, preferably, not only the wiring M2a corresponding to the wiring M102a but also the wiring M2b corresponding to the wiring M102b is provided with the opening SL. Thus, in Figures 23 to 27 this case, a plurality of openings SL are formed in the opening formation region RG2 in the wiring M2b. In a top view, at least a part of the opening formation region RG2 in the wiring M2 overlaps with the opening OP2. In addition, the fact that at least a part of the opening formation region RG2 overlaps with the opening OP2 in a top view implies that, in a top view, at least a part of the plurality of openings SL formed in the wiring M2a overlaps with the opening OP2.

[0230] Preferably, the fifth condition is applied not only to the wiring M2a but also to the wiring M2b. That is, preferably, in a top view, the overlapping region of the wiring M2b and the opening OP2 is included in the opening formation region RG2. In addition, the overlapping region of the wiring M2b and the opening OP2 in a top view corresponds to Figure 32 the shaded region added to the wiring M2b.

[0231] The overlapping region of the wiring M2b and the opening OP2 in a top view corresponds to the region of the wiring M2b that overlaps with the opening OP2 in a top view. In addition, the fact that the overlapping region of the wiring M2b and the opening OP2 in a top view is included in the opening formation region RG2 implies that the entire region of the wiring M2b that overlaps with the opening OP2 in a top view is included in the opening formation region RG2, and thus implies that a plurality of openings SL are arranged in the entire region of the wiring M2b that overlaps with the opening OP2 in a top view. From another viewpoint, the fact that the overlapping region of the wiring M2b and the opening OP2 in a top view is included in the opening formation region RG2 implies that the entire region of the wiring M2b located below the opening OP2 is included in the opening formation region RG2, and thus implies that a plurality of openings SL are arranged in the entire region of the wiring M2b located below the opening OP2.

[0232] If not only the wiring M2a but also the wiring M2b satisfies the fifth condition, then in the regions of the wiring M2a and M2b that overlap with the opening OP2 in a top view, that is, the regions below the opening OP2 in the wiring M2a and M2b, a plurality of openings SL are formed in the wiring M2a and M2b. Thereby, in the region inside the opening OP2 in a top view, the stress applied to the interlayer insulating film IL3 due to the wiring M2a and M2b can be reduced, and thus it is possible to more accurately suppress or prevent cracks from occurring in the interlayer insulating film IL3 starting from the ends (corners) of the wiring M2a and M2b.

[0233] In addition, in the present embodiment, preferably, as the sixth condition, below the opening OP2, a plurality of openings SL are formed in the opening formation region RG1 of the wiring M2a in such a manner that no portion having a width (width of the wiring portion) of 0.6 μm or more is generated in the wiring M2a. In addition, as a premise of the sixth condition, it is assumed that the width W1a of the wiring M2a when no plurality of openings SL are formed in the wiring M2a is 0.6 μm or more.

[0234] As described above, compared with the wiring M2 having a narrow width, the stress applied to the interlayer insulating film IL3 due to the wiring M2 is greater in the wiring M2 having a wide width. According to the research of the present inventors, in the above Figures 28 to 30 research example, if the respective widths of the wirings M102a and M102b are 0.6 μm or more, the possibility of cracks CR occurring starting from the respective end portions (corner portions) of the wirings M102a and M102b in the interlayer insulating film IL3 sandwiched between the wirings M102a and M102b and the pad PD1 increases.

[0235] Therefore, in the present embodiment, preferably, below the opening OP2, a plurality of openings SL are formed in such a manner that no wide (broad) portion is generated in the wiring M2a. Specifically, preferably, below the opening OP2, a plurality of openings SL are formed in the wiring M2a in such a manner that no portion having a width (width of the wiring portion) of 0.6 μm or more is generated in the wiring M2a. Thereby, below the opening OP2, the stress applied to the interlayer insulating film IL3 due to the wiring M2a can be made smaller more accurately, and the generation of cracks in the interlayer insulating film IL3 sandwiched between the wiring M2a and the pad PD1 can be more accurately suppressed or prevented.

[0236] Preferably, the sixth condition is applied not only to the wiring M2a but also to the wiring M2b. That is, below the opening OP2 (directly below), a plurality of openings SL are formed in the opening formation region RG2 of the wiring M2b in such a manner that no portion having a width (width of the wiring portion) of 0.6 μm or more is generated in the wiring M2b. Thereby, below the opening OP2 (directly below), the stress applied to the interlayer insulating film IL3 due to the wirings M2a and M2b can be made smaller more accurately, and the generation of cracks (CR) in the interlayer insulating film IL3 starting from the end portions (corner portions) of the wirings M2a and M2b can be more accurately suppressed or prevented.

[0237] In addition, as a premise of applying the sixth condition to the wiring M2b as well, it is assumed that the width W1b of the wiring M2b when no plurality of openings SL are formed in the wiring M2b is 0.6 μm or more. Moreover, referring to Figure 26In order for the wirings M2a and M2b to satisfy the sixth condition, it is preferred that, in each of the wirings M2a and M2b, a width W2a of a wiring portion sandwiched between openings SL adjacent in the Y direction is less than 0.6 μm.

[0238] In addition, in the present embodiment, it is preferred that, as the seventh condition, no opening SL is formed in the wiring M2 (M2a, M2b) in a region that is 5 μm or more away from the opening OP2 when viewed from above. From another point of view, the seventh condition means that, when viewed from above, the outer periphery of the opening forming regions RG1, RG2 is 5 μm or more away from the opening OP2.

[0239] Figure 33 This is a diagram for explaining the seventh condition. Figure 33 is a top view of the main part of the semiconductor device of this embodiment, corresponding to the Figure 26 The double-dashed line indicating the position of the opening OP1 is removed and a dotted line indicating the region RG3 is added. Figure 33 In the figure, the region RG3 indicated by the dotted line corresponds to the region where the opening OP2 is expanded by 5 μm in the X direction and the Y direction. That is, when viewed from above, the interval L1 between the periphery of the opening OP2 and the periphery of the region RG3 (the interval in the X direction and the interval in the Y direction) is 5 μm (L1=5 μm). Therefore, the size of the region RG3 in the X direction is the value of the size of the opening OP2 in the X direction plus 10 μm, and the size of the region RG3 in the Y direction is the value of the size of the opening OP2 in the Y direction plus 10 μm.

[0240] Figure 33 The region RG3 surrounded by the dotted line corresponds to a region within 5 μm from the opening OP2 in a plan view. Figure 33 The outside of the region RG3 surrounded by the dotted line shown corresponds to a region that is 5 μm or more away from the opening OP2. Preferably, among the wirings M2 (M2a, M2b, M2c) extending below the pad PD1, Figure 33 The seventh condition can be satisfied by not forming the opening SL outside the region RG3 surrounded by the dotted line in FIG. The reason why the seventh condition is preferably satisfied is as follows.

[0241] In the region outside the opening OP2 when viewed from above, not only the insulating film LF but also the resin film PL1 is interposed between the rewiring RW and the pad PD1. The resin film PL1 has a relatively thick thickness (specifically, thicker than the insulating film LF), and in addition, it is relatively soft because it is made of a resin material (specifically, softer than the insulating film LF). Therefore, in the region outside the opening OP2 when viewed from above, not only the insulating film LF but also the resin film PL1 exists between the rewiring RW and the pad PD1. Correspondingly, the pressure (stress) from the rewiring RW is not easily transmitted to the pad PD1, and thus, it is not easily applied to the interlayer insulating film IL3 below the pad PD1. That is, the pressure (stress) applied from the pad PD1 to the interlayer insulating film IL3 in the region outside the opening OP2 when viewed from above is much smaller than the pressure (stress) applied from the pad PD1 to the interlayer insulating film IL3 in the region inside the opening OP2 when viewed from above. Therefore, Figures 23 to 27 Needless to say, in the case of (this embodiment), in Figures 28 to 30 the case of the research example, in the region outside the opening OP2 when viewed from above, the possibility of generating something equivalent to the above crack CR in the interlayer insulating film IL3 is almost non-existent, and even if it exists, it is very small. Therefore, in the region outside the opening OP2 when viewed from above, whether or not to provide the opening SL in the wiring M2 hardly affects the possibility of generating the crack (CR) in the interlayer insulating film IL3. On the other hand, if the opening SL is provided in the wiring M2 in the region outside the opening OP2 when viewed from above, the resistance of the wiring M2 increases accordingly.

[0242] Therefore, in this embodiment, preferably, as the seventh condition, in the region more than 5 μm away from the opening OP2 when viewed from above, a plurality of openings SL are not formed in the wiring M2 (M2a, M2b, M2c). If the seventh condition is satisfied, the opening SL will not be formed in the region of the wiring M2 (M2a, M2b, M2c) where the effect of providing the opening SL cannot be expected (specifically, the region more than 5 μm away from the opening OP2). Thereby, the generation of cracks in the interlayer insulating film IL3 can be suppressed or prevented, and the increase in the resistance of the wiring M2 caused by the provision of the opening SL can be suppressed, so that a reduction in the resistance of the wiring M2 can be achieved.

[0243] The technical idea of this embodiment is summarized as follows. In this embodiment, when the rewiring RW is formed on the pad PD1, it is considered that the pressure (stress) transmitted from the rewiring RW to the pad PD1 is applied to the interlayer insulating film IL3 under the pad PD1, reducing the stress applied to the interlayer insulating film IL3 due to the wiring M2 under the pad PD1, thereby suppressing or preventing cracks from occurring in the interlayer insulating film IL3 sandwiched between the wiring M2 and the pad PD1. As a result, the reliability of the semiconductor device can be improved. In this embodiment, as a means of reducing the stress applied to the interlayer insulating film IL3 due to the wiring M2 under the pad PD1, a plurality of openings SL are formed in the wiring M2 under the pad PD1. In the wiring M2 under the pad PD1, the plurality of openings SL are provided in regions where the pressure (stress) applied from the pad PD1 to the interlayer insulating film IL3 is relatively large (the above first, second, fourth, and fifth conditions). In addition, in the wiring M2 under the pad PD1, the plurality of openings SL are provided in such a manner that no portion with a wide wiring width is generated (the above third and sixth conditions). As a result, the effect obtained by providing the plurality of openings SL (the effect of preventing cracks from occurring in the interlayer insulating film IL3) can be improved. In addition, in the wiring M2 under the pad PD1, no openings (SL) are provided in regions where the effect obtained by providing the plurality of openings SL (the effect of preventing cracks from occurring in the interlayer insulating film IL3) cannot be expected, thereby enabling a reduction in the resistance of the wiring M2 (the above seventh condition).

[0244] As the wirings M2a and M2b in which the plurality of openings SL are formed, a power supply wiring or a ground wiring can be preferably applied, and a ground wiring can be particularly preferably applied. The wiring widths of the power supply wiring and the ground wiring are wide, and generally, the wiring width of the ground wiring is larger than that of the power supply wiring. Therefore, if there is a power supply wiring or a ground wiring (especially a ground wiring) under the pad PD1 as the wiring M2, there is a concern that cracks CR may occur in the interlayer insulating film IL3 sandwiched between the wiring M2 and the pad PD1. In this embodiment, when there are wirings M2a and M2b as the power supply wiring or the ground wiring under the pad PD1, by forming a plurality of openings SL in the wirings M2a and M2b as described above, it is possible to suppress or prevent cracks from occurring in the interlayer insulating film IL3 sandwiched between the power supply wiring or the ground wiring (wirings M2a and M2b) and the pad PD1. Therefore, when the power supply wiring or the ground wiring is applied as the wirings M2a and M2b in which the plurality of openings SL are formed, the effect obtained by providing the plurality of openings SL is large, and particularly when the ground wiring is applied, the effect obtained by providing the plurality of openings SL is extremely large.

[0245] In addition, among the plurality of wirings M2 extending below the pad PD1, it is also possible to have a mixed presence of the wirings M2a and M2b provided with the opening portions SL and the wiring M2c not provided with the opening portions SL. In this regard, the following will be described with reference to Figures 23 to 27 for illustration.

[0246] In Figures 23 to 27 the case, below the pad PD1, as the wiring M2, not only the wirings M2a and M2b extend, but also the wiring M2c (third wiring) extends. The width W1b (second width) of the wiring M2c is relatively small. Specifically, it is smaller than the width W1a (first width) of the wiring M2a assuming that no plurality of opening portions SL are formed in the wiring M2a (W1c < W1a), and is also smaller than the width W1b of the wiring M2b assuming that no plurality of opening portions SL are formed in the wiring M2b (W1c < W1b). For example, the wirings M2a and M2b are power supply wirings or ground wirings, and the wiring M2c is a signal wiring (signal line). The power supply wiring is a wiring used to supply a power supply potential, the ground wiring is a wiring used to supply a ground potential (grounding potential), and the signal wiring is a wiring used to transmit a signal. Generally, the wiring widths of the power supply wiring and the ground wiring are very wide, the wiring width of the signal wiring is relatively small, and the wiring width of the signal wiring is smaller than the wiring widths of the power supply wiring and the ground wiring.

[0247] In Figures 23 to 27 the case, a plurality of opening portions SL are formed in the wirings M2a and M2b, and no equivalent of the opening portion SL is formed in the wiring M2c. The reasons for forming the opening portions SL in the wirings M2a and M2b and not in the wiring M2b are as follows.

[0248] That is, regarding the wirings M2a and M2b, if the opening portions SL are not provided, since the wiring widths are very large, the stress applied to the interlayer insulating film IL3 due to the wirings M2a and M2b becomes large, and thus there is a concern that cracks may occur in the interlayer insulating film IL3 sandwiched between the wirings M2a and M2b and the pad PD1. On the other hand, regarding the wiring M2c, even if the opening portions SL are not provided, since the wiring width is small, the stress applied to the interlayer insulating film IL3 due to the wiring M2c is not so large, and the concern about cracks occurring in the interlayer insulating film IL3 sandwiched between the wiring M2c and the pad PD1 is relatively small.

[0249] Therefore, openings SL are provided in wirings M2a, M2b among the wirings M2a, M2b, M2c extending under the pad PD1, which have a relatively high possibility of causing cracks in the interlayer insulating film IL3 if no opening is formed, thereby suppressing or preventing the generation of cracks in the interlayer insulating film IL3 sandwiched by the wirings M2a, M2b and the pad PD1. On the other hand, openings are not provided in the wiring M2c among the wirings M2a, M2b, M2c extending under the pad PD1, which has a relatively low possibility of causing cracks in the interlayer insulating film IL3 even if no opening is formed, thereby enabling a reduction in the resistance of the wiring M2c. By having a mixture of the wirings M2a, M2b provided with the openings SL and the wiring M2c not provided with the openings among the wirings M2a, M2b, M2c extending under the pad PD1, it is possible to achieve both prevention of cracks in the interlayer insulating film IL3 and reduction in the resistance of the wiring M2.

[0250] In addition, as described in connection with the above third and sixth conditions, it has been found from the research of the present inventor that if the width of the wiring M2 is 0.6 μm or more, the stress applied to the interlayer insulating film IL3 due to the wiring M2 becomes large, and the possibility that the wiring M2 causes the above cracks CR increases.

[0251] Therefore, preferably, as the wiring M2 (M2a, M2b) provided with the opening SL in a manner satisfying any one of the above first to sixth conditions, the wiring M2 (M2a, M2b) is assumed to have a width of 0.6 μm or more when no plurality of openings SL are formed. That is, preferably, for the wiring M2 (M2a, M2b) among the wirings M2 extending under the pad PD1, which has a width of 0.6 μm or more when no opening (SL) is formed, the opening SL is formed in a manner satisfying any one of the above first to sixth conditions.

[0252] On the other hand, it is also possible to provide the opening SL in the wiring M2 (M2c) having a width less than 0.6 μm even when no opening is formed in a manner satisfying any one of the above first to sixth conditions. However, since there is little concern about the generation of cracks in the interlayer insulating film IL3 even if no opening SL is provided, it is also possible not to form something equivalent to the opening SL, and thus, a reduction in the resistance of the wiring M2 (M2c) can be achieved.

[0253] Therefore, regarding wirings M2a and M2b, it is preferable that the widths W1a and W1b assuming that no plurality of openings SL are formed are each 0.6 μm or more, and the wiring M2c is preferably a wiring having a width W1c less than 0.6 μm. Openings SL are provided for wirings M2a and M2b for which the effect of providing the openings SL (the effect of preventing cracks in the interlayer insulating film IL3) is large, and openings are not provided for the wiring M2c having a width less than 0.6 μm for which the effect of providing the openings SL is small. Thus, it is possible to efficiently achieve prevention of cracks in the interlayer insulating film IL3 and reduction of the resistance of the wiring M2.

[0254] In addition, in the present embodiment ( Figures 23 to 27 and Figures 31 to 34 ), a case is illustrated in which one wiring M2a having an opening SL, one M2b having an opening SL, and three wirings M2c not having an opening SL pass under the pad PD1. However, the number of each of the wirings M2a, M2b, and M2c is not limited to this, and various modifications can be made. In addition, there may be a case where there is no wiring M2c under the pad PD1. In addition, there may be a case where both wirings M2a and 2b exist under the pad DP1; a case where one of the wirings M2a and 2b exists but the other does not. Further, as described above, the wiring M2a is a wiring whose end portion is located below the connection region CN (opening OP1) and has an opening SL, and the wiring M2b is a wiring whose end portion is not located below the connection region CN (opening OP1) but is located below the opening OP2 and has an opening SL, and the wiring M2c is a wiring not having an opening SL.

[0255] <Modification Example>

[0256] Each modification example of the present embodiment will be described with reference to the drawings.

[0257] Figure 34 is a cross-sectional view of a main part of a semiconductor device according to a first modification example of the present embodiment, corresponding to the above Figure 23 . Similarly to the above Figure 23 , illustration of the above interlayer insulating film IL2 and the structure thereunder is also omitted in Figure 34 . In addition, Figure 35 and Figure 36 are top views of a main part of a semiconductor device according to a first modification example of the present embodiment, corresponding to the above Figure 27 and [[ID=275 . That is, in ​ and ​ , wirings M2 deeper than the pad PD1 are shown, in ​ , a dashed line indicating the opening formation region RG1 is shown, and in​ The chain double-dashed line indicating the position of the opening OP1 of the above-described insulating film LF and the dashed line indicating the position of the opening OP2 of the above-described resin film PL1 are shown. In addition, ​ This is a top view, but for ease of understanding, shading is added to the wirings M2 (M2a, M2b, M2c). Additionally, ​ The cross-sectional view at the position of the A-A line of ​ roughly corresponds to ​ The top view showing the pad PD1 is the same as the above

[0258] In ​ In the case of the first modification of ​ no openings (SL) are formed in the wirings M2b and M2c among the wirings M2a, M2b, and M2c that extend under the pad PD1. Additionally, a plurality of openings SL are formed in the opening formation region RG1 in the wiring M2a, but ​ the area of the opening formation region RG1 in the first modification of ​ is smaller than the area of the opening formation region RG1 in the case of

[0259] ​ The other structure of the semiconductor device of the first modification of ​ is the same as that of the semiconductor device of

[0260] ​ The first modification of ​ satisfies the above-described first condition, second condition, third condition, fourth condition, and seventh condition, but does not satisfy the above-described fifth condition and sixth condition. ​ Since the first modification of ​ satisfies the above-described first condition, second condition, third condition, and fourth condition, an effect of suppressing or preventing cracks from occurring in the interlayer insulating film IL3 sandwiched between the pad PD1 and the wiring M2 can be obtained. However, in the case of

[0261] Figures 37 to 40 This is a top view of the main part of the semiconductor device of the second modification of the present embodiment, and all correspond to the above Figure 27 In

[0262] In the case of Figure 27 and Figures 37 to 40In each case, a plurality of openings SL are formed in the opening formation regions RG1 and RG2 of the wirings M2a and M2b, but the planar shape of the opening SL is different in the cases of the above Figure 27 and Figures 37 to 40 in each case.

[0263] That is, in the case of the above Figure 27 a plurality of openings SL are formed in a slit shape in the opening formation regions RG1 and RG2 of the wirings M2a and RG2b. In contrast, in each case of Figures 37 to 40 a plurality of openings SL are formed in a grid shape (mesh shape) in the opening formation regions RG1 and RG2 of the wirings M2a and M2b. First, the case of the above Figure 27 will be described.

[0264] In the case of the above Figure 27 the wirings M2a and M2b extend in the X direction. In each of the opening formation regions RG1 and RG2 of the wirings M2a and M2b extending in the X direction, a plurality of slit-shaped openings SL extending in the X direction are arranged in the Y direction. Since each opening SL is slit-shaped, in a top view, it has an elongated planar shape extending in one direction (here the X direction), for example, a rectangular planar shape with the X direction as the long side direction. Therefore, the dimension (length) of each opening SL in the X direction is larger than the dimension (width) in the Y direction. In the case of Figure 27 the widths (dimensions in the Y direction) of the respective openings SL (slits) are the same. In addition, in the case of Figure 27 in each of the opening formation regions RG1 and RG2 of M2a and M2b, a plurality of openings SL (slits) are arranged at the same interval (arrangement pitch) in the Y direction, and thus the widths W2a of the wiring portions sandwiched by the openings SL (slits) (see Figure 26 ) are the same. In addition, the wiring portions sandwiched by the openings SL (slits) extend in the X direction, and preferably, the width W2a of the wiring portion sandwiched by the openings SL (slits) is less than 0.6 μm as described in connection with the above third condition and sixth condition.

[0265] When slit-shaped openings SL are formed in each of the wirings M2a and M2b, preferably, the extending direction (long side direction) of the slit (opening SL) is the same as the extending direction (here the X direction) of the wirings M2a and M2b. Thereby, it is easy to suppress an increase in the resistance of the wiring M2a caused by the formation of the opening SL, which is advantageous for reducing the resistance of the wiring M2a.

[0266] That is, in the wiring M2a, the current direction is the extending direction of the wiring M2a. Therefore, in the wiring M2a, it is easier to ensure the current path and the resistance of the wiring M2a is lower when the slit (opening SL) is provided along the extending direction of the wiring M2a than when the slit (opening SL) is provided in a manner that crosses the extending direction of the wiring M2a (in the X direction here). Therefore, when a slit is provided as the opening SL in the wiring M2a, preferably, the extending direction (long side direction) of the slit (opening SL) is the same as the extending direction of the wiring M2a. The same applies to the wiring M2b.

[0267] Next, the case of Figure 37 (the second modification example) will be described.

[0268] In Figure 37 this case, the wirings M2a and M2b extend in the X direction. In the opening forming regions RG1 and RG2 of the wirings M2a and M2b extending in the X direction, a plurality of openings SL in a grid shape are formed. That is, a plurality of openings SL each having a planar shape such as a rectangular shape or a square shape are arranged in an array (matrix) in the X direction and the Y direction. Additionally, in Figure 37 this case, since a plurality of openings SL (slits) are arranged at the same interval (arrangement pitch) in the X direction and the Y direction, the widths (dimensions in the Y direction) W2b of the wiring portions sandwiched by the openings SL (slits) are the same. Preferably, the width W2b of the wiring portion sandwiched by the openings SL (slits) is less than 0.6 μm as described in connection with the above third condition and sixth condition.

[0269] Furthermore, in Figure 37 the arrangement (array arrangement) of the openings SL, it is also possible to arrange the plurality of openings SL in a so-called staggered arrangement by staggering the arrangement by 1 / 2 pitch for each column. This case (the case of staggered arrangement) is shown in Figure 38 . In Figure 37 this case and Figure 38 this case, it can be regarded that a plurality of openings SL are formed in a grid shape. Additionally, in Figure 37 and Figure 38 , the planar shape of each opening SL is shown as a rectangle, but a planar shape other than a rectangle (such as a circular shape, etc.) can also be adopted. In Figure 39 , the case where the planar shape of each opening SL in Figure 37 is changed to a circular shape is shown, and in Figure 40 , the case where the planar shape of each opening SL in Figure 38 is changed to a circular shape is shown. In Figures 37 to 40In any of these cases, it can also be regarded that a plurality of openings SL are formed in a grid pattern.

[0270] In the opening formation regions RG1 and RG2 of the wirings M2a and M2b, when a plurality of openings SL are formed in a slit shape (the above Figure 27 case), the following advantages are obtained. That is, the amount (volume) of the interlayer insulating film IL3 filled in the opening SL can be efficiently increased, and thus the shrinkage and expansion of the wirings M2a and M2b can be easily suppressed by the interlayer insulating film IL3 filled in the opening SL (slit). Therefore, the effect of suppressing or preventing cracks from occurring in the interlayer insulating film IL3 sandwiched between the wirings M2a and M2b and the pad PD1 can be further improved.

[0271] In the opening formation regions RG1 and RG2 of the wirings M2a and M2b, when a plurality of openings SL are formed in a grid pattern ( Figures 37 to 40 case), the following advantages are obtained. That is, an increase in the resistance of the wirings M2a and M2b caused by providing a plurality of openings SL in the wirings M2a and M2b can be suppressed, and a reduction in the resistance of the wirings M2a and M2b can be achieved. In addition, the phenomenon that current locally concentrates in the wirings M2a and M2b is less likely to occur.

[0272] Next, a third modification of the present embodiment will be described. Figures 41 to 44 is a top view of the main part of the semiconductor device according to the third modification of the present embodiment. In Figures 41 to 44 the wiring M2a that extends under the pad PD1 as the wiring M2 is shown respectively, and for easy understanding, the wiring M2a is shaded. In addition, in Figures 41 to 44 the double-dot chain line indicating the position of the opening OP1 of the insulating film LF, the dotted line indicating the position of the opening OP2 of the resin film PL1, and the dashed line indicating the opening formation region RG1 are also shown respectively. The top view showing the pad PD1 is also the same as the above Figure 24 in the case of the third modification.

[0273] First, the case of Figure 41 will be described. In the case of Figure 41 , the wiring M2a extends under the pad PD1, and the wiring M2a integrally has a wiring portion M2a1 extending in the X direction and a wiring portion M2a2 extending in the Y direction. Figure 41 The wiring portion M2a1 in Figures 25 to 27 corresponds to the wiring M2a shown in the above Figures 25 to 27 , and the wiring formed by integrally connecting the wiring portion M2a2 extending in the Y direction to the wiring M2a shown in the above Figure 41 corresponds to the wiring M2a of Figure 41In the wiring portion M2a1, a plurality of openings SL similar to the plurality of openings SL in the wiring M2a shown above are formed. Further, a plurality of openings SL are also formed in the wiring portion M2a2. That is, in the case of Figures 25 to 27 , a plurality of openings SL are also formed in the opening formation region RG1 in the wiring M2a. Figure 41 In the case of

[0274] , due to satisfying the above first to seventh conditions, the above-described effects can also be obtained. Figures 41 to 44 In the case of

[0275] In addition, when the connection portion between the wiring portion M2a1 and the wiring portion M2a2 is located within the opening OP2 of the resin film PL1 in a top view, particularly when it is located within the opening OP1 of the insulating film LF, in order to prevent cracks from occurring in the interlayer insulating film IL3 sandwiched between the wiring M2a and the pad PD1, it is preferable that openings SL are also formed near the connection portion between the wiring portion M2a1 and the wiring portion M2a2. Therefore, in each case of Figures 41 to 44 , the connection portion between the wiring portion M2a1 and the wiring portion M2a2 is included in the opening formation region RG1, and openings SL are also formed near the connection portion between the wiring portion M2a1 and the wiring portion M2a2.

[0276] However, in the case of Figure 41 , there is a concern that the resistance of the current path flowing from the wiring portion M2a2 to the wiring portion M2a1 increases. Regarding this, an explanation will be given below.

[0277] In the case of Figure 41 , over substantially the entire opening formation region RG1 in the wiring portion M2a1, the plurality of openings SL are formed in a slit shape extending in the X direction. Further, in the case of Figure 41 , over substantially the entire opening formation region RG1 in the wiring portion M2a2, the plurality of openings SL are formed in a slit shape extending in the Y direction.

[0278] The wiring portion M2a2 is connected to the wiring portion M2d1 in the wiring portion M2a1, so the wiring portion M2d1 can function as a path for the current flowing from the wiring portion M2a2 to the wiring portion M2a1, but the other wiring portions M2d2, M2d3, M2d4 can hardly function as a path for the current flowing from the wiring portion M2a2 to the wiring portion M2a1. Here, the wiring portions M2d1, M2d2, M2d3, M2d4 are wiring portions that are part of the wiring portion M2a1, and extend in the Y direction respectively. The wiring portions M2d1, M2d2, M2d3, M2d4 have openings SL therebetween and are separated from each other through the openings SL.

[0279] Therefore, in Figure 41 the case, there is a concern that the resistance of the current path flowing from the wiring portion M2a2 to the wiring portion M2a1 increases. The case where this is improved is Figure 42 the case.

[0280] In Figure 42 the case, similarly to Figure 41 the case, over substantially the entire opening formation region RG1 in the wiring portion M2a2, a plurality of openings SL are formed in a slit shape extending in the Y direction. However, differently from Figure 41 the case, in Figure 42 the case, in the opening formation region RG1 in the wiring portion M2a1, a plurality of openings SL are formed in a grid shape near the connection portion between the wiring portion M2a1 and the wiring portion M2a2, and are formed in a slit shape extending in the X direction in portions other than near the connection portion between the wiring portion M2a1 and the wiring portion M2a2. That is, in Figure 41 the case, in the opening formation region RG1 in the wiring portion M2a1, near the connection portion between the wiring portion M2a1 and the wiring portion M2a2, the opening SL is also formed in a slit shape extending in the X direction, but in Figure 42 the case, in the opening formation region RG1 in the wiring portion M2a1, near the connection portion between the wiring portion M2a1 and the wiring portion M2a2, the opening SL is formed in a grid shape. In addition to this, in Figure 42 the case is also substantially the same as Figure 41 the case.

[0281] In Figure 42 the case, in the opening formation region RG1 in the wiring portion M2a1, near the connection portion between the wiring portion M2a1 and the wiring portion M2a2, the opening SL is formed in a grid shape, whereby not only the wiring portion M2d1, but also the wiring portions M2d2, M2d3, and M2d4 can function as paths for the current flowing from the wiring portion M2a2 to the wiring portion M2a1. This is because the wiring portions M2d2, M2d3, and M2d4 extending in the X direction are connected to each other by the wiring portion extending in the Y direction between the grid-shaped openings. Therefore, in Figure 42 the case, compared with Figure 41 the case, the path resistance of the current flowing from the wiring portion M2a2 to the wiring portion M2a1 can be reduced.

[0282] Figure 43 Corresponding to the case where over substantially the entire opening formation region RG1 in the wiring portion M2a2, a plurality of openings SL are formed in a grid shape. Therefore, in Figure 42 the case, similarly to Figure 43 the case, also in Figure 42Similarly, in the opening formation region RG1 in the wiring portion M2a1, near the connection portion between the wiring portion M2a1 and the wiring portion M2a2, a plurality of openings SL are formed in a grid pattern. In addition, a plurality of openings SL are formed in a slit shape extending in the X direction.

[0283] In Figure 43 the case of, compared with Figure 41 the case of, it is possible to reduce the resistance of the current path flowing from the wiring portion M2a2 to the wiring portion M2a1. In addition, in Figure 43 the case of, in the opening formation region RG1 in the wiring portion M2a2, a plurality of openings SL are formed in a grid pattern, whereby compared with Figure 42 the case of, it is possible to further reduce the resistance of the wiring portion M2a2.

[0284] Figure 44 Corresponding to the entire opening formation region RG1 throughout the wiring M2a, that is, the entire opening formation region RG1 in the wiring portion M2a2 and the entire opening formation region RG1 in the wiring portion M2a1, a plurality of openings SL are formed in a grid pattern. In Figure 44 the case of, compared with Figure 41 the case of, it is possible to reduce the resistance of the current path flowing from the wiring portion M2a2 to the wiring portion M2a1. In addition, in Figure 44 the case of, in the entire opening formation region RG1 in the wiring M2a, a plurality of openings SL are formed in a grid pattern, whereby compared with Figures 41 to 43 each case of, it is possible to further reduce the resistance of the wiring M2a.

[0285] On the other hand, if the opening SL is formed in a slit shape, it is possible to efficiently increase the amount (volume) of the interlayer insulating film IL3 filled in the opening SL. Therefore, it is easy to suppress the shrinkage and expansion of the wiring M2a by the interlayer insulating film IL3 filled in the opening SL (slit). This acts in a way that further improves the effect of suppressing or preventing cracks from occurring in the interlayer insulating film IL3 sandwiched between the wiring M2a and the pad PD1. Therefore, Figure 43 the case of compared with Figure 44 the case of, in addition, Figure 42 the case of compared with Figure 43 the case of, it is possible to further improve the effect of suppressing or preventing cracks from occurring in the interlayer insulating film IL3 sandwiched between the wiring M2a and the pad PD1.

[0286] As described above, the invention completed by the present inventor has been specifically described based on its embodiments. However, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from its gist.

Claims

1. A semiconductor device, characterized in that, comprising: a semiconductor substrate; a first wiring formed on the semiconductor substrate with a first interlayer insulating film therebetween; a second interlayer insulating film formed on the first interlayer insulating film so as to cover the first wiring; a first pad formed on the second interlayer insulating film; a first insulating film formed on the second interlayer insulating film and having a first opening exposing the first pad; a second wiring formed on the first insulating film including above the first pad exposed from the first opening and electrically connected to the first pad; and a second pad formed on the first insulating film and integrally connected to the second wiring, wherein, in a plan view, at least a part of the first wiring overlaps with the first pad, an end portion of the first wiring is located below a connection region between the first pad and the second wiring, a plurality of second openings are formed in a first region of the first wiring, in a plan view, at least a part of the first region overlaps with the connection region, the first wiring integrally has a first wiring portion extending in a first direction and a second wiring portion extending in a second direction intersecting the first direction, a connection portion between the first wiring portion and the second wiring portion is included in the first region, in the first region of the first wiring portion, the plurality of second openings are formed in a grid shape near the connection portion and in a slit shape extending in the first direction in a portion other than near the connection portion.

2. The semiconductor device according to claim 1, wherein in a plan view, an overlapping region between the first wiring and the connection region is included in the first region.

3. The semiconductor device according to claim 1, wherein the plurality of second openings are formed in a slit shape in the first region of the first wiring.

4. The semiconductor device according to claim 1, wherein the plurality of second openings are formed in a grid shape in the first region of the first wiring.

5. The semiconductor device according to claim 1, wherein assuming that a first width of the first wiring when the plurality of second openings are not formed in the first wiring is 0.6 μm or more, in the first region of the first wiring, the plurality of second openings are formed below the connection region so that a portion having a width of 0.6 μm or more is not generated in the first wiring.

6. The semiconductor device according to claim 1, wherein the first insulating film is composed of a stacked film of a second insulating film and a third insulating film on the second insulating film, the third insulating film is composed of a resin film, the first opening is formed by a third opening of the second insulating film and a fourth opening of the third insulating film, in a plan view, the third opening is included inside the fourth opening, the second wiring is connected to the first pad exposed from the third opening of the second insulating film.

7. The semiconductor device according to claim 6, wherein When viewed from above, the overlapping region between the first wiring and the third opening is included in the first region.

8. The semiconductor device according to claim 7, wherein: When viewed from above, the overlapping region between the first wiring and the fourth opening is included in the first region.

9. The semiconductor device according to claim 8, wherein: Assuming that the first width of the first wiring when the plurality of second openings are not formed in the first wiring is 0.6 μm or more, Below the fourth opening, the plurality of second openings are formed in the first region of the first wiring such that no portion with a width of 0.6 μm or more is generated in the first wiring.

10. The semiconductor device according to claim 8, wherein: When viewed from above, the plurality of second openings are not formed in a region that is 5 μm or more away from the fourth opening.

11. The semiconductor device according to claim 8, wherein: The plurality of second openings are formed in a slit shape in the first region of the first wiring.

12. The semiconductor device according to claim 8, wherein: The plurality of second openings are formed in a grid shape in the first region of the first wiring.

13. The semiconductor device according to claim 8, wherein: The second insulating film is composed of a stacked film of a fourth insulating film and a fifth insulating film formed on the fourth insulating film. The fourth insulating film is composed of a silicon oxide film, and the fifth insulating film is composed of a silicon oxynitride film or a silicon nitride film.

14. The semiconductor device according to claim 1, wherein: The first pad is an aluminum pad, The second wiring is a copper wiring.

15. The semiconductor device according to claim 1, wherein: The first wiring is a power supply wiring or a ground wiring.

16. The semiconductor device according to claim 1, wherein: On the first insulating film, there is also a protective insulating film formed to cover the second wiring, The protective insulating film has a fifth opening that exposes the second pad.

17. The semiconductor device according to claim 1, wherein: There is also a third wiring that extends below the first pad and is on the same layer as the first wiring, When viewed from above, at least a part of the third wiring overlaps with the first pad, The end of the third wiring is located below the connection region, No opening is formed in the third wiring, The second width of the third wiring is smaller than the first width of the first wiring assuming that the plurality of second openings are not formed in the first wiring.

18. The semiconductor device according to claim 17, wherein: The first wiring is a power supply wiring or a ground wiring, The third wiring is a signal wiring.

19. A semiconductor device, characterized in that, It has: A semiconductor substrate; A first wiring formed on the semiconductor substrate with a first interlayer insulating film therebetween; A second interlayer insulating film formed on the first interlayer insulating film to cover the first wiring; A first pad formed on the second interlayer insulating film; A first insulating film is formed on the second interlayer insulating film and has a first opening exposing the first pad; A second wiring is formed on the first insulating film including above the first pad exposed from the first opening and is electrically connected to the first pad; And A second pad is formed on the first insulating film and is integrally connected to the second wiring, wherein the first insulating film is composed of a stacked film of a second insulating film and a third insulating film on the second insulating film, the third insulating film is composed of a resin film, the first opening is formed by a third opening of the second insulating film and a fourth opening of the third insulating film, when viewed from above, the third opening is included inside the fourth opening, the second wiring is connected to the first pad exposed from the third opening of the second insulating film, when viewed from above, at least a part of the first wiring overlaps with the first pad, the end of the first wiring is located below the fourth opening, a plurality of second openings are formed in a first region of the first wiring, when viewed from above, at least a part of the first region overlaps with the fourth opening, the first wiring integrally has a first wiring portion extending in a first direction and a second wiring portion extending in a second direction intersecting the first direction, a connecting portion of the first wiring portion and the second wiring portion is included in the first region, in the first region of the first wiring portion, the plurality of second openings are formed in a grid shape near the connecting portion and in a slit shape extending in the first direction in a portion other than near the connecting portion.

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