Semiconductor device and method for manufacturing the same

Abstract

Semiconductor device and method for manufacturing the same. The present invention discloses a semiconductor device comprising: a first substrate; a first metal pillar on a first side of the first substrate; a first semiconductor grain coupled to the first side of the first substrate; a second metal pillar on the first metal pillar; a second semiconductor grain coupled to the first semiconductor grain; a second substrate on the second metal pillar and the second semiconductor grain; and an encapsulation material between the first substrate and the second substrate and encapsulating at least one side of each of the first metal pillar, the first semiconductor grain, the second metal pillar, and the second semiconductor grain.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Current semiconductor devices and methods for manufacturing semiconductor devices are inadequate, for example resulting in manufacturing processes that are too time consuming and / or too expensive, resulting in semiconductor packages that have unreliable connections and / or interconnect structures that have suboptimal dimensions, etc. Further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing these methods with the disclosure set forth in the remainder of this disclosure with reference to the accompanying drawings. Summary of the invention

[0003] Various aspects of the present invention provide semiconductor devices and methods of manufacturing semiconductor devices. As non-limiting examples, various aspects of the present invention provide semiconductor devices including stacked die structures and methods of manufacturing the same.

[0004] One aspect of the present invention is a semiconductor device, comprising: a first substrate; a first metal pillar on a first side of the first substrate; a first semiconductor grain coupled to the first side of the first substrate; a second metal pillar on the first metal pillar; a second semiconductor grain coupled to the first semiconductor grain; a second substrate on the second metal pillar and on the second semiconductor grain; and an encapsulation material between the first substrate and the second substrate and encapsulating at least one side of each of the first metal pillar, the first semiconductor grain, the second metal pillar, and the second semiconductor grain.

[0005] In the aforementioned aspect, the encapsulation material includes: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal column starting from the first substrate; and a second encapsulation material, wherein the second encapsulation material has the same height as the second metal column starting from the second substrate.

[0006] In the aforementioned aspect, the first encapsulating material and the second encapsulating material are formed of the same material.

[0007] In the aforementioned aspect, the first encapsulation material has a height higher than that of the first semiconductor die, measured from the first substrate, and the first encapsulation material encapsulates the first side of the first semiconductor die.

[0008] In the aforementioned aspects, the encapsulating material is a single continuous material layer.

[0009] In the aforementioned aspect, the semiconductor device includes an adhesive member coupling the first semiconductor die and the second semiconductor die to each other.

[0010] In the aforementioned aspect, the encapsulation material includes: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal pillar from the first substrate; and a second encapsulation material surrounding the adhesive member.

[0011] In the aforementioned aspect, the adhesive component has the same height as the second encapsulating material, measured from the second substrate.

[0012] In the aforementioned aspect, the active side of the first semiconductor die is electrically coupled to the active side of the second semiconductor die at least through the first substrate, the first metal pillar, the second metal pillar, and the second substrate.

[0013] In the aforementioned state, the first metal column and the second metal column are offset from each other in a direction perpendicular to the stacking direction of the first metal column and the second metal column; and the semiconductor device includes a column redistribution structure, and the first metal column and the second metal column are electrically connected through the column redistribution structure.

[0014] In the aforementioned state, the encapsulation material includes: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal column, starting from the first substrate; and a second encapsulation material, which is between the first encapsulation material and the second substrate, wherein the column redistribution structure is above the first encapsulation material, and at least a portion of the column redistribution structure is embedded in the second encapsulation material.

[0015] In the aforementioned aspect, the center of the second semiconductor grain is displaced from the center of the first semiconductor grain in a direction perpendicular to a stacking direction in which the first semiconductor grain and the second semiconductor grain are stacked.

[0016] In the aforementioned aspect, there is no intermediate layer between the first metal pillar and the second metal pillar.

[0017] Another aspect of the present invention is a semiconductor device, comprising: a first substrate; a first metal pillar, which is plated on a first side of the first substrate; a first semiconductor grain, comprising: a first side, which is away from the substrate; and a second side, which faces the substrate and includes a plurality of pads connected to the first side of the substrate with a plurality of conductive bumps; a second metal pillar, which is plated on the first metal pillar; a second semiconductor grain, comprising: a first side, which is away from the first semiconductor grain and includes a plurality of pads; and a second side, which is coupled to the first side of the first semiconductor grain; a second substrate, comprising: a first side, which is away from the second semiconductor grain; and a second side, which faces the first semiconductor grain and includes a conductive layer connected to the plurality of pads of the second semiconductor grain; and an encapsulation material, which is between the first substrate and the second substrate and encapsulates at least the first metal pillar, the first semiconductor grain, the second metal pillar and the lateral sides of the second semiconductor grain.

[0018] In another aspect of the foregoing, the encapsulation material includes: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal pillar from the first substrate; and a second encapsulation material extending completely between the first encapsulation material and the second substrate.

[0019] In another aspect of the foregoing, the semiconductor device includes an adhesive member coupling the first semiconductor die and the second semiconductor die to each other.

[0020] In another aspect of the above, the encapsulation material includes: a first encapsulation material; and a second encapsulation material, wherein the second encapsulation material has the same height as the adhesive component, starting from the second substrate.

[0021] In another aspect of the above, the second metal column is directly plated on the first metal column.

[0022] In another aspect of the above, the semiconductor device includes a pillar redistribution structure, wherein the first metal pillar and the second metal pillar are electrically connected through the pillar redistribution structure.

[0023] Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: providing a first substrate; forming a first metal pillar on a first side of the first substrate; coupling a first semiconductor grain to the first side of the first substrate; forming a second metal pillar on the first metal pillar; coupling a second semiconductor grain to the first semiconductor grain; forming a second substrate on the second metal pillar and on the second semiconductor grain; and forming an encapsulation material between the first substrate and the second substrate, the encapsulation material encapsulating at least one side of each of the first metal pillar, the first semiconductor grain, the second metal pillar and the second semiconductor grain. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flowchart is shown of an exemplary method of fabricating a semiconductor device according to various aspects of the present invention.

[0025] Figures 2A to 2J Cross-sectional views are shown to illustrate various steps of a method of manufacturing a semiconductor device according to various aspects of the present invention.

[0026] Figure 3 Cross-sectional views of exemplary semiconductor devices according to various aspects of the present disclosure are shown.

[0027] Figure 4 Cross-sectional views of exemplary semiconductor devices according to various aspects of the present disclosure are shown.

[0028] Figure 5 Cross-sectional views of exemplary semiconductor devices according to various aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0029] The following discussion presents various aspects of the present invention by providing examples of the present invention. These examples are non-limiting, and thus the scope of the various aspects of the present invention is not necessarily limited by any specific features of the examples provided. In the following discussion, the terms "for example," "such as," and "exemplary" are non-limiting and are generally synonymous with "by way of example and not limitation," "for example and not limitation," and similar terms.

[0030] As used herein, "and / or" means any one or more items in a list connected by "and / or". As an example, "x and / or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" means the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z".

[0031] The terms used herein are only used for the purpose of describing specific examples and are not intended to limit the present invention. As used herein, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise. It is further understood that the terms "include", "comprise", "include", "include", "have", "have", "contain" and similar terms used in this specification specify the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0032] It should be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, for example, without departing from the teachings of the present invention, the first element, the first component, or the first part discussed below can be referred to as the second element, the second component, or the second part. Similarly, various spatial terms such as "upper", "above", "lower", "below", "side", "lateral", "horizontal", "vertical" and similar terms can be used to distinguish one element from another element in a relative manner. However, it should be understood that the assembly can be oriented in different ways, for example, the semiconductor device can be turned sideways so that its "top" surface faces horizontally and its "side" surface faces vertically, without departing from the teachings of the present invention.

[0033] It will also be understood that unless expressly stated otherwise, the terms coupled, connected, attached and similar terms include both direct and indirect (e.g., with intervening elements) couplings, connections, attachments, etc. For example, if element A is coupled to element B, element A may be indirectly coupled to element B through an intervening signal distribution structure, element A may be directly coupled to element B (e.g., directly adhered to, directly welded to, attached by direct metal-to-metal bonding, etc.), etc.

[0034] In the accompanying drawings, the sizes (e.g., absolute and / or relative sizes) of structures, layers, regions, etc. may be exaggerated for clarity. Although such dimensions are generally representative of exemplary embodiments, they are not limiting. For example, if structure A is illustrated as being larger than region B, this is generally representative of exemplary embodiments, but unless otherwise specified, structure A is generally not required to be larger than structure B. Additionally, in the accompanying drawings, like reference numerals may refer to like elements throughout the discussion.

[0035] With the current trend toward smaller and thinner electronic products, it is generally desired that semiconductor devices used in such electronic products have increased functionality and reduced size. These goals have led to the development of various semiconductor packaging technologies. Examples of such packaging technologies include a PoP (Package-on-Package) configuration in which a semiconductor package is stacked on another package, a PiP (Package-in-Package) configuration in which a semiconductor package is installed in another package, and the like. However, such packaging technologies are generally associated with increased package (or device) thickness and relatively complex manufacturing processes, such as involving increased cycle time, increased cost, increased chance of defects, and the like.

[0036] Various aspects of the present invention provide semiconductor devices (also referred to herein as semiconductor packages) and methods of manufacturing the same, wherein the semiconductor devices have a reduced overall thickness and facilitate stacking of semiconductor dies.

[0037] Various aspects of the present invention provide a semiconductor device comprising: a first substrate; a first metal pillar on a first side of the first substrate; a first semiconductor grain coupled to the first side of the first substrate; a second metal pillar on the first metal pillar; a second semiconductor grain coupled to the first semiconductor grain; a second substrate on the second metal pillar and on the second semiconductor grain; and an encapsulation material between the first substrate and the second substrate and encapsulating at least one side of each of the first metal pillar, the first semiconductor grain, the second metal pillar, and the second semiconductor grain.

[0038] In various exemplary embodiments, the encapsulation material may, for example, include: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal pillar from the first substrate; and a second encapsulation material, wherein the second encapsulation material has the same height as the second metal pillar from the second substrate. The first encapsulation material and the second encapsulation material may be formed of the same material. The first encapsulation material may, for example, have a height higher than the height of the first semiconductor die from the first substrate, and the first encapsulation material may encapsulate the first side of the first semiconductor die.

[0039] In various exemplary embodiments, the semiconductor device may, for example, include an adhesive member coupling the first semiconductor die and the second semiconductor die to each other. In an exemplary embodiment, the encapsulation material may include: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal pillar from the first substrate; and a second encapsulation material, wherein the second encapsulation material has the same height as the second metal pillar from the second substrate and surrounds the adhesive member. The adhesive member may, for example, have the same height as the second encapsulation material from the second substrate.

[0040] In various exemplary embodiments, the active side of the first semiconductor die is electrically coupled to the active side of the second semiconductor die through at least the first substrate, the first metal pillar, the second metal pillar, and the second substrate.

[0041] In various exemplary embodiments, the first metal pillar and the second metal pillar may be offset from each other in a direction perpendicular to a stacking direction of the first metal pillar and the second metal pillar; and the semiconductor device includes a pillar redistribution structure electrically connecting the first metal pillar and the second metal pillar. The encapsulation material may, for example, include: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal pillar from the first substrate; and a second encapsulation material between the first encapsulation material and the second substrate, wherein the pillar redistribution structure is above the first encapsulation material, and at least a portion of the pillar redistribution structure is embedded in the second encapsulation material.

[0042] In various exemplary embodiments, the second semiconductor grain may be displaced from the first semiconductor grain in a direction perpendicular to a stacking direction in which the first semiconductor grain and the second semiconductor grain are stacked. Furthermore, in various exemplary embodiments, there may be no intermediate layer between the first metal pillar and the second metal pillar.

[0043] Various aspects of the present disclosure also provide a semiconductor device, which includes: a first substrate; a first metal pillar, which is plated on a first side of the first substrate; a first semiconductor grain, including: a first side, which is away from the substrate; and a second side, which faces the substrate and includes a plurality of pads connected to the first side of the substrate with a plurality of conductive bumps; a second metal pillar, which is plated on the first metal pillar; a second semiconductor grain, including: a first side, which is away from the first semiconductor grain and includes a plurality of pads; and a second side, which is coupled to the first side of the first semiconductor grain; a second substrate, including: a first side, which is away from the second semiconductor grain; and a second side, which faces the first semiconductor grain and includes a conductive layer connected to the plurality of grain pads of the second semiconductor grain; and an encapsulation material, which is between the first substrate and the second substrate and encapsulates at least the first metal pillar, the first semiconductor grain, the second metal pillar and the lateral sides of the second semiconductor grain.

[0044] In various exemplary embodiments, the encapsulation material may include: a first encapsulation material, wherein the first encapsulation material has the same height as the first metal pillar from the first substrate; and a second encapsulation material extending completely between the first encapsulation material and the second substrate.

[0045] In various exemplary embodiments, the semiconductor device may include an adhesive member coupling the first semiconductor die and the second semiconductor die to each other. The encapsulation material may, for example, include: a first encapsulation material; and a second encapsulation material, wherein the second encapsulation material has the same height as the adhesive member from the second substrate.

[0046] In various exemplary embodiments, the second metal pillar may be directly plated on the first metal pillar. In various exemplary embodiments, the semiconductor device may include a pillar redistribution structure, wherein the first metal pillar and the second metal pillar are electrically connected through the pillar redistribution structure.

[0047] Various aspects of the present disclosure provide a method for manufacturing a semiconductor device, wherein the manufacturing method includes: providing a first substrate; forming a first metal pillar on a first side of the first substrate; coupling a first semiconductor grain to the first side of the first substrate; forming a second metal pillar on the first metal pillar; coupling a second semiconductor grain to the first semiconductor grain; forming a second substrate on the second metal pillar and on the second semiconductor grain; and forming an encapsulation material between the first substrate and the second substrate, the encapsulation material encapsulating at least one side of each of the first metal pillar, the first semiconductor grain, the second metal pillar, and the second semiconductor grain.

[0048] Various aspects of the present invention will now be described in detail with reference to the accompanying drawings so that they can be easily implemented by those skilled in the art.

[0049] Figure 1 A flow chart is shown of an exemplary method 100 of fabricating a semiconductor device according to various aspects of the present invention. Figures 2A-2J Shows the Figure 1 The following discussion will refer to the cross-sectional view of an exemplary semiconductor device during the manufacture of the exemplary method 100. Figure 1 and Figures 2A-2J .

[0050] refer to Figure 1 , an exemplary method 100 for manufacturing a semiconductor device may include: (S1) forming a first substrate, (S2) forming a first metal pillar, (S3) attaching a first semiconductor die, (S4) forming a first encapsulation material, (S5) performing a first thinning, (S6) forming a second metal pillar, (S7) attaching a second semiconductor die, (S8) forming a second encapsulation material, (S9) performing a second thinning, (S10) forming a second substrate, (S11) attaching an interconnect structure, and (S12) singulation. Reference will now be made to Figures 2A-2J To describe Figure 1 The various blocks (or steps, phases, processes, etc.) of the exemplary method 100 are shown.

[0051] refer to Figure 1 and Figure 2A 200a, the exemplary method 100 may include forming (or providing, receiving, etc.) a carrier 105 and forming a first substrate 110 on the carrier 105 at block S1. The carrier 105 may include any of a variety of characteristics, non-limiting examples of which are provided herein. The carrier 105 may, for example, include a carrier for a single semiconductor device (or package), or may, for example, include a wafer or panel on which any number of semiconductor devices (or packages) may be formed. The carrier 105 may, for example, include a semiconductor wafer or panel. The carrier 105 may also, for example, include a glass wafer or panel, a metal wafer or panel, a ceramic wafer or panel, a plastic wafer or panel, etc.

[0052] In an exemplary embodiment, the carrier 105 may be received without the first substrate 110 already formed thereon. In this embodiment, the first substrate 110 need not be formed at block S1. In another exemplary embodiment, the carrier 105 may be received without the first substrate 110 (or a portion thereof) formed thereon, and block S1 may include forming the first substrate 110 (or the remainder thereof) thereon. Note that the first substrate 110 may also be referred to herein as an interposer.

[0053] For example, block S1 may include forming a first substrate 110 having any number of dielectric layers and conductive layers (e.g., signal distribution layers, pad layers, conductive vias, under bump metallization, etc.). In an exemplary embodiment, the first substrate 110 including a signal distribution layer 112, a dielectric layer 111, and a pad (or via) layer 113 may be formed on a carrier 105.

[0054] The signal distribution layer 112 (which may also be referred to herein as a redistribution layer, a distribution layer, a conductive layer, a trace layer, etc.) may include any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present invention is not limited thereto. The signal distribution layer 112 (or the first substrate 110) may, for example, provide an electrical signal path between a plurality of terminals of the first semiconductor die 130 and the corresponding first metal pillars 120.

[0055] Block S1 may include forming a signal distribution layer 112 in any of a variety of ways, non-limiting examples of which are presented herein. For example, block S1 may include forming the signal distribution layer 112 using any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited thereto. The signal distribution layer 112 may be formed, for example, directly on the carrier 105, on an intermediate dielectric layer, etc.

[0056] In various exemplary embodiments, such as where the signal distribution layer 112 is electroplated, block S1 may include forming one or more seed layers prior to electroplating the signal distribution layer 112. For example, although Figure 2A Not shown, block S1 may include forming one or more seed layers on the top surface of carrier 105. Such seed layers may include any of a variety of materials. For example, the seed layer may include copper. For another example, the seed layer may include one or more layers of any of a variety of metals (e.g., silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc.). The seed layer may be formed using any of a variety of techniques (e.g., sputtering or other physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD), electroless plating, electrolytic plating, etc.). The seed layer may be used, for example, in a subsequent electroplating process.

[0057] Note that in various exemplary embodiments, the carrier 105 may be provided (or formed) with an oxide and / or nitride layer (or other dielectric material) thereon, in which case block 105 may include removing the layer before forming the substrate 110, forming the substrate 110 on the layer, forming another layer on the carrier 105 before forming the substrate 110, and the like.

[0058] The dielectric layer 111 may include one or more layers of any of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, polysilicone, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present invention is not limited to this.

[0059] Block S1 may include forming a dielectric layer 111 using any one or more of a variety of processes (e.g., spin coating, spraying, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the scope of the present invention is not limited to this.

[0060] For example, block S1 may also include patterning dielectric layer 111, such as forming holes therein that expose various portions of various conductive layers discussed herein (e.g., signal distribution layer 112, other signal distribution layers, conductive layers, pad layers, etc.). For example, block S1 may include ablating holes (e.g., using laser ablation, using mechanical ablation, using etching, etc.). Also for example, block S1 may include initially forming dielectric layer 111 with desired holes (e.g., deposition, etc.).

[0061] The pad (or via) layer 113, which may also be referred to herein as a pad, via, trace, land, bonding pad layer, conductive layer, trace layer, etc., may include any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present invention is not limited to this.

[0062] Block S1 may include forming a liner (or via) layer 113 in any of a variety of ways, non-limiting examples of which are presented herein. For example, block S1 may include forming the liner layer 113 using any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited in this regard. For example, block S1 may include forming the liner layer 113 on a portion of the signal distribution layer 112 exposed by a hole in the dielectric layer 111, on a portion of the dielectric layer 111, etc.

[0063] As with the signal distribution layer 112 or any conductive layer discussed herein, block S1 may include forming one or more seed layers as part of the process of forming the pad (or via) layer 113 (e.g., before electroplating the pad layer 113, etc.). For example, while Figure 2A Not shown, but block S1 may include forming one or more seed layers on a top surface of the signal distribution layer 112 , on a top surface of the dielectric layer 111 and / or a hole surface, etc.

[0064] Note that although an illustrative set of conductive and dielectric layers are shown in the figures, block S1 may include forming the first substrate 110 to have any number of such conductive and / or dielectric layers.

[0065] As discussed herein, carrier 105 may include a silicon (or other semiconductor) wafer. In this case, signal distribution layer 112, dielectric layer 111, and pad (or via) layer 113 may be formed in a semiconductor wafer manufacturing process (e.g., in a wafer fab facility, etc.). Any or all of these layers may also be formed, for example, in a packaging process (e.g., a semiconductor device packaging apparatus, etc.), for example, to which a semiconductor wafer may be received as input.

[0066] At any of the various stages of the exemplary method 100, at least a portion of the carrier 105 (and in some exemplary embodiments, all of the carrier) may be removed. Such removal may be performed in any of a variety of ways (e.g., by mechanically grinding the back side of the carrier 105 or a portion thereof, by chemically etching the back side of the carrier 105 or a portion thereof, by performing chemical / mechanical planarization (CMP), etc.). In other exemplary embodiments, the carrier 105 or a portion thereof may be removed by peeling, stretching, shearing, etc. Thus, the scope of the present invention should not be limited by any particular manner of removing all or a portion of the carrier 105. Note that although the carrier 105 is generally shown as a thin layer in the figures, the carrier 105 may be relatively thick (e.g., to provide structural support during various stages of the packaging process) until it is thinned and / or removed.

[0067] Generally, block S1 may include forming (or providing or receiving) a carrier 105 and / or forming a first substrate 110 thereon. Thus, the scope of the present invention should not be limited by the characteristics of any particular carrier or substrate or by the characteristics of any particular manner of forming such a carrier or substrate.

[0068] refer to Figure 1 and Figure 2B In the exemplary structure 200b, the exemplary method 100 may include forming a first metal (or conductive) pillar or a plurality of first metal pillars at block S2. For example, the first metal pillar 120 may be formed on the first substrate 110 (e.g., on its pad layer 113, on its signal distribution layer 112, etc.).

[0069] In an exemplary embodiment, block S2 may include forming a first metal pillar 120 to vertically extend from a liner layer 113 (or a redistribution layer 112) of a first substrate 110. Such formation may be performed in various methods, non-limiting examples of which are provided herein.

[0070] In an exemplary embodiment, block S2 may, for example, include forming a first metal pillar 120 on a corresponding interconnect pad of the pad layer 113 (e.g., formed or received in block S1) or forming a first metal pillar 120 on another conductive layer portion. As discussed herein, the corresponding interconnect pad may, for example, include any of a variety of conductive materials (e.g., copper, aluminum, silver, gold, nickel, alloys thereof, etc.). The corresponding interconnect pad may, for example, be exposed through a hole in the dielectric layer 111 or another dielectric layer. The dielectric layer 111 may, for example, cover the side surface of the corresponding interconnect pad and / or the outer periphery of the top surface of the corresponding interconnect pad.

[0071] In an exemplary embodiment, an under bump metallization (UBM) structure 110a may be formed, and then a first metal pillar 120 may be formed thereon. The UBM structure 110a may also be referred to herein as a pillar seed layer 110a.

[0072] In an exemplary embodiment, block S2 (or block S1) may include forming a UBM seed layer of the UBM structure 110a on the dielectric layer 111 and / or on the portion of the corresponding interconnect pad of the pad layer 113 exposed by the hole in the dielectric layer 111. The UBM seed layer may, for example, include any of a variety of conductive materials (e.g., copper, gold, silver, metal, etc.). The UBM seed layer may be formed in any of a variety of ways (e.g., sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

[0073] Block S2 may, for example, include forming a mask (or template) on the UBM seed layer to define the area where one or more UBM layers and / or the first metal pillar 120 (or other interconnect structures) are to be formed in the UBM structure 110a. For example, the mask may include a photoresist (PR) material or other material, which may be patterned to cover the area other than the area where the UBM layer and / or the first metal pillar 120 are to be formed. Then, block S2 may, for example, include forming one or more UBM layers on the UBM seed layer exposed by the mask. The UBM layer may include any of a variety of materials (e.g., titanium, chromium, aluminum, titanium / tungsten, titanium / nickel, copper, alloys thereof, etc.). Block S2 may include forming a UBM layer on the UBM seed layer in any of a variety of ways (e.g., electroplating, sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

[0074] Then, block S2 may, for example, include forming a first metal pillar 120 (or a rod or other interconnect structure) on the UBM structure 110a (or a pillar seed layer). The first metal pillar 120 may include any of a variety of characteristics. For example, the first metal pillar 120 may be cylindrical, elliptical, rectangular rod-shaped, etc. The first metal pillar 120 may, for example, include a flat upper end, a concave upper end, or a convex upper end. The first metal pillar 120 may, for example, include any material discussed herein with respect to the conductive layer. In an exemplary embodiment, the first metal pillar 120 may include copper (e.g., pure copper, copper with some impurities, a copper alloy, etc.). In an exemplary embodiment, block S2 (or another block of the exemplary method 100) may also include forming a solder cap (or dome) on the first metal pillar 120. Block S2 may include forming the first metal pillar 120 in any manner (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited to this.

[0075] After forming the first metal pillar 120, if a mask is used, block S2 may include stripping or removing the mask (e.g., chemical stripping, ashing, etc.). In addition, block S2 may include removing at least a portion of the UBM seed layer (e.g., at least the portion not covered by the first metal pillar 120 (e.g., by chemical etching, etc.)). Note that, for example, during the etching of the UBM seed layer, at least a lateral edge portion of the UBM seed layer below the UBM layer may be etched. For example, such etching may result in undercutting of the first metal pillar 120 and the UBM structure 110a below the UBM layer.

[0076] refer to Figure 1 and Figure 2C In the exemplary structure 200c, the exemplary method 100 can include, at block S3, attaching a first semiconductor die 130 to a top side (or portion) of a first substrate 110. The first semiconductor die 130 can be oriented, for example, with an active side 131 (e.g., typically formed with a semiconductor) of the first semiconductor die 130 facing the first substrate 110 and an inactive side opposite the active side 131 facing away from the first substrate. Note that the active side 131 can also be referred to as a conductive side (e.g., including a die bonding pad electrically connected to a semiconductor circuit of the die), and the inactive side can also be referred to as a non-conductive side (or non-patterned side). For example, as Figure 2CAs shown, the bottom side of the first semiconductor die 130 can be attached to the interconnect pads of the pad layer 113 with conductive bumps 132 (e.g., C4 bumps, micro bumps, metal pillars, conductive balls, etc.). Block S3 can include attaching the first semiconductor die 130 to the top side of the first substrate 110 in various ways (e.g., mass reflow, thermocompression bonding, direct metal-to-metal metal bonding, laser welding, conductive epoxy bonding, etc.).

[0077] The first semiconductor die 130 may be, for example, centrally located on the substrate 110, but may also be laterally offset. For example, a plurality of first semiconductor dies 130 may be attached to the substrate 110 to be included in the same packaged semiconductor device.

[0078] Note that, for example, when attached to substrate 110, first semiconductor die 130 can be taller than first metal pillar 120, shorter than first metal pillar 120, or substantially the same height as first metal pillar 120. As discussed herein, the top of semiconductor die 130 and / or first metal pillar 120 can be planarized at any of the various stages of method 100.

[0079] The first semiconductor die 130 (like the second semiconductor die 160 discussed herein) may include any of a variety of circuit features. For example, the first semiconductor die 130 may include electrical circuits such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, an application-specific integrated circuit (ASIC), volatile and / or non-volatile memory, etc.

[0080] refer to Figure 1 and Figure 2D 2. Referring to the exemplary structure 200d, the exemplary method 100 may include, at block S4, forming a first encapsulating material 140. Block S4 may include forming the first encapsulating material 140 (or encapsulant) in any of a variety of ways, non-limiting examples of which are provided herein.

[0081] The first encapsulation material 140 may include any of a variety of encapsulation or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxies, epoxy resins with fillers, epoxy acrylates with fillers, silicones, combinations thereof, equivalents, etc.). The first encapsulation material 140 may also include, for example, any of the dielectric materials discussed herein (e.g., with respect to the dielectric layer 111, etc.).

[0082] Block S4 may include forming the first encapsulating material 140 in any of a variety of ways (e.g., compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, film assisted molding, etc.). Also for example, block S4 may include forming the first encapsulating material 140 using any of a variety of techniques that may be used to form dielectric layers, examples of which are provided herein (e.g., with respect to forming dielectric layer 111, etc.).

[0083] like Figure 2D As shown, the first encapsulation material 140 can cover the top side of the substrate 110 (e.g., any dielectric and / or conductive layers exposed on the top side of the substrate 110). The first encapsulation material 140 can also cover the lateral sides of the first semiconductor grain 130 (or multiple first semiconductor grains) and / or the first metal pillar 120 (or multiple first metal pillars) in whole or in part. The first encapsulation material 140 can be formed to also cover the top side of the first semiconductor grain 130 and / or the top side of the first metal pillar 120. Although Figure 2D While the first encapsulation material 140 and other figures herein show only the top side of the first substrate 110, it should be understood that the first encapsulation material 140 may also be formed to cover the lateral sides of the first substrate 110 (e.g., after the first substrate 110 is separated from a wafer or panel or other group of substrates).

[0084] Note that the first encapsulation material 140 may also be filled under the first semiconductor die 130, and / or an underfill separate from the first encapsulation material 140 may be applied during and / or after the attachment of the first semiconductor die 130. For example, such an underfill may include any of various types of materials, such as, but not limited to, epoxy resins, thermoplastic materials, heat-curable materials, polyimides, polyurethanes, polymer materials, filled epoxies, filled thermoplastic materials, filled heat-curable materials, filled polyimides, filled polyurethanes, filled polymer materials, fluxed underfills, and their equivalents. Such underfill may be performed using a capillary underfill process, using a pre-applied underfill, and the like.

[0085] refer to Figure 1 and Figure 2EIn the exemplary structure 200e, the exemplary method 100 may include, at block S5, thinning the assembly encapsulated at block S4 (e.g., performing a first thinning operation, etc.). For example, block S5 may include thinning the top side of the first encapsulation material 140 to a desired thickness (e.g., mechanical grinding, chemical etching, shaving or shearing, peeling, any combination thereof, etc.). For example, block S5 may include thinning the first semiconductor grain 130 (or multiple first semiconductor grains) and / or the first metal pillar 120 (or multiple first metal pillars) (e.g., mechanical grinding, chemical etching, shaving, peeling, any combination thereof, etc.). Figure 2E In the exemplary embodiment shown, block S5 includes performing thinning in a manner that causes the top surfaces of the first encapsulation material 140, the first semiconductor die 130, and / or the first metal pillar 120 to be coplanar, so that at least the respective top surfaces (and / or at least the upper portions of the lateral side surfaces) of the first semiconductor die 130 and the first metal pillar 120 are exposed from (or at) the top surface of the first encapsulation material 140. Note that while the exemplary embodiment shows the top side of the first semiconductor die 130 exposed from the first encapsulation material 140, such exposure is not necessary. For example, in various embodiments, a thin layer of the first encapsulation material 140 covering the top side of the first semiconductor die 130 may remain.

[0086] In various exemplary embodiments, blocks S1-S5 (and / or resulting structures) may share any or all features with substantially similar blocks (and / or resulting structures) shown in U.S. patent application Ser. No. 14 / 823,689, filed on August 11, 2016, entitled “Semiconductor Package and Method of Fabrication Thereof,” the entire contents of which are incorporated herein by reference in their entirety for all purposes.

[0087] refer to Figure 1 and Figure 2F In the exemplary structure 200f, the exemplary method 100 may include forming a second metal pillar (or a plurality of second metal pillars) at block S6. The second metal pillar 150 may be formed on the first metal pillar 120 (e.g., directly formed, formed with one or more intermediate layers). In addition, for example, each of the plurality of second metal pillars 150 may be formed on a corresponding first metal pillar in the plurality of first metal pillars 120.

[0088] In an exemplary embodiment, block S6 may include forming a second metal pillar 150 to extend vertically from the first metal pillar 120. This formation may be performed in any of a variety of ways, non-limiting examples of which are provided herein. For example, block S6 may include forming the second metal pillar 150 in the same manner as the first metal pillar 120 is formed at block S2. For example, block S6 may include forming the second metal pillar 150 in a different manner than the first metal pillar 120 is formed.

[0089] In an exemplary embodiment, block S6 may, for example, include forming a second metal pillar 150 on (e.g., directly or indirectly) a corresponding first metal pillar 120. As discussed herein, the first metal pillar 120 may, for example, include any of a variety of conductive materials (e.g., copper, aluminum, silver, gold, nickel, alloys thereof, etc.). The first metal pillar 120 (e.g., a top surface thereof, a top portion of a side surface thereof, etc.) may, for example, be exposed at a top surface of the first encapsulation material 140. The first encapsulation material 140 may, for example, cover a lower portion or all of a lateral side of the first metal pillar 120 and / or may cover an outer perimeter of a top surface of the first metal pillar 120.

[0090] In an exemplary embodiment, block S6 may include forming a second metal pillar 150 directly on the top surface of the first metal pillar 120. Note that the lateral and / or vertical dimensions (and / or shape) of the second metal pillar 150 may match the lateral and / or vertical dimensions (and / or shape) of the corresponding first metal pillar 120, but this is not necessarily the case. For example, the second metal pillar 150 may include smaller or larger lateral and / or vertical dimensions than the first metal pillar 120.

[0091] In another exemplary embodiment, an under bump metallization (UBM) structure (or interface layer structure) may be formed on the first metal pillar 120, and then a second metal pillar 150 may be formed on the UBM structure. If formed, block S6 may include forming such a UBM structure (or interface layer structure) in the same manner as discussed herein with respect to the UBM structure 110a (or pillar seed layer) that may be formed at block S2, such as using the same or similar masking process, metal forming process, masking and / or metal removal process, etc.

[0092] The second metal pillar 150 may include any of a variety of features. For example, the second metal pillar 150 may be cylindrical, elliptical, rectangular rod-shaped, etc. The second metal pillar 150 may, for example, include a flat upper (and / or lower) end, a concave upper (and / or lower) end, or a convex upper (and / or lower) end. For example, the second metal pillar 150 may include any material discussed herein with respect to the conductive layer, with respect to the first metal pillar 120, etc. In an exemplary embodiment, the second metal pillar 150 may include copper (e.g., pure copper, copper containing impurities, etc., copper alloys, etc.). In an exemplary embodiment, block S6 (or another block of the exemplary method 100) may also include forming a solder cap (or dome) or another metal layer on the second metal pillar 150. Block S6 may include forming the second metal pillar 150 in any of a variety of ways (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited to this.

[0093] As discussed herein, the second metal pillar 150 (or multiple second metal pillars) can be precisely aligned with the corresponding first metal pillar, but such alignment can also be misaligned (e.g., by design or due to manufacturing tolerances). Therefore, there may be surface discontinuities (e.g., steps, sharp curves, etc.) between the second metal pillar 150 and the first metal pillar 120. It is noted that, as described herein, the second metal pillar 150 can be laterally displaced from the first metal pillar 120 so that there is no exact vertical overlap between the second metal pillar 150 and the first metal pillar 120 (e.g., forming a signal distribution structure to electrically connect the second metal pillar 150 and the first metal pillar 120).

[0094] As discussed herein, the second metal pillar 150 can be formed to have any of a variety of height (or vertical) dimensions. For example, block S6 can include forming the second pillar 150 to have a height that is higher than the desired final height (e.g., to compensate for manufacturing tolerances, etc.). Also for example, block S6 can include forming the second metal pillar 150 to have a height that is as high as or higher than the expected height of the second semiconductor die (e.g., installed at block S7, etc.).

[0095] refer to Figure 1 and Figure 2G For the exemplary structure 200g, the exemplary method 100 may include, at block S7, attaching a second semiconductor die 160 (or a plurality of second semiconductor die 160) to a top side (or portion) of the first semiconductor die 160. Block S7 may, for example, share any or all features with block S3.

[0096] In an exemplary embodiment, the second semiconductor grain 160 can be oriented in a manner such that, for example, the active side 161 of the semiconductor grain 160 faces away from the first semiconductor grain 130 and the inactive side of the semiconductor grain 160 faces the first semiconductor grain 130. For example, the respective inactive sides of the first and second semiconductor grains 130 and 160 can face each other. The second semiconductor grain 160 can be, for example, centrally located on the first semiconductor grain 130. The second semiconductor grain 160 can, for example, have a size that is equal to, less than, or greater than the size of the first semiconductor grain 130. Note that, as discussed herein, the second semiconductor grain 160 can be laterally displaced relative to the first semiconductor grain 130. It should also be noted that there can be one or more first semiconductor grains 130 (of the same or different types) and one or more second semiconductor grains 160 (of the same or different types).

[0097] The second semiconductor die 160 (like the first semiconductor die 130 discussed herein) may include any of a variety of circuit features. For example, the second semiconductor die 160 may include electrical circuits such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, an application-specific integrated circuit (ASIC), volatile and / or non-volatile memory, etc. In an exemplary embodiment, the second semiconductor die 160 may perform the same functions as the first semiconductor die 130 (e.g., both perform memory functions, both perform processing functions, etc.). In another exemplary embodiment, the second semiconductor die 160 may perform different functions than the first semiconductor die 130. However, these different corresponding functions may be complementary (e.g., one performs processing functions, one performs memory functions, another die performs communication functions, another die performs sensor functions, etc.).

[0098] For example, Figure 2G As shown, the lower side of the second semiconductor die 160 can be attached to the upper side of the first semiconductor die 130 with an adhesive member 160a. The adhesive member 160a can, for example, include an adhesive paste layer, a liquid adhesive layer, a preformed double-sided tape or sheet (e.g., a die attach tape), etc. The adhesive member 160a can, for example, partially or completely cover the bottom side of the second semiconductor die 160. The adhesive member 160a can also, for example, partially or completely cover the top side of the first semiconductor die 130. For example, although in Figure 2G1 , the adhesive member 160a may cover at least a portion of the top side of the first encapsulation material 140, such as a portion of the top side of the first encapsulation material 140 surrounding the periphery of the first semiconductor die 130 and immediately adjacent to the first semiconductor die 130. The adhesive member 160a may, for example, include a dielectric material that prevents electrical connection between the first semiconductor die 130 and the second semiconductor die 160. However, the adhesive member 160a may be thermally conductive. Note that in various exemplary embodiments, the adhesive member 160a may be electrically conductive.

[0099] Note that the second semiconductor die 160 can be taller than the second metal pillar 150, shorter than the second metal pillar 150, or approximately the same height as the second metal pillar, for example, when attached to the first semiconductor die 130. In an exemplary embodiment, the second semiconductor die 160 can include a conductive bump 162 (or pad, pillar, ball, other interconnect structure, etc.) extending in an upward direction on the active side 161. In such an embodiment, the height of the second metal pillar 150 can be at least as high as the lower end of such conductive bump 162. In such a configuration, the second metal pillar 150 and the conductive bump 162 of the second semiconductor die 160 can be planarized (e.g., at block S9, etc.) without damaging the active circuitry on the active side 161 of the second semiconductor die 160. The top of the conductive bump 162, the second semiconductor die 160, and / or the second metal pillar 150 can be planarized at any of the various stages of the method 100.

[0100] Note that although Figure 1 It is not explicitly shown, but a testing operation may be performed on the assembly prior to attaching the second semiconductor die at block S7.

[0101] refer to Figure 1 and Figure 2H In the exemplary structure 200h of FIG. 1 , the exemplary method 100 may include forming a second encapsulating material 170 at block S8. Block S8 may include forming the second encapsulating material 170 (or encapsulant) in any of a variety of ways, non-limiting examples of which are provided herein. Block S8 may, for example, share any or all features with block S4 discussed herein.

[0102] The second encapsulating material 170 may include various encapsulating or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxies, epoxy resins with fillers, epoxy acrylates with fillers, silicones, combinations thereof, equivalents, etc.). The second encapsulating material 170 may also, for example, include any dielectric material discussed herein (e.g., with respect to the dielectric layer 111, etc.). For example, the encapsulating material 170 may include the same material as the first encapsulating material 140. However, it is noted that in an exemplary embodiment, the second encapsulating material 170 may be a different material than the first encapsulating material 140, such as a material having different physical properties (e.g., a different coefficient of thermal expansion (CTE), elastic modulus, shrink factor, etc.). For example, such an embodiment may be used to reduce or eliminate warpage of a semiconductor package by tuning (or balancing) warpage forces (e.g., due to different corresponding coefficients of thermal expansion of various components of the semiconductor device, etc.).

[0103] Block S8 can include forming the second encapsulating material 170 in any of a variety of ways (e.g., compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, film assisted molding, etc.). Also for example, block S8 can include forming the second encapsulating material 170 using any of a variety of techniques that can be used to form dielectric layers, examples of which are provided herein (e.g., with respect to forming dielectric layer 111, etc.).

[0104] like Figure 2H As shown, the second encapsulation material 170 may cover the top side of the first encapsulation material 140. The second encapsulation material 170 may also cover all or part of the lateral sides of the second semiconductor die 160 and / or the lateral sides of the second metal pillar 150. The second encapsulation material 170 may additionally cover the lateral sides and / or the upper side of the adhesive member 160a. The second encapsulation material 170 may be formed to also cover the top side of the second semiconductor die 160 (e.g., any one or all of the dielectric layers on its top side, the conductive layer on its top side, the conductive bump on the top, etc.) and / or the top side of the second metal pillar 150. As shown in FIG. Figure 2H As shown, the second encapsulation material 170 may cover the lateral sides of the conductive bumps 162 on the active side 161 of the second semiconductor die 160 while the upper ends of the conductive bumps 162 may be exposed. Like the first encapsulation material 140 formed at block S4, the second encapsulation material 170 may be formed simultaneously at the wafer or panel level of multiple semiconductor packages, or may be formed at a single package level.

[0105] It is noted that in exemplary embodiments where there is a space between the second semiconductor die 160 and the first semiconductor die 130 or the first encapsulation material 140 (for example, when the adhesive member 160a does not completely fill such a space, etc.), the second encapsulation material 170 can also be filled below the second semiconductor die 160 between the second semiconductor die 160 and the first semiconductor die 130 and / or the first encapsulation material 140.

[0106] Still reference Figure 1 and 2H , the exemplary method 100 may include, at block S9, thinning the assembly encapsulated at block S8 (e.g., performing a second thinning operation, etc.). For example, block S9 may include thinning (e.g., mechanical grinding, chemical etching, shaving or shearing, peeling, any combination thereof, etc.) the top side of the second encapsulation material 170, the second metal pillar 150, and / or the top side of the second semiconductor die 160 (e.g., the conductive bump 162 on the active side 161 of the second semiconductor die 160) to a desired thickness. Block S9 may, for example, share any or all features with block S5.

[0107] exist Figure 2H In the exemplary embodiment shown, block S9 includes performing thinning in a manner that results in coplanar top surfaces of the second encapsulation material 170, the second semiconductor die 160 (e.g., the conductive bumps 162 or other interconnect structures on its active side 161, etc.), and / or the second metal pillar 150. Thus, at least the respective top surfaces (and / or at least the upper portions of at least the lateral side surfaces) of the conductive bumps 162 on the top sides of the second semiconductor die 160 and the second metal pillar 150 are exposed from the top surface of the second encapsulation material 170.

[0108] As discussed herein, in some embodiments, the second metal pillar 150 can be formed with an interfacial layer (eg, a solder layer, a UBM layer, an interfacial metallization, etc.) on its top end. Figure 2H In the exemplary embodiment shown, block S9 may also include exposing and / or planarizing such an interface layer at a top end of the second metal pillar 150 .

[0109] As discussed herein, the second encapsulating material 170 may be initially formed to have any of a variety of thicknesses. In exemplary embodiments where the second encapsulating material 170 is formed to have a desired thickness and the topside conductor is exposed from the second encapsulating material 170 as desired (e.g., using film assisted molding, spin coating, etc.), the thinning at block S9 may be skipped.

[0110] refer to Figure 1 and Fig.2IAccording to the exemplary structure 200i, the exemplary method 100 may include forming a second substrate 180 at block S10. Block S10 may include, for example, forming the second substrate 180 on top of the second encapsulation material 170, the second metal pillar 150 and / or the second semiconductor die 160.

[0111] Block S10 may include forming a second substrate 180, which may also be referred to herein as an interposer, in any of a variety of ways, non-limiting examples of which are provided herein. For example, block S10 may share any or all features with block S1. For example, block S10 may share any or all features of generally similar blocks (and / or resulting structures) shown in U.S. Patent Application No. 14 / 823,689, entitled “Semiconductor Package and Method of Manufacturing Thereof,” filed on August 11, 2016, the entire contents of which are incorporated herein by reference in their entirety for all purposes.

[0112] For example, block S10 may include forming a second substrate 180 having any number of dielectric layers and conductive layers (e.g., signal distribution layers, pad layers, conductive vias, under-bump metallization, land layers, etc.). In an exemplary embodiment, a second substrate 180 may be formed including a signal distribution layer 182, a dielectric layer 181, and a pad (or via) layer 183. Note that while the second substrate 180 may be substantially different from the first substrate 110, any or all features may be the same, may be vertically and / or horizontally symmetrical, etc.

[0113] The pad (or via) layer 183, which may also be referred to herein as a pad, via, trace, connection pad, bonding pad layer, conductive layer, trace layer, etc., may include any one of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present invention is not limited to this.

[0114] Block S10 may include forming a liner (or via) layer 183 in any of a variety of ways, non-limiting examples of which are presented herein. For example, block S10 may include forming a liner (or via) layer 183 using any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited thereto. Block S10 may, for example, include forming a liner layer 183 on the top side of the second metal pillar 150, on the top side of the conductive bump 162, etc.

[0115] As with any conductive layer discussed herein, block S10 may include forming one or more seed layers as part of the process of forming the pad (or via) layer 183 (e.g., before electroplating the pad layer 183, etc.). For example, while Fig.2I Not shown, block S10 may include forming one or more seed layers on top surfaces of the second metal pillars 150 , the conductive bumps 162 , the second encapsulation material 170 , and the like.

[0116] Note that in various exemplary embodiments, one or more dielectric layers may be formed on the top surface of the second encapsulation material 170 , the second semiconductor die 160 , and / or the second metal pillar 150 before forming the liner (or via) layer 183 .

[0117] The dielectric layer 181 may include one or more layers of any one of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazacyclo (BT), molding materials, phenolic resins, epoxy resins, polysilicone, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present invention is not limited to this.

[0118] Block S10 may include forming a dielectric layer 181 using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the scope of the present invention is not limited to this.

[0119] For example, block S10 may include patterning dielectric layer 181, such as forming holes therein that expose various portions of various conductive layers discussed herein (e.g., pad layer 183, signal distribution layer, etc.). For example, block S10 may include ablating holes (e.g., using laser ablation, using mechanical ablation, using etching, etc.). For another example, block S10 may include initially forming dielectric layer 181 having the desired holes (e.g., deposition, etc.).

[0120] The signal distribution layer 182 (which may also be referred to as a redistribution layer, a distribution layer, a conductive layer, a trace layer, etc.) may include any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present invention is not limited thereto. The signal distribution layer 182 (or the second substrate 180) may, for example, provide an electrical signal path between the terminals of the second semiconductor die 160 and / or the corresponding second metal pillars 120 and / or the corresponding connection pads 184.

[0121] Block S10 may include forming the signal distribution layer 182 in any of a variety of ways, non-limiting examples of which are presented herein. For example, block S10 may include forming the signal distribution layer 182 using any one or more of a variety of processes (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present invention is not limited in this regard.

[0122] Under various exemplary embodiments, such as where the signal distribution layer 182 is electroplated, block S10 may include forming one or more seed layers prior to electroplating the signal distribution layer 182. For example, although Fig.2I Not shown, block S10 may include forming one or more seed layers on the top surface of the second encapsulation material 170, the second semiconductor grains 160 and / or the second metal pillars 150. Such a seed layer may include any of a variety of materials. For example, the seed layer may include copper. For another example, the seed layer may include one or more layers of any of a variety of metals (e.g., silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc.). The seed layer may be formed using any of a variety of techniques (e.g., sputtering or other physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD), electroless plating, electrolytic plating, etc.). The seed layer may be used, for example, in a subsequent electroplating process.

[0123] Block S10 may include forming any number of conductive and dielectric layers of the second substrate 180. Fig.2I In the exemplary embodiment shown, block S10 includes forming a second dielectric layer 185 and a land layer 184. The second dielectric layer 185 and / or its formation may share any or all features with other dielectric layers and / or their formations discussed herein. The land layer 184 and / or its formation may share any or all features with other conductive layers and / or their formations discussed herein. Note that the land layer 184 may also be referred to, for example, as a conductive layer, a pad, a land, a signal distribution structure, etc.

[0124] For example, in an exemplary embodiment, as discussed herein, the connection pad layer 184 may include under-bump metallization. For example, block S10 may include forming the connection pad layer 184 to have one or more metallization layers that facilitate connection to an interconnect structure (e.g., a conductive ball, a conductive post, or a rod, etc.), such as the attachment at block S11. For example, the connection pad layer 184 may be exposed at a top surface of the second substrate 180 (e.g., a second dielectric layer 185, etc.).

[0125] As with the signal distribution layer 182 or any conductive layer discussed herein, block S10 may include forming one or more seed layers as part of the process of forming the connection pad layer 184 (e.g., before electroplating the connection pad layer 184, etc.). Fig.2I Not shown, block S10 may include forming one or more seed layers on a top surface of the signal distribution layer 182 , on a top surface of the dielectric layer 181 , etc. and / or on a hole surface, etc.

[0126] Note that although an illustrative set of conductive and dielectric layers are shown in the figures, block S10 may include forming the second substrate 180 to have any number of such conductive and / or dielectric layers.

[0127] As discussed herein, the first substrate 110 (or interposer) or a portion thereof can be formed in a semiconductor wafer manufacturing process (e.g., in a wafer fab facility, etc.). Also for example, any or all of the layers of the first substrate 110 can be performed in a packaging process, such as a semiconductor wafer can be received as an input to the packaging process. In an exemplary embodiment, the layers of the second substrate 180 (e.g., conductive layers, dielectric layers, etc.) can be performed in the packaging process. Thus, in various exemplary embodiments, one or more substrate portions can be formed in a semiconductor wafer manufacturing process, and one or more substrate portions can be formed in a semiconductor device packaging process.

[0128] Generally, block S10 may include forming a second substrate 180 (or interposer). Thus, the scope of the present invention should not be limited by the features of any particular carrier or substrate or any particular manner of forming such a carrier or substrate.

[0129] refer to Figure 1 and Fig.2I According to the exemplary structure 200 i , the exemplary method 100 may include, at block S11 , forming a conductive interconnect structure 190 on a second substrate 180 .

[0130] Conductive interconnect structure 190 may include any of a variety of features. For example, interconnect structure 190 may include conductive balls or bumps (e.g., solder balls or bumps, wafer bumps, solid core or copper core solder balls, etc.). For example, in exemplary embodiments including solder balls or bumps, such balls or bumps may include tin, silver, lead, Sn-Pb, Sn-Pb, etc. 37 -Pb, Sn 95 The conductive interconnect structure 190 may include any conductive material discussed herein (e.g., metal, conductive adhesive, etc.).

[0131] The conductive interconnect structure 190 can be configured in any or a variety of configurations. For example, the conductive interconnect structure 190 can be configured in a ball grid array configuration, a planar grid array configuration, and the like.

[0132] Block S11 may include forming (or attaching) such an interconnect structure 190 in any of a variety of ways, non-limiting examples of which are provided herein. For example, block S11 may include forming (or attaching) such an interconnect structure 190 by ball dropping, bumping, metal plating, pasting, and reflow, etc. For example, block S11 may include dropping a conductive ball onto the land layer 184 (or pad), reflowing, and cooling.

[0133] Step S11 may also form (or attach) a component 191 (e.g., a passive component, an active component, etc.), for example, on the land layer 184 of the second substrate 180. In an exemplary embodiment, the component 191 may have a smaller height than the conductive interconnect structure 190. For example, the component 191 may have a smaller height than the solder ball conductive interconnect structure 190, a smaller height than the solid core (e.g., a copper core, etc.) of the solder ball conductive interconnect structure 190, etc. In such an embodiment, when the conductive interconnect structure 190 is attached to another substrate or component, the conductive interconnect structure 190 may provide a space to maintain the space of the component 191.

[0134] refer to Figure 1 and Fig.2I Based on the exemplary structure 200i, the exemplary method 100 may include, at block S12, singulating the semiconductor device package from the plurality of connected packages.

[0135] As described herein, any or all blocks of the exemplary method 100 may be performed at the wafer or panel level, such as to form multiple semiconductor packages simultaneously. The wafer or panel may then be singulated into individual packages, for example. Such singulation may be performed, for example, by any one or more of mechanical cutting (e.g., sawing, cutting, grinding, biting, etc.), energy cutting (e.g., laser cutting, plasma cutting, etc.), chemical cutting (e.g., etching, dissolving, etc.), etc. In an exemplary embodiment, such singulation may form coplanar lateral side surfaces of the package. For example, one or more lateral side surfaces of the first substrate 110, the first encapsulation material 140, the second encapsulation material 170, and / or the second substrate 180 may be coplanar on one or more lateral side surfaces of the singulated semiconductor package.

[0136] like Figure 2J The exemplary semiconductor device package 200 shown may be formed by Figure 1 The exemplary method 100 shown is produced as discussed herein. Note that other method steps may be performed on the exemplary package 200, such as adding or deleting components, etc., without departing from the scope of the present invention. Note that the exemplary semiconductor device 200 (or any device discussed herein) may be referred to as a semiconductor package, an electronic device, an electronic package, a device, a package, etc.

[0137] As discussed herein, in exemplary embodiments, block S5 may be skipped or may be performed to the extent that the first encapsulation material 140 has a higher height than the first semiconductor die 130. For example, the top surface of the first encapsulation material 140 and the top surface of the first metal pillar 120 may be coplanar, while the top surface of the first semiconductor die 130 remains covered by the first encapsulation material 140. In such exemplary embodiments, block S7 may include attaching the second semiconductor die 160 to the top surface of the first encapsulation material 140 (e.g., directly above and centrally located on the first semiconductor die 130, partially above and partially not directly above the first semiconductor die 130, completely laterally offset from the first semiconductor die 130, etc.) using an adhesive member 160a. Figure 3 An exemplary semiconductor device 300 that may result from such a process is shown.

[0138] More specifically, Figure 3 1 shows a cross-sectional view of an exemplary semiconductor device 300 according to various aspects of the present invention. It should be understood that the exemplary device 300 can be combined with other exemplary devices discussed herein (e.g., Figures 2A-2J , 4 and 5) share any or all features.

[0139] like Figure 3As shown, in the exemplary semiconductor device 300, the top of the first encapsulation material 240 covers the top side of the first semiconductor die 130. The first metal pillar 120 is higher than the first semiconductor die 130. The top of the first metal pillar 120 and the top side of the first encapsulation material 140 can be, for example, coplanar. The adhesive unit 160a contacts the top side of the first encapsulation material 140 and contacts the bottom side of the second semiconductor die 160.

[0140] During processing, the first encapsulation material 240 may, for example, prevent foreign matter from being formed on the first semiconductor die 130. For example, if grinding is performed after forming the first metal pillar 120 to expose the first metal pillar 120, there is a possibility that metal particles (e.g., copper particles, etc.) from the grinding of the first metal pillar 120 may be scattered toward the first semiconductor die 130. However, since the first encapsulation material 240 encapsulates the top side (or portion) of the first semiconductor die 130, the first encapsulation material 240 prevents the metal particles from directly contacting and / or being mounted on the first semiconductor die 130. Therefore, the encapsulation material 240 may prevent damage to the first semiconductor die 130.

[0141] In another exemplary embodiment, blocks S4 and / or S5 of exemplary method 100 may be skipped. For example, block S8 may include performing the first encapsulation step instead of the second encapsulation step. For example, block S8 may be combined with Figure 4 In such an exemplary embodiment, block S8 may include forming a single integral encapsulation material that covers various elements of the semiconductor device discussed herein with respect to both the first encapsulation material 140 and the second encapsulation material 170. For example, the single integral encapsulation material may encapsulate the first metal pillar 120, the first semiconductor wafer 130, the second metal pillar 150, and the second semiconductor die 160. Figure 4 An exemplary semiconductor device 400 that may result from such a process is shown.

[0142] More specifically, Figure 4 4 shows a cross-sectional view of an exemplary semiconductor device 400 according to various aspects of the present invention. It should be understood that the exemplary device 400 can be combined with other exemplary devices discussed herein (e.g., Figures 2A-2J , 3 and 5) share any or all features.

[0143] like Figure 4As shown, a single unitary continuous encapsulating material 370 replaces the first encapsulating material 140 and the second encapsulating material 170 of various other embodiments. For example, the encapsulating material 370 can share any or all features with the first encapsulating material 140 and the second encapsulating material discussed herein, despite being a single unitary continuous encapsulating material.

[0144] In an exemplary embodiment, for example, at block S8 of the exemplary method 100 (e.g., skipping block S4, etc.), the encapsulant 370 may be formed after the first metal pillar 120, the first semiconductor die 130, the second metal pillar 150, and the second semiconductor die 160 are all formed on the top side of the first substrate 110. For example, block S8 may include forming the encapsulant 370 by simultaneously forming the first encapsulant 140 and the second encapsulant 170 of the semiconductor device 100.

[0145] In such an embodiment, encapsulant 370 may be formed in a simplified manner, thereby reducing the number of process steps and time for manufacturing semiconductor device 400 .

[0146] In another exemplary embodiment, as discussed herein, the first metal pillar 120 and the second metal pillar 150 may be laterally offset from each other and may be electrically coupled to each other, for example, via a signal distribution structure. Additionally, any number of semiconductor dies (or other electrical components) may be used. Figure 5 An exemplary semiconductor device 500 that may result from such a process is shown.

[0147] More specifically, Figure 5 1 shows a cross-sectional view of an exemplary semiconductor device 500 according to various aspects of the present invention. It should be understood that the exemplary device 500 may share any or all features with other exemplary devices discussed herein, for example, Figures 2A-2J , 3 and 4 show other exemplary devices.

[0148] For example, the signal distribution structure 450a may be, for example, Figure 1 1 and 10. For example, after block S5, signal distribution structure 450a may be formed on (or over) first encapsulation material 140, first metal pillar 120, and / or first semiconductor die 130. Signal distribution structure 450a may also be referred to as a pillar redistribution layer, a redistribution layer, a pillar redistribution structure, a trace, etc.

[0149] The signal distribution structure 450a may share any or all features with the first substrate 110 and / or the second substrate 180 discussed herein. For example, the signal distribution structure 450a may be formed in a manner that shares any or all features with the formation of the first substrate 110 of block S1 and / or the formation of the second substrate 180 of block S10. The signal distribution structure 450a may, for example, be formed to connect to the first metal pillar 120. The signal distribution structure 450a may, for example, include a conductive layer that laterally redistributes electrical signals to and / or from the first metal pillar 120. The signal distribution structure 450a may, for example, include a liner layer (or other conductive layer, UBM layer, etc.) upon which the second metal pillar 450 of block S6 may then be formed.

[0150] Note that the signal distribution structure 450a may be formed on top of the first metal pillar 120, the first semiconductor die 130, and the first encapsulation material 140. In an exemplary embodiment, the second encapsulation material 170 may be formed to cover the signal distribution structure 450a. For example, the top side and / or lateral side portions of the signal distribution structure 450a may be covered by the second encapsulation material 170.

[0151] In addition, as discussed herein, multiple semiconductor dies may be used at each level of a semiconductor device (or package) rather than a single semiconductor die, which are presented as a single die for clarity of illustration. As an example, the semiconductor device 500 includes multiple semiconductor dies instead of the second semiconductor die 160 of other embodiments.

[0152] Specifically, the second semiconductor die 460 can be attached to the first semiconductor die, for example, with an adhesive member 460a, and the third semiconductor die 465 can be attached to the first semiconductor die, for example, with an adhesive member 465a. The adhesive members 460a and 465a can be, for example, the same as those discussed herein. Figure 1 and 2A -2H share any or all features with the exemplary adhesive member 160a.

[0153] The second semiconductor die 460 may, for example, include an active side 461 having conductive bumps attached to the second substrate 180, and the third semiconductor die 465 may, for example, include an active side 466 having conductive bumps attached to the second substrate 180. Such conductive bumps and / or their connections to the second substrate 180 may, for example, share any or all features with other conductive bumps and / or their connections discussed herein.

[0154] Note that, as described herein, the second semiconductor die 460 and the third semiconductor die 465 can be laterally offset (partially or entirely) from the first semiconductor die 460. For example, the second semiconductor die 460 is attached to the top side of the first semiconductor die 130 and the top side of the first encapsulation material 140, and protrudes from at least one lateral side of the first semiconductor die 130. Therefore, the first encapsulation material 140 is vertically located just below a portion of the second semiconductor die 460. For another example, the third semiconductor die 465 is laterally positioned inward from the lateral side of the first semiconductor die 130, so that a portion of the second encapsulation material 170 is located just above a portion of the first semiconductor die 130.

[0155] In summary, various aspects of the present invention provide semiconductor devices and methods for manufacturing semiconductor devices. As non-limiting examples, various aspects of the present invention provide semiconductor devices including stacked grain structures and methods for manufacturing the same. Although the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the scope of the present invention. Therefore, the purpose of the present invention is not to be limited to the specific examples disclosed, but the present invention will include all examples that fall within the scope of the appended claims.

Claims

1. A semiconductor device comprising: A first substrate having no active electronic device and comprising: a first substrate top side; a first substrate bottom side; a first signal distribution layer; and a first dielectric layer; a first metal post on a top side of the first substrate; The first semiconductor crystal grain comprises: a first die bottom side including an active die side; a first die top side; and a conductive bump on the bottom side of the first die, The conductive bump is directly coupled to the top side of the first substrate; a second metal column on the first metal column, wherein a bottom end of the second metal column is connected to a top end of the first metal column; The second semiconductor crystal grain comprises: a second die top side including an active die side; and a second die bottom side coupled to the first die top side such that there is no intervening substrate between the first semiconductor die and the second semiconductor die; a second substrate on top of the second metal pillar and on the second die top side; and An encapsulation material is between the first substrate and the second substrate, wherein the encapsulation material encapsulates at least a lateral side of each of the first metal pillar, the first semiconductor grain, the second metal pillar, and the second semiconductor grain, and the encapsulation material contacts and covers the first dielectric layer of the first substrate.

2. The semiconductor device of claim 1, wherein the encapsulation material comprises: a first encapsulation material, wherein a top side of the first encapsulation material has the same height as the top end of the first metal pillar from the first substrate, and the top side of the first encapsulation material has the same height as the top side of the first die from the first substrate; as well as A second encapsulation material, wherein a height of a bottom side of the second encapsulation material measured from the first substrate is the same as a height of a bottom end of the second metal pillar measured from the first substrate.

3. The semiconductor device according to claim 2, wherein: The second encapsulation material does not cover the bottom side of the second semiconductor die; The second semiconductor die comprises a second conductive bump, the second conductive bump has a top side, and a height of the top side of the second conductive bump from the first substrate is the same as a height of a top side of the second encapsulation material; as well as A portion of the second die top side is covered by the second encapsulation material.

4. The semiconductor device according to claim 2, wherein: The first die top side comprises an inactive die side; and The second encapsulation material includes only a single layer of material and directly contacts and covers the first die top side. 5 . The semiconductor device of claim 1 , comprising an adhesive member directly vertically between the second die bottom side and the first die top side, and wherein the conductive bumps of the first semiconductor die are soldered to the first substrate. 6 . The semiconductor device of claim 5 , wherein the adhesive member is directly coupled to the second die bottom side, and wherein the adhesive member does not contact the first die bottom side.

7. The semiconductor device of claim 6, wherein the encapsulation material comprises: a first encapsulation material, wherein a top side of the first encapsulation material has a same height as the top end of the first metal pillar, measured from the top side of the first substrate; as well as A second encapsulation material laterally surrounds the adhesive member, laterally surrounds the second semiconductor die, and covers at least a portion of the second die top side.

8. The semiconductor device according to claim 7, wherein: The height of the bottom side of the adhesive member measured from the top side of the first substrate is the same as the height of the bottom side of the second encapsulating material measured from the top side of the first substrate; as well as The second encapsulation material contacts connection pads on the second die top side.

9. The semiconductor device of claim 1, wherein the active die side of the first semiconductor die is electrically coupled to the active die side of the second semiconductor die through at least the first substrate, the first metal pillar, the second metal pillar, and the second substrate.

10. The semiconductor device according to claim 1, wherein: The first metal pillar and the second metal pillar are offset from each other in a direction perpendicular to a stacking direction of the first metal pillar and the second metal pillar; as well as The semiconductor device comprises a pillar redistribution structure, wherein the first metal pillar and the second metal pillar are electrically connected through the pillar redistribution structure having a conductive layer; The top end of the second metal pillar is coplanar with the conductive bump of the second semiconductor die; and The top end of the first metal pillar and the bottom end of the second metal pillar are vertically separated only by the thickness of the conductive layer of the pillar redistribution structure.

11. The semiconductor device of claim 10, wherein the encapsulation material comprises: a first encapsulation material, wherein a top side of the first encapsulation material has a same height as the top end of the first metal pillar and the first die top side of the first semiconductor die from the top side of the first substrate; as well as a second encapsulating material between the first encapsulating material and the second substrate, The column redistribution structure is above the first encapsulation material, and at least a portion of the column redistribution structure is embedded in the second encapsulation material.

12. The semiconductor device according to claim 1, wherein the center of the second semiconductor grain is displaced from the center of the first semiconductor grain in a direction perpendicular to a stacking direction in which the first semiconductor grain and the second semiconductor grain are stacked, and the second semiconductor grain does not extend laterally beyond the lateral side of the first semiconductor grain; and Also included is a third semiconductor die coupled to the top side of the first die such that there is no intermediate substrate between the first semiconductor die and the third semiconductor die, wherein a first portion of the third semiconductor die is directly above the first semiconductor die and a second portion of the third semiconductor die is laterally displaced from the first semiconductor die.

13. The semiconductor device of claim 2, comprising a conductive layer, and wherein: The bottom end of the second metal column is connected to the top end of the first metal column at least through the conductive layer; The conductive layer is located directly vertically between the first encapsulation material and the second encapsulation material, but not directly vertically between the first semiconductor die and the second semiconductor die; and A bottom side of the conductive layer and the bottom side of the second encapsulating material are coplanar.

14. A semiconductor device comprising: a first substrate; a first metal post plated on a top side of the first substrate; The first semiconductor crystal grain comprises: a top side facing away from the first substrate; and a bottom side facing the first substrate and comprising a plurality of pads connected to the top side of the first substrate with solder; a second metal column plated on the first metal column, wherein a bottom end of the second metal column is connected to a top end of the first metal column; The second semiconductor crystal grain comprises: a top side facing away from the first semiconductor die and comprising a plurality of pads; and a bottom side coupled to a top side of the first semiconductor die such that there is no intervening substrate between the first semiconductor die and the second semiconductor die; The second substrate comprises: a top side facing away from the second semiconductor die; and a bottom side facing the second semiconductor die and comprising a conductive layer directly connected to the plurality of pads of the second semiconductor die without solder; and an encapsulation material between the first substrate and the second substrate, wherein the encapsulation material encapsulates at least the first metal pillar, the first semiconductor die, the second metal pillar, and a lateral side of the second semiconductor die, The bottom surface of the encapsulation material is lower than the bottom end of the first metal column.

15. The semiconductor device of claim 14, wherein the encapsulation material comprises: a first layer of a single encapsulation material, wherein the top side of the first layer of the single encapsulation material has the same height as the top end of the first metal pillar, measured from the top side of the first substrate; as well as A second layer of unitary encapsulating material extends completely between the top side of the first layer of unitary encapsulating material and the bottom side of the second substrate.

16. The semiconductor device of claim 14, comprising a top side of the first semiconductor die having no pads, and a bottom side of the second semiconductor die having no pads, and further comprising a single layer of adhesive material directly coupling the top side of the first semiconductor die and the bottom side of the second semiconductor die to each other.

17. The semiconductor device of claim 16, wherein the encapsulation material comprises: a first layer of mold encapsulation material; as well as A second layer of molding encapsulation material, wherein a bottom side of the second layer of molding encapsulation material has the same height as a bottom side of the single layer of adhesive material, measured from the top side of the first substrate.

18. The semiconductor device according to claim 16, wherein: the adhesive material directly couples the top side of the first semiconductor die and the bottom side of the second semiconductor die to each other; as well as The entire adhesive material is vertically higher than the first metal pillar.

19. The semiconductor device of claim 14, comprising a conductive layer directly connected to the bottom end of the second metal pillar and directly connected to the top end of the first metal pillar.

20. A method for manufacturing a semiconductor device, the method comprising: A first substrate is formed, which has no active electronic devices and includes: a first substrate top side; a first substrate bottom side; a first signal distribution layer; and a first dielectric layer; forming a first metal pillar on a top side of the first substrate; attaching a first semiconductor die to the first substrate top side, the first semiconductor die comprising: a first die bottom side including an active die side; a first die top side; and a conductive bump on the bottom side of the first die, The conductive bump is directly coupled to the top side of the first substrate; forming a first encapsulation material that encapsulates at least a lateral side of each of the first metal pillar and the first semiconductor die and contacts and covers the first dielectric layer of the first substrate; forming a second metal column on the first metal column, wherein a bottom end of the second metal column is connected to a top end of the first metal column; attaching a second semiconductor die to the first semiconductor die, the second semiconductor die comprising: a second die top side including an active die side; and a second die bottom side coupled to the first die top side such that there is no intervening substrate between the first semiconductor die and the second semiconductor die; forming a second encapsulation material, wherein the second encapsulation material encapsulates at least a lateral side of each of the second metal pillar and the second semiconductor die; and A second substrate is formed on top ends of the second metal pillars, on top sides of the second die, and on top sides of the second encapsulation material.

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