Method and structure for forming packaged semiconductor device using linked conductive connection components

Abstract

Method and structure for forming packaged semiconductor devices with ganged conductive connection components. A method for forming a packaged semiconductor device includes providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first subassembly, wherein the second conductive frame structure includes a plurality of interconnected conductive connection structures. The method includes encapsulating the first subassembly with an encapsulation layer to provide an encapsulated subassembly. The method includes removing the bonded conductive portions of the first conductive frame structure to form a plurality of conductive wing surfaces disposed on side edge surfaces of the encapsulated subassembly. The method includes forming a conductive layer on the conductive wing surfaces. The method includes separating the encapsulated subassemblies to provide the packaged semiconductor devices, each packaged semiconductor device having a portion of the conductive wing surface covered by the conductive layer.

Description

Technical Field

[0001] The present invention relates to electronic components, and more particularly to semiconductor packages, structures thereof, and methods of forming semiconductor packages. Background Art

[0002] In the past, packaged power semiconductor devices have used various manufacturing techniques to deposit conductive material on the exposed portion of the conductive lead frame. In discrete power semiconductor devices, such as discrete field effect transistor (FET) semiconductor devices or diode semiconductor devices, manufacturers use a matrix lead frame, which generally includes an array of die attach pads, each die attach pad having a plurality of leads arranged adjacently but isolated from the die attach pad. Semiconductor dies are attached to the die attach pads and electrically connected to the leads using discrete, independent or separate connection structures (such as wire bonding interconnects or clamps). This subassembly is then encapsulated to provide a molded package body for each semiconductor die. The encapsulated subassembly is then placed in an electroplating apparatus and conductive material is electroplated onto the exposed surface of the conductive lead frame. During the electroplating process, an electric current is passed through the conductive leads, which reduces dissolved metal cations to form a thin continuous metal coating on the exposed surface of the conductive lead frame.

[0003] One problem with past methods is that in order for current to pass through the entire conductive lead frame, certain leads from adjacent portions of the lead frame must be bonded together. After the plating process, the individually packaged semiconductor devices are then separated using a sawing process. The sawing process separates the bonded leads to provide lead faces or flank surfaces that are free of plating material. This leaves lead frame material, which is typically copper, that is not desired to be exposed. The exposed copper does not adhere to the solder, which produces a weaker solder bond and has an adverse effect on the reliability of the assembled electronic component.

[0004] In an attempt to address this problem, manufacturers have drilled holes in the bonded leads, created half-etched areas in the bonded leads, or used side grooves in the bonded leads to provide certain side or flank surfaces covered with the plated material. While these solutions provide between about 20% and 60% adherent surface coverage of the side or flank surfaces of the lead faces, these solutions do not provide 100% coverage and therefore still produce inferior solder bonds. Furthermore, these solutions do not provide sufficiently robust solder bond protection required at the assembly board level to meet stringent automotive specifications, which require 100% adherent side coverage.

[0005] Therefore, it is still desirable to have a method and structure for providing a packaged semiconductor device that improves the attachable surface coverage of the side and flank surfaces of the lead frame and that can be easily incorporated into a manufacturing process and is cost-effective. Summary of the invention

[0006] The present invention includes, among other features, a method for manufacturing a packaged semiconductor using a conductive frame structure having a plurality (i.e., at least two) of conductive connection structures that are linked together. The linked conductive connection structures are used to conduct current to a conductive member on another conductive frame structure, the other conductive frame structure having an exposed conductive wing surface that helps improve the coverage of the exposed conductive wing surface with solderable material. Among other things, the method and the structure formed provide a packaged semiconductor device that is constructed to provide up to 100% attachable wing surface. That is, the method and structure provide exposed side edges or conductive wing surfaces that are substantially covered with solderable material, which helps improve the wettable surface for attachment to a next-level component (e.g., a printed circuit board). The method and structure provide for improved reliability by means of a more robust solder joint than previous solutions. The method and structure are applicable to packaged semiconductor devices and other electronic devices having exposed flank or side edge surfaces that are constructed for subsequent deposition of solderable materials, but the method and structure are not limited to power semiconductor devices having flank surfaces on two opposite sides of the packaged semiconductor device.

[0007] In particular, in one embodiment, a method for forming a packaged semiconductor device includes providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first subassembly, wherein the second conductive frame structure includes a plurality of interconnected conductive connection structures. The method includes encapsulating the first subassembly by an encapsulation layer to provide an encapsulated subassembly. The method includes removing the bonded conductive portions of the first conductive frame structure to form a plurality of conductive wing surfaces disposed on side edge surfaces of the encapsulated subassembly. The method includes forming a conductive layer on the conductive wing surfaces. The method includes separating the encapsulated subassemblies to provide the packaged semiconductor devices, each packaged semiconductor device having a portion of the conductive wing surface covered by the conductive layer.

[0008] In another embodiment, a method of manufacturing a packaged electronic device includes: providing a first conductive frame structure including a first substructure having a first conductive member; a second substructure having a second conductive member, wherein the first conductive member is adjacent to the second conductive member to provide a bonded conductive structure to connect the first substructure to the second substructure; a first electronic die is coupled to the first substructure; and a second electronic die is coupled to the second substructure. The method includes: providing a second conductive frame structure including a first conductive connection structure and a second conductive connection structure, wherein the first conductive connection structure is actually interconnected to the second conductive connection structure; attaching the first conductive connection structure to the first electronic die and the first conductive member; and attaching the second conductive connection structure to at least the second electronic die to form a first subassembly. The method includes encapsulating a portion of the first subassembly by an encapsulation layer to form an encapsulated subassembly, wherein at least a portion of the first conductive frame structure is exposed outside the encapsulated subassembly. The method includes removing all of the bonded conductive structures to form exposed side surfaces of the first conductive member and exposed side surfaces of the second conductive member. The method includes forming a conductive layer on the exposed surface of the first conductive frame structure, on the exposed side surface of the first conductive member, and on the exposed side surface of the second conductive member. The method includes separating the encapsulated subassembly to provide a first packaged electronic device having the exposed side surface of the first conductive member covered by the conductive layer and a second packaged electronic device having the exposed side surface of the second conductive member covered by the conductive layer.

[0009] In a further embodiment, a packaged semiconductor device includes a die attach pad, a plurality of leads disposed adjacent to the die attach pad, each lead having a lead bottom surface and a lead end surface. A semiconductor die is connected to the die attach pad and a conductive clamp is attached to the semiconductor die and the plurality of leads, wherein the conductive clamp includes at least one tie bar. A package body encapsulates the semiconductor die, the conductive clamp, portions of the plurality of leads, at least a portion of the at least one tie bar portion, and at least a portion of the die attach pad, wherein each lead end surface is exposed on a side surface of the package body, and wherein an end surface of the at least one tie bar is exposed to the outside of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the at least one tie bar. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A cross-sectional view and a partial perspective view of a packaged semiconductor device according to an embodiment of the present invention are shown, wherein the cross-sectional view is along the Figure 3A The reference line 1-1 is intercepted;

[0011] Figure 2 Graphics Figure 1 a partial cross-sectional view of a portion of the packaged semiconductor device;

[0012] Figure 3A Graphics Figure 1 a top view of the packaged semiconductor device, wherein a portion of the package body is illustrated as being partially transparent;

[0013] Figure 3B Graphics Figure 3A a partial enlarged side view of the packaged semiconductor device;

[0014] Figure 4 illustrates a top view of a conductive frame structure having an electronic die attached to a die attach pad in accordance with an embodiment of the present invention;

[0015] Figure 5 FIG. 1 is a top view of a conductive frame structure according to an embodiment of the present invention, the conductive frame structure having interconnected conductive connection structures;

[0016] Figure 6 Graphics Figure 5 The conductive frame structure is configured to cover Figure 4 A top view of the conductive frame structure providing a subassembly according to an embodiment of the present invention;

[0017] Figure 7 Graphics Figure 6 A cross-sectional view of the subassembly along reference line 7-7;

[0018] Figure 8 Graphics Figure 6 A cross-sectional view of the subassembly along reference line 8-8;

[0019] Fig. 9 FIG. 1 shows a diagram of a further processed image according to an embodiment of the present invention. Figure 8 a cross-sectional view of the subassembly; and

[0020] Fig.10 Figure 2 shows the image after additional processing according to an embodiment of the present invention. Fig. 9 A cross-sectional view of the subassembly.

[0021] For the sake of simplicity and clarity of explanation, the elements in the drawings are not necessarily drawn to scale, and the same element symbols in different figures represent the same elements. In addition, for the sake of simplicity of explanation, the description and details of well-known steps and elements are omitted. As used herein, the term "and / or" is to include any and all combinations of one or more of the items listed in the relevant table. In addition, the terms used here are only for the purpose of describing specific embodiments, and are not intended to limit the disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that when the term "include and / or include" is used in this specification, it indicates the existence of the characteristics, quantity, step, operation, element and / or member, but does not exclude the existence or addition of one or more other characteristics, quantity, step, operation, element, member and / or its group. It will be understood that although the terms "first, second, etc." may be used here to describe various components, elements, regions, layers and / or sections, these components, elements, regions, layers and / or sections should not be limited to these terms. These terms are only used to distinguish components, elements, regions, layers and / or sections from each other. Thus, for example, a first component, a first element, a first region, a first layer and / or a first section discussed below may be referred to as a second component, a second element, a second region, a second layer and / or a second section without departing from the teachings of the present disclosure. Reference to "one embodiment" or "an embodiment" indicates that a specific feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, the appearance of the phrase "in one embodiment" or "in an embodiment" throughout this specification is not necessarily all reference to the same embodiment, but in some cases it may be reference to the same embodiment. Furthermore, in one or more embodiments, the specific features, structures or characteristics may be combined in any appropriate manner that will be obvious to a person skilled in the art. In addition, the term "when" indicates that an action occurs at least within a portion of a duration of the initial action. The use of the words "about", "approximately" or "substantially" indicates that a value of an element is expected to be close to a state value or position. However, as is well known in the art, there are always minor variations where the values ​​or positions are not exactly as described. Unless otherwise indicated, the words "on" or "over" as used herein include locations, arrangements, or relationships where the specified elements may be in direct or indirect physical contact. It is further understood that the embodiments depicted and described below may suitably have embodiments and / or be implemented in the absence of any element not expressly disclosed herein. DETAILED DESCRIPTION

[0022] The following is a detailed description of the technical means used by the present invention to achieve the intended purpose of the invention with reference to the drawings and preferred embodiments of the present invention.

[0023] Figure 1 A cross-sectional view and a partial perspective view of a packaged electronic device 10 are shown, for example, a packaged semiconductor device 10 according to a first embodiment, wherein the cross-sectional view is taken along Figure 3A 1-1 of . According to the described embodiments, the packaged semiconductor device 10 includes a die attach pad 11, a die pad 11 or a support pad 11 and a lead 12 disposed adjacent to but separated from the die attach pad 11. In one embodiment, an electronic chip 16 or an electronic die 16, such as a semiconductor device 16 or a semiconductor die 16, is connected or attached to the die attach pad 11 using a die attach material 17. In some embodiments, the semiconductor device 16 is a power semiconductor device, such as a power field effect transistor (FET) structure, a diode structure, or a rectifier structure. It is understood that the electronic chip 16 can be any type of electronic device. For example, the die attach material 17 can be a solder paste, a conductive epoxy, a conductive adhesive, a conductive film, a non-conductive epoxy, a non-conductive adhesive, a non-conductive film, or other suitable attachment materials known to those skilled in the art. In some embodiments, non-conductive refers to electrically insulating and it is understood that these materials may still be thermally conductive.

[0024] The packaged semiconductor device 10 further includes a conductive connection structure 19 attached to a major surface of the semiconductor device 16 and further connected to one or more leads 12. In a preferred embodiment, the conductive connection structure 19 is a conductive clip-type interconnect structure attached to the lead 12, generally as shown in FIG. Figure 3A As shown. In other embodiments, the conductive connection structure 19 is attached to a single lead 12. In some embodiments, the conductive connection structure 19 is mainly composed of copper, but other conductive materials can also be used. Figure 1 and 3AAs shown, the conductive connection structure 19 includes a die attach portion 191 that is connected to the semiconductor device 16 using a die attach material 18, which can be a solder paste, a conductive epoxy, a conductive adhesive, a conductive film, or other suitable attaching materials known to those skilled in the art. The conductive connection structure 19 further includes a bonding portion 192 that extends outwardly or away from the die attach portion 191 at an angle to place the bonding portion 192 in an appropriate position to be attached to the lead 12 using an attachment layer 23. For example, the attachment layer 23 can be a solder paste, a conductive epoxy, a conductive adhesive, a conductive film, or other suitable attaching materials known to those skilled in the art. According to the described embodiment, the conductive connection structure 19 is constructed to provide electrical interconnection to the lead 12 for transmitting electrical signals to and from the semiconductor device 16 in a completed packaged form; and when in a subassembly form, to provide electrical interconnection for electroplating purposes during the manufacturing process of the packaged semiconductor device 10.

[0025] The packaged semiconductor device 10 further includes a package body 36 that covers or encapsulates the conductive connection structure 19, the semiconductor die 16, at least a portion of the lead 12, and at least a portion of the die attach pad 11, and in some embodiments, leaves a lower or bottom surface 122 of the lead 12, and a conductive side surface 121 (also referred to as a conductive wing surface 121) of the lead 12 exposed outside the packaged semiconductor device 10, such as Figure 1 As shown. In some embodiments, the package body 36 may be a polymer-based composite material, such as epoxy with fillers, epoxy acrylic with fillers, or a polymer with appropriate fillers. The package body 36 includes a non-conductive and environmentally friendly material that protects the semiconductor die 16 from external elements and contaminants. The package body 36 can be formed using paste printing, compression molding, transfer molding, over-molding, liquid sealant molding, vacuum lamination, other appropriate applicators, or other processes known to those skilled in the art. In some embodiments, the package body 36 is an epoxy molding compound ("EMC") and can be formed using transfer or injection molding techniques.

[0026] According to the embodiment, the conductive side surface 121 or the conductive side wing surface 121 is exposed through the side surface 360 ​​of the package body 36 and is further covered by a conductive layer 26 (such as a solderable layer 26). For example, the conductive layer 26 includes tin and is preferably formed using an electroplating technique according to the embodiment. In some embodiments, the conductive layer 26 is further disposed on the lower surface 122 of the lead 12 and the bottom or lower surface 110 of the die attach pad 11, generally as shown in FIG. Figure 1 shown.

[0027] As will be described in detail below, during the fabrication of the packaged semiconductor device 10 with other packaged semiconductor devices, such as in a subassembly form, the conductive connection structure 19 is interconnected or linked with other conductive connection structures (e.g., other conductive connection structures 19), which according to the present embodiment enables the conductive layer 26 to be disposed on all conductive wing surfaces 121 of the lead 12. In particular, the interconnected conductive connection structures 19 enable current to flow through the lead 12 to facilitate the formation of the conductive layer 26 during the electroplating process to provide increased coverage of the conductive layer 26 compared to existing structures or processes. According to the embodiment, substantially all of the conductive wing surfaces 121 are covered by the conductive layer 26. In particular, in some embodiments, more than 60% of the surface of each conductive wing surface 121 is covered by the conductive layer 26. In some embodiments, more than 75% of the surface of each conductive wing surface 121 is covered by the conductive layer 26. In a preferred embodiment, each conductive wing surface 121 is approximately 100% or entirely covered by the conductive layer 26.

[0028] Figure 2 A partial cross-sectional view of a portion of a packaged semiconductor device 10 is shown. Figure 2 , a portion of the packaged semiconductor device 10 is shown attached to a next level component 200, such as a printed circuit board 200, the printed circuit board having a conductive trace 201 disposed adjacent to a first surface 203. According to the embodiment, the conductive flank surface 121 of the lead 12 is substantially covered by the conductive layer 26, which facilitates approximately 100% wettable attach flanks for solder attach material 24. Compared to prior methods that fail to provide greater than 60% coverage of solderable material on the flank surface, according to embodiments of the present invention, the solder joint strength and reliability of the assembled component are improved.

[0029] Figure 3A A top view of the packaged semiconductor device 10 is shown, wherein a portion of the package body 36 is shown as partially transparent to allow the internal portion of the device to be seen. According to the embodiment, the conductive connection structure 19 further includes one or more tie bars 194, for example, extending from the die attachment portion 191 of the conductive connection structure 19 toward the side surfaces 361 and 362 of the package body 36. In a preferred embodiment, the conductive connection structure 19 includes at least two tie bars 194, respectively, at opposite sides 196 and 197 of the conductive connection structure 19, generally as shown in FIG. Figure 3AIn one embodiment, tie bars 194 are configured to interconnect, physically connect, or link together conductive connection structure 19 with other conductive connection structures (e.g., other conductive connection structures 19) according to the described embodiments. In one embodiment, conductive connection structure 116 (e.g., wire bonding) electrically connects other pad portions on semiconductor device 16 to lead 12, generally as shown. Figure 3A shown.

[0030] Figure 3B 1 is a partial enlarged side view of packaged semiconductor device 10 depicting a portion of side surface 362 of package body 36, wherein distal surface 195 of tie bar 194 is exposed through package body 36. According to the described embodiment, distal surface 195 is devoid of conductive layer 26 because tie bar 194 is separated or singulated after conductive layer 26 is formed.

[0031] Reference now Figure 4-10 , a method for forming a packaged electronic device or a packaged semiconductor device containing the packaged semiconductor device 10 will be described. Figure 4 A top view of a conductive frame structure 40 with an electronic die 16 (e.g., a semiconductor die) attached to a die attach pad 11 according to a first embodiment is shown. In an earlier step of manufacturing, the conductive frame structure 40 is provided with a plurality of substructures 41, 42, 43, and 44 or subframe structures 41, 42, 43, and 44. In one embodiment, the conductive frame structure 40 may be provided as an NxM array of substructures, including, for example, Figure 4 In some embodiments, each substructure may include a die attach pad 11 attached to a conductive frame 51 or frame 51, the frame 51 being separate from and surrounding the die attach pad 11. In some embodiments, each frame 51 may have a square shape and the die attach pad 11 may be attached to the frame 51 by one or more tie bars 53 and / or lead portions 511. The leads 12 are configured to be separate from but adjacent to the die attach pad 11 and the leads 12 may be attached to the frame 51 at ends distal from the die attach pad 11, generally as shown in FIG. Figure 4 shown.

[0032] In some embodiments, the conductive frame structure 40 includes a main portion 48 or a tap portion 48 disposed on one side of the conductive frame structure 40, which may further include one or more holes 49. In some embodiments, the leads 12 corresponding to the die attach pad 11 in the substructure are disposed on only one side of the die attach pad 11. In other embodiments, the leads 12 may be disposed on more than one side of the die attach pad 11. Generally, as shown in FIG. Figure 4As shown, the leads 12 of the substructure 41 have distal ends that are bonded to the distal ends of the lead portions 511 extending outward from the die attach pad 11 in the substructure 42. In some embodiments, the locations where these distal ends are bonded are referred to as bonded conductive portions 56. In some embodiments, each bonded conductive portion 56 includes at least a portion of the frame 51 between the lead 12 and the distal ends of the lead portions 511. It is understood that the bonded conductive portions 56 may also include portions that are directly attached to the die attach pad 11 and adjacent to the leads 12 in the adjacent substructure, may include portions from the adjacent substructure and adjacent to the leads 12, and may include combinations thereof. In general, the bonded conductive portions 56 are portions of the conductive frame structure 40 that will be separated, singulated, or removed in a subsequent process, thereby exposing the conductive flank surfaces, conductive side surfaces, or conductive distal end surfaces of the leads, lead portions, die attach pads, or the conductive portions exposed after the separation process.

[0033] According to the described embodiment, the frame structure 40 includes a conductive material. In one embodiment, the conductive frame structure 40 is mainly composed of copper and has a thickness of about 100 μm to 508 μm. In other embodiments, the frame structure 40 can be mainly composed of Fe-Ni (such as alloy 42) or other metal materials known to technicians in the relevant technical field. The conductive frame structure 40 can be formed or manufactured using masking and etching techniques, stamping techniques, bending or forming techniques, electroplating techniques, deposition techniques, processing and / or combinations of the foregoing. As described above, each electronic die 16 (such as semiconductor die 16) can be connected to the die attach pad 11 using a die attach material 17, generally such as Figure 1 In some embodiments, the pad portion of each electronic die 16 is electrically connected to the lead 12 via a conductive connection structure 116 (e.g., a wire bonding structure). It should be understood that the conductive connection structure 116 can be formed in a later stage of manufacturing, such as after the conductive frame structure 60 is attached.

[0034] Figure 5 A top view of a conductive frame structure 60 with interconnected conductive connection structures 19 according to an embodiment is shown, which may be provided in a manufacturing step. According to the embodiment, the conductive frame structure 60 may be provided as an NxM array, which is similar to a general structure such as Figure 5The conductive frame structure 40 of the 2x2 array is shown. For example, the conductive frame structure 60 can be constructed to include a plurality of substructures 61, 62, 63 and 64 or subframe structures 61, 62, 63 and 64. According to the embodiment, the conductive connection structures 19 in each substructure 61, 62, 63 and 64 are physically and electrically interconnected or linked together, so that the interconnected conductive connection structures 19 can be used to provide current to the conductive members in the conductive frame structure 40 in a subsequent electroplating process. In some embodiments, each of the conductive connection structures 19 is interconnected to a conductive frame 71 or frame 71, which is separated from the conductive connection structure 19 and surrounds each conductive connection structure 19, generally as shown in FIG. Figure 5 In some embodiments, tie bars 194 are used to interconnect the conductive connection structure 19 with the frame 71. In a preferred embodiment, each conductive connection structure 19 includes at least two tie bars 194 on opposite sides 196 and 197 of the conductive connection structure 19, respectively, as shown in FIG. Figure 5 As shown. In a preferred embodiment, tie bars 194 are positioned within conductive frame structure 60 to be perpendicular to leads 12 in conductive frame structure 40. In other words, tie bars 194 are positioned so that when conductive frame structure 60 is attached to conductive frame 40, tie bars 194 are located on the side of each subassembly that lacks conductive flank surfaces, which will subsequently be plated. This configuration prevents tie bars 194 from being singulated prematurely when the bonded conductive portions 56 are removed.

[0035] In some embodiments, the conductive frame structure 60 includes a main portion 68 or a tap portion 68 disposed on one side of the conductive frame structure 60, which may further include one or more holes 69. As will be described in detail below, the main portion 68 is constructed to physically contact or electrically connect to the main portion 48 of the conductive frame structure 40 to allow current to flow through both the conductive frame structure 40 and the conductive frame structure 60 including the conductive interconnect structure 19 during the electroplating process.

[0036] According to the described embodiment, the frame structure 60 comprises a conductive material. In one embodiment, the conductive frame structure 60 is primarily composed of copper and is approximately 100 μm to 508 μm thick. In other embodiments, the frame structure 60 may be primarily composed of Fe-Ni (e.g., Alloy 42) or other metal materials known to those skilled in the art. The conductive frame structure 60 may be formed or manufactured using masking and etching techniques, stamping techniques, bending or forming techniques, electroplating techniques, deposition techniques, machining, and / or combinations thereof.

[0037] Figure 6The conductive frame structure 60 is shown configured to overlie the conductive frame structure 40 to provide a top view of a subassembly 80 according to one embodiment. In one embodiment, in an additional step, the conductive frame structure 60 and the conductive frame 40 are connected together, for example, by attaching the conductive connection structure 19 to the semiconductor die 16 and to the lead 12. As previously described, each conductive connection structure 19 can be attached to the semiconductor die 16 ( Figure 1 The die attach material 18 may be solder paste, conductive epoxy, conductive adhesive, conductive film, or other suitable attaching materials known to those skilled in the art. In addition, each conductive connection structure 19 may be attached to the lead 12 (eg, Figure 1 ), the attachment layer 23 may be solder paste, conductive epoxy, conductive adhesive, conductive film, or other suitable attachment materials known to those skilled in the art. In some embodiments, the additional attachment layer 418 (eg, Figure 7 The additional attachment layer 418 (shown) can be used to attach other portions of the conductive frame structure 60 to the conductive frame 40, such as attaching the main portion 68 to the main portion 48, physically contacting the two portions together. Figure 7 ) may be a material similar to the die attach material 18. In this step, a subassembly 80 is provided according to the described embodiment. Figure 6 The portion 401 of the present invention will be removed later, and further Fig.10 and are described together.

[0038] Figure 7 Graphics Figure 6 A cross-sectional view of the subassembly 80 taken along reference line 7-7, and Figure 8 Graphics Figure 6 A cross-sectional view of the subassembly 80 taken along reference line 8-8. Figure 7 As shown in the drawings, the main portion 68 of the conductive frame structure 60 is physically in contact with the main portion 48 of the conductive frame structure 40, for example, by means of the attachment layer 418. According to the embodiment, this contact can be used to subsequently contact the subassembly to the strip fingers of the electroplating equipment, which suspend the subassembly in the electroplating solution. According to the embodiment, the conductive connection structure 19 is interconnected or linked together by the connecting rod 194 and the frame 71, and is further interconnected to the main portion 68. Furthermore, this structure facilitates the transmission of current to the lead 12 during the electroplating process to form the conductive layer 26 on the conductive flank surface 121 (shown as a dotted line) of the lead 12.

[0039] Fig. 9 The figure shows the Figure 8 80. In one embodiment, an encapsulation step is used to form one or more encapsulated package bodies 36 covering at least a portion of the subassembly 80 to provide an encapsulated subassembly 90. In some embodiments, the package body 36 may be a polymer-based compound material, such as epoxy with filler, epoxy acrylic with filler, or a polymer with appropriate filler. The package body 36 includes a non-conductive and environmentally friendly material that protects the semiconductor die 16 from external elements and contaminants. The package body 36 can be formed using paste printing, compression molding, transfer molding, over-molding, liquid sealant molding, vacuum lamination, other suitable applicators, or other processes known to those skilled in the art. In some embodiments, the package body 36 is an epoxy molding compound ("EMC") and can be formed using transfer or injection molding techniques.

[0040] Fig.10 A cross-sectional view of the encapsulation subassembly 90 is shown after additional processing according to the described embodiments. According to the described embodiments, the portion of the encapsulation subassembly 90 (e.g., portion 401) is removed including removing the bonded conductive portion 56 from the conductive frame structure 40. In a preferred embodiment, the bonded conductive portion 56 is completely removed to fully expose the end surfaces of the leads 12 and the lead portions 511 (i.e., the conductive flank surfaces 121). In some embodiments, a local cutting process is used to remove the portion of the conductive frame structure 40, which includes the bonded conductive portion 56. In some embodiments, portions of the encapsulation layer 360 are also removed. Other processes may be used to remove the portion 401, including, for example, masking and etching techniques, ablation techniques, laser techniques, and other techniques known to those skilled in the art.

[0041] In subsequent steps, the conductive layer 26 is disposed along the exposed surfaces of the conductive frame structure 40, including, for example, the exposed surfaces of the die attach pad 11, the leads 12, and the lead portions 511. In a preferred embodiment, the encapsulated subassembly is placed in a plating bath or plating solution and an electric current is passed through the conductive frame structure 40 and the conductive frame structure 60 to plate the conductive layer 26 on the exposed surfaces of the conductive frame structure 40. According to the described embodiment, the interconnecting conductive connection structure 19 is constructed to facilitate electrical connection to the leads 12, thereby plating the conductive layer 26 on the exposed conductive flank surfaces 121 of the leads 12, providing up to about 100% coverage of these surfaces compared to less than 60% coverage provided by prior processes and structures. The conductive layer 26 can be a solderable material, such as a tin-based solder or other solderable material known to those skilled in the art. In one embodiment, conductive layer 26 may be a matte tin material having a thickness of about 300 to 800 inches (about 7.6 microns to about 23 microns). In one embodiment, strip fingers are attached to main portions 48 and 68 of encapsulation subassembly 90 for placement in the plating tank or plating solution.

[0042] In some embodiments, after the conductive layer 26 is formed, the encapsulated subassembly 90 is singulated or separated along, for example, the separation regions 403 to provide a plurality of packaged semiconductor devices, such as the packaged semiconductor device 10. In some embodiments, a sawing process is used to singulate the encapsulated subassembly 90, but other separation processes known to those skilled in the art may also be used.

[0043] In some embodiments, one or more of the die attach pads 11, leads 12, conductive connection structures 19, as well as the tie bars 194, frame 51, tie bars 53, lead portions 511, bonded conductive portions 56, main portions 48, tie bars 194, frame 71, main portions 68 and / or portions thereof are non-limiting examples of conductive components.

[0044] According to the above, a person skilled in the art may determine, according to one embodiment, that coupling the second conductive frame structure includes physically contacting a portion of the first conductive frame structure with the second conductive frame structure.

[0045] In further embodiments, removing the bonded conductive portion includes partially cutting the encapsulated subassembly to completely remove the bonded conductive portion. In further embodiments, forming the conductive layer includes forming a solderable material with approximately 100% coverage of the conductive flank surface.

[0046] Based on the above, a person skilled in the art may determine that removing all of the bonded conductive structures includes cutting through the bonded conductive structures according to another embodiment.

[0047] In further embodiments, forming the conductive layer comprises approximately 100% covering the exposed side surface of the first conductive member; and approximately 100% covering the exposed side surface of the second conductive member. In other embodiments, forming the conductive layer comprises forming a conductive layer containing a solderable material. In other embodiments,

[0048] From the foregoing, it is apparent that the present invention discloses a novel method and structure for manufacturing a packaged semiconductor device having improved coverage of conductive wing surfaces with solderable material. Among other features, there is a conductive frame structure having an interconnecting conductive connection structure, which is connected to a lead structure in a second conductive frame structure. The conductive frame structure facilitates electrical connection to conductive members (such as leads), thereby providing improved solderable material coverage on the conductive wing surfaces. When the packaged semiconductor device is attached to a next-level component (such as a printed circuit board), the method and structure provide up to 100% wettable attach wing coverage. Compared to existing structures and methods, the present invention provides a more robust solder bond and improves reliability. The method and structure provide a cost-effective solution to improve wettable attach wing coverage and is compatible with existing assembly methods.

[0049] Although the purpose of the present invention is to be described using specific preferred embodiments and exemplary embodiments, the previous drawings and their descriptions only depict the typical embodiments and are therefore not to be considered as limiting the scope thereof. It is obvious that many alternatives and variations will be apparent to those skilled in the art.

[0050] As reflected in the claims below, the invention may be characterized by less than all of the features of a single previously disclosed embodiment. Therefore, the claims set forth below are hereby expressly incorporated into this detailed description of the drawings, with each claim standing on its own as a separate embodiment of the invention. Furthermore, although certain embodiments described herein include some features that are included in other embodiments and do not include other features, combinations of features of different embodiments are intended to fall within the scope of the invention and are intended to form different embodiments as will be understood by those skilled in the art.

Claims

1. A method of forming a packaged semiconductor device, comprising: providing a first conductive frame structure including a first die pad, a first lead associated with and proximate to the first die pad, a second die pad, and a second lead associated with and proximate to the second die pad, wherein the first lead is connected to the second die pad as a bonded conductive portion at a location between the first die pad and the second die pad; attaching a first semiconductor component to the first die pad; attaching a second semiconductor component to the second die pad; providing a second conductive frame structure comprising a first conductive clamp connected to a first portion of the second conductive frame structure and a second conductive clamp connected to a second portion of the second conductive frame structure; attaching the second conductive frame structure to the first conductive frame structure to provide a first subassembly, wherein the first conductive clamp is attached to the semiconductor component and the first lead, and the second conductive clamp is attached to the second semiconductor component and the second lead; encapsulating the first subassembly with an encapsulation layer to provide an encapsulated subassembly; removing the bonded conductive portions of the first conductive frame structure to form a plurality of conductive wing surfaces disposed on side edge surfaces of the encapsulation subassembly; After the step of removing the bonded conductive portion, forming a conductive layer onto the conductive wing surface; as well as separating the encapsulated subassemblies to provide the packaged semiconductor devices, each of the packaged semiconductor devices having a portion of the conductive flank surface covered by the conductive layer, wherein: forming the conductive layer includes electroplating the conductive layer onto the conductive wing surface using the first conductive fixture and the second conductive fixture to pass current through a portion of the first conductive frame structure; and After separation, the conductive layer covers 100% of the surface of the conductive wing.

2. The method according to claim 1, characterized in that: Separating includes providing each of the packaged semiconductor devices with a distal end portion of the second conductive frame structure exposed outside the encapsulation layer; and The distal end portion is devoid of the conductive layer.

3. The method according to claim 1, characterized in that: Providing the first conductive frame structure includes providing: a first portion of the first conductive frame structure between the first lead and the second die pad; the first lead attached to one side of the first portion; and a lead portion attached to opposite sides of the first portion and to one side of the second die pad; and The bonded conductive portion includes the first portion of the first conductive frame structure.

4. The method according to claim 1, characterized in that: Removing includes removing all of the bonded conductive portions.

5. The method according to claim 1, characterized in that: Forming the conductive layer comprises: forming the conductive layer on bottom surfaces of the first die attach pad and the second die attach pad; and The conductive layer is formed on the bottom surfaces of the first lead and the second lead.

6. A method for manufacturing a packaged electronic device, characterized in that: Include: Providing a first conductive frame structure comprises: a first substructure having a first conductive member; a second substructure having a second conductive member, wherein the first conductive member abuts to the second conductive member to provide a bonded conductive structure connecting the first substructure to the second substructure; a first electronic grain coupled to the first substructure; as well as a second electronic grain coupled to the second substructure; Providing a second conductive frame structure comprises: a first conductive connection structure; and a second conductive connection structure, wherein the first conductive connection structure is physically interconnected to the second conductive connection structure; attaching the first conductive connection structure to the first electronic die and the first conductive member and attaching the second conductive connection structure to at least the second electronic die to form a first subassembly; encapsulating a portion of the first subassembly by an encapsulation layer to form an encapsulated subassembly, wherein at least a portion of the first conductive frame structure is exposed outside the encapsulated subassembly; removing all of the bonded conductive structures to form exposed side surfaces of the first conductive member and exposed side surfaces of the second conductive member; forming a conductive layer on the exposed surface of the first conductive frame structure, on the exposed side surface of the first conductive member, and on the exposed side surface of the second conductive member; as well as separating the encapsulated subassemblies to provide a first packaged electronic device having the exposed side surface of the first conductive member covered by the conductive layer and a second packaged electronic device having the exposed side surface of the second conductive member covered by the conductive layer, wherein: After the encapsulated subassembly is separated, the conductive layer covers 100% of the exposed side edge surface of the first conductive member and the exposed side edge surface of the second conductive member.

7. The method according to claim 6, characterized in that The forming of the conductive layer comprises: placing the encapsulated subassembly in an electroplating solution; and Current is passed through the first conductive frame structure and the second conductive frame structure to electroplate the conductive layer on the exposed surface of the first conductive frame structure, on the exposed side surface of the first conductive component, and on the exposed side surface of the second conductive component.

8. The method according to claim 6, characterized in that: Providing the first conductive frame structure comprises: Providing that the first conductive member comprises a lead; providing the second conductive member comprises a die attach pad; Providing the second conductive frame structure comprises: Providing a first clamp structure linked with a second clamp; and Providing the first clamp structure physically interconnected to the second conductive frame structure on at least two sides having tie bars; Attaching the first conductive connection structure includes physically contacting a portion of the first conductive frame structure with the second conductive frame structure; as well as Separating includes providing each of the first packaged electronic device and the second packaged electronic device with a distal end portion of the second conductive frame structure exposed outside the encapsulation layer, which is devoid of the conductive layer.

9. The method according to claim 6, characterized in that The forming of the conductive layer comprises: forming the conductive layer on the lower surface of the first conductive member; and The conductive layer is formed on the lower surface of the second conductive component.

10. A packaged semiconductor device, characterized in that: Include: a die attach pad; a plurality of leads disposed adjacent to the die attach pad, each lead having a lead bottom surface and a lead tip surface; a semiconductor die coupled to the die attach pad; a conductive clamp comprising a die attach portion attached to the semiconductor die, a bonding portion connected to the die attach portion and to at least one of the plurality of leads, and a first tie bar; a package body encapsulating the semiconductor die, the conductive clamp, portions of the plurality of leads, at least portions of the first tie bars, and at least portions of the die attach pad, wherein an end surface of each lead is exposed on a side surface of the package body, and wherein an end surface of the first tie bar is exposed outside the package body; and A conductive layer is disposed on the surface of each lead end but not on the end surface of the first tie bar, wherein the conductive layer covers 100% of the surface of each lead end.

11. The packaged semiconductor device according to claim 10, wherein: Also includes: A conductive connection structure is electrically coupled to one of the plurality of leads and the semiconductor device.

12. The packaged semiconductor device according to claim 10, wherein: The conductive layer covers 100% of the surface of each lead end.

13. The packaged semiconductor device according to claim 10, wherein: The conductive layer is disposed on the bottom surface of the lead and the bottom surface of the die attach pad.

14. The packaged semiconductor device according to claim 10, wherein: The conductive fixture further comprises a second connecting rod; The first tie bar and the second tie bar are disposed on opposite sides of the die attach portion; and The bonding portion is attached to at least two leads.

15. The packaged semiconductor device according to claim 10, wherein: A portion of the die attach pad is exposed in a portion of the side surface of the package body; and The conductive layer is disposed on the portion of the die attach pad exposed in the portion of the side surface of the package body.

16. A packaged semiconductor device, characterized in that: Include: a die attach pad having a die attach pad top surface and a die attach pad bottom surface, and a die attach pad side surface extending between the die attach pad top surface and the die attach pad bottom surface; leads disposed adjacent to the die attach pad, each lead having a lead bottom surface and a lead tip surface; a semiconductor die coupled to the die attach pad top surface; a conductive clamp attached to the semiconductor device and to at least one of the leads, wherein the conductive clamp includes a first tie bar extending from a first side edge surface of the conductive clamp; a package body encapsulating the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad, wherein: Each lead end surface is exposed in the first side surface of the package body; The end surface of the first connecting rod is exposed in a second side surface of the packaging body which is different from the first side surface; The die attach pad side surface is exposed in the third side surface of the package body; and a conductive layer is disposed on each lead end surface and the die attach pad side surface but not on the end surface of the first tie bar, The conductive layer covers 100% of the surface of each lead end.

17. The packaged semiconductor device according to claim 16, wherein: The conductive layer comprises an electroplated solderable material.

18. The packaged semiconductor device according to claim 16, wherein: The conductive fixture further comprises a second connecting rod; The first connecting rod and the second connecting rod are disposed on opposite sides of the conductive fixture; and The second connecting bar includes another end surface exposed in the third side surface of the package body opposite to the second side surface.

19. The packaged semiconductor device according to claim 18, wherein: A portion of the die attach pad is exposed in a fourth side surface of the package body; The die attach pad bottom surface is exposed in the bottom surface of the package body; as well as The conductive layer is disposed on the portion of the die attach pad exposed in the fourth side surface and on the die attach pad bottom surface.

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