Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same. A semiconductor device includes: a first signal distribution structure having a signal distribution structure top side, a signal distribution structure bottom side, and a plurality of signal distribution structure lateral sides, wherein the first signal distribution structure includes a first dielectric layer and a first conductive layer; a first electronic component coupled to the signal distribution structure top side; a first encapsulation material covering at least a portion of the signal distribution structure top side and at least a portion of the first electronic component; a semiconductor die coupled to the signal distribution structure bottom side and located directly below the first electronic component; a plurality of conductive pillars coupled to the signal distribution structure bottom side and positioned laterally around the semiconductor die; and a second encapsulation material covering at least a portion of the signal distribution structure bottom side, at least a portion of the semiconductor die, and at least a portion of the conductive pillars.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Existing semiconductor devices and methods for manufacturing semiconductor devices are inadequate, for example resulting in a manufacturing process that is too time consuming and / or too expensive, resulting in semiconductor packages having unreliable connections and / or interconnect structures having suboptimal dimensions, etc. Further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing the conventional and traditional methods with the present disclosure set forth in the remainder of this application with reference to the drawings. Summary of the invention

[0003] Various aspects disclosed in the present invention provide a semiconductor device and a method for manufacturing the semiconductor device. As a non-limiting example, various aspects disclosed in the present invention provide a semiconductor device including a plurality of encapsulation layers and a plurality of signal distribution structures and a method for manufacturing the semiconductor device.

[0004] One aspect of the present invention is a semiconductor device, comprising: a first signal distribution structure having a signal distribution structure top side, a signal distribution structure bottom side and a plurality of signal distribution structure lateral sides, wherein the first signal distribution structure comprises a first dielectric layer and a first conductive layer; a first electronic component coupled to the top side of the signal distribution structure; a first encapsulation material covering at least a portion of the top side of the signal distribution structure and at least a portion of the first electronic component; a semiconductor grain coupled to the bottom side of the signal distribution structure and located directly below the first electronic component; a plurality of conductive pillars coupled to the bottom side of the signal distribution structure and positioned laterally around the semiconductor grain; and a second encapsulation material covering at least a portion of the bottom side of the signal distribution structure, at least a portion of the semiconductor grain and at least a portion of the conductive pillars.

[0005] In the semiconductor device of the aspect, a bottom side of each of the plurality of conductive pillars and a bottom side of the semiconductor die are exposed from the second encapsulation material at a bottom side of the second encapsulation material.

[0006] In the semiconductor device of this aspect, the bottom side of each of the plurality of conductive pillars, the bottom side of the semiconductor die, and the bottom side of the second encapsulation material are coplanar.

[0007] The semiconductor device of the aspect includes a lower dielectric layer on a bottom side of the second encapsulation material, wherein the lower dielectric layer includes a plurality of holes, each hole of the plurality of holes exposing a corresponding conductive pillar of the plurality of conductive pillars through the lower dielectric layer.

[0008] The semiconductor device of the aspect includes a plurality of conductive balls, each of the plurality of conductive balls being electrically connected to a corresponding conductive pillar of the plurality of conductive pillars through a corresponding hole of the plurality of holes.

[0009] In the semiconductor device of the aspect, the top side of the first electronic component is covered by the first encapsulation material, and the bottom side of the semiconductor die is exposed from the second encapsulation material.

[0010] The semiconductor device of this aspect includes a second signal distribution structure on a bottom side of the second encapsulation material.

[0011] The semiconductor device of the embodiment includes a plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned directly below the semiconductor die, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive pillar of the plurality of conductive pillars.

[0012] In the semiconductor device of the aspect, a signal distribution structure lateral side of the plurality of signal distribution structure lateral sides is coplanar with corresponding lateral sides of the first encapsulation material, the second encapsulation material, and the second signal distribution structure.

[0013] Another aspect of the present invention is a semiconductor device, comprising: a first signal distribution structure having a first signal distribution structure top side, a first signal distribution structure bottom side, and a plurality of first signal distribution structure lateral sides extending between the first signal distribution structure top side and the first signal distribution structure bottom side; a first electronic component coupled to the first signal distribution structure top side; a first encapsulation material covering at least a portion of the first signal distribution structure top side and at least a portion of the first electronic component; a second electronic component coupled to the first signal distribution structure bottom side and located below the first electronic component; a conductive column coupled to the first signal distribution structure bottom side; a second encapsulation material covering at least a portion of the first signal distribution structure bottom side, at least a portion of the second electronic component, and at least a portion of the conductive column; and a second signal distribution structure having a second signal distribution structure top side, a second signal distribution structure bottom side, and a plurality of second signal distribution structure lateral sides extending between the second signal distribution structure top side and the second signal distribution structure bottom side.

[0014] In the semiconductor device of the aspect, a bottom side of each of the conductive pillars and a bottom side of the second electronic component are exposed from the second encapsulating material at a bottom side of the second encapsulating material.

[0015] In the semiconductor device of this aspect, the bottom side of each of the conductive pillars, the bottom side of the second electronic component, and the bottom side of the second encapsulating material are coplanar.

[0016] In the semiconductor device of the aspect, a top side of the first electronic component is covered by the first encapsulation material, and a bottom side of the second electronic component is exposed from the second encapsulation material.

[0017] The semiconductor device of the embodiment includes a plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned directly below the second electronic component, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive post of the conductive posts.

[0018] The semiconductor device of the embodiment includes a second plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned laterally outside the footprint of the second electronic component, and wherein the second signal distribution structure electrically connects each conductive ball of the second plurality of conductive balls to a corresponding conductive post of the conductive posts.

[0019] In the semiconductor device of the embodiment, a first signal distribution structure lateral side of the plurality of first signal distribution structure lateral sides is coplanar with a corresponding lateral side of the first encapsulation material, a corresponding lateral side of the second encapsulation material, and a corresponding one of the plurality of second signal distribution structure lateral sides.

[0020] In the semiconductor device of the aspect, each of the first signal distribution structure and the second signal distribution structure includes a plurality of conductive layers and a plurality of dielectric layers.

[0021] Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: providing a first signal distribution structure, the first signal distribution structure having a signal distribution structure top side, a signal distribution structure bottom side and a plurality of signal distribution structure lateral sides, wherein the first signal distribution structure comprises a first dielectric layer and a first conductive layer; providing a first electronic component coupled to the top side of the signal distribution structure; providing a first encapsulation material covering at least a portion of the top side of the signal distribution structure and at least a portion of the first electronic component; providing a semiconductor grain coupled to the bottom side of the signal distribution structure and located directly below the first electronic component; providing a plurality of conductive pillars coupled to the bottom side of the signal distribution structure and positioned laterally around the semiconductor grain; and providing a second encapsulation material covering at least a portion of the bottom side of the signal distribution structure, at least a portion of the semiconductor grain and at least a portion of the plurality of conductive pillars.

[0022] The method of the embodiment includes: providing a lower dielectric layer on the bottom side of the second encapsulation material, wherein the lower dielectric layer includes a plurality of holes, each of the plurality of holes penetrating through the lower dielectric layer to expose a corresponding conductive column among the plurality of conductive columns; and providing a plurality of conductive balls, wherein each of the plurality of conductive balls is electrically connected to a corresponding conductive column among the plurality of conductive columns through a corresponding hole among the plurality of holes.

[0023] The method of the embodiment includes: providing a second signal distribution structure on the bottom side of the second encapsulation material; and providing a plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned directly below the semiconductor die, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive post among the plurality of conductive posts. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flowchart is shown of an exemplary method of fabricating a semiconductor device according to various aspects of the present disclosure.

[0025] Figure 2A-2I Cross-sectional views are shown to illustrate various steps of an exemplary method of fabricating a semiconductor device according to various aspects of the present disclosure.

[0026] Figure 3A Cross-sectional views of exemplary semiconductor devices according to various aspects of the present disclosure are shown.

[0027] Figure 3B A bottom view of an exemplary semiconductor device according to various aspects of the present disclosure is shown.

[0028] Figures 4A-4B Cross-sectional views are shown to illustrate various steps of an exemplary method of fabricating a semiconductor device according to various aspects of the present disclosure.

[0029] Figure 5A Cross-sectional views of exemplary semiconductor devices according to various aspects of the present disclosure are shown.

[0030] Figure 5B A bottom view of an exemplary semiconductor device according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0031] The following discussion presents various aspects of the present disclosure by providing examples of the present disclosure. These embodiments are non-limiting, and thus the scope of the various aspects of the present disclosure is not necessarily limited by any specific features of the embodiments provided. In the following discussion, the terms "such as", "for example", and "exemplary" are non-limiting and are generally synonymous with "as an example and not limitation", "for example and not limitation", etc.

[0032] As used herein, "and / or" refers to any one or more items in a list connected by "and / or". For example, "x and / or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" means "the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z".

[0033] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the disclosure of the present invention. As used herein, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise. It is further understood that the terms "comprise", "include", "includes", "comprising", "having", "containing", "having" and the like used in this specification specifically indicate the presence of the described features, integers, steps, operations, components and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, components and / or their sets.

[0034] It should be understood that although the terms first, second, etc. used in this article can describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, for example, without departing from the teachings disclosed in the present invention, the first component, first component, or first part discussed below can be referred to as the second component, second component, or second part. Similarly, various spatial terms such as "upper", "above", "lower", "below", "lateral", "lateral", "horizontal", "vertical", etc. can be used to distinguish one component from another component in a relative manner. However, it should be understood that the components can be oriented in different ways, for example, the semiconductor device can be turned sideways so that its "top" surface is horizontally facing and its "side" surface is vertically facing, without departing from the teachings of the present disclosure.

[0035] It will also be understood that unless expressly stated otherwise, the terms coupled, connected, attached, etc. include direct and indirect (e.g., with intervening components) couplings, connections, attachments, etc. For example, if component A is coupled to component B, component A may be indirectly coupled to component B via an intervening signal distribution structure, component A may be directly coupled to component B (e.g., directly adhered, directly welded, attached by direct metal-to-metal bonding, etc.), etc.

[0036] In the drawings, the sizes (e.g., absolute and / or relative sizes) of structures, layers, regions, etc. may be exaggerated for clarity. However, such sizes are generally representative of exemplary embodiments, and they are not limiting. For example, if structure A is shown as being larger than region B, this is generally representative of exemplary embodiments, and unless otherwise specified, structure A generally need not be larger than structure B. Additionally, in the drawings, like component symbols may refer to like components throughout the discussion.

[0037] In recent years, portable electronic products such as mobile phones or portable media players (PMP) have been continuously required to be small, lightweight and cost-effective while having high functionality. In order to meet these requirements, semiconductor packages mounted on portable electronic products are being developed into innovative, cost-effective three-dimensional (3D) packages.

[0038] Therefore, wafer-level chip size packages, chip size packages, chip stack packages and other packaging types that have a size or thickness almost the same as that of a chip are being developed, and examples of these stack type packages include system in package (SIP), multi-chip package (MCP), package-on-package (POP), etc.

[0039] Various aspects disclosed in the present invention provide a semiconductor device and a method for manufacturing the same, which include: a first signal distribution structure (SDS) having a signal distribution structure top side, a signal distribution structure bottom side, and a plurality of signal distribution structure lateral sides, wherein the first signal distribution structure includes a first dielectric layer and a first conductive layer; a first electronic component coupled to the signal distribution structure top side; a first encapsulation material covering at least a portion of the signal distribution structure top side and at least a portion of the first electronic component; a semiconductor die coupled to the signal distribution structure bottom side and directly below the first electronic component; a plurality of conductive pillars coupled to the signal distribution structure bottom side and laterally positioned around the semiconductor die; and a second encapsulation material covering at least a portion of the signal distribution structure bottom side, at least a portion of the semiconductor die, and at least a portion of the plurality of conductive pillars.

[0040] In various exemplary embodiments, the bottom side of each of the plurality of conductive pillars and the bottom side of the semiconductor die may be exposed from the second encapsulation material at the bottom side of the second encapsulation material; and the bottom side of each of the plurality of conductive pillars, the bottom side of the semiconductor die, and the bottom side of the second encapsulation material may be coplanar. In various exemplary embodiments, the device may include a lower dielectric layer on the bottom side of the second encapsulation material, wherein the lower dielectric layer includes a plurality of holes, each of the plurality of holes exposing a corresponding conductive pillar of the plurality of conductive pillars through the lower dielectric layer; and may include a plurality of conductive balls, wherein each of the plurality of conductive balls is electrically connected to a corresponding conductive pillar of the plurality of conductive pillars through a corresponding hole of the plurality of holes. In various exemplary embodiments, the top side of the first electronic component may be covered by the first encapsulation material, and the bottom side of the semiconductor die may not be covered by the second encapsulation material. In various exemplary embodiments, the device may include: a second signal distribution structure (SDS) on a bottom side of the second encapsulation material; and a plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned directly below the semiconductor die, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive pillar of the plurality of conductive pillars. Additionally, in various exemplary embodiments, at least one of the plurality of signal distribution structure lateral sides may be coplanar with a corresponding lateral side of the first encapsulation material, a corresponding lateral side of the second encapsulation material, and a corresponding lateral side of the second signal distribution structure.

[0041] Various aspects disclosed in the present invention provide a semiconductor device and a method for manufacturing the same, which include: a first signal distribution structure (SDS), having a first signal distribution structure top side, a first signal distribution structure bottom side, and a plurality of first signal distribution structure lateral sides extending between the first signal distribution structure top side and the first signal distribution structure bottom side; a first electronic component coupled to the signal distribution structure top side; a first encapsulation material covering at least a portion of the signal distribution structure top side and at least a portion of the first electronic component; a second electronic component coupled to the signal distribution structure bottom side and located below the first electronic component; a conductive column coupled to the signal distribution structure bottom side; a second encapsulation material covering at least a portion of the signal distribution structure bottom side, at least a portion of the second electronic component, and at least a portion of the conductive column; and a second signal distribution structure (SDS), having a second signal distribution structure top side, a second signal distribution structure bottom side, and a plurality of second signal distribution structure lateral sides extending between the second signal distribution structure top side and the second signal distribution structure bottom side.

[0042] In various exemplary embodiments, the bottom side of each of the plurality of conductive pillars and the bottom side of the second electronic component (e.g., a semiconductor die) may be exposed from the second encapsulation material at the bottom side of the second encapsulation material, for example, wherein the bottom side of each of the plurality of conductive pillars, the bottom side of the second electronic component, and the bottom side of the second encapsulation material are coplanar. In various exemplary embodiments, the top side of the first electronic component may be covered by the first encapsulation material, and the bottom side of the second electronic component may be exposed from the second encapsulation material. In various exemplary embodiments, the device may include: a plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned directly below the second electronic component, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive pillar of the plurality of conductive pillars; and a second plurality of conductive balls coupled to the bottom side of the second signal distribution structure and positioned laterally outside the footprint of the second electronic component, and wherein the second signal distribution structure electrically connects each of the second plurality of conductive balls to a corresponding conductive pillar of the plurality of conductive pillars. In various exemplary embodiments, one of the multiple signal distribution structure lateral sides may be coplanar with a corresponding side of the first encapsulation material, a corresponding side of the second encapsulation material, and a corresponding side of the second signal distribution structure; and / or each of the first signal distribution structure and the second signal distribution structure may include multiple conductive layers and multiple dielectric layers.

[0043] Figure 1 A flowchart is shown of an exemplary method of fabricating a semiconductor device according to various aspects of the present disclosure. Figure 2A-2IThe cross-sectional views of various steps of a method for manufacturing a semiconductor device according to various aspects disclosed in the present invention are shown. For example, Figure 2A-2I Can display according to Figure 1 A cross-sectional view of an exemplary semiconductor device during fabrication of an exemplary method 100 of the present invention. The following discussion generally refers to Figure 1 and Figure 2A-2I .

[0044] refer to Figure 1 , an exemplary method 100 for manufacturing a semiconductor device may include: (110) preparing a carrier, (120) attaching a first component, (130) first encapsulation, (140) flipping and carrier removal, (150) forming a first signal distribution structure, (160) forming a pillar and attaching a second component, (170) second encapsulation, (180) thinning / planarization, (190) forming a second signal distribution structure and an interconnect structure, and (195) singulation.

[0045] Now refer to Figure 2A-2I To describe Figure 1 Various blocks (or steps, phases, processes, etc.) of an exemplary method 100 are shown.

[0046] refer to Figure 1 and Figure 2A 1 , the exemplary method 100 may include, at block 110, preparing (or providing, receiving, etc.) a carrier 61. The carrier 61 may include any kind of features, not limited to the examples provided herein. The carrier 61 may, for example, include a carrier for a single semiconductor device (or package), or may, for example, include a wafer or panel on which any number of semiconductor devices (or packages) may be formed. The carrier 61 may, for example, include a semiconductor wafer or panel. The carrier 61 may also, for example, include a glass wafer or panel, a metal wafer or panel, a ceramic wafer or panel, a plastic wafer or panel, etc.

[0047] Block 110 may also, for example, include forming an adhesive layer 62 on the carrier. The adhesive layer 62 may, for example, include an adhesive paste layer, a liquid adhesive layer, a preformed double-sided tape or sheet (e.g., a die attach tape), a printed adhesive, etc. The adhesive layer 62 may, for example, partially or completely cover the top side of the carrier 61. Block 110 may include forming the adhesive layer 62 in any of a variety of ways. For example, block 110 may include forming the adhesive layer 62 by applying a preformed sheet or film of the adhesive layer 62 to the carrier 61, printing the adhesive layer 62 on the carrier 61, spin coating the adhesive layer 62 on the carrier 61, dipping the carrier 61 in an adhesive, spraying the adhesive layer 62 on the carrier, etc.

[0048] It should be noted that in an exemplary scenario of receiving a carrier 61 to which an adhesive layer 62 is already applied, block 110 may skip applying the adhesive layer 62. It should also be noted that in an exemplary case, a component coupled to the carrier 61 (e.g., at block 120, etc.) may be coated with the adhesive layer 62 (or a portion thereof) prior to applying the component to the carrier 61.

[0049] Next reference Figure 1 and Figure 2B 2 , the exemplary method 100 may include, at block 120, coupling (or attaching or forming) one or more first electronic components 23 to the carrier 61. Block 120 may, for example, include placing the first electronic components 23 on the top side of the adhesive layer 62 (e.g., with the bottom side of the adhesive layer 62 facing the carrier 61).

[0050] One or more first electronic components 23 (or any electronic components discussed herein) may include characteristics of any of various types of electronic components. For example, any or all of the first electronic components 23 (or any electronic components discussed herein) may include passive electronic components (e.g., resistors, capacitors, inductors, antenna components, etc.), integrated passive devices (IPDs), etc. In the exemplary case where one or more first electronic components 23 include IPDs, each of these first electronic components 23 may have a relatively small thickness (e.g., 50 microns or less, etc.).

[0051] For another example, any or all of the first electronic components 23 may include active electronic components (e.g., semiconductor dies, transistors, etc.). For example, any or all of the first electronic components 23 may include processor dies, microprocessors, microcontrollers, coprocessors, general purpose processors, application specific integrated circuits, programmable and / or discrete logic devices, memory devices, combinations thereof, equivalents, etc.

[0052] The exemplary first electronic component 23 may, for example, include a component terminal 28. In an exemplary embodiment, the component terminal 28 of the first electronic component 23 may be placed in contact with the adhesive layer 62. In various exemplary cases, the component terminal 28 (e.g., all or part of its lateral side) may be embedded in the adhesive layer 62. Block 120 may include placing one or more first electronic components 23 in any of a variety of ways (e.g., using an automatic pick and place system, manual placement, performing any combination of automatic and manual placement, etc.).

[0053] Next reference Figure 1 and Figure 2CFor the exemplary structure 200c of FIG. 1 , the exemplary method 100 may include forming a first encapsulation material at block 130. For example, block 130 may include covering the top side of the adhesive layer 62 and any or all sides of the first electronic component 23 (e.g., the top side, the bottom side facing the adhesive layer 62 where there is a gap between the component and the adhesive layer 62, the lateral side, etc.) with the first encapsulation material 26. In addition, the first encapsulation material 26 may cover any portion of the conductive terminal 28 that is not yet covered (e.g., a portion that is not yet covered by the adhesive layer 62, other portions of the first electronic component 23, etc.). It should be noted that any side of one or more of the first electronic components 23 may remain uncovered by the first encapsulation material 26.

[0054] Block 130 may include forming the first encapsulating material 26 in any of a variety of ways, not limited to the examples provided herein. For example, block 130 may include forming the first encapsulating material 26 using one or more of compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, film assisted molding, etc. For another example, block 130 may include forming the first encapsulating material 26 using one or more of spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.

[0055] The first encapsulation material 26 may include one or more of a variety of encapsulation materials, not limited to the examples provided herein. For example, the first encapsulation material 26 may include any of a variety of encapsulation or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, silicone resins, combinations thereof, equivalents thereof, etc.). For another example, the first encapsulation material 26 may include any of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si 3 N 4 、SiO 2 , SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, polysilicone, acrylate polymers, equivalents thereof, etc.).

[0056] It should be noted that, as discussed herein with respect to the second encapsulation material formed at block 170, the first encapsulation material 26 can be initially formed to a desired thickness, but can also be thinned (e.g., thinned but still covering the first electronic components 23, thinned to expose the top surfaces of one or more first electronic components 23, etc.).

[0057] Next reference Figure 1 and Figure 2D The exemplary method 100 may include, at block 140, flipping (or flipping) the first encapsulated structure 200c and removing the carrier 61 and the adhesive layer 62. Figure 2D Not shown, but in an exemplary embodiment a second carrier (or tool structure) may be coupled to the first encapsulation material 26 (eg, on a side opposite to the carrier 61 and the adhesive layer 62, etc.), and then the carrier 61 and the adhesive layer 62 may be removed.

[0058] Block 140 may include removing the carrier 61 and the adhesive layer 62 in any of a variety of ways, not limited to the examples provided herein. For example, block 140 may include applying energy (e.g., heat, laser energy, etc.) to the adhesive layer 62 and / or the carrier 61 to release the adhesive layer 62. For another example, block 140 may include peeling, shearing, and / or pulling the carrier 61 from the first encapsulation material 26 and the first electronic component 23. For another example, block 140 may include grinding (or abrading) and / or chemically etching away the carrier 61 and / or the adhesive layer 62. It should be noted that in various exemplary cases, a portion of the conductive terminal 28 and / or the first encapsulation material 26 adjacent to the adhesive layer 62 may also be removed (e.g., planarized, etc.).

[0059] It should be noted that the removal of the carrier 61 and the adhesive layer 62 may expose the side of the first encapsulating material 26 previously covered by the adhesive layer 62 and the carrier 61, and may also expose the side of the component terminals 28 previously covered by the adhesive layer 62 and the carrier 61 (e.g., the side facing the carrier 61, the side that may have been embedded in the adhesive layer 62, etc.). It should be noted that, depending on the geometry of the first electronic component 23 and / or the conductive terminals 28, the removal of the carrier 61 and the adhesive layer 62 may also expose a portion of the first electronic component 23 in addition to the conductive terminals 28.

[0060] Next reference Figure 1 and Figure 2E200e, the exemplary method 100 may include forming a signal distribution structure 21 on the first encapsulation material 26 and on the first electronic component 23 (and / or its conductive terminals 28) at block 150. Block 150 may include forming the signal distribution structure 21 in any of a variety of ways, not limited to the examples provided herein. For example, block 150 may share any or all features of a substantially similar block (and / or resulting structure) shown in U.S. Patent Application No. 14 / 823,689, filed on August 11, 2016, entitled “Semiconductor Package and Method of Manufacturing Thereof,” the entire contents of which are incorporated herein by reference in their entirety for all purposes.

[0061] Block 150 may, for example, include forming and patterning one or more dielectric layers and one or more conductive layers to form a signal distribution structure 21. It should be noted that the signal distribution structure 21 may also be referred to as a redistribution layer, a redistribution layer stack, a redistribution structure, an interposer, and the like.

[0062] Block 150 may, for example, include forming a signal distribution structure 21 having any number of dielectric layers and conductive layers (e.g., signal distribution layers, redistribution layers, pad layers, conductive vias, under bump metallization, land layers, etc.). In an exemplary example, block 150 may include forming a signal distribution structure 21 including a first dielectric layer 21a, a first conductive layer 21b (e.g., a pad or land layer, a trace layer, etc.), a second dielectric layer 21c, a second conductive layer 21d (e.g., a pad or land layer, a trace layer, etc.), and an under bump metallization (UBM) structure (or layer) 21e.

[0063] For example, block 150 may include forming the first dielectric layer 21a using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the scope of the present invention is not limited to this.

[0064] The first dielectric layer 21a may include one or more layers of any of various dielectric materials, such as inorganic dielectric materials (e.g., Si 3 N 4 、SiO 2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, polysilicone, acrylate polymers, equivalents thereof, etc.), but the scope of the present invention is not limited thereto.

[0065] For example, block 150 may also include patterning the first dielectric layer 21a, such as forming holes therein to expose various portions of the electronic components 23 discussed herein (e.g., the conductive terminals 28, etc.). For example, block 150 may include ablation holes (e.g., by laser ablation, by mechanical ablation, by chemical ablation (or etching), etc.). For another example, block 150 may include initially forming the first dielectric layer 21a (e.g., by deposition, etc.) with the desired holes (e.g., by masking and / or printing processes, etc.).

[0066] Block 150 may include forming a first conductive layer 21b (e.g., a pad or land layer, a trace layer, etc.) in any of a variety of ways, not limited to the examples provided herein. For example, block 150 may include forming the first conductive layer 21b using any one or more of a variety of processes (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto. For example, block 150 may include forming a first conductive layer 21b, the first conductive layer 21b including pads or lands in holes of the first dielectric layer 21a, such as on the top side of the conductive terminal 28 of the electronic component 23. Block 150 may also, for example, include forming traces on the first dielectric layer 21a (and / or in the channels formed herein).

[0067] As with any conductive layer discussed herein, block 150 may include forming one or more seed layers as part of the process of forming the first conductive layer 21b (e.g., prior to electroplating the first conductive layer 21b, etc.). Figure 2E Not shown, block 150 may include forming one or more seed layers on a top surface of the first dielectric layer 21 a , on a sidewall of a hole in the first dielectric layer 21 a , on a top surface of the conductive terminal 28 , and the like.

[0068] The first conductive layer 21b, which may also be referred to herein as a pad, via, trace, land, bonding liner layer, conductive layer, trace layer, redistribution layer, etc., may include any one of a variety of materials (such as copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope disclosed in the present invention is not limited thereto.

[0069] Block 150 may include, for example, forming a second dielectric layer 21c on and / or over a portion of the first dielectric layer 21a (or a portion thereof) and / or the first conductive layer 21b (or a portion thereof). For example, block 150 may include forming the second dielectric layer 21c in any one of a variety of ways, such as any of the ways discussed herein with respect to the first dielectric layer 21a. For example, block 150 may include forming the second dielectric layer 21c in the same manner as the first dielectric layer 21a, or in a different manner. The second dielectric layer 21c may include, for example, any of the features discussed herein with respect to the first dielectric layer 21a. The second dielectric layer 21c may be formed, for example, of the same dielectric material or a different dielectric material as the first dielectric layer 21a.

[0070] Similar to the first dielectric layer 21a, block 150 may include patterning the second dielectric layer 21c in any one of a variety of ways. For example, block 150 may include forming holes in the second dielectric layer 21c to expose pads, lands, or traces of the first conductive layer 21b, for example, to establish electrical contact with the second conductive layer 21d.

[0071] Block 150 may include, for example, forming a second conductive layer 21d on the second dielectric layer 21c, in the holes of the second dielectric layer 21c, in a portion of the first conductive layer 21b (or other material) exposed through the holes of the second dielectric layer 21c, and / or on a portion thereof. Block 150 may, for example, include forming the second conductive layer 21d in any of the ways discussed herein with respect to the first conductive layer 21b. For example, block 150 may include forming the second conductive layer 21d in the same manner as the first conductive layer 21b, or in a different manner. The second conductive layer 21d may include, for example, any or all of the features discussed herein with respect to the first conductive layer 21b. The second conductive layer 21d may be formed, for example, of the same conductive material or a different conductive material as the first conductive layer 21b.

[0072] In an exemplary embodiment, the second conductive layer 21d (or a portion thereof) may include a first pad or land of an interconnect structure to which one or more electronic components may be attached and a second pad or land having a conductive post (or rod) formed thereabove. It should be noted that the first pad or land and the second pad or land may be the same or may have respective different characteristics (such as metallurgical characteristics, geometric characteristics, etc.).

[0073] It should be noted that block 150 may include forming the signal distribution structure 21 to have any number of conductive and / or dielectric layers, such as one or more conductive layers, one or more dielectric layers, etc. It should also be noted that the configurations of the signal distribution structure 21 shown in the various figures herein are merely exemplary and not limiting. For example, the signal distribution structure 21 (or its conductive layer) may provide an electrical path through the signal distribution structure 21, such as directly vertically or indirectly vertically (e.g., vertically and horizontally, etc.), between the first electronic component 23 and the second electronic component 22 and / or the conductive pillar 25 (or other components). For another example, the signal distribution structure 21 (or its conductive layer) may provide a lateral (or horizontal) electrical channel through the signal distribution structure 21, such as between the first electronic component 23 and the second electronic component 22 and / or the pillar 25 (or other components).

[0074] Block 150 may also include, for example, forming an under-bump metallization (UBM) structure 21e (or layer) on the second conductive layer 21d and / or the second dielectric layer 21c (e.g., on a portion of the second dielectric layer 21c surrounding the periphery of the hole in the second dielectric layer 21c where the second conductive layer 21d is exposed, etc.). For example, block 150 may include forming the UBM structure 21e to have one or more metallization layers that facilitate attachment (or formation) of interconnect structures (e.g., conductive balls, conductive pillars, or rods, etc.) formed and / or attached, for example, at block 160. The UBM structure 21e may be exposed, for example, at the top surface of the signal distribution structure 21 (e.g., as shown in FIG. 1 ). Figure 2E The UBM structure 21e may also be referred to herein as a land or pad.

[0075] Block 150 may include forming a UBM structure 21e in any of a variety of ways, not limited to the examples provided herein. In an exemplary example, block 150 may include forming a UBM seed layer of the UBM structure 21e over the second dielectric layer 21c and / or over a portion of the second conductive layer 21d (e.g., a pad or land, a trace, etc.) exposed through a hole in the second dielectric layer 21c. The UBM seed layer may, for example, include any of a variety of conductive materials (e.g., copper, gold, silver, metal, etc.). The UBM seed layer may be formed in any of a variety of ways (e.g., sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

[0076] Block 150 may, for example, include forming a mask (or template) over the UBM seed layer to define the area (or volume) where one or more additional UBM layers (and / or conductive pillars 25 or other interconnect structures) of the UBM structure 21e are to be formed. For example, the mask may include a photoresist (PR) material or other material that may be patterned to cover areas other than the areas where the UBM layers (and / or conductive pillars 25) are to be formed. Block 150 may then, for example, include forming one or more UBM layers on the UBM seed layer exposed through the mask. The UBM layer may include any of a variety of materials (e.g., titanium, chromium, aluminum, titanium / tungsten, titanium / nickel, copper, alloys thereof, etc.). Block 150 may include forming a UBM layer on the UBM seed layer in any of a variety of ways (e.g., electroplating, sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

[0077] It should be noted that the UBM structure 21e may or may not be present, for example, depending on interconnection needs. In an exemplary embodiment, the UBM structure 21e may be formed for interconnection with the second electronic component 22, but not for interconnection with the conductive pillar 25. In another exemplary embodiment, the UBM structure 21e may be formed for interconnection with the second electronic component 22 and for interconnection with the conductive pillar 25. In such an exemplary embodiment, the corresponding UBM structure 21e for interconnection with the second electronic component 22 may be different (e.g., metallurgically different, geometrically different, etc.) from the corresponding UBM structure 21e for interconnection with the conductive pillar 25 (or such UBM structures 21e may be all the same). Another exemplary embodiment may not include the UBM structure 21e. Another exemplary embodiment may include a UBM structure 21e for interconnection with the conductive pillar 25 but not for interconnection with the second electronic component 22. It should be noted that a conductive connection pad or liner may be used instead of the UBM structure 21e, or in addition to the UBM structure 21e.

[0078] As discussed herein, the signal distribution structure 21 can vertically and / or horizontally arrange any electrical signals of the first electronic component 23, the second electronic component 22 (to be mounted at block 160), and / or the conductive pillars (to be formed at block 160). For example, the signal distribution structure 21 can arrange any such signals vertically and / or vertically and horizontally (or laterally).

[0079] Generally, block 150 may include forming a signal distribution structure 21 (or interposer). Thus, the scope of the present disclosure should not be limited by the characteristics of any particular signal distribution structure or any particular manner of forming such a signal distribution structure.

[0080] Next reference Figure 1 and Figure 2F In the exemplary structure 200f, the exemplary method 100 may include, at block 160, forming one or more conductive posts (or rods) on the signal distribution structure, and coupling one or more second electronic components (e.g., semiconductor dies, etc.) to the signal distribution structure (e.g., as formed at block 150, etc.).

[0081] Block 160 may, for example, include forming one or more conductive pillars 25 on the signal distribution structure 21. The conductive pillars 25 may, for example, be formed on corresponding portions of the second conductive layer 21d and / or at least partially on the second dielectric layer 21c. The conductive pillars 25 may also be formed on corresponding UBM structures 21e (if present). In an exemplary embodiment, block 160 may include forming the conductive pillars 25 to extend vertically from the signal distribution structure 21 (e.g., from corresponding UBM structures 21e, from corresponding pads or lands or traces of the second conductive layer 21d, etc.). Such formation may be performed in any of a variety of ways, but is not limited to the examples provided herein.

[0082] As discussed herein, the second conductive layer 21d can, for example, include any of a variety of conductive materials (e.g., copper, aluminum, silver, gold, nickel, alloys thereof, etc.). The second conductive layer 21d can, for example, be exposed through a hole in the second dielectric layer 21c or another dielectric layer. For example, the second dielectric layer 21c can cover the side surfaces of the second conductive layer 21d (or its pads or lands) and / or the outer periphery of the top surface of the second conductive layer 21d. The second dielectric layer 21c can also, for example, maintain at least a portion of the lateral side surfaces of the second conductive layer 21d exposed.

[0083] The conductive pillar 25 (or a plurality thereof) may include any of a variety of characteristics. For example, the conductive pillar 25 may be cylindrical, elliptical, rectangular, etc. The conductive pillar 25 may, for example, include a flat upper end, a concave upper end, or a convex upper end. The conductive pillar 25 may, for example, include any material discussed herein with respect to the conductive layer. In an exemplary embodiment, the conductive pillar 25 may include copper (e.g., pure copper, copper with some impurities, etc.), a copper alloy, etc. In an exemplary embodiment, block 160 (or another block of the exemplary method 100) may also include forming a weld cap (or dome) on the conductive pillar 25.

[0084] Block 160 may include forming the conductive pillar 25 in any of a variety of ways (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto. It should be noted that the conductive pillar 25 may also be formed by attaching pre-formed wires (e.g., die bonding wires, etc.), by filling a through hole or groove in a temporary or permanent mask (e.g., a photoresist mask, a molding material mask, etc.), etc.

[0085] After forming the conductive pillars 25, if a mask is used, block 160 may include stripping or removing the mask (e.g., chemical stripping, ashing, etc.). In addition, block 160 may include removing (e.g., by chemical etching, etc.) at least a portion of the seed layer if used to form the conductive pillars 25. It should be noted that during the etching of the seed layer, at least the lateral edge portions of the seed layer below other non-etched layers may be, for example, etched. For example, such etching may result in undercutting below the remaining non-etched layers (e.g., conductive pillars 25, UBM structures 21e, etc.). For example, in an exemplary embodiment where the UBM structure 21e and the corresponding conductive pillar 25 are both formed over the same seed layer, such etching of the seed layer may result in undercutting below the UBM structure 21e formed thereon and / or below the conductive pillar 25. For another example, in an exemplary embodiment where the conductive pillar 25 is formed over the seed layer, such etching of the seed layer may result in undercutting below the conductive pillar 25.

[0086] After forming the conductive pillars 25, block 160 may, for example, include attaching (or coupling or forming) one or more second electronic components 22 to the signal distribution structure 21. The second electronic components 22 may, for example, include any or all types of components discussed herein with respect to the first electronic components 23. For example, in an exemplary embodiment, the first electronic component 23 may include a passive electronic device, and the second electronic component 22 may include a semiconductor die. In another exemplary embodiment, the first electronic component 23 may include a semiconductor die, and the second electronic component 22 may include a semiconductor die. In yet another exemplary embodiment, the first electronic component 23 may include a semiconductor die, and the second electronic component 22 may include a passive electronic device. In yet another exemplary embodiment, the first electronic component 23 may include a semiconductor die and a passive component, and the second electronic component 22 may include a semiconductor die and a passive component.

[0087] Block 160 may, for example, include attaching a second electronic component 22 to a top side (or portion) of the signal distribution structure 21. In the exemplary case where the second electronic component 22 includes a semiconductor die, the second electronic component 22 may, for example, be oriented in such a manner that an active side of the die (e.g., on which semiconductor circuitry is typically formed) faces the signal distribution structure 21 (e.g., in a flip-chip configuration, etc.) and an inactive side of the die opposite the active side of the die faces away from the signal distribution structure 21. It should be noted that the active side of such a semiconductor die may include a die bond pad electrically connected to the semiconductor circuitry of the die. For example, as Figure 2F As shown, the bonding pads 29 / 29a (and / or other interconnecting terminals of the second electronic component 22 at the lower side of the second electronic component 22) can be attached to the corresponding UBM structure 21e (if present) and / or the exposed portion (e.g., pads, lands, etc.) of the second conductive layer 21d of the signal distribution structure 21. Such attachment (or connection) can be performed, for example, with conductive bumps 29 / 29a (e.g., C4 bumps, micro bumps, metal pillars, conductive balls, etc.). Block 160 can include attaching the second electronic component 22 to the top side of the signal distribution structure 21 in any of a variety of ways (e.g., mass reflow, thermocompression bonding, direct metal-to-metal metal-to-metal bonding, laser welding, conductive epoxy bonding, conductive film bonding, etc.). It should be noted that the signal distribution structure 21 can electrically connect the conductive pillars 25 to the pads or terminals of the first electronic component 23 and / or the second electronic component 22.

[0088] The second electronic component 22 can be positioned on the signal distribution structure 21 in any of a variety of ways. For example, the second electronic component 22 can be centered on the signal distribution structure 21, but can also be laterally offset. In addition, for example, multiple second electronic components 22 (like the first electronic component 23) can also be attached to the signal distribution structure 21 to be included in the same packaged semiconductor device.

[0089] The conductive pillars 25 (or rods) and the second electronic components 22 may be configured in any of a variety of ways. For example, the second electronic component 22 (or a plurality thereof) may be laterally surrounded (e.g., on two, three, or four sides) by a plurality of conductive pillars 25. In another exemplary embodiment, one or more conductive pillars 25 may be positioned laterally between second electronic components 22 of the same packaged semiconductor device.

[0090] It should be noted that, for example, when the second electronic component 22 is attached to the signal distribution structure 21, the second electronic component 22 can be taller than the conductive pillar 25, shorter than the conductive pillar 25, or substantially the same height as the conductive pillar 25. As discussed herein, the tops of the second electronic component 22, the conductive pillar 25, and / or the second encapsulation material 27 can be planarized in any of a variety of ways.

[0091] Typically, block 160 may include forming one or more conductive posts (or rods) on the signal distribution structure and / or forming one or more second electronic components. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular conductive posts or the manner in which such posts are formed, or by the characteristics of any particular electronic components or the manner in which such electronic components are formed (or attached).

[0092] Next reference Figure 1 and Figure 2G For example, the exemplary structure 200g of FIG. 1 , the exemplary method 100 may include forming a second encapsulation material at block 170 . For example, block 170 may share any or all features with block 130 .

[0093] For example, block 170 may include covering the top side of the signal distribution structure 21, any or all sides of the conductive pillars 25 (e.g., the top side, the lateral side, the bottom side exposed through the undercut, etc.), and any or all sides of the second electronic components 22 (e.g., the top side, the bottom side facing the signal distribution structure 21 with a gap between the component and the signal distribution structure 21, the lateral side, etc.) with the second encapsulation material 27. In addition, the second encapsulation material 27 may cover any portion of the bonding pads or bumps of the second electronic components 22 that are not already covered. It should be noted that any side of one or more second electronic components 22 may remain uncovered by the second encapsulation material 27.

[0094] In an exemplary embodiment, the second encapsulation material 27 may cover the top side of the signal distribution structure 21 (e.g., any dielectric layer and / or conductive layer exposed at the top side of the signal distribution structure 21). The second encapsulation material 27 may also cover, in whole or in part, the lateral sides of the second electronic component 22 (or multiple thereof) and / or the lateral sides of the conductive pillar 25 (or multiple thereof). The second encapsulation material 27 may be formed to also cover the top side of the second electronic component 22 and / or the conductive pillar 25. Although the present invention is not limited to the embodiment of the present invention, the second encapsulation material 27 may be formed to also cover the top side of the second electronic component 22 and / or the conductive pillar 25. Figure 2G While the second encapsulation material 27 and other figures show that it covers only the top side of the signal distribution structure 21, it should be understood that the second encapsulation material 27 may also be formed to cover the lateral sides of the signal distribution structure 21 and / or the lateral sides of the first encapsulation material 26 (for example, after the electronic device is separated from a wafer or panel or other such combination of electronic devices).

[0095] It should be noted that the second encapsulation material 27 may also bottom fill the second electronic component 22, and / or a bottom filler different from the second encapsulation material 27 may be applied during and / or after the attachment of the second electronic component 22. For example, such bottom filler may include any of various types of materials, such as, but not limited to, epoxy resins, thermoplastic materials, thermosetting materials, polyimides, polyurethanes, polymer materials, filled epoxies, filled thermoplastic materials, filled thermosetting materials, filled polyimides, filled polyurethanes, filled polymer materials, fluxing bottom fillers, and their equivalents. Such bottom filling may be performed using a capillary bottom filling process, using a pre-applied bottom filler, etc. For example, any of the electronic components discussed herein may be similarly bottom filled.

[0096] Block 170 may include forming the second encapsulating material 27 in any of a variety of ways, not limited to the examples provided herein. For example, block 170 may include forming the second encapsulating material 27 using one or more of compression molding, transfer molding, liquid encapsulating agent molding, vacuum lamination, paste printing, film assisted molding, etc. For another example, block 170 may include forming the second encapsulating material 27 using one or more of spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.

[0097] The second encapsulation material 27 may include one or more of a variety of encapsulation materials, not limited to the examples provided herein. For example, the second encapsulation material 27 may include any of a variety of encapsulation or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, silicone resins, combinations thereof, equivalents thereof, etc.). Also for example, the second encapsulation material 27 may include any of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si 3 N 4 、SiO 2 , SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, polysilicone, acrylate polymers, equivalents thereof, etc.).

[0098] The second encapsulating material 27 (or its formation) may share any or all characteristics with the first encapsulating material 26. However, the scope of the present disclosure is not limited in this regard. For example, block 170 may include forming the second encapsulating material 27 in a manner different from the manner in which the first encapsulating material 26 is formed in block 130. Also for example, the second encapsulating material 27 may be a different type of material than the first encapsulating material 26.

[0099] Next reference Figure 1 and Figure 2H Based on the exemplary structure 200h, the exemplary method 100 may include, at block 180, thinning (or planarizing) the assembly encapsulated at block 170.

[0100] For example, block 180 may include thinning or flattening (e.g., mechanical grinding, chemical etching, shaving or shearing, peeling, any combination thereof, etc.) the top side of the second encapsulation material 27 to a desired thickness. Block 180 may also, for example, include thinning (e.g., mechanical grinding, chemical etching, shaving, peeling, any combination thereof, etc.) the second electronic component 22 (or multiple thereof) and / or the conductive pillar 25 (or multiple thereof). Figure 2H In the exemplary embodiment shown, block 180 includes performing thinning in a manner that results in coplanar top surfaces of the second encapsulating material 27, the second electronic component 22, and / or the conductive pillars 25. Thus, at least the respective top surfaces (and / or at least the upper portions of the lateral side surfaces) of the second electronic component 22 and the conductive pillars 25 are exposed from (or at) the top surface of the second encapsulating material 27. It should be noted that while the exemplary embodiment shows the top side of the second electronic component 22 exposed from the second encapsulating material 27, such exposure is not required. For example, in various embodiments, a thin layer of the second encapsulating material 27 covering the top side of the second electronic component 22 may remain.

[0101] In various exemplary embodiments, blocks 110-180 (and / or resulting structures) may share any or all features of the generally equivalent blocks (and / or resulting structures) shown in U.S. patent application Ser. No. 14 / 823,689, filed on Aug. 11, 2016, and entitled “Semiconductor Package and Method of Fabrication Thereof,” the entire contents of which are incorporated herein by reference in their entirety for all purposes.

[0102] Next reference Figure 1 and Fig.2I Based on the exemplary structure 200i, the exemplary method 100 may include forming a second signal distribution structure and an interconnect structure at block 190. Block 190 may include performing these operations in any of a variety of ways, not limited to the examples provided herein.

[0103] For example, block 190 may share any or all features with block 150. Fig.2I In the illustrated exemplary embodiment 200i, block 190 includes forming a dielectric layer 63 on the second encapsulation material 27, the conductive pillars 25, and / or the second electronic component 22. The dielectric layer 63 (and its formation) may, for example, share any or all characteristics with any of the dielectric layers (and their formation) discussed herein, including the formation of holes.

[0104] The exemplary dielectric layer 63 is shown having a hole in a central region exposing at least the top end of the conductive pillar 25. Block 190 can, for example, include forming such a hole in any of the various ways, examples provided herein (eg, in the discussion of block 150).

[0105] Block 190 may, for example, include forming interconnect structures 24 on top of conductive pillars 25 (eg, through corresponding holes through dielectric layer 63 ) and / or on portions of dielectric layer 63 (eg, around corresponding holes through dielectric layer 63 ).

[0106] Interconnect structure 24 may include any of a variety of properties. For example, interconnect structure 24 may include conductive balls or bumps (e.g., solder balls or bumps, wafer bumps, solid or copper core solder balls, etc.). For example, in an exemplary embodiment including solder balls or bumps, such balls or bumps may include tin, silver, lead, Sn-Pb, Sn-Pb, etc. 37 -Pb, Sn 95 The interconnect structure 24 may include any conductive material discussed herein (e.g., metal, conductive adhesive, etc.).

[0107] The interconnect structure 24 can be configured in any or a variety of configurations. For example, the interconnect structure 24 can be configured as a ball grid array configuration, a planar grid array configuration, etc. The interconnect structure 24 can be arranged, for example, around the perimeter of the semiconductor package (e.g., surrounding the footprint (or outline) of the second electronic component 22 and / or the first electronic component 23). The interconnect structure 24 can also be arranged, for example, in a row / column matrix array (e.g., at least a portion of the matrix / array is within the footprint (or outline) of the second electronic component 22 and / or the first electronic component 23).

[0108] Block 190 may include forming (or attaching) such an interconnect structure 24 in any of a variety of ways, not limited to the examples provided herein. For example, block 190 may include forming (or attaching) such an interconnect structure 24 through ball dropping, bumping, metal plating, pasting, and reflow, etc. For example, block 190 may include dropping a conductive ball onto the end of the conductive pillar 25 (or the exposed conductor or pad or land of the second signal distribution structure or UBM structure).

[0109] Although not shown, block 190 may also include, for example, forming (or attaching) additional components (e.g., passive components, active components, etc.) laterally between interconnect structures 24. In an exemplary embodiment, such components may have a smaller height than interconnect structures 24. For example, such components may have a smaller height than solder ball conductive interconnect structures 24, a smaller height than a solid core (e.g., copper core, etc.) of solder ball interconnect structures 24, etc. In such an embodiment, when interconnect structures 24 are attached to another substrate or component, interconnect structures 24 may provide spacing to keep these components spaced.

[0110] Next reference Figure 1 and Fig.2I 1, the exemplary method 100 may include singulating the electronic package from a wafer or panel or otherwise connected plurality of electronic packages at block 195. Block 195 may include performing such singulation in any of a variety of ways, not limited to the examples provided herein.

[0111] For example, any or all blocks of the exemplary method 100 may be performed at a wafer or panel level, such as to form multiple semiconductor devices (or packages) simultaneously. The wafer or panel may then be singulated into individual packages, for example. Such singulation may be performed, for example, by any one or more of mechanical cutting (e.g., sawing, cutting, abrasion, snapping, etc.), energy cutting (e.g., laser cutting, plasma cutting, etc.), chemical cutting (e.g., etching, dissolving, etc.), etc. In an exemplary embodiment, such singulation may form coplanar lateral side surfaces of the semiconductor devices (or packages). For example, one or more lateral side surfaces of the first encapsulation material 26, the first signal distribution structure 21, the second encapsulation material 27, and the second signal distribution structure 25 may be coplanar on one or more lateral sides of the singulated semiconductor devices (or packages).

[0112] Figure 3A shows a cross-sectional view of an exemplary semiconductor device 300 according to various aspects of the present disclosure, and Figure 3B A bottom view of an exemplary semiconductor device 300 according to various aspects of the present disclosure is shown. Figure 3A and3B The exemplary semiconductor device 300 shown may be formed by Figure 1 The exemplary method 100 is implemented as follows, for example Figure 2A-2I shown and discussed herein.

[0113] For example, the exemplary semiconductor device 300 (or package) may be used with Fig.2I The resulting semiconductor device 200i shown shares any or all of the characteristics. It should be noted that other method steps may be performed on the exemplary package 300, such as adding or deleting components, etc., without departing from the scope of the present disclosure. It should be noted that the exemplary semiconductor device 300 (or any device discussed herein) may be referred to as a semiconductor package, an electronic device, an electronic package, a device, a package, etc.

[0114] As discussed herein, for example, in the discussion of block 190 of the exemplary method 100, the conductive pillars 25 and / or the interconnect structures 24 coupled thereto may be configured in a variety of ways. Figure 3A and 3B As shown, the conductive pillars 25 and the interconnect structures 24 may be arranged around the perimeter of the footprint (or outline) of the second electronic component 22. For example, in such an exemplary arrangement, locations within the footprint (or outline) of the second electronic component 22 may not have fan-in of the interconnect structures 24. Figure 3A and 3B As shown, there is no interconnect structure 24 directly below the second electronic component 22 .

[0115] However, as discussed herein (eg, in the discussion of block 190 of exemplary method 100), the second signal distribution structure (in Fig.2I and 3A The dielectric layer 63 (shown as having holes filled with conductive material) may include any number of dielectric layers and / or conductive layers. For example, the second signal distribution structure may share any or all characteristics with the signal distribution structure 21 formed at block 150.

[0116] For example, refer to Figure 1 and Figure 4A In the exemplary structure 400a of FIG. 1 , the exemplary method 100 may include forming a second signal distribution structure 31 at block 190. The second signal distribution structure 31 (and / or its formation) may share any or all characteristics with the first signal distribution structure 21 (and / or its formation). The exemplary second signal distribution structure 31 includes, for example, a plurality of dielectric layers and a plurality of conductive layers (e.g., pad or land layers, trace layers, UBM layers, etc.).

[0117] For example, in addition to the dielectric layer 63, the second signal distribution structure 31 may also include a first dielectric layer 31a, a first conductive layer 31b, a second dielectric layer 31c, a second conductive layer 31d, and a UBM structure 31e (or alternatively a pad). For example, the first conductive layer 31b may be connected to the conductive pillar 25 through a hole in the dielectric layer 63. Any number of conductive layers and dielectric layers may then be formed to form the signal distribution structure 31. Such conductive layers (e.g., the first conductive layer 31b, the second conductive layer 31d, etc.) may distribute respective signals from any location on the footprint of the semiconductor device to the conductive pillar 25 and from the conductive pillar 25 to any location on the footprint of the semiconductor device.

[0118] For example, refer to Figure 1 and Figure 4B Referring to the exemplary structure 400 b , the exemplary method 100 may, at block 190 , include forming an interconnect structure 34 attached to the second signal distribution structure 31 (eg, to a pad, land, UBM structure, etc.).

[0119] Figure 5A shows a cross-sectional view of an exemplary semiconductor device 500 according to various aspects of the present disclosure, and Figure 5B A bottom view of an exemplary semiconductor device 500 according to various aspects of the present disclosure is shown. Figure 5A and 5B The exemplary semiconductor device 500 shown may Figure 1 The exemplary method 100 is implemented, for example, Figure 2A-2I and Figures 4A-4B shown and discussed in this article.

[0120] For example, the exemplary semiconductor device 500 (or package) may be used with Figure 4B The resulting semiconductor device 400b is shown as well as Fig.2I The semiconductor device 200i shown shares any or all characteristics. It should be noted that other method steps can be performed on the exemplary package 500, such as adding or deleting components, etc., without departing from the scope of the present disclosure. It should be noted that the exemplary semiconductor device 500 (or any device discussed herein) can be referred to as a semiconductor package, an electronic device, an electronic package, a device, a package, etc.

[0121] As discussed herein, for example, in the discussion of block 190 of the exemplary method 100, the conductive pillars 25 and / or the interconnect structures 24 coupled thereto may be configured in any of a variety of configurations. One such example is Figure 5A and 5BAs shown, the conductive pillars 25 can be arranged around the perimeter of the footprint (or outline) of the second electronic component 22. For example, in such an exemplary configuration, there may be a complete matrix of interconnect structures 24, such as the second signal distribution structure 31, which provides fan-in at locations within the footprint (or outline) of the second electronic component 22. For example, Figure 5B As shown, some interconnect structures 34 are directly below the second electronic component 22, and some of the interconnect structures 34 are not directly below the second electronic component 22. For example, some of the interconnect structures 34 may be directly below the corresponding conductive pillars 25, and some of the interconnect structures 34 may be laterally offset from the corresponding conductive pillars 25.

[0122] In summary, the various aspects disclosed in the present invention provide semiconductor devices and methods for manufacturing semiconductor devices. As non-limiting examples, the various aspects disclosed in the present invention provide semiconductor devices and methods for manufacturing the same including multiple encapsulation layers and multiple signal distribution structures. Although reference has been made to certain aspects and embodiments described above, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt specific situations or materials to the teachings disclosed in the present invention without departing from its scope. Therefore, the purpose of the present invention is not limited to the specific examples disclosed, but the present invention will include all examples that fall within the scope of the appended claims.

Claims

1. A semiconductor device, It is characterized in that include: a first signal distribution structure having a signal distribution structure top side, a signal distribution structure bottom side, and a plurality of signal distribution structure lateral sides, wherein the first signal distribution structure comprises a first dielectric layer at the signal distribution structure top side, a second dielectric layer at the signal distribution structure bottom side, and a first conductive layer between the first dielectric layer and the second dielectric layer; a passive electronic component, wherein the passive electronic component is a capacitor electronic component, a component terminal of the capacitor electronic component being coupled to the first conductive layer through the top side of the signal distribution structure; a first encapsulation material covering at least a portion of the top side of the signal distribution structure and at least a portion of the capacitor electronic assembly; a semiconductor die coupled to the bottom side of the signal distribution structure and located directly below the capacitor electronic component; a plurality of conductive pillars coupled to the first conductive layer through a bottom side of the signal distribution structure and positioned laterally around the semiconductor die; as well as A second encapsulation material covers at least a portion of the bottom side of the signal distribution structure, at least a portion of the semiconductor die, and at least a portion of the conductive pillar.

2. The semiconductor device according to claim 1, It is characterized in that A bottom side of each of the plurality of conductive pillars and a bottom side of the semiconductor die are exposed from the second encapsulation material at a bottom side of the second encapsulation material.

3. The semiconductor device according to claim 2, It is characterized in that The bottom side of each of the plurality of conductive pillars, the bottom side of the semiconductor die, and the bottom side of the second encapsulation material are coplanar.

4. The semiconductor device according to claim 1, It is characterized in that A lower dielectric layer is included on a bottom side of the second encapsulation material, wherein the lower dielectric layer includes a plurality of holes, each hole of the plurality of holes exposing a corresponding conductive pillar of the plurality of conductive pillars through the lower dielectric layer.

5. The semiconductor device according to claim 4, It is characterized in that A plurality of conductive balls are included, wherein each conductive ball of the plurality of conductive balls is electrically connected to a corresponding conductive post of the plurality of conductive posts through a corresponding hole of the plurality of holes.

6. The semiconductor device according to claim 1, It is characterized in that The first encapsulating material covers and contacts a top side of the capacitor electronic component; The first signal distribution structure includes a conductive via, the conductive via vertically passing through the first dielectric layer and the second dielectric layer, such that the first dielectric layer exposes a top side of the conductive via at a top side of the signal distribution structure, and the second dielectric layer exposes a bottom side of the conductive via at a bottom side of the signal distribution structure; an electronic component terminal of the capacitor electronic component is coupled to the top side of the conductive via through the signal distribution structure top side; and The semiconductor die includes a conductive terminal coupled to the bottom side of the conductive via through a bottom side of the signal distribution structure.

7. The semiconductor device according to claim 1, It is characterized in that A second signal distribution structure is included on a bottom side of the second encapsulating material.

8. The semiconductor device according to claim 7, It is characterized in that A plurality of conductive balls are included that are coupled to a bottom side of the second signal distribution structure and positioned directly below the semiconductor die, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive pillar of the plurality of conductive pillars.

9. The semiconductor device according to claim 7, It is characterized in that A signal distribution structure lateral side of the plurality of signal distribution structure lateral sides is coplanar with a corresponding lateral side of the first encapsulating material, a corresponding lateral side of the second encapsulating material, and a corresponding lateral side of the second signal distribution structure.

10. A semiconductor device, It is characterized in that include: a first signal distribution structure having a first signal distribution structure top side, a first signal distribution structure bottom side, a plurality of first signal distribution structure lateral sides extending between the first signal distribution structure top side and the first signal distribution structure bottom side, and conductive vias vertically passing through the first signal distribution structure such that the first signal distribution structure exposes a top side of each conductive via at the first signal distribution structure top side and a bottom side of each conductive via at the first signal distribution structure bottom side; a first electronic component and a second electronic component, wherein component terminals of the first electronic component and component terminals of the second electronic component are respectively coupled to the top sides of respective conductive vias through the top side of the first signal distribution structure; a first encapsulation material covering at least a portion of a top side of the first signal distribution structure and at least a portion of the first electronic component; a semiconductor die coupled to a bottom side of the first signal distribution structure and located below the first electronic component and the second electronic component such that a footprint of the first electronic component and a footprint of the second electronic component are completely within the footprint of the semiconductor die; a conductive column coupled to the bottom side of the first signal distribution structure; a second encapsulation material covering at least a portion of a bottom side of the first signal distribution structure, at least a portion of the semiconductor die, and at least a portion of the conductive pillar; as well as A second signal distribution structure has a second signal distribution structure top side, a second signal distribution structure bottom side, and a plurality of second signal distribution structure lateral sides extending between the second signal distribution structure top side and the second signal distribution structure bottom side.

11. The semiconductor device according to claim 10, It is characterized in that A bottom side of each of the conductive pillars and a bottom side of the semiconductor die are exposed from the second encapsulation material at a bottom side of the second encapsulation material.

12. The semiconductor device according to claim 11, It is characterized in that The bottom side of each of the conductive pillars, the bottom side of the semiconductor die, and the bottom side of the second encapsulation material are coplanar.

13. The semiconductor device according to claim 10, It is characterized in that A top side of the first electronic component and a top side of the second electronic component are covered by the first encapsulation material, and a bottom side of the semiconductor die is exposed from the second encapsulation material.

14. The semiconductor device according to claim 10, It is characterized in that A plurality of conductive balls are included that are coupled to a bottom side of the second signal distribution structure and positioned directly below the semiconductor die, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive pillar of the conductive pillars.

15. The semiconductor device according to claim 14, It is characterized in that A second plurality of conductive balls is included that are coupled to a bottom side of the second signal distribution structure and positioned laterally outside the footprint of the semiconductor die, and wherein the second signal distribution structure electrically connects each conductive ball of the second plurality of conductive balls to a corresponding conductive pillar of the conductive pillars.

16. The semiconductor device according to claim 10, Features: One of the plurality of first signal distribution structure lateral sides is coplanar with a corresponding lateral side of the first encapsulating material, a corresponding lateral side of the second encapsulating material, and a corresponding one of the plurality of second signal distribution structure lateral sides; and The first electronic component is a capacitor electronic component.

17. The semiconductor device according to claim 10, Features: Each of the first signal distribution structure and the second signal distribution structure comprises a plurality of conductive layers and a plurality of dielectric layers; The conductive vias pass through the plurality of dielectric layers such that a top side of each conductive via is exposed at a top side of the first signal distribution structure and a bottom side of each conductive via is exposed at a bottom side of the first signal distribution structure; The first electronic component includes a conductive terminal coupled to a top side of a first conductive via of the conductive vias; and The semiconductor die includes a conductive terminal coupled to a bottom side of the first conductive via.

18. A method of manufacturing a semiconductor device, It is characterized in that The method comprises: providing a first signal distribution structure having a signal distribution structure top side, a signal distribution structure bottom side, and a plurality of signal distribution structure lateral sides, wherein the first signal distribution structure comprises a first dielectric layer at the signal distribution structure top side, a second dielectric layer at the signal distribution structure bottom side, and a first conductive layer between the first dielectric layer and the second dielectric layer; providing a passive electronic component, wherein the passive electronic component is a capacitor electronic component, a component terminal of the capacitor electronic component being coupled to the first conductive layer through a top side of the signal distribution structure; providing a first encapsulating material covering at least a portion of a top side of the signal distribution structure and at least a portion of the capacitor electronics; providing a semiconductor die coupled to a bottom side of the signal distribution structure and positioned directly below the capacitor electronics component such that a footprint of the capacitor electronics component is completely within the footprint of the semiconductor die; providing a plurality of conductive pillars coupled to the first conductive layer through the bottom side of the signal distribution structure and positioned laterally around the semiconductor die; and A second encapsulation material is provided covering at least a portion of the bottom side of the signal distribution structure, at least a portion of the semiconductor die, and at least a portion of the plurality of conductive pillars.

19. The method according to claim 18, It is characterized in that include: providing a lower dielectric layer on a bottom side of the second encapsulation material, wherein the lower dielectric layer comprises a plurality of holes, each hole of the plurality of holes penetrating through the lower dielectric layer to expose a corresponding conductive pillar of the plurality of conductive pillars; as well as A plurality of conductive balls are provided, wherein each conductive ball of the plurality of conductive balls is electrically connected to a corresponding conductive post of the plurality of conductive posts through a corresponding hole of the plurality of holes.

20. The method according to claim 18, It is characterized in that include: providing a second signal distribution structure on a bottom side of the second encapsulating material; as well as A plurality of conductive balls coupled to a bottom side of the second signal distribution structure and positioned directly below the semiconductor die are provided, and wherein the second signal distribution structure electrically connects each of the plurality of conductive balls to a corresponding conductive pillar of the plurality of conductive pillars.

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