Semiconductor device, electronic circuit including the same, and method for forming semiconductor device

Abstract

The present application relates to a semiconductor device, an electronic circuit including the same, and a semiconductor device forming method. A semiconductor device includes: a plurality of first conductive lines formed in a first layer and indicating a fixed potential; and an inductor formed in a second layer stacked on the first layer, and in a plan view, a wiring width of a first conductive line of the plurality of first conductive lines located within a range of a formation region of the inductor is formed to be narrower than a wiring width of a first conductive line located outside the range of the formation region of the inductor.

Description

Technical Field

[0001] This invention relates to a semiconductor device, an electronic circuit including the semiconductor device, and a method for forming the semiconductor device. More specifically, this invention relates to, for example, a semiconductor device suitable for suppressing the characteristic degradation of an inductor without increasing circuit size, an electronic circuit including the semiconductor device, and a method for forming the semiconductor device. Background Technology

[0002] As digital circuits become increasingly faster, there is a need for amplifier circuits that amplify digital signals by using inductors as loads to perform matching, thereby increasing the gain of high-frequency input signals.

[0003] When an inductor is formed on a semiconductor substrate along with electronic circuitry, the magnetic flux generated by the inductor induces a back electromotive force (EMF) current in the conductors through which a fixed potential, such as the power supply voltage or ground voltage, propagates. There is a problem where the inductor is affected by the magnetic flux generated by this back EMF current and therefore malfunctions.

[0004] A solution to this problem is disclosed in Japanese Unexamined Patent Application Publication No. 2011-199225. The semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2011-199225 includes a shielding conductor (shielding) between the inductor element and the wire to prevent the magnetic flux generated by the back electromotive force current on the wire from degrading the characteristics of the inductor. Summary of the Invention

[0005] However, the configuration according to Japanese Unexamined Patent Application Publication No. 2011-199225 requires the inclusion of additional shielding, thus resulting in an increased circuit size. Other problems of the related art and the novel features of the present invention will become apparent from the description and drawings.

[0006] According to one embodiment, a semiconductor device includes: a plurality of first wires formed in a first layer and configured to indicate a fixed potential; and an inductor formed in a second layer stacked on the first layer, wherein, in a plan view, the wiring width of the first wire located within the formation region of the inductor is formed to be narrower than the wiring width of the first wire located outside the formation region of the inductor.

[0007] According to another embodiment, a semiconductor device includes: a plurality of first conductors formed in a first layer; a plurality of second conductors formed in a second layer stacked on the first layer that intersect the plurality of first conductors; a plurality of first vias formed at the intersections of the plurality of first conductors and the plurality of second conductors; and an inductor formed in a third layer stacked on the first and second layers, wherein, in a plan view, the plurality of first vias are arranged such that the length of the loop with minimum length in a plurality of current path loops formed by the plurality of first conductors, the plurality of second conductors and the plurality of first vias is longer than a predetermined length.

[0008] According to yet another embodiment, a method for forming a semiconductor device includes: forming a plurality of first wires configured to indicate a fixed potential in a first layer; and forming an inductor in a second layer stacked on the first layer, wherein, in the formation of the plurality of first wires, in a plan view, the wiring width of the first wires located within the formation region of the inductor is narrowed compared to the wiring width of the first wires located outside the formation region of the inductor.

[0009] One embodiment may provide a semiconductor device that suppresses the degradation of inductor characteristics without increasing circuit size, an electronic circuit including the semiconductor device, and a method for forming the semiconductor device. Attached Figure Description

[0010] The above and other aspects, advantages and features will become more apparent from the following description of certain embodiments, taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a schematic plan view illustrating an example of the layout configuration of a semiconductor device according to the first embodiment;

[0012] Figure 2 Is Figure 1 A schematic cross-sectional view of a semiconductor device shown in the figure;

[0013] Figure 3 This is a schematic plan view illustrating an example of the layout configuration of a semiconductor device with a protective ring.

[0014] Figure 4 Is Figure 3 A schematic cross-sectional view of a semiconductor device shown in the figure;

[0015] Figure 5 This is a diagram used to explain the effects of the semiconductor device according to the first embodiment;

[0016] Figure 6 This is a schematic plan view of an inductor of another shape.

[0017] Figure 7 This is a schematic plan view of an inductor of another shape.

[0018] Figure 8 This is a schematic plan view of an inductor of another shape.

[0019] Figure 9 It is a graphical application. Figure 1 The circuit diagram shown in the figure illustrates an example configuration of an amplifier circuit with an inductor structure for a semiconductor device.

[0020] Figure 10 It is a graphical application. Figure 1 The diagram shows a circuit diagram illustrating an example configuration of an oscillator in an inductor structure of a semiconductor device, including an LC tank.

[0021] Figure 11 It is a graphical application. Figure 1 The diagram shows an example configuration of an amplifier circuit including a matching circuit for an inductor structure of a semiconductor device.

[0022] Figure 12 This is a circuit diagram illustrating a specific configuration example of the matching circuit;

[0023] Figure 13 This is a circuit diagram illustrating another specific configuration example of the matching circuit;

[0024] Figure 14 It is a graphical application. Figure 1 The circuit diagram shown in the figure illustrates an example configuration of a balun in the inductor structure of a semiconductor device.

[0025] Figure 15 This is a graph illustrating the relationship between the frequency characteristics and gain of an amplifier circuit before and after the application of an inductor.

[0026] Figure 16 It is a diagram. Figure 1 A schematic plan view of a modified example 1 of the semiconductor device shown in the figure;

[0027] Figure 17 It is a diagram. Figure 1 A schematic plan view of a modified example 2 of the semiconductor device shown in the figure;

[0028] Figure 18 Illustration Figure 1 A schematic plan view of a modified example 3 of the semiconductor device shown in the figure;

[0029] Figure 19 Illustration Figure 1 A schematic plan view of a modified example 4 of the semiconductor device shown in the figure;

[0030] Figure 20 Illustration Figure 1A schematic plan view of a modified example 5 of the semiconductor device shown in the figure;

[0031] Figure 21 This is a schematic plan view illustrating an example layout configuration of a semiconductor device according to a second embodiment; and

[0032] Figure 22 It is a diagram. Figure 21 A schematic plan view of a modified example of the semiconductor device shown in the figure. Detailed Implementation

[0033] Embodiments will now be described with reference to the accompanying drawings. In this regard, the drawings are simplified; however, the technical scope of these embodiments should not be narrowly interpreted based on the description in these drawings. Furthermore, identical parts will be assigned the same reference numerals, and overlapping descriptions will be omitted.

[0034] For ease of description, the following embodiments will be divided into multiple parts or multiple embodiments as necessary, but unless otherwise specified, they are not unrelated to each other. One embodiment is related to some or all of the other embodiments as a modification example, application example, detailed description, or supplementary description. In addition, in the following embodiments, unless specifically specified or substantially obviously limited to a particular quantity, the number (number, value, quantity, range) of components mentioned is not limited to a particular quantity and may be a specific number or more.

[0035] Furthermore, in the following embodiments, a component (including operating steps) is not necessarily indispensable unless specifically specified or substantially obvious. Similarly, in the following embodiments, the shape and positional relationships of the components mentioned include substantially approximate or similar shapes unless specifically specified and substantially not obvious. This also applies to the numbers (including numbers, numerical values, quantities, and ranges) mentioned above.

[0036] <First Embodiment>

[0037] The semiconductor device 1 according to the first embodiment will now be described.

[0038] (Layout configuration of semiconductor device 1)

[0039] Figure 1 This is a schematic plan view illustrating an example layout configuration of the semiconductor device 1 according to the first embodiment. For ease of description, Figure 1 The example only illustrates the structure of the second metal layer M2, the third metal layer M3, and the fourth metal layer M4.

[0040] like Figure 1As shown, the second metal layer M2 is formed such that a plurality of conductors W2 extend in one direction (the y-axis direction in this embodiment). For example, a plurality of these conductors W2 are formed in a slit shape throughout the second metal layer M2. Figure 1 The diagram illustrates conductors W2_1 to W2_5, which are part of a plurality of conductors W2. Furthermore, a fixed potential propagates through the plurality of conductors W2. An example of this embodiment, in which the power supply voltage VDD propagates through the plurality of conductors W2, will now be described.

[0041] Inductor L1 is formed in a third metal layer M3 and a fourth metal layer M4 stacked on a second metal layer M2. Inductor L1 is mainly formed in a spiral shape in the fourth metal layer M4, and the cross portion L1a is formed only in the third metal layer M3.

[0042] (Schematic cross-sectional view of semiconductor device 1)

[0043] Figure 2 This is a schematic cross-sectional view of semiconductor device 1. Figure 2 The schematic cross-section diagram shows Figure 1 Section A-A' in the middle.

[0044] like Figure 2 As shown, in semiconductor device 1, P-wells and N-wells are formed on the surface of silicon substrate 101, and a diffusion layer, a gate oxide film, and polysilicon are formed thereon to form a plurality of MOS transistors constituting internal circuit 102. In this respect, the plurality of MOS transistors include, for example, MOS transistors Tr1 and Tr2 used in amplifier circuit 11 described below.

[0045] Above the layer forming the internal circuit 102, a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 are stacked in sequence, wherein a silicon oxide film 103 is inserted between the metal layers.

[0046] In the first metal layer M1, multiple wires W1 are arranged to connect multiple MOS transistors. In the second metal layer M2, multiple wires W2 are arranged to transmit a power supply voltage VDD, which is a fixed potential.

[0047] An inductor L1 is formed in the third metal layer M3 and the fourth metal layer M4. The inductor L1 is mainly formed in a spiral shape in the fourth metal layer M4, and the cross portion L1a is formed only in the third metal layer M3.

[0048] A silicon nitride film 104 is formed on the surface of the fourth metal layer M4, and a polyimide 105 is further formed thereon.

[0049] Refer again Figure 1 , continue the description.

[0050] Furthermore, an inductor forming region LA1 is defined for inductor L1. In a plan view, the inductor forming region LA1 includes at least the area surrounded by the outer periphery of inductor L1.

[0051] In addition, when the guard ring is arranged in the same layer as the inductor L1 forming layer, in the plan view, the inductor forming area LA1 is the area surrounded by the guard ring.

[0052] Figure 3 This is a schematic plan view illustrating an example layout configuration of a semiconductor device 1z with a protective ring provided. Figure 4 This is a schematic cross-sectional view of a semiconductor device 1z with a guard ring. The guard ring GR1 functions to prevent magnetic flux generated from the inductor L1 from leaking to the outside of the area surrounded by the guard ring GR1. More specifically, as Figure 3 As shown in the plan view, the guard ring GR1 is formed to surround the outer periphery of the inductor L1. Furthermore, as... Figure 4 As shown, the guard ring GR1 is formed in the third metal layer M3 and the fourth metal layer M4 that constitute the inductor L1. In this respect, the guard ring GR1 may be formed in only one of the third metal layer M3 and the fourth metal layer M4.

[0053] Furthermore, it is preferable to determine the inductor forming region LA1 based on the inner diameter ID of the inductor L1 in the plan view. For example, by decreasing the inner diameter ID while keeping its outer diameter constant, the magnetic flux generated by the inductor L1 increases, thus making the inductor forming region LA1 larger. Conversely, by increasing the inner diameter ID while keeping the outer diameter constant, the magnetic flux generated by the inductor L1 decreases, thus making the inductor forming region LA1 smaller.

[0054] Furthermore, in the plan view, the wiring width (length in the x-axis direction) of the conductor W2 located within the inductor forming region LA1 and formed in the fixed potential wiring layer (second metal layer M2) is formed to be narrower than the wiring width of the conductor W2 located outside the inductor forming region LA1 and formed in the fixed potential wiring layer. In this example, the wiring width of conductors W2_2, W2_3, and W2_4 located within the inductor forming region LA1 is formed to be narrower than the wiring width of conductors located outside the inductor forming region LA1.

[0055] Therefore, the influence of the magnetic flux from inductor L1 can be prevented from generating a back electromotive force current in conductor W2. Furthermore, by preventing the generation of a back electromotive force current, the degradation of the characteristics of inductor L1 caused by the influence of the magnetic flux generated by the back electromotive force current can be prevented.

[0056] In this regard, in the plan view, the percentage of each unit area occupied by the conductor W2 within the inductor forming region LA1 is preferably the same as the percentage occupied outside that region. Therefore, the resistivity of the conductor W2 located inside the inductor forming region LA1 can be made the same as that of those located outside that region. In this embodiment, the three conductors W2_2, W2_3, and W2_4 arranged outside the inductor forming region LA1 in the plan view are divided into seven conductors within the inductor forming region LA1.

[0057] Furthermore, in the plan view, in the fixed-potential wiring layer (second metal layer M2) located at the boundary line between the inductor forming region LA1 and the non-forming region, multiple conductors W2 are formed to be short-circuited with each other. In this embodiment, in the plan view, in the fixed-potential wiring layer located at the boundary line between the inductor forming region LA1 and the non-forming region, conductors W2a and W2b are short-circuited between conductors W2_2 and W2_3, and conductors W2c and W2d are short-circuited between conductors W2_3 and W2_4. Therefore, the potential of the multiple conductors W2 can be adjusted to the same potential near the boundary line.

[0058] (Effect of semiconductor device 1)

[0059] Figure 5 This is a diagram used to explain the effect of semiconductor device 1. Furthermore, Figure 5 The diagram illustrates a layout configuration of multiple conductors W2 in the inductor forming region LA1 without narrowing in a plan view (left view), and a layout configuration of multiple conductors W2 in the inductor forming region LA1 with narrowing in a plan view (right view).

[0060] First, the case where the conductor W2, located in the inductor forming region LA1 in the planar diagram, is not narrowed will be described. In this case, the magnetic flux generated by the inductor L1 produces a back electromotive force (EMF) current in the conductor W2, which propagates to it from a fixed potential. Eddy currents formed on the conductor W2 by the back EMF current are formed to flow in the direction that counteracts the magnetic flux of the inductor L1. In this respect, the eddy currents have a current path with a large inner diameter corresponding to the wide wiring width of the conductor W2, thus producing a large magnetic flux. The inductor L1 is affected by the magnetic flux generated by the back EMF current and cannot function properly (in other words, the characteristics of the inductor L1 deteriorate).

[0061] Next, the case where the conductor W2 located in the inductor forming region LA1 in the planar diagram is narrowed will be described. In this case, the magnetic flux generated by the inductor L1 produces a back electromotive force (EMF) current in the conductor W2, which propagates to it with a fixed potential. The eddy current formed by the back EMF current on the conductor W2 is formed to flow in the direction that counteracts the magnetic flux of the inductor L1. In this respect, the eddy current has a current path with a small inner diameter corresponding to the wiring width of the conductor W2, and therefore produces a small magnetic flux compared to the case where the conductor W2 is not narrowed. The inductor L1 is almost unaffected by the magnetic flux generated by the back EMF current, and therefore can operate normally (in other words, characteristic degradation can be prevented).

[0062] Therefore, in the planar diagram, narrowing the wire W2 located in the inductor forming region LA1 compared to the wire W2 located outside the inductor forming region LA1 can prevent the characteristics of the inductor L1 from deteriorating without increasing the circuit size.

[0063] Therefore, in the plan view, by narrowing the conductors W2 located in the inductor formation region LA1 compared to the conductors W2 located outside the inductor formation region LA1, the semiconductor device 1 according to this embodiment can prevent the characteristics of the inductor L1 from deteriorating. Furthermore, in this case, it is not necessary to arrange a shield between the inductor L1 and the conductors W2, thereby preventing an increase in circuit size.

[0064] This embodiment is described using the case where the power supply voltage VDD propagates to multiple conductors W2 as an example, but it is not limited thereto. For example, the ground voltage GND can propagate to the multiple conductors W2 as a fixed potential. Alternatively, a predetermined signal indicating a fixed potential can propagate to the multiple conductors W2.

[0065] Furthermore, this embodiment has been described using the case where only a plurality of conductors W2 are arranged in the second metal layer M2 as an example, but it is not limited thereto. For example, in the second metal layer M2, in addition to the plurality of conductors W2 to which the power supply voltage VDD propagates, a plurality of conductors W3 to which the ground voltage GND propagates may also be arranged. In this case, the plurality of conductors W3 located within the inductor forming region LA1 in the plan view are narrower compared to the plurality of conductors W3 located outside the inductor forming region LA1.

[0066] Furthermore, this embodiment has been described as an example of arranging multiple wires W2 with a fixed potential propagating thereto only in the second metal layer M2, but it is not limited thereto. For example, multiple wires W4 with a fixed potential propagating thereto may also be arranged in an additionally formed metal layer (not shown). In this case, in the plan view, the multiple wires W4 located within the inductor forming region LA1 are narrower compared to the multiple wires W4 located outside the inductor forming region LA1.

[0067] Furthermore, this embodiment has been described using the case where the inductor L1 and the fixed potential wire W2 are formed on the same semiconductor chip as an example, but it is not limited thereto. For example, there may be a flip-chip configuration in which the inductor L1 and the fixed potential wire W2 are formed on different semiconductor chips and these semiconductor chips are arranged facing each other.

[0068] Furthermore, this embodiment has been described using the case where the inductor L1 is formed in a spiral shape in a planar diagram as an example, but it is not limited thereto. The inductor L1 may have the following characteristics: Figure 6 The symmetry type shown in the figure may be in Figure 7 or Figure 8 The diagram shows the horseshoe type.

[0069] (Structure and application example of semiconductor device 1)

[0070] Figure 9 This is a circuit diagram illustrating an example configuration of an amplifier circuit 11 that utilizes an inductor structure based on a semiconductor device 1.

[0071] like Figure 9 As shown, amplifier circuit 11 is a differential amplifier circuit that amplifies differential input signals IN1 and IN2 and outputs differential output signals OUT1 and OUT2, and includes N-channel MOS transistors Tr1 and Tr2, resistors R1 and R2, capacitive elements C1 and C2, constant current source I1, and inductors L1 and L2.

[0072] A MOS transistor Tr1 is positioned between nodes N1 and N3, which are connected to the output terminal OUT1, and is turned on and off based on a differential input signal IN1. A resistor R1 and an inductor L1 are connected in series between node 1 and the power supply voltage terminal VDD. A capacitive element C1 is positioned between node N1 and the ground voltage terminal GND.

[0073] MOS transistor Tr2 is positioned between nodes N2 and N3, which are connected to the output terminal OUT2, and is turned on and off based on another differential input signal IN2. Resistor R2 and inductor L2 are connected in series between node N2 and the power supply voltage terminal VDD. Capacitive element C2 is positioned between node N2 and the ground voltage terminal GND.

[0074] The constant current source I1 is positioned between node N3 and the ground voltage terminal GND.

[0075] When one differential input signal IN1 in amplifier circuit 11 is greater than the other differential input signal IN2, the current flowing in transistor Tr1 is greater than the current flowing in transistor Tr2. Therefore, one differential output signal OUT1 becomes greater than the other differential output signal OUT2. Conversely, when one differential input signal IN1 is less than the other differential input signal IN2, the current flowing in transistor Tr1 is less than the current flowing in transistor Tr2. Therefore, one differential output signal OUT1 is less than the other differential output signal OUT2.

[0076] Figure 15 This is a graph illustrating the relationship between the frequency characteristics and gain of amplifier circuit 11 before and after the application of inductors L1 and L2. In this respect, in Figure 15 In the diagram, the horizontal axis represents the frequency characteristics of the differential input signals IN1 and IN2, and the vertical axis represents the gain of amplifier circuit 11.

[0077] Figure 15 The diagram illustrates the improved characteristics of amplifier circuit 11 with inductors L1 and L2 compared to the amplifier circuit before the application of inductors L1 and L2. Therefore, amplifier circuit 11 with inductors L1 and L2 can amplify high-frequency differential input signals with high gain.

[0078] (Other application examples)

[0079] Figure 10 This is a circuit diagram illustrating an example configuration of an oscillator 12 with an LC tank incorporating an inductor structure using a semiconductor device 1. The oscillator 12 includes transistors MP1, MP2, MN1 and MN2, variable capacitors C21 and C22, an inductor L1, and a constant current source I2.

[0080] Transistor MP1 includes a source connected to the power supply voltage terminal VDD, a drain connected to the output terminal OUT, and a gate connected to the output terminal OUTB. Transistor MN1 includes a source connected to the ground voltage terminal GND via a constant current source I2, a drain connected to the output terminal OUT, and a gate connected to the output terminal OUTB.

[0081] Transistor MP2 includes a source connected to the power supply voltage terminal VDD, a drain connected to the output terminal OUTB, and a gate connected to the output terminal OUT. Transistor MN2 includes a source connected to the ground voltage terminal GND via a constant current source I2, a drain connected to the output terminal OUTB, and a gate connected to the output terminal OUT.

[0082] That is, the first inverter composed of transistors MP1 and MN1 and the second inverter composed of transistors MP2 and MN2 are connected in a loop.

[0083] Inductor L1 is positioned between output terminals OUT and OUTB. Variable capacitor C21 is positioned between output terminal OUT and a common terminal providing the reference voltage Vref. Variable capacitor C22 is positioned between output terminal OUTB and a common terminal providing the reference voltage Vref.

[0084] Oscillator 12 outputs an oscillation signal (and its inverted signal) from output terminal OUT (and output terminal OUTB) at a resonant frequency determined by the inductance of inductor L1 and the capacitance of varactor diode.

[0085] Figure 11 This is a diagram illustrating an example configuration of an amplifier circuit 13, including matching circuitry, that utilizes an inductor structure based on semiconductor device 1. Amplifier circuit 13 includes a resistor element R3, an inductor L3, a transistor MN3, a constant current source I3, and matching circuits 131 and 132.

[0086] Resistor R3, inductor L3, transistor MN3, and constant current source I3 are connected in series between the power supply voltage terminal VDD and the ground voltage terminal GND. Furthermore, in amplifier circuit 13, the input signal IN is provided to the gate of transistor MN3, and the output signal OUT is output from the drain of transistor MN3.

[0087] In this respect, matching circuit 131 matches the output impedance of the pre-amplifier circuit that outputs the input signal IN with the input impedance of matching circuit 13. Therefore, amplifier circuit 13 can receive the input signal IN without incurring losses. Furthermore, matching circuit 132 matches the output impedance of amplifier circuit 13 with the input impedance of the subsequent stage circuit to which the output signal OUT is provided. Therefore, amplifier circuit 13 can transmit the output signal OUT without incurring losses.

[0088] Figure 12 This is a circuit diagram illustrating a specific configuration example of matching circuit 131a. Matching circuit 131a includes an inductor L31 employing an inductor structure of semiconductor device 1 and a capacitive element C31. The capacitive element C31 is arranged between input terminal T1 and output terminal T2. The inductor L31 is arranged between output terminal T2 and ground voltage terminal GND. Matching circuit 132 may also employ the same circuit configuration as matching circuit 131a.

[0089] Figure 13This is a circuit diagram illustrating another specific configuration example of matching circuit 131b. Matching circuit 131b includes an inductor L32 having an inductor structure of semiconductor device 1 and a capacitive element C32. Inductor L32 is arranged between input terminal T1 and output terminal T2. Capacitive element C32 is arranged between input terminal T1 and ground voltage terminal GND. Matching circuit 132 can also adopt the same circuit configuration as matching circuit 132b.

[0090] Figure 14 This is a circuit diagram illustrating an example configuration of a balun 14 that incorporates the inductor structure of semiconductor device 1. The balun 14 includes inductors L41 and L42 with the inductor structure of semiconductor device 1. The balun 14 converts a single-ended input signal IN into magnetic flux using inductor L41, and converts the magnetic flux into differential signals OUT and OUTB using inductor L42.

[0091] In addition to the above, the circuit using the inductor can adopt the inductor structure of semiconductor device 1.

[0092] Next, some examples of modifications to semiconductor device 1 will be described.

[0093] (Example 1 of the modification of semiconductor device 1)

[0094] Figure 16 This is a schematic plan view of a modified example 1 of semiconductor device 1, which is shown as semiconductor device 1a. According to... Figure 1 In the semiconductor device 1 shown, in a fixed potential wiring layer (second metal layer M2) located at the boundary line between the inductor formation region LA1 and the non-formation region in the plan view, a plurality of wires W2 are formed to be short-circuited to each other. In contrast, according to... Figure 16 In the semiconductor device 1a shown, in a fixed potential wiring layer located at the boundary between the inductor forming region LA1 and the non-forming region in the plan view, a plurality of wirings W2 are formed so as not to be short-circuited to each other.

[0095] The other components of semiconductor device 1a are the same as those in semiconductor device 1, and therefore will not be described again.

[0096] Semiconductor device 1a can also provide substantially the same effect as semiconductor device 1. Furthermore, according to semiconductor device 1a, in a fixed-potential wiring layer located at the boundary line between the inductor forming region LA1 and the non-forming region in a planar view, multiple wirings W2 are formed so as not to short-circuit each other. Therefore, different fixed potentials can be propagated to adjacent wires W2. For example, the power supply voltage VDD can be propagated to wires W2_1, W2_3, and W2_5, and the ground voltage GND can be propagated to wires W2_2 and W2_4.

[0097] (Example 2 of the modification of semiconductor device 1)

[0098] Figure 17 This is a schematic plan view of a modified example 2 of semiconductor device 1, which is shown as semiconductor device 1b.

[0099] like Figure 17 As shown, in semiconductor device 1b, an inductor L1 with an inner diameter ID larger than a predetermined inner diameter is formed in the plan view. In this case, the magnetic flux in the central region of inductor L1 is small. Therefore, it is not necessary to narrow the wire W2 located in the central region of inductor L1 in the plan view. Therefore, in semiconductor device 1b, the wire W2 located in the central region of the inductor forming region LA1 in the plan view ( Figure 17 The wiring width of the conductor W2e is formed to be wider than the wiring width of the conductor W2 located in the rest of the inductor forming region LA1.

[0100] The other components of semiconductor device 1b are the same as those of semiconductor device 1a, and therefore will not be described further.

[0101] Semiconductor device 1b can also provide essentially the same effect as semiconductor device 1a. Furthermore, by widening the wiring width of the conductor W2e located in the central region of the inductor forming region LA1 in the plan view, semiconductor device 1b can reduce the resistance value of conductor W2 compared to the case where the wiring width is not widened.

[0102] (Example 3 of the modification of semiconductor device 1)

[0103] Figure 18 This is a schematic plan view of a modified example 3 of semiconductor device 1, which is shown as semiconductor device 1c.

[0104] like Figure 18 As shown, in semiconductor device 1c, an inductor L1 is formed in a planar view with an inner diameter ID smaller than a predetermined inner diameter. In this case, the magnetic flux in the central region of inductor L1 is large. Therefore, in order to avoid the magnetic flux, a space region W2f is formed in the fixed potential wiring layer located in the central region of inductor L1 in the planar view instead of arranging wires W2.

[0105] The other components of semiconductor device 1c are the same as those of semiconductor device 1a, and therefore will not be described further.

[0106] Semiconductor device 1c can also provide substantially the same effect as semiconductor device 1a. Furthermore, in semiconductor device 1c, the space region W2f is formed in a fixed potential wiring layer located in the central region of the inductor forming region LA1 in the planar view. Therefore, it is possible to prevent the strong magnetic flux generated in the central region of the inductor L1 from generating a large back electromotive force current in the conductor W2.

[0107] (Example 4 of the modification of semiconductor device 1)

[0108] Figure 19 This is a schematic plan view of a modified example 4 of semiconductor device 1, which is shown as semiconductor device 1d.

[0109] When wire W2 is placed in a fixed potential wiring layer that overlaps with inductor L1 in the plan view, wire W2 receives a large magnetic flux from inductor L1. Therefore, to avoid magnetic flux, a space region is formed in the fixed potential wiring layer that overlaps with inductor L1 in the plan view instead of placing wiring W2.

[0110] exist Figure 19 In the example, spatial regions W2g and W2h are formed in a fixed potential wiring layer, which overlaps with an inductor portion extending in the same direction as the extension direction (y-axis direction) of the conductor W2 in the fixed potential wiring layer. The fixed potential wiring layer overlaps with the inductor L1 in the plan view.

[0111] The other components of semiconductor device 1d are the same as those of semiconductor device 1, and therefore will not be described further.

[0112] Semiconductor device 1d can also provide essentially the same effect as semiconductor device 1a. Furthermore, in semiconductor device 1d, spatial regions W2g and W2h are formed in a fixed potential wiring layer that overlaps with inductor L1 in the planar diagram. Therefore, it is possible to prevent the strong magnetic flux generated near inductor L1 from producing a large back electromotive force current in conductor W2.

[0113] (Example 5 of the modification of semiconductor device 1)

[0114] Figure 20 This is a schematic plan view of a modified example 5 of semiconductor device 1, which is shown as semiconductor device 1e.

[0115] like Figure 20 As shown in the plan view, the semiconductor device 1e includes a plurality of wirings W2i, W2j, W2k and W2l extending radially from a fixed potential wiring layer located in the central region of the inductor forming region LA1.

[0116] The other components of semiconductor device 1e are the same as those of semiconductor device 1a, and therefore will not be described further.

[0117] Semiconductor device 1e can also provide substantially the same effect as semiconductor device 1a. Furthermore, in the plan view, semiconductor device 1e includes conductors W2i, W2j, W2k, and W21 extending radially from a fixed-potential wiring layer located in the central region of the inductor forming region LA1. Therefore, the resistance value of conductor W2 can be reduced.

[0118] <Second Embodiment>

[0119] Figure 21 This is a schematic plan view illustrating the layout configuration of the semiconductor device 2 according to the second embodiment. In this embodiment, conductors are formed across two layers. More specifically, in the lower layer MD, a plurality of conductors W5 extending in the x-axis direction in a slit shape in the y-axis direction, propagating a fixed potential (e.g., ground voltage GND) thereto. In the upper layer MU, a plurality of conductors W6 extending in the y-axis direction in a slit shape in the x-axis direction, propagating the same level of fixed potential as the plurality of conductors W5. That is, in the plan view, the plurality of conductors W5 formed in the lower layer MD and the plurality of conductors W6 formed in the upper layer MU intersect at right angles.

[0120] In this regard, this embodiment describes the case where a fixed potential, such as ground voltage GND, propagates to conductors W5 and W6, but is not limited thereto. Signals with fluctuating potentials can propagate to conductors W5 and W6.

[0121] In this respect, if vias (or groups of vias of small vias) V1 are arranged at all intersections of multiple conductors W5 and W6, multiple low-resistance current paths are formed by conductors W5 and W6 and vias V1. Therefore, the magnetic flux from inductor L1 easily generates large eddy currents in the fixed potential wiring layer. Consequently, the magnetic flux generated by these large eddy currents is likely to affect inductor L1 and degrade its characteristics.

[0122] Therefore, in this embodiment, via V1 is partially arranged in the inductor forming region LA1 such that the length of the minimum loop LPmin in the current path loop formed by using wires W5 and W6 and via V1 is longer than a predetermined length (e.g., the loop length when via V1 is arranged at all intersections). In this respect, in Figure 21 In the example, multiple vias V1 are distinguished as vias V1a to V1k.

[0123] More specifically, a square region SA1 is defined in the plan view, including the inductor forming region LA1. In this respect, when the inductor forming region LA1 has a square shape, the inductor forming region LA1 can be region SA1.

[0124] Subsequently, multiple vias 1a are arranged at multiple intersections along a diagonal of region SA1. Then, in the same row as the multiple vias 1a along the diagonal, and at multiple intersections of the next two columns in the positive y-axis direction, multiple vias V1b corresponding to the multiple vias 1a are arranged. Furthermore, in the same row as the multiple vias 1b, and at multiple intersections of the next three columns in the positive y-axis direction, multiple vias V1c corresponding to the multiple vias 1b are arranged. Subsequently, within region SA1, the arrangement of vias in the next two columns in the positive y-axis direction and the arrangement of vias in the next three columns in the positive y-axis direction are repeated.

[0125] Furthermore, in the same column as the multiple vias V1a and at multiple intersections in the next three rows in the positive x-axis direction, multiple vias V1g corresponding to the multiple vias V1a are arranged. Furthermore, in the same column as the multiple vias V1g and at multiple intersections in the next two rows in the positive x-axis direction, multiple vias V1h corresponding to the multiple vias V1g are arranged. Subsequently, within region SA1, the arrangement of vias in the next three rows in the positive x-axis direction and the arrangement of vias in the next two rows in the positive x-axis direction are repeated.

[0126] Therefore, in the fixed potential wiring layer located in the inductor forming region LA1 in the planar diagram, the length of the minimum loop LPmin in the current path loop formed by using conductor W5, conductor W6, and via V1 is longer than a predetermined length (e.g., the loop length when via V1 is arranged at all intersections). That is, a high-resistance current path is formed in the fixed potential wiring layer located in the inductor forming region LA1 in the planar diagram. Therefore, the eddy current formed by the magnetic flux from inductor L1 is reduced. As a result, inductor L1 is almost unaffected by the magnetic flux generated by the eddy current, thereby preventing characteristic degradation.

[0127] In this regard, the via V1 arrangement method described in this embodiment is an exemplary method, and it can also be another via V1 arrangement method that can increase the length of the current path loop LPmin. Furthermore, the inductor structure of the semiconductor device 2 can be employed by electronic circuits such as amplifier circuit 11.

[0128] (Example of modification to semiconductor device 2)

[0129] Figure 22 This is a schematic plan view illustrating a modified example of semiconductor device 2 as semiconductor device 2a.

[0130] In semiconductor device 2, one type of fixed potential wire is formed across two layers. In contrast, in semiconductor device 2a, two types of fixed potential wires are formed across two layers.

[0131] More specifically, in the lower layer MD, multiple conductors W5 extending in the x-axis direction and propagating ground voltage GND and power supply voltage VDD are alternately arranged in the y-axis direction. In the upper layer MU, multiple conductors W6 extending in the y-axis direction and propagating ground voltage GND and power supply voltage VDD are alternately arranged in the x-axis direction. That is, in the plan view, the multiple conductors W5 and W7 alternately arranged in the lower layer MD and the multiple conductors W6 and W8 alternately arranged in the upper layer MU intersect at right angles.

[0132] Furthermore, this embodiment has been described using the case of a fixed potential propagating to conductors W5 to W8 as an example, but it is not limited to this. Signals with fluctuating potentials can also propagate to conductors W5 to W8.

[0133] In this respect, via V1 is partially arranged in the inductor forming region LA1 such that the length of the minimum loop LPmin1 in the current path loop formed by using conductors W5, W6, and via V1 is longer than a predetermined length (e.g., the loop length when via V1 is arranged at all intersections of conductors W5 and W6). Similarly, via V2 is partially arranged in the inductor forming region LA1 such that the length of the minimum loop LPmin2 in the current path loop formed by using conductors W7, W8, and via V2 is longer than a predetermined length (e.g., the loop length when via V2 is arranged at all intersections of conductors W7 and W8).

[0134] In this case, firstly, a square region SA1, including the inductor forming region LA1, is also defined in the plan view. In this respect, when the inductor forming region LA1 has a square shape, the inductor forming region LA1 can be region SA1.

[0135] The method for arranging via V1 at the intersection of multiple conductors W5 and W6 is the same as that for semiconductor device 2. Furthermore, the method for arranging via V2 at the intersection of multiple conductors W7 and W8 is the same as that for arranging via V2 at the intersection of multiple conductors W5 and W6.

[0136] Therefore, in the fixed potential wiring layer located in the inductor forming region LA1 in the planar diagram, the length of the minimum loop LPmin1 in the current path loop formed by using conductor W5, conductor W6, and via V1 is longer than a predetermined length (e.g., the loop length when via V1 is arranged at all intersections). That is, a high-resistance current path is formed in the fixed potential wiring layer located in the inductor forming region LA1 in the planar diagram. Therefore, the eddy current formed by the magnetic flux from inductor L1 is small. As a result, inductor L1 is almost unaffected by the magnetic flux generated by the eddy current, thereby preventing characteristic degradation.

[0137] Therefore, in the fixed potential wiring layer located in the inductor forming region LA1 in the planar diagram, the length of the minimum loop LPmin2 in the current path loop formed by using conductor W7, conductor W8, and via V2 is longer than a predetermined length (e.g., the loop length when via V2 is arranged at all intersections). That is, a high-resistance current path is formed in the fixed potential wiring layer located in the inductor forming region LA1 in the planar diagram. Therefore, the eddy current formed by the magnetic flux from inductor L1 is small. As a result, inductor L1 is almost unaffected by the magnetic flux generated by the eddy current, thereby preventing characteristic degradation.

[0138] In this regard, the arrangement of vias V1 and V2 described in this embodiment is exemplary, and can also be another arrangement of vias V1 and V2 that can increase the length of current path loops LPmin1 and LPmin2. Furthermore, the inductor structure of the semiconductor device 2a can be employed by electronic circuits such as amplifier circuit 11.

[0139] As described above, by reducing the wiring width of the fixed potential conductor within the inductor formation region LA1 in the planar diagram and increasing the current path loop, the semiconductor devices 1 and 2 according to the first and second embodiments reduce the eddy currents formed on the fixed potential conductor by the magnetic flux from the inductor L1. Therefore, in the semiconductor devices 1 and 2 according to the first and second embodiments, since the inductor L1 is almost unaffected by the magnetic flux generated by the eddy currents, characteristic degradation can be prevented. Furthermore, in this case, it is not necessary to arrange a shield between the fixed potential conductor and the inductor L1, thereby suppressing the increase in circuit size.

[0140] The invention described above is based on specific embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

[0141] For example, the semiconductor device according to the above embodiments can be configured such that the conductivity type of the semiconductor substrate, the conductivity type of the semiconductor layer, and the conductivity type (p-type or n-type) of the diffusion layer (diffusion region) can be reversed. Therefore, when one of the n-type and p-type conductivity types is the first conductivity type, and the other of the n-type and p-type conductivity types is the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type. Conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0142] Some or all of the embodiments may be described as follows, but are not limited to the following supplementary description.

[0143] (Supplementary Note 1)

[0144] A method for forming a semiconductor device, comprising:

[0145] In the first layer, a plurality of first wires configured to indicate a fixed potential are formed; and

[0146] An inductor is formed in the second layer stacked on top of the first layer, and

[0147] In the formation of multiple first conductors, in a plan view, the wiring width of the first conductor located within the formation area of ​​the inductor is narrowed compared to the wiring width of the first conductor located outside the formation area of ​​the inductor.

[0148] (Supplementary Note 2)

[0149] According to Supplementary Note 1, in the method for forming a semiconductor device, the forming region of the inductor in the plan view includes the region surrounded by the outer peripheral side of the inductor.

[0150] (Supplementary Explanation 3)

[0151] According to Supplementary Note 1, the method for forming a semiconductor device further includes forming a protective ring in the second layer to surround the inductor, and

[0152] In a plan view, the area where the inductor is formed is the area surrounded by a guard ring.

[0153] (Supplementary Note 4)

[0154] The method for forming a semiconductor device according to Supplementary Description 1 further includes forming an inductor in a spiral shape in a planar view, and

[0155] The inductor formation area is determined based on the inductor's inner diameter in the plan view.

[0156] (Supplementary Note 5)

[0157] According to Supplementary Note 1, the method for forming a semiconductor device further includes configuring a plurality of first wires to allow one of a power supply voltage and a ground voltage to propagate thereto.

[0158] (Supplementary Note 6)

[0159] According to Supplementary Note 1, the method for forming a semiconductor device further includes forming a plurality of first conductive lines in a slit shape over the entire first layer.

[0160] (Supplementary Note 7)

[0161] According to Supplementary Note 1, the method for forming a semiconductor device further includes forming a plurality of first wires that are short-circuited in a first layer in a plan view at the boundary line between the forming region and the non-forming region of the inductor.

[0162] (Supplementary Note 8)

[0163] The method for forming a semiconductor device according to Supplementary Note 1 further includes:

[0164] An inductor with an inner diameter larger than a predetermined inner diameter is formed in a spiral shape in a plan view; and

[0165] In the plan view, the wiring width of the first conductor located in the central region of the inductor formation area is widened compared to the wiring width of the first conductor located in the rest of the inductor formation area.

[0166] (Supplementary Note 9)

[0167] The method for forming a semiconductor device according to Supplementary Note 1 further includes:

[0168] An inductor with an inner diameter smaller than a predetermined inner diameter is formed in a spiral shape in a plan view; and

[0169] In the plan view, multiple first conductors with predetermined spatial regions are formed in the first layer located in the central region of the inductor formation area.

[0170] (Supplementary Note 10)

[0171] The method for forming a semiconductor device according to Supplementary Description 1 further includes: further forming a plurality of second conductive lines in a first layer, the plurality of second conductive lines being configured to indicate a fixed potential different from that of a plurality of first conductive lines, and

[0172] In the formation of multiple second conductors, in a plan view, the wiring width of the second conductor located within the formation area of ​​the inductor is narrowed compared to the wiring width of the second conductor located outside the formation area of ​​the inductor.

[0173] (Supplementary Note 11)

[0174] The method for forming a semiconductor device according to Supplementary Note 10 further includes:

[0175] Configure multiple first conductors to allow the transmission of power supply voltage to them; and

[0176] Multiple second conductors are configured to allow ground voltage to propagate to them.

[0177] (Supplementary Note 12)

[0178] According to Supplementary Note 10, the method for forming a semiconductor device further includes arranging a plurality of first wires and a plurality of second wirings alternately in a slit shape throughout the first layer.

[0179] (Supplementary Note 13)

[0180] The method for forming a semiconductor device according to Supplementary Note 10 further includes:

[0181] An inductor with an inner diameter larger than a predetermined inner diameter is formed in a spiral shape in a plan view; and

[0182] In the plan view, the wiring width of the first conductor located in the central region of the inductor formation area is widened compared to the wiring width of the first conductor located in the rest of the inductor formation area; and

[0183] In the plan view, the wiring width of the second conductor located in the central region of the inductor formation area is widened compared to the wiring width of the second conductor located in the rest of the inductor formation area;

[0184] (Supplementary Note 14)

[0185] The method for forming a semiconductor device according to Supplementary Note 10 further includes:

[0186] An inductor with an inner diameter smaller than a predetermined inner diameter is formed in a spiral shape in a plan view;

[0187] A plurality of first conductors having predetermined spatial regions are formed in a first layer located in the central region of the inductor's forming region; and

[0188] Multiple second conductors with predetermined spatial regions are formed in the first layer located in the central region of the inductor's formation area.

[0189] (Supplementary Note 15)

[0190] The method for forming a semiconductor device according to Supplementary Description 1 further includes: further forming a plurality of third wires configured to indicate a fixed potential in a third layer stacked on the first layer; and

[0191] In the formation of multiple third conductors, in a plan view, the wiring width of the third conductor located within the formation area of ​​the inductor is narrowed compared to the wiring width of the third conductor located outside the formation area of ​​the inductor.

[0192] (Supplementary Note 16)

[0193] A method for forming an electronic circuit includes forming an inductor employing the structure of a semiconductor device according to Supplementary Description 1.

[0194] (Supplementary Note 17)

[0195] A method for forming a semiconductor device, comprising:

[0196] Multiple first conductors are formed in the first layer;

[0197] In a second layer stacked on top of the first layer, a plurality of second conductors are formed to intersect with a plurality of first conductors;

[0198] Multiple first vias are formed at the intersections of multiple first conductors and multiple second conductors; and

[0199] An inductor is formed in a third layer stacked on top of the first and second layers, and

[0200] In forming the plurality of first vias, in a plan view, the plurality of first vias are arranged such that the length of the loop with minimum length among the plurality of current path loops formed by the plurality of first conductors, the plurality of second conductors and the plurality of first vias is longer than a predetermined length.

[0201] (Supplementary Note 18)

[0202] The method for forming a semiconductor device according to Supplementary Note 17 includes:

[0203] Further, multiple third conductors are formed in the first layer;

[0204] Further, multiple fourth conductors are formed in the second layer to intersect with multiple third conductors; and

[0205] Furthermore, multiple second vias are formed at the intersections of multiple third and multiple fourth conductors.

[0206] In forming multiple second vias, in a plan view, the multiple second vias are arranged such that the length of the loop with the minimum length in the multiple current path loops formed by the multiple third conductors, the multiple fourth conductors and the multiple second vias is longer than a predetermined length.

[0207] (Supplementary Note 19)

[0208] A method for forming an electronic circuit includes forming an inductor employing the structure of a semiconductor device according to Supplementary Description 17.

[0209] Those skilled in the art can combine the first embodiment and the second embodiment as needed.

[0210] Although the invention has been described with reference to several embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims, and that the invention is not limited to the examples described above.

[0211] Furthermore, the scope of the claims is not limited to the above embodiments.

[0212] Furthermore, it should be noted that the applicant's intent is to cover equivalence of all claim elements, even if amended later during the examination period.

Claims

1. A semiconductor device, comprising: Multiple first conductors are formed in the first layer and configured to indicate a fixed potential; as well as The inductor is formed in a second layer stacked on top of the first layer. In the plan view, the wiring width of the first conductor located within the forming region of the inductor is formed to be narrower than the wiring width of the first conductor located outside the forming region of the inductor. The plurality of first conductors are formed as slits on the entire surface of the first layer.

2. The semiconductor device of claim 1, wherein the forming region of the inductor includes a region surrounded by the outer peripheral side of the inductor in the plan view.

3. The semiconductor device of claim 1, further comprising a protective ring arranged to surround the inductor in the second layer. The forming region of the inductor is the region surrounded by the protective ring in the plan view.

4. The semiconductor device according to claim 1, wherein, The inductor is formed in a spiral shape in the plan view, and The forming region of the inductor is determined based on the inner diameter of the inductor in the plan view.

5. The semiconductor device of claim 1, wherein the plurality of first conductors are configured to allow one of a power supply voltage and a ground voltage to propagate to the plurality of first conductors.

6. The semiconductor device of claim 1, wherein in the first layer located at the boundary line between the formed region and the non-formed region of the inductor in a plan view, the plurality of first conductors are formed to be short-circuited to each other.

7. The semiconductor device according to claim 1, wherein, In the plan view, the inductor is formed in a spiral shape, and In the plan view, the wiring width of the first conductor located in the central region of the forming region of the inductor is configured to be wider than the wiring width of the first conductor located in other parts of the forming region of the inductor.

8. The semiconductor device according to claim 1, wherein, In the plan view, the inductor is formed in a spiral shape, and In the plan view, the plurality of first conductors have a spatial region in the first layer located in the central region of the forming region of the inductor.

9. The semiconductor device of claim 1, further comprising a plurality of second conductive lines formed in the first layer and configured to indicate a fixed potential having a different level from the fixed potential indicated by the plurality of first conductive lines. In the plan view, the wiring width of the second conductor located within the range of the forming region of the inductor is formed to be narrower than the wiring width of the second conductor located outside the range of the forming region of the inductor.

10. The semiconductor device according to claim 9, wherein, The plurality of first conductors are configured to allow power supply voltage to propagate to the plurality of first conductors, and The plurality of second conductors are configured to allow ground voltage to propagate to the plurality of second conductors.

11. The semiconductor device of claim 9, wherein the plurality of first conductors and the plurality of second conductors are arranged alternately in a slit shape over the entire first layer.

12. The semiconductor device according to claim 9, wherein, In the plan view, the inductor is formed in a spiral shape. In the plan view, the wiring width of the first conductor located in the central region of the forming region of the inductor is formed to be wider than the wiring width of the first conductors located in other parts of the forming region of the inductor. In the plan view, the wiring width of the second conductor located in the central region of the forming region of the inductor is formed to be wider than the wiring width of the second conductor located in other parts of the forming region of the inductor.

13. The semiconductor device according to claim 9, wherein, In the plan view, the inductor is formed in a spiral shape. In the plan view, the plurality of first conductors include a spatial region in the first layer located in the central region of the forming region of the inductor, and In the plan view, the plurality of second conductors include a spatial region in the first layer located in the central region of the forming region of the inductor.

14. The semiconductor device of claim 1, further comprising a plurality of third conductive lines formed in a third layer stacked on the first layer and configured to indicate a fixed potential. In the plan view, the wiring width of the third conductor located within the range of the forming region of the inductor is formed to be narrower than the wiring width of the third conductor located outside the range of the forming region of the inductor.

15. An electronic circuit comprising an inductor employing the structure of a semiconductor device according to claim 1.

16. A semiconductor device, comprising: Multiple first conductors are formed in the first layer; A plurality of second conductors are formed in a second layer stacked on the first layer and intersect with the plurality of first conductors; Multiple first vias are formed at the intersections of the multiple first conductors and the multiple second conductors; as well as The inductor is formed in a third layer stacked on top of the first and second layers. In the plan view, the plurality of first vias are arranged such that the length of the loop with the minimum length among the plurality of current path loops formed by the plurality of first conductors, the plurality of second conductors, and the plurality of first vias is longer than a first predetermined length. The first predetermined length includes the loop length in the case where first vias are arranged at all the intersections of the plurality of first conductors and the plurality of second conductors.

17. The semiconductor device of claim 16, further comprising: Multiple third conductors are formed in the first layer; Multiple fourth conductors are formed in the second layer and intersect with the multiple third conductors; as well as Multiple second vias are formed at the intersections of the multiple third conductors and the multiple fourth conductors. In the plan view, the plurality of second vias are arranged such that the length of the loop with the minimum length among the plurality of current path loops formed by the plurality of third conductors, the plurality of fourth conductors, and the plurality of second vias is longer than a second predetermined length, and The two predetermined lengths include the loop length in the case where a second via is arranged at all the intersections of the plurality of third conductors and the plurality of fourth conductors.

18. An electronic circuit comprising an inductor employing the structure of a semiconductor device according to claim 16.

19. A method for forming a semiconductor device, comprising: In the first layer, a plurality of first wires configured to indicate a fixed potential are formed; as well as An inductor is formed in a second layer stacked on top of the first layer. In the formation of the plurality of first conductors, in a plan view, the wiring width of the first conductor located within the formation region of the inductor is narrower compared to the wiring width of the first conductor located outside the formation region of the inductor. The plurality of first conductors are formed in a slit-like manner on the entire surface of the first layer.

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