Computational Optimization of Neural Networks

Abstract

One embodiment provides a computing device for performing machine learning operations, the device comprising: a decoding unit for decoding a single instruction into a decoded instruction that specifies a plurality of operands including an input value and a quantized weight value associated with a neural network; an arithmetic logic unit that includes a barrel shifter, an adder, and an accumulator register, wherein, to execute the decoded instruction, the barrel shifter shifts the input value by the quantized weight value to generate a shifted input value, and the adder adds the shifted input value to the value stored in the accumulator register and updates the value stored in the accumulator register.

Description

Technical Field

[0001] Embodiments generally relate to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed function computing units to process graphics data; however, recently, multiple portions of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques (such as, pipelining operations) that attempt to process as much graphics data in parallel across different portions of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple groups of parallel threads attempt to synchronously execute program instructions together as often as possible to improve processing efficiency. A general overview of the software and hardware for a SIMT architecture can be found in: CUDA Programming by Shane Cook, Chapter 3, pages 37 - 51 (2013); and / or CUDA Handbook by Nicholas Wilt (A Comprehensive Guide to GPU Programming), Sections 2.6.2 to 3.1.2 (June 2013). Brief Description of the Drawings

[0004] To enable a detailed understanding of the features of the present invention, a more specific description of the present invention may be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings only illustrate typical embodiments and are therefore not to be considered as limiting the scope of all embodiments.

[0005] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A to 2D shows a parallel processor component according to an embodiment;

[0007] Figures 3A to 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A to 4FShows an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 Shows a graphics processing pipeline according to an embodiment;

[0010] Figure 6 Shows a machine learning software stack according to an embodiment;

[0011] Figure 7 Shows a highly parallel general-purpose graphics processing unit according to an embodiment;

[0012] Figure 8 Shows a multi-GPU computing system according to an embodiment;

[0013] Figures 9A to 9B Shows the layers of an exemplary deep neural network;

[0014] Figure 10 Shows an exemplary recurrent neural network;

[0015] Figure 11 Shows the training and deployment of a deep neural network;

[0016] Figure 12 Is a block diagram showing distributed learning;

[0017] Figure 13 Shows an exemplary inference on-chip system (SOC) suitable for performing inference using a trained model;

[0018] Figure 14 Illustrates an arithmetic logic unit according to an embodiment;

[0019] Figure 15 Illustrates the logic within the ALU for performing fused barrel shift accumulation according to an embodiment;

[0020] Figure 16 Is a flowchart of the logic for a fused barrel shift accumulation instruction according to an embodiment;

[0021] Figure 17 Illustrates the computation of a binary weighted neural network with N-bit features according to an embodiment;

[0022] Figure 18 Illustrates the logic within the ALU for performing a fused N-bit by 1-bit multiply-accumulate operation according to an embodiment;

[0023] Figure 19 Illustrates an exemplary multiplier according to an embodiment;

[0024] Figure 20Shows a flowchart of logic for fusing barrel shift accumulate instructions according to an embodiment;

[0025] Figure 21 Shows logic for performing fused XNOR and population count operations according to an embodiment;

[0026] Figure 22 Is a block diagram of a processing system according to an embodiment.

[0027] Figure 23 Is a block diagram of a processor according to an embodiment;

[0028] Figure 24 Is a block diagram of a graphics processor according to an embodiment;

[0029] Figure 25 Is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0030] Figure 26 Is a block diagram of a graphics processor provided by additional embodiments;

[0031] Figure 27 Shows thread execution logic, which includes an array of processing elements employed in some embodiments;

[0032] Figure 28 Is a block diagram showing a graphics processor instruction format according to some embodiments;

[0033] Figure 29 Is a block diagram of a graphics processor according to another embodiment;

[0034] Figures 30A to 30B Shows a graphics processor command format and command sequence according to some embodiments;

[0035] Figure 31 Shows an exemplary graphics software architecture of a data processing system according to some embodiments;

[0036] Figure 32 Is a block diagram showing an IP core development system according to an embodiment;

[0037] Figure 33 Is a block diagram showing an exemplary system-on-chip integrated circuit according to an embodiment;

[0038] Figure 34 Is a block diagram showing an additional exemplary graphics processor; and

[0039] Figure 35 Is a block diagram showing an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. Detailed Implementation Modes

[0040] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0041] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of ordinary skill in the art that embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the embodiments.

[0042] System Overview

[0043] Figure 1 is a block diagram showing a computer system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, and the one or more processors and the system memory communicate via an interconnect path that may include a memory hub 105. The memory hub 105 can be a separate component within a chipset component or integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, and the I / O hub can enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 can enable a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, one or more display devices 110A coupled to the I / O hub 107 can include a local display device, an internal display device, or an embedded display device.

[0044] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, and the one or more parallel processors are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a compute-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 110B.

[0045] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform such as a network adapter 118 and / or a wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0046] The computing system 100 can include other components not explicitly shown, which include USB or other port connectors, an optical storage drive, a video capture device, etc., and can also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components can be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol such as an NV-Link high-speed interconnect or an interconnect protocol known in the art.

[0047] In one embodiment, one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and the circuitry constitutes a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while retaining the underlying computational architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, the memory hub 105, the processor(s) 102, and the I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0048] It should be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology may be modified as needed, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, the system memory 104 is connected directly to the processor(s) 102 rather than through a bridge, and other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of the processor(s) 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0049] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be omitted. Additionally, some architectures may use different terms to describe components similar to those Figure 1 shown. For example, in some architectures, the memory hub 105 may be referred to as the north bridge, while the I / O hub 107 may be referred to as the south bridge.

[0050] Figure 2AShows a parallel processor 200 according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the illustrated parallel processor 200 is Figure 1 A variant of one or more of the parallel processors 112 shown.

[0051] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface such as the memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands related to performing processing operations and the memory crossbar 216 receives commands related to performing memory operations.

[0052] When the host interface 206 receives command buffers via the I / O unit 204, the host interface 206 may direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 that is configured to distribute commands or other work items to an array of processing clusters 212. In one embodiment, the scheduler 210 ensures that the array of processing clusters 212 is properly configured and in an active state before distributing tasks to the processing clusters within the array of processing clusters 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The scheduler 210 implemented by the microcontroller is configurable to perform complex scheduling and work distribution operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software may demonstrate the workload to be scheduled on the processing array 212 via one of a plurality of graphics processing doorbell mechanisms. These workloads may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0053] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each of the clusters 214A to 214N of the processing cluster array 212 can execute a large number of concurrent threads. The scheduler 210 can use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A to 214N of the processing cluster array 212, and these algorithms can vary according to the workload caused by each type of program or calculation. The scheduling can be dynamically handled by the scheduler 210, or can be partially assisted by compiler logic during the process of compiling the program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A to 214N of the processing cluster array 212 can be allocated to process different types of programs or to perform different types of calculations.

[0054] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 can include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformation.

[0055] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In an embodiment where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, tessellation logic, and other vertex processing logic. Additionally, the processing cluster array 212 can be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 can transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data can be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0056] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable the graphics processing operations to be distributed to the multiple clusters 214A through 214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A through 214N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 214A through 214N for further processing.

[0057] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, and the scheduler receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include data to be processed such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as indices of status parameters and commands (e.g., which program to execute) defining how to process the data. The scheduler 210 may be configured to obtain the index corresponding to the task or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to an effective state before the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0058] Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, which may receive memory requests from the processing cluster array 212 as well as the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning unit 220B, up to partitioning unit 220N), which may each be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A through 220N is configured to be equal to the number of memory units such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A through 220N may not be equal to the number of memory devices.

[0059] In various embodiments, the memory units 224A through 224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A through 224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A through 224N can vary and can be selected from one of various conventional designs. Rendering targets such as frame buffers or texture maps can be stored on the memory units 224A through 224N, allowing the partition units 220A through 220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, to support a unified memory design that utilizes system memory along with local cache memory, the local instance of the parallel processor memory 222 can be excluded.

[0060] In one embodiment, any one of the clusters 214A through 214N of the processing cluster array 212 can process data to be written to any one of the memory units 224A through 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to route the output of each cluster 214A through 214N to any of the partition units 220A through 220N or to another cluster 214A through 214N, where additional processing operations can be performed on the output. Each of the clusters 214A through 214N can communicate with the memory interface 218 through the memory crossbar 216 for read or write operations to various external memory devices. In one embodiment, the memory crossbar 216 can be connected to the memory interface 218 to communicate with the I / O unit 204 and can be connected to the local instance of the parallel processor memory 222, enabling processing units within different processing clusters 214A through 214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 can use virtual channels to separate the traffic flow between the clusters 214A through 214N and the partition units 220A through 220N.

[0061] While a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may also be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if they have different numbers of processing cores, different amounts of local parallel processor storage, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include floating point units with higher precision relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0062] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2A an instance of one of partition units 220A through 220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). L2 cache 221 is a read / write cache that is configured to perform loads and store operations received from memory crossbar 216 and ROP 226. Read misses and urgent write-back requests are output from L2 cache 221 to frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via frame buffer interface 225 for processing. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in parallel processor memory (e.g., memory units 224A through 224N of FIG. 2 (e.g., within parallel processor memory 222)).

[0063] In a graphics application, ROP 226 is a processing unit that performs raster operations (e.g., stencil, z-test, blending, etc.). ROP 226 then outputs the processed graphics data that is stored in the graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic may be lossless compression logic that uses one or more of a variety of compression algorithms. The type of compression performed by ROP 226 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta-color compression is performed on depth and color data on a per-tile basis.

[0064] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A - 214N of FIG. 2) rather than within the partition unit 220. In this embodiment, read and write requests for pixel data are transmitted via the memory crossbar 216 rather than pixel fragment data. The processed graphics data can be displayed on one of one or more display devices 110 such as Figure 1 and routed by the (one or more) processors 102 for further processing, or routed by Figure 2A one of the processing entities within the parallel processor 200 of

[0065] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A - 214N of FIG. 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular input data set. In some embodiments, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of substantially synchronous threads using a common instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters. Unlike SIMD execution mechanisms where all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0066] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processor. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of a plurality of possible destinations including other shading units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the data to be distributed via the data crossbar 240.

[0067] Each graphics multiprocessor 234 within processing cluster 214 may include the same set of functional execution logic (e.g., arithmetic logic units, load / store units, etc.). The functional execution logic may be configured in a pipelined fashion, where new instructions may be issued before the completion of previous instructions. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, boolean operations, shift operations, and the evaluation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0068] Instructions transmitted to processing cluster 214 form a thread. A set of threads executed on a set of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group may be assigned to a different processing engine within graphics multiprocessor 234. The thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycles of processing the thread group. The thread group may also include more threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing may be performed over consecutive clock cycles. In one embodiment, multiple thread groups may be executed simultaneously on graphics multiprocessor 234.

[0069] In one embodiment, graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, graphics multiprocessor 234 may forego the internal cache and instead use the cache memory (e.g., L1 cache 308) within processing cluster 214. Each graphics multiprocessor 234 may also access the L2 cache within a partition unit (e.g., partition units 220A - 220N of FIG. 2) shared among all processing clusters 214 and may be used to transfer data between threads. Graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 may be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 may share common instructions and data that may be stored in L1 cache 308.

[0070] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 may reside within the memory interface 218 of FIG. 2. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to the physical addresses of tiles and optionally cache line indices. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical addresses are processed to distribute surface data locality to enable efficient request interleaving among partition units. The cache line index may be used to determine whether a request to a cache line is a hit or a miss.

[0071] In graphics and computing applications, the processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. The texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within the graphics multiprocessor 234, and is fetched from the L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to the data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units that may be positioned with partition units (e.g., partition units 220A to 220N of FIG. 2) as described herein. The preROP 242 unit may optimize color blending, organize pixel color data, and perform address translation.

[0072] It should be understood that the core architecture described herein is illustrative and variations and modifications are possible. For example, any number of processing units such as the graphics multiprocessor 234, texture unit 236, preROP 242, etc. may be included within the processing cluster 214. Additionally, while only one processing cluster 214 is shown, the parallel processing unit as described herein may include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0073] Figure 2DFIG. 234 shows a graphics multiprocessor according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0074] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch the instructions as a thread group (e.g., a warp), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 262. Instructions may access any one of the local, shared, or global address spaces by specifying an address within a unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a different memory address accessible by the load / store unit 266.

[0075] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 262, load / store units 266) coupled to the graphics multiprocessor 234. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among the different warps being executed by the graphics multiprocessor 234.

[0076] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. According to an embodiment, the architectures of the GPGPU cores 262 may be similar or different. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. Additionally, the graphics multiprocessor 234 may also include one or more fixed-function or special-function units for performing specific functions such as copy rectangle or pixel blend operations. In one embodiment, one or more of the GPGPU cores may also contain fixed or special-function logic.

[0077] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions of the GPGPU core may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads that perform the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0078] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so the data transfer between the GPGPU core 262 and the register file 258 has very low latency. The shared memory 270 can be used to enable communication between the threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, the threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0079] Figures 3A to 3B Additional graphics multiprocessors according to an embodiment are shown. The illustrated graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The illustrated graphics multiprocessors 325, 350 can be configured as streaming multiprocessors (SMs) capable of concurrently executing a large number of execution threads.

[0080] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes multiple additional instances of the execution resource units relative to Figure 2D the graphics multiprocessor 234. For example, the graphics multiprocessor 325 can include multiple instances of instruction units 332A to 332B, register files 334A to 334B, and (multiple) texture units 344A to 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple sets of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0081] Various components can communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbars to enable communication between the components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A - 336B, 337A - 337B, and 338A - 338B can each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0082] Figure 3B FIG. 350 shows a graphics multiprocessor according to an additional embodiment. As Figure 2D and Figure 3A shown, the graphics processor includes multiple sets of execution resources 356A - 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load / store units. The execution resources 356A - 356D can work with the (multiple) texture units 360A - 360D to perform texture operations while sharing the instruction cache 354 and the shared memory 362. In one embodiment, the execution resources 356A - 356D can share the instruction cache 354 and the shared memory 362 as well as multiple instances of the texture and / or data cache memories 358A - 358B. Various components can communicate via an interconnect structure 352 similar to the interconnect structure 327 of Figure 3A .

[0083] Those skilled in the art will understand that Figure 1 , Figures 2A to 2D and Figures 3A to 3B the architectures described in are descriptive and do not limit the scope of the embodiments of the present invention. Thus, the techniques described herein can be implemented on any suitably configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computer or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as the parallel processing unit 202 of FIG. 2; and one or more graphics processors or specialized processing units, without departing from the scope of the embodiments described herein.

[0084] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0085] Techniques for GPU-to-Host Processor Interconnect

[0086] Figure 4A An exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440 to 443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0087] Furthermore, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as those used for high-speed links 440 to 443. Similarly, two or more of the multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communication between the various system components shown may be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0088] In one embodiment, each of the multi-core processors 405-406 is communicatively coupled to the processor memories 401-402 via the memory interconnects 430-431, respectively, and each of the GPUs 410-413 is communicatively coupled to the GPU memories 420-423 via the GPU memory interconnects 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example, and not limitation, the processor memories 401-402 and the GPU memories 420-423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics double data rate SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0089] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed across all of the various physical memories. For example, each of the processor memories 401-402 may include 64 GB of system memory address space, and each of the GPU memories 420-423 may include 32 GB of system memory address space (resulting in a total of 256 GB of addressable storage space in the example).

[0090] Figure 4B Additional details of the interconnect between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0091] The illustrated processor 407 includes multiple cores 460A through 460D, each having a translation lookaside buffer 461A through 461D and one or more caches 462A through 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown so as not to obscure the basic principles of the present invention. Caches 462A through 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by groups of cores 460A through 460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 caches and one of the L3 caches are shared by two adjacent cores. Processor 407 and graphics accelerator integration module 446 are connected to system memory 441, which may include processor memories 401 through 402.

[0092] Data and instructions stored in various caches 462A through 462D, 456, and system memory 441 are kept consistent via inter-core communication through coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and are not described in detail herein so as not to obscure the basic principles of the present invention.

[0093] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0094] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, 43N of the graphics acceleration module 446. The graphics processing engines 431, 432, 43N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, 43N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and block image transfer engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431, 432, 43N, or the graphics processing engines 431 to 432, 43N may be separate GPUs integrated on a common package, line card, or chip.

[0095] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 that performs various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one embodiment, the accelerator integrated circuit 436 includes a fetch unit 491 for fetching commands, instructions, work descriptors, etc. that define the operations to be performed. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432N. In one embodiment, the data stored in the cache 438 and the graphics memories 433 to 434N is kept consistent with the core caches 462A to 462D, 456, and the system memory 411. As mentioned, this may be done via the proxy circuit 425, which participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433 to 434N (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 462A to 462D, 456 to the cache 438 and receiving updates from the cache 438).

[0096] A set of registers 449 stores context data of threads executed by graphics processing engines 431 to 432, 43N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations to save and restore contexts of various threads during context switching (e.g., where a first thread is saved and a second thread is stored such that the second thread can be executed by a graphics processing engine). For example, at context switch, context management circuitry 448 may store current register values to a specified area in memory (e.g., identified by a context pointer). The context management circuitry may restore the register values upon return to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0097] In one implementation, a virtual / valid address from graphics processing engine 431 is translated to an actual / physical address in system memory 411 by MMU 439. One embodiment of accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. Graphics accelerator module 446 may be dedicated to a single application executing on processor 407 or may be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented where resources of graphics processing engines 431 to 432, 43N are shared among multiple applications or virtual machines (VMs). Resources may be subdivided into "slices" allocated to different VMs and / or applications based on processing requirements and priorities associated with the VM and / or application.

[0098] Thus, the accelerator integrated circuit acts as a bridge for the system of graphics accelerator modules 446 and provides address translation and system memory cache services. Additionally, accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage virtualization of graphics processing engines, interrupts, and memory management.

[0099] Since the hardware resources of graphics processing engines 431 to 432, 43N are explicitly mapped to the actual address space seen by host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of accelerator integrated circuit 436 is the physical separation of graphics processing engines 431 to 432, 43N such that they appear as independent units on the system.

[0100] As mentioned, in the illustrated embodiments, one or more graphics memories 433 - 434, 43M are coupled to each of graphics processing engines 431 - 432, 43N, respectively. The graphics memories 433 - 434, 43M store instructions and data being processed by each of the graphics processing engines 431 - 432, 43N. The graphics memories 433 - 434, 43M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non - volatile memories such as 3D XPoint or Nano - Ram.

[0101] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433 - 434, 43M is data most frequently used by graphics processing engines 431 - 432, 43N, and data that cores 460A - 460D preferably do not use (or at least do not use frequently). Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not by graphics processing engines 431 - 432, 43N) within caches 462A - 462D, 456 of the cores and system memory 411.

[0102] Figure 4C Another embodiment is shown where accelerator integrated circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431 - 432, 43N communicate directly with accelerator integrated circuit 436 via interface 437 and interface 435 over high - speed link 440 (which can also utilize any form of bus or interface protocol). Accelerator integrated circuit 436 can perform the same operations as described with respect to Figure 4B but may operate with higher throughput considering its close proximity to coherence bus 462 and caches 462A - 462D, 426.

[0103] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0104] In one embodiment of the dedicated process model, graphics processing engines 431 - 432, 43N are dedicated to a single application or process under a single operating system. A single application can aggregate other application requests to graphics engines 431 - 432, 43N, thereby providing virtualization within a VM / partition.

[0105] In a dedicated process programming model, graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. The shared model requires a hypervisor that virtualizes the graphics processing engines 431 to 432, 43N to allow access by each operating system. For a single-partition system without a hypervisor, the graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0106] For a shared programming model, the graphics acceleration module 446 or a separate graphics processing engine 431 to 432, 43N uses a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to physical address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431 to 432, 43N (i.e., calling system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0107] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process elements 483 contain the processing state of the corresponding application 480. The work descriptor (WD) 484 contained in the process elements 483 can be a single job requested by the application or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue in the application address space 482.

[0108] The graphics acceleration module 446 and / or a separate graphics processing engine 431 to 432, 43N can be shared by all or some of the processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending the WD 484 to the graphics acceleration module 446 to start a job in a virtual environment.

[0109] In one implementation, the dedicated process programming model is implementation - specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the partition to which it belongs, and the operating system initializes the accelerator integrated circuit 436 when the graphics acceleration module 446 is allocated to obtain the process to which it belongs.

[0110] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, the data from the WD 484 can be stored in the register 449 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing a graphics operation, the effective address 493 generated by the graphics processing engines 431 to 432, 43N is translated to an actual address by the MMU 439.

[0111] In one embodiment, the same set of registers 449 is replicated for each of the graphics processing engines 431 to 432, 43N and / or the graphics acceleration module 446, and this set of registers can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0112] Table 1 - Hypervisor - Initialized Registers

[0113] 1 Fragment Control Register 2 Real Address (RA) Scheduler Process Area Pointer 3 Authorization Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Descriptor Register

[0114] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0115] Table 2 - Operating - System - Initialized Registers

[0116] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Resume Pointer 3 Virtual Address (RA) Accelerator Utilization Record Pointer 4 Virtual Address (RA) Storage Segment Table Pointer 5 Authorization Mask 6 Work Descriptor

[0117] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 to 432, 43N. The WD contains all the information required for the graphics processing engines 431 to 432, 43N to complete their work, or the WD can be a pointer to a memory location where the application has established a command queue of work to be done.

[0118] Figure 4E Shows additional details of an embodiment of the shared model. The embodiment includes a hypervisor physical address space 498 in which a list of process elements 499 is stored. The hypervisor physical address space 498 can be accessed via a hypervisor 496 that virtualizes the graphics acceleration module engine of an operating system 495.

[0119] The shared programming model allows all or part of the processes from all or part of the partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-slicing sharing and graphics direct sharing.

[0120] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functions available to all operating systems 495. To enable the graphics acceleration module 446 to support the virtualization of the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., do not require maintaining the state between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees the completion of application job requests within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in the direct sharing programming model, fairness of the graphics acceleration module 446 in the process must be guaranteed.

[0121] In one embodiment, for a shared model, an application 480 is required to utilize the graphics acceleration module 446 type, work descriptor (WD), authorization mask register (AMR) value, and context save / restore area pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can be in the form of: a graphics acceleration module 446 command; a valid address pointer to a user-defined structure; a valid address pointer to a command queue; or any other data structure for describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authorization mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. The hypervisor 496 can optionally apply the current authorization mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 449 that contains a valid address of a region in the application address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if there is no need to save state between jobs or when a job is preempted. The context save / restore area can be plugged system memory.

[0122] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then utilizes the information shown in Table 3 to call the hypervisor 496.

[0123] Table 3 - Operating System Call Parameters to the Hypervisor

[0124] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / Resume Area Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0125] Upon receiving the hypervisor call, the hypervisor 496 can verify that the operating system 495 is registered and authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element can contain the information shown in Table 4.

[0126] Table 4 - Process Element Information

[0127] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / Resume Area Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table, Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0128] In one embodiment, the hypervisor initializes the registers 449 of the plurality of accelerator integrated slices 490.

[0129] As Figure 4F Shown, one embodiment of the present invention employs a unified memory that can be addressed via a common virtual memory address space for accessing the physical processor memories 401-402 and the GPU memories 420-423. In this implementation, operations executed on the GPUs 410-413 utilize the same virtual / effective memory address space to access the processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 401-402 and the GPU memories 420-423, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0130] In one embodiment, the bias / coherency management circuits 494A-494E within one or more of the MMUs 439A-439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410-413, and implement a biasing technique for indicating the physical memory in which certain types of data should be stored. Although Figure 4F multiple instances of the bias / coherency management circuits 494A-494E are shown, the bias / coherency circuits may also be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0131] One embodiment allows the GPU - attached memories 420 - 423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, without suffering the typical performance drawbacks associated with full - system cache coherence. The ability to access the GPU - attached memories 420 - 423 as system memory does not incur a heavy cache - coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access computed results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, which are all inefficient compared to simple memory accesses. At the same time, the ability to access the GPU - attached memories 420 - 423 without cache - coherence overhead can be critical to the execution time of offloaded computations. For example, in the case of a large number of streaming write - to - memory transactions, the cache - coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 410 - 413. The efficiency of operand setting, result access, and GPU computation all play important roles in determining the effectiveness of GPU offloading.

[0132] In one implementation, the choice between GPU bias and host - processor bias is driven by a bias - tracker data structure. For example, a bias table can be used, which can be a page - granularity structure (i.e., controlled at the granularity of memory pages) that includes 1 or 2 bits per GPU - attached memory page. The bias table can be implemented within the stolen - memory range of one or more of the GPU - attached memories 420 - 423, with or without a bias cache in the GPUs 410 - 413 (e.g., to cache frequently / most - recently - used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0133] In one implementation, the bias - table entry associated with each access to the GPU - attached memories 420 - 423 is accessed before actually accessing the GPU memory, enabling the following operations. First, local requests from the GPUs 410 - 413 that find their pages in GPU bias are forwarded directly to the corresponding GPU memories 420 - 423. Local requests from the GPUs that find their pages in host bias are forwarded to the processor 405 (e.g., via a high - speed link as described above). In one embodiment, a request from the processor 405 that finds the requested page in host - processor bias completes the request as a normal memory read. Alternatively, a request for a GPU - bias page can be forwarded to the GPUs 410 - 413. If the GPU is not currently using the page, the GPU can convert the page to host - processor bias.

[0134] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, for a limited set of cases, a hardware-only mechanism.

[0135] A mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU to cause the GPU to change the bias state and, for some transitions, perform a cache dump flush operation in the host. The cache dump flush operation is necessary for the transition from host processor 405 bias to GPU bias and not necessary for the reverse transition.

[0136] In one embodiment, cache coherence is maintained by temporarily presenting GPU-biased pages that are non-cacheable by the host processor 405. To access these pages, processor 405 may request access from GPU 410, and the GPU may or may not immediately grant access depending on the implementation. Thus, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that the GPU-biased pages are pages that are needed by the GPU but not by the host processor 405, and vice versa.

[0137] Graphics Processing Pipeline

[0138] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the shown graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2. In one embodiment, the parallel processor is Figure 1Variants of the (multiple) parallel processors 112. As described herein, various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 of FIG. 2). For example, a shader unit (e.g., the graphics multiprocessor 234 of FIG. 3) may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partition units (e.g., the partition units 220A to 220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., the parallel processor memory 222 as shown in FIG. 2) via a memory interface 528, which may be an instance of the memory interface 218 of FIG. 2.

[0139] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for processing the vertex data, and may be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0140] The first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 50. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. The graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0141] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. These control points are transformed from an input representation of the patch (e.g., the basis of the patch) to a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also compute tessellation factors for the edges of the geometric patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edges. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitives.

[0142] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and compute parameters for rasterizing the new graphics primitives.

[0143] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for processing geometric data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0144] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate segments and outputs these segments and associated coverage data to the segment / pixel processing unit 524. The segment / pixel processing unit 524 is a programmable execution unit configured to execute a segment shader program or a pixel shader program. The segment / pixel processing unit 524 transforms the segments or pixels received from the rasterizer 522 as specified by the segment or pixel shader program. For example, the segment / pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded segments or pixels output to the raster operations unit 526. The segment / pixel processing unit 524 may read data stored in the parallel processor memory or the system memory to use when processing segment data. The segment or pixel shader program may be configured to shade at a sample, pixel, tile, or other granularity according to a sampling rate configured for the processing unit.

[0145] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphics data to be stored in the graphics memory (e.g., the parallel processor memory 222 in FIG. 2, and / or the system memory 104 as in Figure 1 to be displayed on one or more display devices 110 or further processed by one of the one or more processors 102 or (multiple) parallel processors 112. In some embodiments, the raster operations unit 526 is configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0146] Machine Learning Overview

[0147] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms may be designed to model high-order abstractions within a data set. For example, an image recognition algorithm may be used to determine which of several categories a given input belongs to; a regression algorithm may output a numerical value given an input; and a pattern recognition algorithm may be used to generate translated text or perform text-to-speech and / or speech recognition.

[0148] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph where nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the inputs received by the input layer into representations useful for generating an output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., “fed forward”) via an activation function to the nodes of the output layer, which calculates the state of the nodes of each successive layer in the network based on coefficients (“weights”), each of which is associated with one of the edges connecting these layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0149] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting the weights until the network model exhibits a minimum error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared to the “correct” labeled output for that instance; an error signal representing the difference between the output and the labeled output is calculated; and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backward through the layers of the network. The network is considered “trained” when the error for each output generated from an instance in the training data set is minimized.

[0150] The accuracy of a machine learning algorithm is greatly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may require a large amount of time on a conventional general-purpose processor. Accordingly, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed when adjusting the coefficients in a neural network are themselves naturally amenable to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within a general-purpose graphics processing device.

[0151] Figure 6It is a generalized diagram of a machine learning software stack 600. The machine learning application 602 can be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. The machine learning application 602 can include training and inference functions for neural networks and / or dedicated software, which can be used to train neural networks before deployment. The machine learning application 602 can implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0152] Hardware acceleration for the machine learning application 602 can be achieved via the machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are the basic operations that machine learning algorithms typically perform. Without the machine learning framework 604, developers of machine learning algorithms would need to create and optimize the main computational logic associated with the machine learning algorithms and then re-optimize the computational logic when a new parallel processor is developed. Instead, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning framework 604. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 604 can also provide primitives for implementing basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0153] The machine learning framework 604 can process the input data received from the machine learning application 602 and generate appropriate inputs to the compute framework 606. The compute framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 so that the machine learning framework 604 can utilize hardware acceleration via the GPGPU hardware 610 without the machine learning framework 604 being very familiar with the architecture of the GPGPU hardware 610. Additionally, the compute framework 606 can implement hardware acceleration for the machine learning framework 604 across multiple types and generations of GPGPU hardware 610.

[0154] GPGPU Machine Learning Acceleration

[0155] Figure 7 Displays a highly parallel general-purpose graphics processing unit 700 according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient in processing this type of computational workload associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0156] The GPGPU 700 includes a host interface 702 for implementing a connection with a host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a vendor - specific communication interface or communication fabric. The GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with those commands to a set of compute clusters 706A through 706H. The compute clusters 706A through 706H share a cache memory 708. The cache memory 708 can act as a cache - of - caches within the cache memories in the compute clusters 706A through 706H.

[0157] The GPGPU 700 includes memories 714A through 714B that are coupled to the compute clusters 706A through 706H via a set of memory controllers 712A through 712B. In various embodiments, the memories 714A through 714B can include various types of memory devices, including dynamic random - access memory (DRAM) or graphics random - access memory (such as synchronous graphics random - access memory (SGRAM), including graphics double - data - rate (GDDR) memory), and can also include 3D stacked memory, including but not limited to high - bandwidth memory (HBM).

[0158] In one embodiment, each of the compute clusters 706A through 706H includes a set of graphics multiprocessors, such as Figure 4A the graphics multiprocessor 400. The graphics multiprocessors of the compute clusters include various types of integer and floating - point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine - learning computations. For example and in one embodiment, at least one subset of the floating - point units in each of the compute clusters 706A through 706H can be configured to perform 16 - bit or 32 - bit floating - point operations, while a different subset of the floating - point units can be configured to perform 64 - bit floating - point operations.

[0159] Multiple instances of GPGPU 700 can be configured to operate as a compute cluster. The communication mechanisms used by the compute cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, which enables a direct connection to other instances of the GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect for transferring and receiving data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via a network device that can be accessed via host interface 702. In one embodiment, in addition to or as an alternative to host interface 702, GPU link 710 can also be configured to enable connection to a host processor.

[0160] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer compute clusters 706A through H relative to the training configuration. Additionally, the memory technologies associated with memories 714A through 714B can differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions that are typically used during inference operations for deployed neural networks.

[0161] Figure 8 FIG. 800 shows a multi-GPU computing system 800 according to an embodiment. The multi-GPU computing system 800 can include a processor 802 that is coupled to multiple GPGPUs 806A through D via a host interface switch 804. In one embodiment, host interface switch 804 is a PCI Express switch device that couples processor 802 to a PCI Express bus through which processor 802 can communicate with the set of GPGPUs 806A through D. Each of the multiple GPGPUs 806A through 806D can be Figure 7An instance of the GPGPU 700. The GPGPUs 806A - D can be interconnected via a set of high - speed point - to - point GPU - GPU links 816. The high - speed GPU - GPU links can be connected to each of the GPGPUs 806A - 806D via dedicated GPU links (e.g., such as the GPU link 710 in Figure 7 ). The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A - D without communicating through the host interface bus (to which the processor 802 is connected). In the case of GPU - GPU traffic over the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi - GPU computing system 800 (e.g., via one or more network devices). Although in the illustrated embodiment the GPGPUs 806A - D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A - 806D.

[0162] Machine Learning Neural Network Implementation

[0163] The computing architectures provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can generally be generalized as a network of functions with graphical relationships. As is well known in the art, there are multiple types of neural network implementations used in machine learning. An exemplary type of neural network is the feed - forward network as previously described.

[0164] The second exemplary type of neural network is a Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network for processing data with a known, grid-like topology (such as, image data). Thus, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized as a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in successive layers of the network. The computations used for a CNN include applying the convolution mathematical operation to each filter to produce the output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function with respect to convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as the feature map. For example, the input to a convolutional layer can be a multi-dimensional data array that defines the various color components of an input image. The convolution kernel can be a multi-dimensional parameter array, where the parameters are adapted through a training process for the neural network.

[0165] A Recurrent Neural Network (RNN) is a class of feedforward neural networks that includes feedback connections between layers. RNNs enable the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. These loops represent the influence of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which language data can be composed.

[0166] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe general processes for training and deploying each of those types of networks. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiments described herein, and generally the concepts presented can be applied to deep neural networks and machine learning techniques in general.

[0167] The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Neural networks with more depth are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error relative to shallow machine learning techniques.

[0168] Deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without performing manual feature engineering for the model. Instead, the deep neural network can learn features based on the statistical structure or correlations within the input data. The learned features can be provided to the mathematical model, which can map the detected features to an output. The mathematical model used by the network is typically specific to the particular task to be performed, and different models will be used to perform different tasks.

[0169] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of error is a commonly used method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the desired output, and an error value is calculated for each neuron in the output layer. These error values are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as the stochastic gradient descent algorithm) to update the weights of the neural network.

[0170] Figure 9A To B show exemplary convolutional neural networks. Figure 9A Show the individual layers within the CNN. As Figure 9A shown, an exemplary CNN for modeling image processing can receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). Optionally, the output from the plurality of convolutional layers can be processed by a set of fully connected layers 908. Neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layers 908 can be used to generate an output result from the network. Matrix multiplication rather than convolution can be used to calculate the activation functions within the fully connected layers 908. Not all CNN implementations use the fully connected layers 908. For example, in some implementations, the convolutional layer 906 can generate the output of the CNN.

[0171] The convolutional layer is sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, the convolutional layer is sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state values of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, and the output of the convolution operation is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables the CNN to scale to handle large images.

[0172] Figure 9B Exemplary computational stages within the convolutional layer of the CNN are shown. The input 912 to the convolutional layer of the CNN can be processed in three stages of the convolutional layer 914. These three stages can include a convolution stage 916, a detector stage 918, and a pooling stage 920. Then, the convolutional layer 914 can output data to a successive convolutional layer. The last convolutional layer of the network can generate output feature map data or provide an input to the fully connected layer, for example, to generate classification values for the input to the CNN.

[0173] A number of convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activation functions. The convolution stage 916 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function connected to a specific region in the input (e.g., a neuron), and the specific region can be determined as the local region associated with the neuron. The neuron computes the dot product between the weights of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activation functions to be processed by successive stages of the convolutional layer 914.

[0174] The linear activation functions can be processed by the detector stage 918. In the detector stage 918, each linear activation function is processed by a non - linear activation function. The non - linear activation function increases the non - linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non - linear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x), such that the activation function is thresholded to zero.

[0175] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with summary statistical values of nearby outputs. The pooling function can be used to introduce translational invariance into the neural network such that a slight translation of the input does not change the pooled output. Invariance to local translations can be useful when the presence of features in the input data is more important than the exact location of the features. Various types of pooling functions can be used during the pooling stage 920, including max pooling, average pooling, and L2 norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations substitute additional convolutional stages that have an increased stride relative to the previous convolutional stage.

[0176] Then, the output from the convolutional layer 914 can be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9A the first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first of the fully connected layers 908.

[0177] Figure 10 An exemplary recurrent neural network 1000 is shown. In a recurrent neural network (RNN), the previous state of the network affects the output of the network's current state. RNNs can be constructed in a wide variety of ways using a wide variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict upcoming words given a previous sequence of words. The illustrated RNN 1000 can be described as having the following: an input layer 1002 that receives an input vector; a hidden layer 1004 for implementing a recurrent function; a feedback mechanism 1005 for implementing a'memory' of the previous state; and an output layer 1006 for outputting a result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x 1 ) at the first time step can be processed by the hidden layer 1004. The second input (x 2 ) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x 1 ). A given state can be calculated as s t = f(Ux t + Ws t-1), where U and W are parameter matrices. The function f is typically non-linear, such as the hyperbolic tangent function (Tanh) or a variant of the rectifier function f(x) = max(0, x). However, the specific mathematical function used in the hidden layer 1004 can vary depending on the specific implementation details of the RNN 1000.

[0178] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. The LSTM RNN is capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of the CNN is the convolutional deep belief network, which has a structure similar to the CNN and is trained in a manner similar to the deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. Greedy unsupervised learning can be used to train the DBN layer by layer. Then, the learned weights of the DBN can be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0179] Figure 11 Illustrates the training and deployment of a deep neural network. Once a given network has been structured for a task, the training dataset 1102 is used to train the neural network. Various training frameworks 1104 have been developed for implementing hardware acceleration of the training process. For example, Figure 6 the machine learning framework 604 can be configured as the training framework 604. The training framework 604 can be hooked up to the untrained neural network 1106 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate the trained neural network 1108.

[0180] To initiate the training process, the initial weights can be selected randomly or by pre-training using a deep belief network. Then, the training loop is performed in a supervised or unsupervised manner.

[0181] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training data set 1102 includes inputs (which are paired with the desired outputs of the inputs), or in cases where the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. Then, the error is backpropagated through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools for monitoring the extent to which the untrained neural network 1106 converges to a model suitable for generating correct answers based on the known input data. When adjusting the weights of the network to improve the output generated by the neural network, the training process occurs repeatedly. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1108. Then, the trained neural network 1108 can be deployed to perform any number of machine learning operations.

[0182] Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0183] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used for further training of the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge ingrained in the network during initial training.

[0184] Regardless of whether it is supervised or unsupervised, the training process for particularly deep neural networks can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to accelerate the training process.

[0185] Figure 12is a block diagram showing distributed learning. Distributed learning is the training of a model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more of general processing nodes, such as the highly parallel general-purpose graphics processing unit 700 as shown in Figure 7 . As shown, distributed learning can perform model parallelism 1202, data parallelization 1204, or a combination of model and data parallelization 1204.

[0186] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of a distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables the training of ultra-large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0187] In data parallelization 1204, different nodes of a distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from different nodes are then combined. While different methods for data parallelization are possible, all data parallel training methods require a technique for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that holds the parameter data. Update-based data parallelization is similar to parameter averaging, except that instead of passing the parameters from the nodes to the parameter server, updates to the model are passed. Additionally, update-based data parallelization can be performed in a decentralized manner where the updates are compressed and passed between nodes.

[0188] For example, combined model and data parallelization 1206 can be implemented in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where individual GPUs within each node are used to train different parts of the model.

[0189] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement techniques for reducing the overhead of distributed training, including techniques for implementing high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0190] Exemplary Machine Learning Applications

[0191] Machine learning can be applied to solve a number of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The scope of computer vision applications ranges from reproducing human visual capabilities (e.g., recognizing human faces) to creating new classes of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in an object visible in a video. Machine learning accelerated by parallel processors enables the use of training data sets that are significantly larger than previously feasible for training computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0192] Machine learning accelerated by parallel processors has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train a driving model based on a data set that defines the appropriate response to a particular training input. The parallel processors described herein can enable the rapid training of increasingly complex neural networks for autonomous driving solutions, and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0193] Parallel processor accelerated deep neural networks have implemented machine learning methods for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has been implemented to replace the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0194] Machine learning accelerated by parallel processors can also be used to accelerate natural language processing. An automatic learning program can use statistical inference algorithms to produce models that are robust to errors or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0195] The parallel processing platform for machine learning can be divided into a training platform and a deployment platform. The training platform is typically highly parallel and includes optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7highly parallel general-purpose graphics processing unit 700 and Figure 8 multi-GPU computing system 800. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0196] Figure 13 Exemplary inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model is shown. SOC 1300 may integrate multiple processing components, including media processor 1302, vision processor 1304, GPGPU 1306, and multi-core processor 1308. SOC 1300 may additionally include on-chip memory 1305, which may implement a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of SOC 1300 may be used as part of the main control system for an autonomous vehicle. In the case where SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for the deployment jurisdiction.

[0197] During operation, media processor 1302 and vision processor 1304 may work in concert to accelerate computer vision operations. Media processor 1302 may enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams may be written to a buffer in on-chip memory 1305. Vision processor 1304 may then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare the frames for processing using a trained image recognition model. For example, vision processor 1304 may accelerate the convolutional operations for a CNN (for performing image recognition on high-resolution video data), and the backend model computations are performed by GPGPU 1306.

[0198] Multi-core processor 1308 may include control logic to facilitate the ordering and synchronization of data transfers and shared memory operations performed by media processor 1302 and vision processor 1304. Multi-core processor 1308 may also act as an application processor to execute software applications that may use the inference computing capabilities of GPGPU 1306. For example, at least a portion of the navigation and driving logic may be implemented in software executed on multi-core processor 1308. Such software may directly issue computational workloads to GPGPU 1306, or may issue computational workloads to multi-core processor 1308, which may offload at least a portion of those operations to GPGPU 1306.

[0199] The GPGPU 1306 may include a compute cluster, such as a low-power configuration of compute clusters 706A through 706H within the highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 may support instructions that are explicitly optimized for performing inference computations on a trained neural network. For example, the GPGPU 1306 may support instructions for performing low-precision computations (e.g., 8-bit and 4-bit integer vector operations).

[0200] Computational Optimization of Neural Networks

[0201] The embodiments described herein provide various computational optimizations to improve the efficiency of a general-purpose graphics processing unit when performing operations of machine learning via a neural network. One embodiment provides a fused barrel shift accumulate instruction. One embodiment provides a densely packed weight index for weights in a binary weighted neural network. One embodiment provides an architecture for 1-bit by N-bit operations. One embodiment provides a processing architecture for extremely low-precision neural networks.

[0202] Fused Barrel Shift Accumulate Operations

[0203] Current neural network research examines quantizing weights to powers of two (e.g., 2 x ) values to reduce multiple operations on weights to barrel shifts. To accelerate such networks, the embodiments provided herein implement a fused barrel shift accumulate instruction, which can significantly accelerate the processing operations of these networks when executing the GPGPU described herein.

[0204] A barrel shifter is a combinational logic block that accepts an N-bit input value and provides an N-bit value that is the input value shifted left or right by P bits. The barrel shifter can perform the operation in a single cycle, which would otherwise require P cycles to perform without using the barrel shifter. The barrel shifter can be used to quickly perform a power-of-two multiplication operation. Shifting the input left by P is equivalent to multiplying the input by 2 P . For neural networks using weight values quantized to 2 X values, computations can be performed very quickly via the fused barrel shift accumulate operation provided by the embodiments described herein.

[0205] Figure 14Shows an arithmetic logic unit according to an embodiment. The arithmetic logic unit (ALU 1400) is configured to receive a first operand 1401 and a second operand 1402. In neural network processing, an input value can be multiplied by a weight value to generate a result value. The result value can then be applied to an activation function to determine the output value of a node. The ALU 1400 accelerates those operations in a quantized neural network by enabling fused barrel shift and accumulate operations. In one embodiment, the first operand 1401 can be the input value to be multiplied by the weight value, and the second operand 1402 is the weight value that has been quantized to a power of 2. For example, the first operand 1401 can represent feature data within a neural network. The ALU 1400 can receive a fused barrel shift accumulate opcode 1403 that causes the ALU 1400 to perform a fused barrel shift accumulate operation on the input operands. The ALU 1400 can generate a result 1406 of the operation and a status 1404 of the operation. The status 1404 can indicate individual signals that convey supplementary information about the result of the operation performed on the ALU 1400. The status 1404 can be stored in a status register for subsequent use.

[0206] In one embodiment, the result 1406 is the same as the value that would be output from a fused multiply accumulate operation on the first operand and 2 X where X = the second operand 1402. However, the internal logic of the ALU 1400 is implemented using a barrel shifter instead of conventional multiplication logic and can perform the calculations significantly faster than using conventional multiplication logic.

[0207] Figure 15 Shows the logic within the ALU for performing a fused barrel shift accumulate according to an embodiment. In one embodiment, a first stage 1500 includes an N-bit input register 1501, a quantized weight register 1502, a barrel shifter 1504, and an intermediate register 1506. A second stage 1510 includes an N-bit adder 1512, an accumulator register 1514, and an N-bit output register 1516.

[0208] In one embodiment, an N-bit input register 1501 stores an N-bit (e.g., 4, 8, 16, 32, 64) input value, where the specific size of the input varies across embodiments. A quantized weight register 1502 may store exponent values of neural network weights quantized to a power of two (e.g., 0, 1, 2, 4, 8, 16, 32, 64, etc.). The quantized weight register 1502 may provide a shift value to a barrel shifter 1504 to indicate the amount by which the value in the N-bit input register 1501 is to be shifted. The barrel shifter 1504 may generate an output to be stored in an intermediate register 1506. In one embodiment, the barrel shifter may output the result to the intermediate register 1506 in a single cycle and not perform a rounding operation.

[0209] An N-bit adder 1512 in a second stage 1510 may read data from the N-bit intermediate register 1506 as a first operand for an addition operation. A second operand of the addition is a value read from an accumulator register 1514 that stores the output from the previous cycle. Subsequently, the output of the addition may be written to an N-bit output register 1516.

[0210] Figure 16 is a flowchart of logic 1600 for a fused barrel shift accumulate instruction according to an embodiment; in one embodiment, the logic 1600 of the illustrated instruction is executed within a compute unit of a general purpose graphics processing unit as described herein to accelerate machine learning and neural network operations. In one embodiment, as shown at block 1602, the logic 1600 decodes a single instruction that specifies multiple operands including an input value and a weight value of a neural network. As shown at block 1604, the logic 1600 may then issue the single instruction for execution within a compute unit of the general purpose graphics processing unit. In response to the execution of the single instruction, the logic 1600 may generate a result based on shifting the input value by the weight value of the neural network and adding the shifted value to a value stored in an accumulator register, as shown at block 1606.

[0211] Weight Indexing for Weight Dense Packing in Binary Weighted Neural Networks

[0212] Machine learning implementations may implement neural networks that utilize floating point or high precision fixed point feature data in combination with binary weights. Such networks may be used to achieve high precision while using lower precision computational logic. However, due to the use of floating point or fixed point feature data, such implementations cannot use bit manipulation instructions to efficiently utilize binary weights. To densely pack and efficiently access weights, bit-level indexing of words within a register may be implemented within the GPGPU logic described herein. Such an implementation may be used in conjunction with hardware support for binary multiply-accumulate operations.

[0213] Figure 17Shows the computation of a binary weighted neural network with N-bit features according to an embodiment. Some neural network models use low-precision weights consistent with N-bit feature data. The N-bit feature data can be a power of two or any number of bits, while the weight data is represented as a single bit. It has been found that binary weight networks can be used for inference deployment, where lower precision values can produce similar results relative to higher precision values. A neural network trained with N-bit weights can binaryize these weights for inference, replacing the weight value with one of two possible values based on whether the weight value is greater than or equal to a certain threshold.

[0214] To achieve efficient storage of densely packed weights, multiple binary weights 1702 are packed into a single N-bit register. Bit indices are used to reference individual weights for simultaneous processing across multiple N-bit features 1704A - 1704N. Multiple parallel fused binary multiply-accumulate operations 1706A - 1706N can be executed in parallel within the compute units of a general-purpose processor. The weight operands input to the binary multiply-accumulate operations 1706A - 1706N include a register and an index to the position of the weight value within the register for computation. For an N-bit register, N binary weights can be stored. In one embodiment, the compute units of a GPGPU provide support for vector binary multiply-accumulate instructions, where N binary bits within an N-bit register can be multiplied by N N-bit features 1704A - 1704N, which can be stored in an N x N width vector register. For example and in one embodiment, a single instruction is provided where the first operand is an input register storing eight 1-bit weights, where each weight is stored at an index position [0:7] within the register. Eight 8-bit feature values can be packed into a second register. Each of the eight 1-bit weights will be multiplied by the associated 8-bit feature value, and the products will be accumulated to generate an M-bit output value. In various embodiments, the M-bit output of an 8-bit by 1-bit product can be an 8-bit value with saturation or greater than an 8-bit value, such as a 16-bit value. For N equal to 8, the accumulator register for storing the accumulated value will be greater than 8 bits.

[0215] The binaryization can be performed deterministically or randomly transform the N-bit weights into bipolar binaries 1701 with bipolar extremes (-1, 1). The deterministic binaryization is shown in Equation (1). The random binaryization is shown in Equation (2).

[0216]

[0217] In Equation (2), σ(x) is the hard sigmoid-type function shown in Equation (3).

[0218]

[0219] Figure 18 Illustrates the logic within the ALU for performing a fused N - bit by 1 - bit multiply - accumulate operation according to an embodiment. In one embodiment, the first stage 1800 includes an N - bit register storing the feature input 1801, the indexed weight 1802 within the packed weight register, a multiplier 1804, and an intermediate register 1806. The second stage 1810 includes an N - bit adder 1812, an accumulator register 1814, and an M - bit output register 1816.

[0220] If the indexed weight 1802 has a bipolar weight value of one (0b1), the value of the N - bit feature input can be passed through without modification. The multiplier 1804 includes a sign - flip unit 1805 to perform multiplication on the bipolar weight value of negative one (-1) represented by the bit value 0b0. A standard multiplier cannot be used because the result value would be zero. Instead, the sign - flip unit 1805 is used to perform a multiplication operation on the n - bit feature input 1801. This value can be stored in the intermediate register 1806 to be used as an input to the M - bit adder 1812, which adds the product to the value in the accumulator register 1814. The value in the accumulator register can be updated with the sum of the added result and the result value, and the result value can be output via the M - bit output register 1816.

[0221] Although bipolar binary weight values are shown, one embodiment supports both bipolar binary weights and ternary weights. With ternary weights, two bits can be used to represent the values (-1, 0, +1). The mapping between binary and ternary values can vary, and an embodiment can be configured to selectively use different mappings. For example, bipolar binary and ternary values can be mapped as shown in Table 5 below.

[0222] Table 5 - Exemplary Weight Mapping

[0223] Machine Value Binary Value Ternary Value 0b00 -1 -1 0b01 1 1 0b1X N / A 0

[0224] Alternative mappings between binary and ternary values can also be implemented. For example, one embodiment can use the mapping shown in Table 6.

[0225] Table 6 - Additional Exemplary Weight Mapping

[0226] Machine Value Binary Value Ternary Value 0b00 -1 0 0b01 1 1 0b11 N / A -1 0b10 N / A 0 or N / A

[0227] In the configuration of Table 6, bit [1] of the machine value is the sign bit, such that 0b11 represents (-1). In one embodiment, quaternary weights can be supported in the configuration shown in Table 6 by mapping 0b10 to the fourth value used by a quaternary - weight neural network.

[0228] Figure 19An exemplary multiplier according to an embodiment is shown. In one embodiment, a binary multiplier 1910 is provided that is configured to perform 1-bit by N-bit multiplication using 1-bit binary bipolar weights. The index weight 1802 is coupled to the NOT gate 1902 such that a weight value of 0b0 (-1) activates the sign flip unit 1805 to flip the sign of the N-bit feature input 1801. The nature of the sign flip varies based on the data type of the N-bit feature input. For integer and fixed-point representations, the sign flip unit 1805 performs a two's complement operation to flip the sign of the feature input. For floating-point representations, the sign bit of the value is flipped. As an alternative to using the NOT gate 1902, in one embodiment, the sign flip unit 1805 is configured with an active-low input.

[0229] One embodiment provides a ternary multiplier 1920 to implement multiplication via ternary index weights. The ternary multiplier 1920 includes a multiplexer 1904 and a sign flip unit 1805. In one embodiment, the multiplexer 1904 accepts the N-bit feature input at one input and the second input is tied to zero. The ternary multiplier 1920 is controlled by two bits of a ternary value. In the illustrated embodiment, bit 0[0] 1802A of the index weight represents the weight value, and bit 1[1] 1802B is the sign bit. In operation, the index weight bit [0] 1802A determines whether the value of the N-bit feature input 1801 or a zero value is provided to the sign flip unit 1805 via the multiplexer 1904. An index weight bit [0] 1802 value of 0b1 can pass the N-bit feature value, while a 0b0 value will pass a zero input. The index weight bit [1] 1802B determines whether the sign flip unit 1805 performs a sign flip or passes the input value without modification (e.g., sign bit flip or two's complement). As an alternative to the illustrated ternary multiplier 1920, in one embodiment, fused multiply-add logic can be implemented, where a zero value is handled by using the index weight bit [0] as an enable bit for an accumulator. In such an embodiment, when a zero input value is received, the value of the N-bit feature input 1801 is not added to the accumulator register.

[0230] Figure 20FIG. 2000 shows a flow chart of logic 2000 for fusing barrel shift accumulate instructions according to an embodiment. In one embodiment, the logic 2000 of the instruction shown is executed within a computing unit of a general purpose graphics processing unit as described herein to accelerate machine learning and neural network operations. In one embodiment, as shown at block 2002, the logic 2000 decodes a single instruction that specifies a plurality of operands including an input value and a reference to a binary or ternary weight value of a neural network. In one embodiment, the reference to the binary or ternary weight value of the neural network is an input register and an index to a location within the input register. The index location can be a single bit for binary weights and two bits for ternary weights. As shown at block 2004, the logic 2000 can then issue the single instruction for execution within a computing unit of the general purpose graphics processing unit. In response to the execution of the single instruction, the logic 2000 can generate a result based on the product of the feature input value and the weights.

[0231] Processing Architecture for Exemplary Ultra-Low Precision Neural Networks

[0232] In addition to 1-bit weights and N-bit features, fully binary neural networks can also be implemented where both weight and feature data are stored as binary values. Deterministic or stochastic binarization via equation (1) or equation (2) above can be used to binarize the weight and feature data. In some instances, fully binary neural networks can achieve inference accuracy similar to higher precision networks and significantly reduce memory storage and bandwidth requirements as well as computational complexity. Specifically, the dot product of a binary neural network can be performed via XNOR and population count operations. In conventional graphics processing logic, XNOR and population count operations are separate operations. Additionally, not all processing elements or computing units can support the population count function. To accelerate binary neural network operations, the embodiments described herein provide a fused XNOR and population count function to enable efficient high throughput convolution of binary neural networks.

[0233] Figure 21Shows logic for performing fused XNOR and population count operations according to an embodiment. In one embodiment, the fused XNOR and population count logic is included in a first stage 2100 of a binary input, M-bit output binary multiply-accumulate unit within a processing element of a GPGPU as described herein. The first stage 2100 includes a 1-bit feature input 2101 and a 1-bit weight input 2102, where the feature input and weight input have been binaryized to bipolar binary values of (-1, 1), where -1 is represented as 0b0. The fused XNOR and population count logic is included within a fused XNOR and population count unit 2104, which includes an XNOR unit 2103 and a population count unit 2105. The fused XNOR and population count unit 2104 outputs to an intermediate register 2106, which serves as an input to the second stage 1810 described above Figure 18 described above. In one embodiment, the fused XNOR and population count unit 2104 is included within all processing elements of a GPGPU. In one embodiment, only a subset of the processing elements within a GPGPU includes the fused XNOR and population count unit 2104.

[0234] Additional example graphics processing systems

[0235] The details of the embodiments described above can be incorporated into the graphics processing systems and devices described below. Figures 22 to 35 The graphics processing systems and devices of show alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0236] The details of the embodiments described above can be included in the graphics processing systems and apparatuses described below. Figures 22 to 35 The graphics processing systems and apparatuses of show alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0237] Figure 22 is a block diagram of a processing system 2200 according to an embodiment. In various embodiments, the system 2200 includes one or more processors 2202 and one or more graphics processors 2208, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2202 or processor cores 2207. In one embodiment, the system 2200 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device.

[0238] Embodiments of system 2200 may include or incorporate a server-based gaming platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 2200 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. The data processing system 2200 may also include a wearable device (such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled to, or integrated in, the wearable device. In some embodiments, the data processing system 2200 is a television or a set-top box device having one or more processors 2202 and a graphical interface generated by one or more graphics processors 2208.

[0239] In some embodiments, each of the one or more processors 2202 includes one or more processor cores 2207 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 2207 is configured to process a particular instruction set 2209. In some embodiments, the instruction set 2209 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The multiple processor cores 2207 may each process a different instruction set 2209, which may include instructions for facilitating the emulation of other instruction sets. The processor cores 2207 may also include other processing devices, such as a digital signal processor (DSP).

[0240] In some embodiments, the processor 2202 includes a cache memory 2204. Depending on the architecture, the processor 2202 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among the components of the processor 2202. In some embodiments, the processor 2202 also uses an external cache (e.g., a level 3 (L3) cache or a last-level cache (LLC)) (not shown), and known cache coherence techniques may be used to share the external cache among the processor cores 2207. Additionally, a register file 2206 is included in the processor 2202, and the processor may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 2202.

[0241] In some embodiments, the processor 2202 is coupled to a processor bus 2210, which is used to transfer communication signals, such as address, data, or control signals, between the processor 2202 and other components within the system 2200. In one embodiment, the system 2200 uses an exemplary 'hub' system architecture, including a memory controller hub 2216 and an input / output (I / O) controller hub 2230. The memory controller hub 2216 facilitates communication between the memory device and other components of the system 2200, while the I / O controller hub (ICH) 2230 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2216 is integrated within the processor.

[0242] The memory device 2220 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to be used as a processing memory. In one embodiment, the memory device 2220 can operate as the system memory of the system 2200 to store data 2222 and instructions 2221 for use when one or more processors 2202 execute an application or process. The memory controller hub 2216 is also coupled to an optional external graphics processor 2212, which can communicate with one or more graphics processors 2208 in the processor 2202 to perform graphics and media operations.

[0243] In some embodiments, the ICH 2230 enables peripheral components to be connected to the memory device 2220 and the processor 2202 via a high-speed I / O bus. The I / O peripherals include but are not limited to: an audio controller 2246, a firmware interface 2228, a wireless transceiver 2226 (e.g., Wi-Fi, Bluetooth), a data storage device 2224 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 2240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 2242 connect multiple input devices, such as a keyboard and mouse 2244 combination. A network controller 2234 can also be coupled to the ICH 2230. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2210. It should be understood that the system 2200 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways can also be used. For example, the I / O controller hub 2230 can be integrated within one or more processors 2202, or the memory controller hub 2216 and the I / O controller hub 2230 can be integrated within a discrete external graphics processor (such as the external graphics processor 2212).

[0244] Figure 23 is a block diagram of an embodiment of a processor 2300 having one or more processor cores 2302A through 2302N, an integrated memory controller 2314, and an integrated graphics processor 2308. Figure 23 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these. Processor 2300 may include additional cores up to and including additional core 2302N represented by the dashed box. Processor cores 2302A through 2302N each include one or more internal cache units 2304A through 2304N. In some embodiments, each processor core may also access one or more shared cache units 2306.

[0245] Internal cache units 2304A through 2304N and shared cache unit 2306 represent the cache memory hierarchy internal to processor 2300. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as the LLC before external memory. In some embodiments, cache coherence logic maintains coherence between cache units 2306 and 2304A through 2304N.

[0246] In some embodiments, processor 2300 may also include a group of one or more bus controller units 2316 and a system agent core 2310. One or more bus controller units 2316 manage a group of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). System agent core 2310 provides management functions for the various processor components. In some embodiments, system agent core 2310 includes one or more integrated memory controllers 2314 for managing access to various external memory devices (not shown).

[0247] In some embodiments, one or more of processor cores 2302A through 2302N include support for simultaneous multithreading. In such embodiments, system agent core 2310 includes components for coordinating and operating cores 2302A through 2302N during multithreaded processing. Additionally, system agent core 2310 may also include a power control unit (PCU) that includes logic and components for regulating the power states of processor cores 2302A through 2302N and graphics processor 2308.

[0248] In some embodiments, additionally, the processor 2300 further includes a graphics processor 2308 for performing graphics processing operations. In some embodiments, the graphics processor 2308 is coupled to the shared cache unit 2306 set and the system agent core 2310, and the system agent core includes one or more integrated memory controllers 2314. In some embodiments, the display controller 2311 is coupled to the graphics processor 2308 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2311 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2308 or the system agent core 2310.

[0249] In some embodiments, the ring interconnect 2312 is used to couple the internal components of the processor 2300. However, alternative interconnect units can be used, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques well known in the art. In some embodiments, the graphics processor 2308 is coupled to the ring interconnect 2312 via the I / O link 2313.

[0250] The exemplary I / O link 2313 represents at least one of a plurality of varieties of I / O interconnects, including package I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 2318 (such as an eDRAM module). In some embodiments, each of the processor cores 2302A to 2302N and the graphics processor 2308 use the embedded memory module 2318 as a shared last-level cache.

[0251] In some embodiments, the processor cores 2302A to 2302N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2302A to 2302N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 2302A to 2302N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2302A to 2302N are homogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, the processor 2300 can be implemented on one or more chips or implemented as a SoC integrated circuit with the components shown in addition to other components.

[0252] Figure 24is a block diagram of a graphics processor 2400, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and uses commands placed in the processor memory. In some embodiments, the graphics processor 2400 includes a memory interface 2414 for accessing memory. The memory interface 2414 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0253] In some embodiments, the graphics processor 2400 further includes a display controller 2402 for driving display output data to a display device 2420. The display controller 2402 includes hardware for one or more overlapping planes of the display and components of multi-layer video or user interface elements. In some embodiments, the graphics processor 2400 includes a video codec engine 2406 for encoding, decoding, or transcode media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0254] In some embodiments, the graphics processor 2400 includes a block image transfer (BLIT) engine 2404 for performing two-dimensional (2D) rasterizer operations, including for example bit boundary block transfer. However, in one embodiment, one or more components of the graphics processing engine (GPE) 2410 are used to perform 2D graphics operations. In some embodiments, the GPE 2410 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0255] In some embodiments, the GPE 2410 includes a 3D pipeline 2412 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions for 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2412 includes programmable and fixed function elements that perform various tasks within the elements of the 3D / media subsystem 2415 and / or the generated execution threads. Although the 3D pipeline 2412 can be used to perform media operations, embodiments of the GPE 2410 also include a media pipeline 2416 specifically for performing media operations, such as video post-processing and image enhancement.

[0256] In some embodiments, media pipeline 2416 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video deinterleaving, and video encode acceleration, instead of, or on behalf of, video codec engine 2406. In some embodiments, additionally, media pipeline 2416 also includes a thread generation unit to generate threads for execution on 3D / media subsystem 2415. The generated threads perform calculations for media operations on one or more graphics execution units included in 3D / media subsystem 2415.

[0257] In some embodiments, 3D / media subsystem 2415 includes logic for executing threads generated by 3D pipeline 2412 and media pipeline 2416. In one embodiment, the pipeline sends thread execution requests to 3D / media subsystem 2415, which includes thread dispatch logic for arbitrating and dispatching the requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 2415 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and for storing output data.

[0258] Additional Exemplary Graphics Processing Engines

[0259] Figure 25 is a block diagram of graphics processing engine 2510 of a graphics processor according to some embodiments. In one embodiment, graphics processing engine (GPE) 2510 is Figure 24 a version of GPE 2410 as shown. Figure 25 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to those described elsewhere herein, but are not limited to these. For example, 3D pipeline 2412 and media pipeline 2416 are shown. Media pipeline 2416 is optional in some embodiments of GPE 2510 and may not be explicitly included within GPE 2510. For example and in at least one embodiment, a separate media and / or image processor is coupled to GPE 2510. Figure 24 In some embodiments, 3D / media subsystem 2415 includes logic for executing threads generated by 3D pipeline 2412 and media pipeline 2416. In one embodiment, the pipeline sends thread execution requests to 3D / media subsystem 2415, which includes thread dispatch logic for arbitrating and dispatching the requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 2415 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and for storing output data.

[0260] In some embodiments, the GPE 2510 is coupled to or includes the command stream converter 2503, which provides a command stream to the 3D pipeline 2412 and / or the media pipeline 2416. In some embodiments, the command stream converter 2503 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command stream converter 2503 receives commands from the memory and sends these commands to the 3D pipeline 2412 and / or the media pipeline 2416. The commands are instructions fetched from a ring buffer storing commands for the 3D pipeline 2412 and the media pipeline 2416. In one embodiment, additionally, the ring buffer may further include a batch command buffer storing multiple batches of multiple commands. Commands for the 3D pipeline 2412 may also include references to data stored in the memory, such as but not limited to vertex and geometry data for the 3D pipeline 2412 and / or image data and memory objects for the media pipeline 2416. The 3D pipeline 2412 and the media pipeline 2416 process the commands by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to the execution unit array 2514.

[0261] In various embodiments, the 3D pipeline 2412 may execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2514. The graphics core array 2514 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2514 includes support for various 3D API shader languages and may execute multiple simultaneously executing threads associated with multiple shaders.

[0262] In some embodiments, the graphics core array 2514 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units include general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic may execute processing operations in parallel with or in combination with the general-purpose logic within the (multiple) processor cores 2207 or Figure 22 the cores 2302A to 2302N within Figure 23 .

[0263] Output data generated by threads executing on the graphics core array 2514 can output data to memory in the unified return buffer (URB) 2518. The URB 2518 can store data for multiple threads. In some embodiments, the URB 2518 can be used to send data between different threads executing on the graphics core array 2514. In some embodiments, the URB 2518 can additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 2520.

[0264] In some embodiments, the graphics core array 2514 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of the GPE 2510. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0265] The graphics core array 2514 is coupled to shared function logic 2520, which includes multiple resources shared among the graphics cores within the graphics core array. The shared functions within the shared function logic 2520 are hardware logic units that provide dedicated complementary functions to the graphics core array 2514. In various embodiments, the shared function logic 2520 includes, but is not limited to, sampler 2521, math 2522, and inter-thread communication (ITC) 2523 logic. Additionally, some embodiments implement one or more caches 2525 within the shared function logic 2520. The shared function is implemented in cases where the demand for a given dedicated function is not sufficient to be included within the graphics core array 2514. Instead, a single instance of the dedicated function is implemented as an independent entity within the shared function logic 2520 and shared among the execution resources within the graphics core array 2514. The exact set of functions shared among and included within the graphics core array 2514 varies between embodiments.

[0266] Figure 26 is a block diagram of a graphics processor 2600 provided by additional embodiments. Figure 26 Those elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0267] In some embodiments, the graphics processor 2600 includes a ring interconnect 2602, a pipeline front end 2604, a media engine 2637, and graphics cores 2680A through 2680N. In some embodiments, the ring interconnect 2602 couples the graphics processor to other processing units, including other graphics processors or one or more general processor cores. In some embodiments, the graphics processor is one of multiple processors integrated within a multi-core processing system.

[0268] In some embodiments, the graphics processor 2600 receives multiple batches of commands via the ring interconnect 2602. The incoming commands are interpreted by the command stream converter 2603 in the pipeline front end 2604. In some embodiments, the graphics processor 2600 includes scalable execution logic for performing 3D geometry processing and media processing via the (multiple) graphics cores 2680A through 2680N. For 3D geometry processing commands, the command stream converter 2603 supplies the commands to the geometry pipeline 2636. For at least some of the media processing commands, the command stream converter 2603 supplies the commands to the video front end 2634, which is coupled to the media engine 2637. In some embodiments, the media engine 2637 includes a video quality engine (VQE) 2630 for video and image post-processing and a multi-format encoding / decoding (MFX) 2633 engine for providing hardware-accelerated encoding and decoding of media data. In some embodiments, the geometry pipeline 2636 and the media engine 2637 each generate execution threads for the thread execution resources provided by at least one of the graphics cores 2680A.

[0269] In some embodiments, the graphics processor 2600 includes scalable thread execution resource characterization module cores 2680A through 2680N (sometimes referred to as core slices), each of which has multiple sub-cores 2650A through 2650N, 2660A through 2660N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2600 can have any number of graphics cores 2680A through 2680N. In some embodiments, the graphics processor 2600 includes a graphics core 2680A that has at least a first sub-core 2650A and a second sub-core 2660A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2650A). In some embodiments, the graphics processor 2600 includes multiple graphics cores 2680A through 2680N, each of which includes a set of first sub-cores 2650A through 2650N and a set of second sub-cores 2660A through 2660N. Each sub-core in the set of first sub-cores 2650A through 2650N includes at least a first set of execution units 2652A through 2652N and media / texture samplers 2654A through 2654N. Each sub-core in the set of second sub-cores 2660A through 2660N includes at least a second set of execution units 2662A through 2662N and samplers 2664A through 2664N. In some embodiments, each of the sub-cores 2650A through 2650N, 2660A through 2660N shares a set of shared resources 2670A through 2670N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0270] Additional Exemplary Execution Units

[0271] Figure 27 shows thread execution logic 2700, which includes an array of processing elements employed in some embodiments. Figure 27 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to those described elsewhere herein, but are not limited to these.

[0272] In some embodiments, thread execution logic 2700 includes a shader processor 2702, a thread dispatcher 2704, an instruction cache 2706, a scalable array of execution units including multiple execution units 2708A through 2708N, a sampler 2710, a data cache 2712, and a data port 2714. In one embodiment, the scalable array of execution units may be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2708A, 2708B, 2708C, 2708D, up to 2708N-1 and 2708N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 2700 includes one or more connections to memory (such as system memory or cache memory) via instruction cache 2706, data port 2714, sampler 2710, and one or more of the execution unit arrays 2708A through 2708N. In some embodiments, each execution unit (e.g., 2708A) is an independent programmable general-purpose computing unit capable of executing multiple synchronous hardware threads and processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2708A through 2708N is scalable to include any number of individual execution units.

[0273] In some embodiments, execution units 2708A through 2708N are primarily used to execute shader programs. Shader processor 2702 may process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2704. In one embodiment, the thread dispatcher includes logic for arbitrating requests for threads initiated from the graphics and media pipelines and instantiating the requested threads on one or more of execution units 2708A through 2708N. For example, a geometry pipeline (e.g., Figure 26 of 2636) may dispatch vertex processing, tessellation, or geometry processing threads to thread execution logic 2700 ( Figure 27)Process. In some embodiments, the thread dispatcher 2704 may also process runtime thread generation requests from executing shader programs.

[0274] In some embodiments, execution units 2708A through 2708N support an instruction set (which includes native support for many standard 3D graphics shader instructions), enabling shader programs from graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal translation. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of execution units 2708A through 2708N is capable of performing multi-issue single instruction multiple data (SIMD), and multi-threaded operations can achieve an efficient execution environment in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single-precision floating-point, and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations, execution is multi-issue per clock. When waiting for data from one of the memory or shared functions, the dependency logic within execution units 2708A through 2708N puts the waiting threads to sleep until the requested data has returned. While the waiting threads are sleeping, the hardware resources may be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution units can perform operations on pixel shaders, fragment shaders, or another type of shader program including a different vertex shader.

[0275] Each of execution units 2708A through 2708N operates on an array of data elements. The number of data elements is the "execution size", or the number of lanes of an instruction. Execution lanes are the logical units that perform data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2708A through 2708N support integer and floating-point data types.

[0276] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (quad-word (QW) sized data elements), eight separate 32-bit compressed data elements (double-word (DW) sized data elements), sixteen separate 16-bit compressed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0277] One or more internal instruction caches (e.g., 2706) are included in the thread execution logic 2700 to cache the thread instructions of the execution unit. In some embodiments, one or more data caches (e.g., 2712) are included for caching thread data during thread execution. In some embodiments, a sampler 2710 is included for providing texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2710 includes specialized texture or media sampling functions to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0278] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2700 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2702 is called to further compute the output information and cause the results to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes the values of the vertex attributes, which are interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2702 then executes the pixel or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 2702 dispatches the thread to an execution unit (e.g., 2708A) via the thread dispatcher 2704. In some embodiments, the shader processor 2702 uses the texture sampling logic in the sampler 2710 to access the texture data in the texture map stored in memory. Arithmetic operations on the texture data and the input geometric data compute the pixel color data for each geometric fragment, or discard one or more pixels without further processing.

[0279] In some embodiments, data port 2714 provides a memory access mechanism for thread execution logic 2700 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2714 includes or is coupled to one or more cache memories (e.g., data cache 2712) to cache data via the data port for memory access.

[0280] Figure 28 is a block diagram showing a graphics processor instruction format 2800 according to some embodiments. In one or more embodiments, the graphics processor execution units support an instruction set with instructions of multiple formats. The solid boxes show the components that are typically included in the execution unit instructions, while the dashed boxes include optional components or components only included in a subset of the instructions. In some embodiments, the described and shown instruction format 2800 is a macro-instruction as they are the instructions supplied to the execution unit, as opposed to the micro-operations generated from instruction decoding (once the instruction is processed).

[0281] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 2810. A 64-bit compact instruction format 2830 can be used for some instructions based on the selected instructions, multiple instruction options, and the number of operands. The native 128-bit instruction format 2810 provides access to all instruction options, while some options and operations are restricted in the 64-bit compact instruction format 2830. The native instructions available in the 64-bit compact instruction format 2830 vary according to embodiments. In some embodiments, a set of index values in the index field 2813 is used to partially compress the instruction. The execution unit hardware references a set of compression tables based on the index values and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 2810.

[0282] For each format, the instruction opcode 2812 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, which represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2814 enables control of certain execution options, such as channel selection (e.g., predication) and data channel ordering (e.g., blending). For instructions in the 128-bit instruction format 2810, the execution size field 2816 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2816 is not available for the 64-bit compact instruction format 2830.

[0283] Some execution unit instructions have up to three operands, including two source operands (src0 2820, src1 2822) and one destination 2818. In some embodiments, the execution unit supports dual-destination instructions, where one of these destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2824), where the instruction opcode 2812 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0284] In some embodiments, the 128-bit instruction format 2810 includes an access / address mode field 2826, and the access / address mode information, for example, defines whether to use direct register addressing mode or indirect register addressing mode. When using the direct register addressing mode, the register addresses of one or more operands are directly provided by bits in the instruction.

[0285] In some embodiments, the 128-bit instruction format 2810 includes an access / address mode field 2826, and the access / address mode field specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes, including 16-byte aligned access mode and 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0286] In one embodiment, the address mode part of the access / address mode field 2826 determines whether the instruction uses direct addressing or indirect addressing. When using the direct register addressing mode, the bits in the instruction directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate number field in the instruction.

[0287] In some embodiments, instructions are grouped based on the 28-bit opcode field to simplify opcode decoding 2840. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of the opcode. The exact opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2842 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2842 shares the five most significant bits (MSBs), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2844 (e.g., call, jmp) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2846 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2848 includes per-component arithmetic instructions (e.g., add, mul) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2848 performs arithmetic operations in parallel across data channels. The vector math group 2850 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot product operations.

[0288] Additional Exemplary Graphics Pipelines

[0289] Figure 29 is a block diagram of a graphics processor 2900 according to another embodiment. Figure 29 Those elements having the same reference numbers (or names) as the elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0290] In some embodiments, the graphics processor 2900 includes a graphics pipeline 2920, a media pipeline 2930, a display engine 2940, thread execution logic 2950, and a render output pipeline 2970. In some embodiments, the graphics processor 2900 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or is controlled via commands issued to the graphics processor 2900 via the ring interconnect 2902. In some embodiments, the ring interconnect 2902 couples the graphics processor 2900 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2902 are interpreted by a command stream converter 2903, which supplies instructions to individual components of the graphics pipeline 2920 or the media pipeline 2930.

[0291] In some embodiments, the command stream converter 2903 directs the operation of a vertex fetcher 2905, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2903. In some embodiments, the vertex fetcher 2905 provides vertex data to a vertex shader 2907, which performs coordinate space transformations and lighting operations on each vertex. In some embodiments, the vertex fetcher 2905 and the vertex shader 2907 execute vertex processing instructions by dispatching execution threads to execution units 2952A through 2952B via a thread dispatcher 2931.

[0292] In some embodiments, execution units 2952A through 2952B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 2952A through 2952B have attached L1 caches 2951, which are dedicated to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0293] In some embodiments, the graphics pipeline 2920 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operation. A programmable domain shader 817 provides a backend evaluation of the tessellation output. The tessellator 2913 operates in the direction of the hull shader 2911 and includes specialized logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2920. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 2911, tessellator 2913, domain shader 2917) can be bypassed.

[0294] In some embodiments, a complete geometric object can be processed by the geometry shader 2919 via one or more threads dispatched to the execution units 2952A - 2952B, or can proceed directly to the clipper 2929. In some embodiments, the geometry shader operates on entire geometric objects (as opposed to vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2919 receives input from the vertex shader 2907. In some embodiments, the geometry shader 2919 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0295] Before rasterization, the clipper 2929 processes vertex data. The clipper 2929 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 2973 in the render output pipeline 2970 dispatches pixel shaders to convert geometric objects into their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2950. In some embodiments, an application can bypass the rasterizer and depth test component 2973 and access the un-rasterized vertex data via the egress unit 2923.

[0296] The graphics processor 2900 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the major components of the graphics processor. In some embodiments, the execution units 2952A - 2952B and associated cache(s) 2951, texture and media sampler 2954, and texture / sampler cache 2958 are interconnected via a data port 2956 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 2954, caches 2951, 2958, and execution units 2952A - 2952B each have separate memory access paths.

[0297] In some embodiments, the rendering output pipeline 2970 includes a rasterizer and depth test component 2973 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated render cache 2978 and depth cache 2979 are also available in some embodiments. Pixel operation component 2977 performs pixel-based operations on the data, although in some instances, pixel operations associated with 2D operations (e.g., bit blit image transfer with blending) are performed by 2D engine 2941 or, at display time, by display controller 2943 using overlapping display planes instead. In some embodiments, shared L3 cache 2975 is available to all graphics components, allowing data to be shared without using the main system memory.

[0298] In some embodiments, the graphics processor media pipeline 2930 includes a media engine 2937 and a video front end 2934. In some embodiments, the video front end 2934 receives pipeline commands from command stream converter 2903. In some embodiments, the media pipeline 2930 includes a separate command stream converter. In some embodiments, the video front end 2934 processes media commands before sending the commands to media engine 2937. In some embodiments, media engine 2937 includes a thread generation function for generating threads for dispatch to thread execution logic 2950 via thread dispatcher 2931.

[0299] In some embodiments, the graphics processor 2900 includes a display engine 2940. In some embodiments, the display engine 2940 is external to the processor 2900 and is coupled to the graphics processor via a ring interconnect 2902 or some other interconnect bus or mechanism. In some embodiments, the display engine 2940 includes a 2D engine 2941 and a display controller 2943. In some embodiments, the display engine 2940 contains dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2943 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0300] In some embodiments, the graphics pipeline 2920 and the media pipeline 2930 may be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API dispatches dedicated to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for all of the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

[0301] Additional Exemplary Graphics Pipeline Programming

[0302] Figure 30A is a block diagram showing a graphics processor command format 3000 according to some embodiments. Figure 30B is a block diagram showing a graphics processor command sequence 3010 according to an embodiment. Figure 30A The solid boxes in show components that are typically included in a graphics command, while the dashed boxes include components that are optional or included only in a subset of the graphics commands. Figure 30A An exemplary graphics processor command format 3000 includes a target client 3002 for identifying the command, a command operation code (opcode) 3004, and a data field 3006 for the relevant data for the command. Some commands also include a sub-opcode 3005 and a command size 3008.

[0303] In some embodiments, client 3002 defines the client unit of a graphics device that processes command data. In some embodiments, the graphics processor command parser examines the client fields of each command to adjust further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 3004 and the sub-opcode 3005 (if present) to determine the operation to be performed. The client unit uses the information within the data field 3006 to execute the command. For some commands, an explicit command size 3008 is expected to define the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned by a multiple of the double-word length.

[0304] Figure 30B The flow diagram in FIG. shows an exemplary graphics processor command sequence 3010. In some embodiments, software or firmware of a data processing system characterized by an embodiment of the graphics processor uses a version of the shown command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, and the embodiments are not limited to these specific commands or this command sequence. Also, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the command sequence in at least a partially concurrent manner.

[0305] In some embodiments, the graphics processor command sequence 3010 may begin with a pipeline dump clear command 3012 to cause any active graphics pipeline to complete the current outstanding commands for that pipeline. In some embodiments, the 3D pipeline 3022 and the media pipeline 3024 do not operate concurrently. The pipeline dump clear is performed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline dump clear, the command parser for the graphics processor will stop command processing until the active drawing engine completes the outstanding operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be dumped to memory. In some embodiments, the pipeline dump clear command 3012 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0306] In some embodiments, the pipeline select command 3013 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 3013 is only required once in an execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, the pipeline dump clear command 3012 is required just before a pipeline switch via the pipeline select command 3013.

[0307] In some embodiments, the pipeline control command 3014 is configured to operate the graphics pipeline and to program the 3D pipeline 3022 and the media pipeline 3024. In some embodiments, the pipeline control command 3014 configures the pipeline state of the active pipeline. In one embodiment, the pipeline control command 3014 is used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0308] In some embodiments, the return buffer status command 3016 is used to configure a set of return buffers for the respective pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers into which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross-thread communication. In some embodiments, the return buffer status command 3016 includes selecting the size and number of return buffers for a set of pipeline operations.

[0309] The remaining commands in the command sequence differ based on the active pipeline being used. Based on the pipeline determination 3020, the command sequence is customized for the 3D pipeline 3022 starting with the 3D pipeline state 3030, or for the media pipeline 3024 starting at the media pipeline state 3040.

[0310] The commands for the 3D pipeline state 3030 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 3030 commands can also selectively disable or bypass specific pipeline elements if those elements will not be used.

[0311] In some embodiments, the 3D primitive 3032 command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via the 3D primitive 3032 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 3032 command data to generate a plurality of vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 3032 command is used to perform vertex operations on 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 3022 dispatches shader execution threads to the graphics processor execution units.

[0312] In some embodiments, the 3D pipeline 3022 is triggered via the execution of a 3034 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via the 'go' or 'kick' commands in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution in order to clear a command sequence via a graphics pipeline dump. The 3D pipeline will perform geometric processing on the 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. For these operations, additional commands for controlling pixel coloring and pixel backend operations may also be included.

[0313] In some embodiments, when performing media operations, the graphics processor command sequence 3010 follows the media pipeline 3024 path. Generally, the specific uses and ways of programming the media pipeline 3024 depend on the media or computing operations to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and resources provided by one or more general-purpose processing cores can be used to perform media decoding wholly or in part. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to rendering graphics primitives.

[0314] In some embodiments, the media pipeline 3024 is configured in a manner similar to the 3D pipeline 3022. A set of commands for configuring the media pipeline state 3040 are dispatched or placed into a command queue, before the media object commands 3042. In some embodiments, the media pipeline state 3040 includes data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state 3040 also supports the use of one or more pointers for "indirect" state elements that contain a batch of state settings.

[0315] In some embodiments, the media object commands 3042 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers that contain video data to be processed. In some embodiments, all media pipeline states must be valid before the media object commands 3042 are issued. Once the pipeline state is configured and the media object commands 3042 are queued, the media pipeline 3024 is triggered via an execute 3044 command or an equivalent execution event (e.g., a register write). The output from the media pipeline 3024 can then be post-processed by operations provided by the 3D pipeline 3022 or the media pipeline 3024. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0316] Additional Exemplary Graphics Software Architectures

[0317] Figure 31 An exemplary graphics software architecture of a data processing system 3100 is shown in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 3110, an operating system 3120, and at least one processor 3130. In some embodiments, the processor 3130 includes a graphics processor 3132 and one or more general-purpose processor cores 3134. The graphics application 3110 and the operating system 3120 each execute in the system memory 3150 of the data processing system.

[0318] In some embodiments, the 3D graphics application 3110 includes one or more shader programs that include shader instructions 3112. The shader language instructions can be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3114 that are in a machine language suitable for execution by the general-purpose processor cores 3134. The application also includes graphics objects 3116 defined by vertex data.

[0319] In some embodiments, the operating system 3120 is from Microsoft Corporation operating system, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a Linux kernel variant. The operating system 3120 may support a graphics API 3122, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 3120 uses a front-end shader compiler 3124 to compile any shader instructions 3112 in HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 3110, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 3112 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by the Vulkan API.

[0320] In some embodiments, the user-mode graphics driver 3126 includes a backend shader compiler 3127 for converting the shader instructions 3112 into a hardware-specific representation. When the OpenGL API is in use, the shader instructions 3112 in the high-level GLSL language are passed to the user-mode graphics driver 3126 for compilation. In some embodiments, the user-mode graphics driver 3126 uses the operating system kernel-mode function 3128 to communicate with the kernel-mode graphics driver 3129. In some embodiments, the kernel-mode graphics driver 3129 communicates with the graphics processor 3132 to dispatch commands and instructions.

[0321] Additional Exemplary IP Core Implementations

[0322] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within the processor. When read by a machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of the logic of an integrated circuit and may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine for fabricating the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0323] Figure 32is a block diagram showing an IP core development system 3200 that can be used to fabricate integrated circuits to perform operations according to an embodiment. The IP core development system 3200 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 3230 can generate a software simulation 3210 of an IP core design using a high-level programming language (e.g., C / C++). The software simulation 3210 can be used to design, test, and verify the behavior of the IP core using a simulation model 3212. The simulation model 3212 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3215 can then be created or synthesized by the simulation model 3212. The RTL design 3215 is an abstraction of the behavior of an integrated circuit (including associated logic executed using modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 3215, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0324] The RTL design 3215 or an equivalent can be further synthesized by the design facility into a hardware model 3220, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 3240 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 3265. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 3250 or a wireless connection 3260. The manufacturing facility 3265 can then fabricate an integrated circuit at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0325] Additional Exemplary System-on-Chip Integrated Circuits

[0326] Figures 33 to 35 Shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to those shown, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0327] Figure 33is a block diagram showing an exemplary system - on - chip integrated circuit 3300 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 3300 includes one or more application processors 3305 (e.g., CPUs), at least one graphics processor 3310, and may additionally include an image processor 3315 and / or a video processor 3320, any of which may be a modular IP core from the same or multiple different design facilities. The integrated circuit 3300 includes peripheral or bus logic, including a USB controller 3325, a UART controller 3330, an SPI / SDIO controller 3335 and an 2 S / I 2 C controller 3340. Additionally, the integrated circuit may also include a display device 3345, which is coupled to one or more of a high - definition multimedia interface (HDMI) controller 3350 and a mobile industry processor interface (MIPI) display interface 3355. Storage may be provided by a flash memory subsystem 3360 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 3365 to access SDRAM or SRAM memory devices. Additionally, some integrated circuits also include an embedded security engine 3370.

[0328] Figure 34 is a block diagram showing an exemplary graphics processor 3410 of a system - on - chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3410 may be Figure 33 a variant of the graphics processor 3310. The graphics processor 3410 includes a vertex processor 3405 and one or more fragment processors 3415A through 3415N (e.g., 3415A, 3415B, 3415C, 3415D, up to 3415N - 1 and 3415N). The graphics processor 3410 can execute different shader programs via separate logic such that the vertex processor 3405 is optimized to perform the operations of a vertex shader program, while one or more of the fragment processors 3415A through 3415N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. The vertex processor 3405 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (multiple) fragment processors 3415A through 3415N use the primitives and vertex data generated by the vertex processor 3405 to produce a frame buffer that is displayed on a display device. In one embodiment, the (multiple) fragment processors 3415A through 3415N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0329] Additionally, the graphics processor 3410 further includes one or more memory management units (MMUs) 3420A to 3420B, one or more caches 3425A to 3425B, and (multiple) circuit interconnections 3430A to 3430B. One or more MMUs 3420A to 3420B provide virtual-to-physical address mapping for the graphics processor 3410 to the vertex processor 3405 and / or one or more fragment processors 3415A to 3415N. In addition to vertex or image / texture data stored in one or more caches 3425A to 3425B, the virtual-to-physical address mapping may also reference vertex or image / texture data stored in memory. In one embodiment, one or more MMUs 3425A to 3425B may be synchronized with one or more MMUs included in other MMUs within the system, including one or more MMUs associated with Figure 33 one or more application processors 3305, image processors 3315, and / or video processors 3320 of, such that each processor 3305 to 3320 may participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnections 3430A to 3430B enable the graphics processor 3410 to interact with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0330] Figure 35 is a block diagram showing an additional exemplary graphics processor 3510 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3510 may be Figure 33 a variant of the graphics processor 3310. The graphics processor 3510 includes Figure 34 one or more MMUs 3420A to 3420B, caches 3425A to 3425B, and circuit interconnections 3430A to 3430B of the integrated circuit 3400 of.

[0331] The graphics processor 3510 includes one or more shader cores 3515A through 3515N (e.g., 3515A, 3515B, 3515C, 3515D, 3515E, 3515F, up to 3515N-1 and 3515N), the one or more shader cores providing a unified shader core architecture where a single core or type of core can execute all types of programmable shader code including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary in embodiments and implementations. Additionally, the graphics processor 3510 also includes an inter-core task manager 3505, the inter-core task manager acting as a thread dispatcher for dispatching execution threads to the one or more shader cores 3515A through 3515N and a tiling unit 3518 for accelerating tiling operations for tile-based rendering, where the rendering operations of a scene are subdivided in image space, e.g., to take advantage of local spatial coherence within the scene or to optimize the use of internal caches.

[0332] The following clauses and / or examples relate to particular embodiments or examples thereof. Details of the examples can be used anywhere in one or more embodiments. The various features of different embodiments or examples can be combined in different ways with some of the features included and other features excluded to suit various different applications. Examples can include a subject matter such as a method, an apparatus for performing actions of the method, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform actions of the method or actions of a device or system according to the embodiments and examples described herein. The various components can be apparatuses for performing the described operations or functions.

[0333] One embodiment provides a computing device for performing machine learning operations, the device including: a decoding unit for decoding a single instruction into a decoded instruction that specifies a plurality of operands including input values and quantization weight values associated with a neural network; an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, where, to execute the decoded instruction, the barrel shifter shifts an input value by a quantization weight value to generate a shifted input value, and the adder adds the shifted input value to a value stored in the accumulator register and updates the value stored in the accumulator register.

[0334] One embodiment provides a method of performing machine learning operations, the method comprising: decoding a single instruction specifying a plurality of operands, the operands specifying data including input values and weight values of a neural network; issuing the single instruction for execution within a computing unit of a general purpose graphics processing unit; and in response to execution of the single instruction, generating a result based on shifting the input values by the weight values of the neural network and adding the shifted values to a value stored in an accumulation register.

[0335] One embodiment provides a data processing system, the data processing system comprising: a non-transitory machine-readable medium for storing instructions to be executed by one or more processors of the data processing system; and a general purpose graphics processing unit comprising: a decoding unit for decoding a single instruction into a decoded instruction, the single instruction specifying a plurality of operands including input values and quantized weight values associated with a neural network; and an arithmetic logic unit comprising a barrel shifter, an adder, and an accumulation register, wherein to execute the decoded instruction, the barrel shifter shifts the input values by the quantized weight values to generate shifted input values, and the adder adds the shifted input values to a value stored in the accumulation register and updates the value stored in the accumulation register.

[0336] The embodiments described herein refer to specific configurations of hardware, such as application specific integrated circuits (ASICs), which are configured to perform certain operations or have a predetermined function. Such electronic devices typically include a set of one or more processors coupled to one or more other components (e.g., one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboard, touch screen, and / or display), and network connectors). The coupling of the set of processors to the other components is typically achieved through one or more buses and bridges (also referred to as bus controllers). The storage device and the signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on the set of one or more processors of the electronic device.

[0337] Of course, different combinations of software, firmware, and / or hardware can be used to implement one or more portions of the embodiments. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the embodiments may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in detail so as not to obscure the inventive subject matter of the embodiments. Accordingly, the scope and spirit of the present invention should be determined according to the following claims.

Claims

1. A computing device for performing machine learning operations, the device comprises: a decoding unit for decoding a single instruction into a decoded instruction, the decoded instruction specifying a plurality of operands, the plurality of operands including an input value and a quantized weight value associated with a neural network, wherein the quantized weight value is an exponential value of a neural network weight, and the neural network weight is constrained to be a power value of a base value; and an arithmetic logic unit comprising a barrel shifter, an adder, and an accumulator register, wherein, to execute the decoded instruction, the barrel shifter shifts the input value by the quantized weight value to generate a shifted input value, and the adder adds the shifted input value to a value stored in the accumulator register and updates the value stored in the accumulator register.

2. The computing device according to claim 1, additionally comprising an output register for storing an output value of the single instruction.

3. The computing device according to claim 1, wherein, the neural network weight is constrained to be a power value of two.

4. The computing device according to claim 3, wherein, an exponent associated with the quantized weight value is input to the barrel shifter.

5. The computing device according to claim 4, wherein, the input value is a multi-bit input value.

6. The computing device according to claim 1, wherein, the computing device comprises a plurality of arithmetic logic units configured as single instruction multiple data computing units.

7. The computing device according to claim 6, wherein, the single instruction multiple data computing unit is used to execute operations of multiple threads of a single instruction multiple thread computing architecture.

8. The computing device according to claim 1, wherein, the computing device is a system-on-chip integrated circuit including a media processor and a vision processor.

9. The computing device according to claim 8, wherein, the media processor is used to decode a plurality of simultaneous video streams and output the plurality of decoded video streams to on-chip memory.

10. The computing device according to claim 9, wherein, the vision processor is used to parse the decoded video stream to perform processing operations on frames of the decoded video stream via a trained image recognition model associated with the neural network.

11. A method for performing machine learning operations, the method comprises: decoding a single instruction specifying a plurality of operands, the operands specifying data including an input value of a neural network and a quantized weight value, wherein the quantized weight value is an exponential value of a neural network weight, and the neural network weight is constrained to be a power value of a base value; issuing the single instruction for execution within a computing unit of a general purpose graphics processing unit; and in response to the execution of the single instruction, generating a result based on shifting the input value by the quantized weight value of the neural network and adding the shifted value to a value stored in an accumulator register.

12. The method according to claim 11, It is characterized in that the neural network weights are constrained to be powers of two.

13. The method according to claim 12, it is characterized in that shifting the input value by the quantized weight value of the neural network includes shifting the input value via barrel shifter logic, and the quantized weight value input to the barrel shifter logic is the exponential value of the neural network weights.

14. A general-purpose graphics processor comprising means for performing the method according to any one of claims 11-13.

15. A data processing system, comprising: a non-transitory machine-readable medium for storing instructions executed by one or more processors of the data processing system; and a general-purpose graphics processing unit comprising: a decoding unit for decoding a single instruction into a decoded instruction, the decoded instruction specifying a plurality of operands, the plurality of operands including an input value and a quantized weight value associated with a neural network, wherein the quantized weight value is the exponential value of the neural network weights, the neural network weights being constrained to be powers of a base value; and an arithmetic logic unit comprising a barrel shifter, an adder, and an accumulator register, wherein, in order to execute the decoded instruction, the barrel shifter shifts the input value by the quantized weight value to generate a shifted input value, and the adder adds the shifted input value to a value stored in the accumulator register and updates the value stored in the accumulator register.

16. The data processing system according to claim 15, wherein the general-purpose graphics processing unit comprises an output register for storing an output value of the single instruction.

17. The data processing system according to claim 15, it is characterized in that the neural network weights are constrained to be powers of two.

18. The data processing system according to claim 17, it is characterized in that the exponent associated with the quantized weight value is input to the barrel shifter.

19. The data processing system according to claim 18, it is characterized in that the input value is a multi-bit input value.

20. The data processing system according to claim 15, it is characterized in that the general-purpose graphics processing unit comprises a plurality of arithmetic logic units configured as single instruction multiple data computing units.

21. The data processing system according to claim 20, it is characterized in that the single instruction multiple data computing unit is used to perform operations of multiple threads of a single instruction multiple thread computing architecture.

22. The data processing system according to claim 15, it is characterized in that the general-purpose graphics processing unit is a system-on-chip integrated circuit including a media processor and a visual processor.

23. The data processing system according to claim 22, it is characterized in that the media processor is used to decode a plurality of simultaneous video streams and output the decoded several video streams to on-chip memory.

24. The data processing system according to claim 23, it is characterized in that The visual processor is used to parse the decoded video stream to perform processing operations on the frames of the decoded video stream via a trained image recognition model associated with the neural network.

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