Method and apparatus for improved etch stop or hard mask layer for memory devices

Abstract

The present invention relates to methods and apparatus for improved etch stop layers or hard mask layers for memory devices. In one embodiment, an apparatus comprises: an etch stop layer, the etch stop layer comprising one or more of hafnium, silicon or magnesium, and aluminum oxide; and a channel formed through one or more layers deposited on the etch stop layer, the channel extending to the etch stop layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of computer development and, more particularly, to memory devices. Background Art

[0002] A memory device may include one or more semiconductor memory chips, each of which includes one or more memory cell arrays for storing data. During the manufacture of a memory device, various layers may be deposited on a substrate. The manufacture may also include applying a mask and etching through portions of one or more layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A horizontal cross-section of a portion of a memory chip having a blanket etch stop layer is shown in accordance with certain embodiments.

[0004] Figure 2 A ternary phase diagram for predicted crystallization temperatures for various combinations of hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and silicon dioxide (SiO 2 ) is shown according to certain embodiments.

[0005] Figure 3 A ternary phase diagram depicting specific composition regions of an etch stop layer that provide good crystallization temperature and wet etch rate according to certain embodiments is shown.

[0006] Figure 4 A ternary phase diagram for predicted wet etch rates for various combinations of magnesium oxide (MgO), aluminum oxide (Al2O3), and hafnium oxide (HfO2) is shown in accordance with certain embodiments.

[0007] Figure 5 A ternary phase diagram for predicted etch rates for various combinations of aluminum oxide (Al2O3), magnesium oxide (MgO), and silicon dioxide (SiO2) is shown in accordance with certain embodiments.

[0008] Figure 6 An exemplary process for fabricating a memory device having an etch stop layer comprising a combination of aluminum oxide and one or more of hafnium, silicon, or magnesium is shown.

[0009] Figure 7 An exemplary process for manufacturing a memory device using a hard mask employing magnesium oxide (MgO) or magnesium aluminum oxide (MgAl2O4) is shown in accordance with certain embodiments.

[0010] Figure 8 An exemplary portion of a NAND flash memory array is shown in accordance with certain embodiments.

[0011] Fig. 9 A block diagram illustrating components of a computer system according to certain embodiments is shown.

[0012] Fig.10 A horizontal cross-section of a portion of a memory chip having a discontinuous etch stop layer in accordance with certain embodiments is shown.

[0013] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0014] The concept of each embodiment is applicable to the memory device used in any suitable computer system. The example of the system in which the teaching of the present disclosure can be used includes desktop computer systems, server computer systems, storage systems, handheld devices, tablet computers, other thin notebooks, system on chip (SOC) devices and embedded applications. Some examples of handheld devices include cellular phones, digital cameras, media players, personal digital assistants (PDAs) and handheld PCs. Embedded applications can include microcontrollers, digital signal processors (DSPs), SOCs, network computers (NetPCs), set-top boxes, network hubs, wide area networks (WAN) switches or any other system that can perform the functions and operations taught below. The various embodiments of the present disclosure can be applied in any suitable computing environment, such as personal computing devices, servers, mainframes, cloud computing service provider infrastructures, data centers, communication service provider infrastructures (e.g., one or more parts of an evolved packet kernel) or other environments including one or more computing devices.

[0015] Figure 1A horizontal cross section of a portion of a memory chip 100 with a uniformly thick etch stop layer 108 according to a particular embodiment is shown. In various embodiments, the memory chip 100 may include a 3D NAND flash memory array, but the teachings of the present disclosure may also be applied to any suitable semiconductor device. The memory chip 100 includes a stack (tier) formed by alternating polysilicon layers 102 and dielectric material layers 104, the dielectric material being, for example, an oxide (e.g., silicon dioxide), silicate glass, a low-k insulator (e.g., silicon oxycarbide), or other suitable dielectric materials. These layers are arranged on the memory chip 100 in a substantially horizontal manner. In a particular embodiment, these layers may be formed by deposition on a substrate 112 (there may be one or more other intermediate layers formed between the stack and the substrate, such as an etch stop layer 108, one or more lower metal layers, or other suitable layers). The polysilicon layer or dielectric layer of the stack may be formed using any suitable deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or other suitable deposition process.

[0016] In various embodiments, there may be any suitable number of polysilicon layers 102 and dielectric layers 104 in the stack of memory chip 100. Memory cells of memory chip 100 may be formed in polysilicon layers 102. In certain embodiments, multiple polysilicon layers 102 (e.g., a majority of polysilicon layers) are further processed to form active word lines of a memory array (one or more word lines are formed in each polysilicon layer 102). One or more other polysilicon layers 102 may be used to form dummy word lines and / or source and drain select gates.

[0017] Although the present disclosure focuses on a stack comprising alternating polysilicon layers 102 and dielectric layers 104, any of the embodiments described herein may employ layers comprising any suitable conductive material or employ layers comprising polysilicon and one or more other materials in place of polysilicon layers. Thus, the stack may include alternating layers of dielectric material and any suitable conductive layers (i.e., layers that (at least partially) comprise a conductive material such as polysilicon, tungsten, other metals, or other suitable conductive materials). In particular embodiments, the stack may be formed by depositing alternating layers of silicon nitride and dielectric material. In some embodiments, during manufacture of the memory device 100, at least a portion of the silicon nitride may be dug out and replaced with a conductive material. In particular embodiments, the stack may be formed using any suitable alternating layers to form an array of replacement gates or an array of charge trapping NAND memory cells.

[0018] The substrate 112 may include any suitable solid material, to which another material layer may be applied. For example, the substrate 112 may be a thin sheet of one or more of silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide, silicon germanium alloy, indium phosphide, or other suitable materials. Various circuits associated with the memory chip 100, such as sense amplifiers, decoders, pull-up or pull-down drivers, electrostatic protection circuits, or other circuits, may be formed on the substrate.

[0019] During manufacturing, a hard mask 114 may be applied on top of the stack (in various embodiments, one or more other intervening layers may be located between the hard mask and the stack). The hard mask may include various holes 116 that define the desired etching locations. A dry etching material may then be applied. The hard mask may withstand the dry etching material so that it protects the stack below from the dry etching material. The dry etching may etch a channel 110 downward through the stack at the location of the hole 116. In a particular embodiment, the channel may be used to form a string (e.g., a word line) of a NAND cell. In a particular embodiment, the channel may be a NAND column in a 3D NAND memory chip. In various embodiments, after the channel is formed, the channel may be filled with a dielectric material and / or other suitable material to produce a NAND cell. In various embodiments, various hard masks may be applied in conjunction with various etching steps (e.g., to form vias or channels leading to each polysilicon layer).

[0020] The etch stop layer 108 can provide a buffer between the bottom of the stack and other portions of the wafer (e.g., layers) disposed below the etch stop layer 108. In certain embodiments, the etch stop layer 108 covers the entire wafer (i.e., the etch stop layer 108 is a "blanket layer"). In other embodiments, the etch stop layer is not a blanket layer, but can include depositions of etch stop material at various discrete locations (e.g., within the same horizontal plane) on the wafer. Fig.10 Specific embodiments where the etch stop layer 108 is not a blanket layer are discussed.

[0021] The composition of the etch stop layer 108 and / or the composition of the hard mask layer 114 can have an important impact on the manufacture of the memory device 100. The etch stop layer 108 can be relatively resistant to dry etching (i.e., has a low dry etching rate), but after the dry etching is applied, the residual material in the channel (from the etch stop layer 108) can be removed using a wet etching material. If the wet etching rate of the etch stop layer 108 is too high, the wet etching can remove the material of the etch stop layer 108 in a horizontal direction, so the stack may be easy to fall off the wafer. However, if the wet etching rate of the etch stop layer 108 is too low, the residue may not be fully removed. As another example, if the crystallization temperature of the etch stop layer 108 is too low, the etch stop layer may crystallize, making it more difficult and / or more costly to remove the residual etch stop layer material from the channel 110.

[0022] In various embodiments, the composition for the etch stop layer 108 may have advantages over other materials that may be used for the etch stop layer, such as aluminum oxide (AlO x In certain embodiments, the composition used for the hard mask layer 114 can have one or more properties that are superior to the properties of other materials that can be used for the hard mask layer 114, such as CVD carbon, tungsten-doped carbon, or other hard masks with high metal content.

[0023] Various embodiments of the present disclosure provide compositions with improved properties for the etch stop layer 108 and / or the hard mask layer 114. In certain embodiments, the etch stop layer 108 may include a combination of aluminum oxide and one or more of hafnium (Hf), silicon (Si), or magnesium (Mg). For example, the etch stop layer 108 may include aluminum hafnium silicon oxide (i.e., Al v Hf w Si x O y ), aluminum hafnium oxide (Al v Hf w O y ), aluminum magnesium hafnium oxide (i.e. Al v Mg z Hf w O y ) or aluminum magnesium silicon oxide (i.e., Al v Mg z Si x O y), where v, w, x, y, and z can be any suitable integer. In a particular embodiment, the hard mask layer 114 can include a combination of magnesium oxide (MgO) and one or more of aluminum, hafnium, or silicon. Various embodiments can provide an etch stop layer 108 with an improved crystallization temperature, dry etch rate, and / or wet etch rate. Certain embodiments can provide a hard mask layer 114 with an improved dry etch rate, wet etch rate, and / or optical transparency.

[0024] Figure 2 A ternary phase diagram for predicted crystallization temperatures for various combinations of hafnium oxide (HfO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2) according to a particular embodiment is shown. Each axis represents the percentage of a particular compound composition. Each vertex of the triangle represents 100% of the particular compound composition, and the line opposite the vertex represents 0% of the particular compound composition. The percentage of a particular compound decreases linearly with increasing distance from the associated vertex (the points on a particular line opposite a vertex each represent the percentage of the compound specified by the annotation on the axis associated with that compound).

[0025] As shown in the figure, the composition of pure Al2O3 has a relatively low crystallization temperature (T c ). For example, pure Al2O3 and pure HfO2 may have a crystallization temperature of 900°C or less. Pure SiO2 has a crystallization temperature above 1100°C. However, when Al2O3 is mixed with a certain amount of HfO2 and / or SiO2, the crystallization temperature increases. v Hf w Si x O y or Al v Hf w O y The etch stop layer of can have a higher crystallization temperature than the etch stop layer of Al2O3. In various embodiments, the etch stop layer 108 can include a combination of Al2O3 and one or two of HfO2 and SiO2, so that the composition ratio of the etch stop layer 108 is in one of the regions shown with a crystallization temperature above 1000°C (or a region with a crystallization temperature above 1050°C). In various embodiments, by adding a small amount of HfO2 to Al2O3 (e.g., 15-40% HfO2), the crystallization temperature of the film is increased to greater than 1025°C. In a specific embodiment, the composition can be Al v Hf w Si x O y , which contains 25% or more SiO 2. In some embodiments, adding moderate to large amounts of SiO 2 to Al 2 O 3 can result in a similar temperature increase.

[0026] In various embodiments, the temperature increase may be sufficient to prevent crystallization of the etch stop layer during a rapid thermal processing (RTP) spike annealing process step performed to activate implants and dopants. In various embodiments, the annealing may be performed at a high temperature, for example, about 1000°C. Crystallization of aluminum oxide may result in the inability to remove aluminum oxide from the peripheral area of ​​the channel 110 using standard wet chemicals. Therefore, the crystallized aluminum oxide may be amorphized again (e.g., via an argon beam line implant) so that it can be removed by wet etching. However, this is a very costly step. By using a composition of the etch stop layer 108 having a higher crystallization temperature than the temperature applied during the annealing stage, the etch stop layer 108 does not crystallize during the annealing stage, and the composition of the etch stop layer 108 may be removed using a wet etch comprising any one or more of hydrofluoric acid, nitric acid, water, ammonium fluoride, phosphoric acid, acetic acid, or other suitable etching materials.

[0027] The wet etch rate of the etch stop layer 108 can also be adjusted by changing the amount of hafnium and / or silicon in the etch stop layer 108 (for example, by changing the amount of HfO2 and / or SiO2 combined with Al2O3 to form the etch stop layer 108). If the wet etch rate is too high, the wet etching may be difficult to control, and if the wet etch rate is too low, the etching may be ineffective. In various embodiments, the composition can be adjusted to have a wet etch rate similar to that of Al2O3 (or other suitable wet etch rates). Because the desired wet etch rate can vary depending on the process, the wet etch rate adjustability based on the composition of the etch stop layer can help manufacture various memory or other semiconductor devices.

[0028] Figure 3 A ternary phase diagram depicting a specific composition region 302 that provides good crystallization temperature and wet etch rate according to a specific embodiment is shown. In some embodiments, when a 2000:1 diluted HF mixture (i.e., 2000 parts water to 1 part hydrofluoric acid) is used as a wet etchant, the wet etch rate of the depicted region is greater than 20 angstroms per minute. In a specific embodiment, the composition of the etch stop layer 108 can include 20% to 60% HfO2. In a specific embodiment, the composition of the etch stop layer 108 achieves a wet etch rate of 20 to 300 angstroms per minute when a 2000:1 diluted HF solution is used.

[0029] Figure 4 A ternary phase diagram for predicted wet etch rates for various combinations of aluminum oxide (Al2O3), magnesium oxide (MgO), and hafnium oxide (HfO2) is shown in accordance with certain embodiments. Figure 5A ternary phase diagram for predicted etch rates for various combinations of aluminum oxide (Al2O3), magnesium oxide (MgO), and silicon dioxide (SiO2) is shown in accordance with certain embodiments.

[0030] MgO-based alloy films have significantly improved dry etch selectivity compared to Al2O3, but suffer from extremely high wet etch rates. However, by precisely alloying MgO with Al2O3 and one or more low wet etch rate oxides (e.g., HfO2 or SiO2), the wet etch rate of the etch stop layer can be adjusted to an acceptable wet etch rate while maintaining a low dry etch rate. In one embodiment, the composition of the etch stop layer 108 includes Al2O3 and SiO2. v Mg z Hf w O y , which has excellent dry etch stopping capability (i.e., low dry etch rate) and customizable wet etch rate (e.g., based on the ratio of various elements). In another embodiment, the composition of the etch stop layer 108 includes Al v Mg z Si x O y , which also has excellent dry etch stop capability and customizable wet etch rate.

[0031] If the etch stop layer 108 does not have sufficient etch stop capability, the manufacturing process may be plagued by random penetration of the etch stop layer. To alleviate this problem, some processes can use a separately patterned plug (e.g., a CVD tungsten filler) as an etch stop. This provides a high etch selectivity metal at the bottom of the NAND stack. However, various complications may arise. For example, it may be difficult to completely dig out the plug material from the channel 110. In addition, the digging out may cause redeposition of tungsten on the tier level below (resulting in the formation of tungsten silicon oxide on the active cell and forming a dead bit due to a short circuit). As another example, an additional mask layer is required to define the plug for the metal stop layer.

[0032] Adding Hf or Si to Al2O3 (e.g., by means of HfO2 or SiO2) can change the wet etch rate of the etch stop layer, but has minimal effect on the dry etch selectivity of the etch stop layer. Adding MgO to Al2O3 can produce a MgO with high dry etch stopping ability but very high wet etch rate (e.g., when HF is used as the wet etch material). z Al v O y Membrane. z Al v O yAdding a low wet etch rate oxide (e.g., HfO2 or SiO2) to a film (e.g., MgAl2O4) can reduce the wet etch rate of the composition, thereby increasing the suitability of the composition for use as an etch stop layer. v Mg z Hf w O y It can be a suitable composition for the etch stop layer 108, providing excellent dry etch stopping capability and customizable wet etch rate. v Mg z Hf w O y The film is amorphous and smooth after deposition (and after RTP spike annealing, the film can remain smooth, indicating that Al v Mg z Hf w O y is not broken into its component parts) and is etched evenly.

[0033] In this figure, the wet etch rate generally increases from the right side of the triangle to the left side of the triangle, with region 402 exhibiting the lowest wet etch rate and region 408 exhibiting the highest wet etch rate. In a particular embodiment, region 406 and adjacent compositions produce the best wet etch rate for a particular manufacturing process (although the novel embodiments disclosed herein are not limited thereto). In a particular embodiment, a composition of approximately 50% HfO2+25% MgO+25% Al2O3 (indicated by an asterisk) produces a particularly good combination of wet etch rate and dry etch stop capability.

[0034] exist Figure 5 In the figure, region 502 represents compositions where the wet etch rate is predicted to be higher than the desired rate (at least for some manufacturing processes), region 504 represents compositions where the dry etch rate is predicted to be too low, and region 506 represents compositions where both the wet and dry etch rates are predicted to be good (for other manufacturing processes, the optimal composition may be different). In a particular embodiment, stoichiometric cordierite (Mg2Al4Si5O) which is a naturally occurring mineral may be used. 18 ) or pyrope (Mg3Al2Si3O 12 ) to form an etch stop layer 108. Figure 5 The asterisk in shows the composition of cordierite.

[0035] Figure 6An exemplary process for manufacturing a memory device having an etch stop layer comprising a combination of aluminum oxide and one or more of hafnium, silicon, or magnesium is shown. At 602, various circuits of a memory chip 100 or other semiconductor device are formed on a substrate. For example, a pull-up or pull-down driver, an electrostatic protection circuit, a sense amplifier, a decoder, and / or other circuits may be formed.

[0036] At 604, an etch stop layer 108 is formed. In a particular embodiment, the etch stop layer 108 may be formed by combining aluminum oxide with one or more of hafnium, silicon, or magnesium (e.g., by combining with the corresponding oxides of hafnium, silicon, and / or magnesium). The etch stop layer may be formed in any suitable manner. In a particular embodiment, a multi-cathode sputtering tool may sputter aluminum oxide with one cathode while sputtering hafnium oxide, silicon dioxide, or magnesium oxide onto a wafer using another cathode (or multiple other cathodes may each sputter one of hafnium oxide, silicon dioxide, or magnesium oxide). In another embodiment, the sputtering tool may sputter a bulk target comprising aluminum oxide premixed with one or more of aluminum, magnesium, or silicon. In yet another embodiment, any of aluminum oxide, magnesium oxide, silicon dioxide, and hafnium oxide may be premixed with one or more other compounds to form a bulk target, and the bulk target may be deposited (e.g., sputtered) simultaneously with depositing (e.g., by sputtering) the one or more other compounds.

[0037] The etch stop layer 108 may be formed using any suitable deposition technique such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), thermal evaporation deposition, or other suitable deposition processes.

[0038] At 606, an RTP spike anneal is performed. For example, the wafer may be rapidly heated to a temperature in excess of 1000°C and then slowly cooled. Annealing may cause dopants within the wafer to activate. In various embodiments, the annealing does not cause crystallization of the etch stop layer 108 (since the etch stop layer has a higher crystallization temperature than the annealing temperature). In various embodiments, the annealing stage may occur at any suitable time in the process. For example, if the etch stop layer 108 does not crystallize during the annealing, it does not matter whether the annealing is performed before or after the deposition of the etch stop layer. In some embodiments, the annealing stage is not performed (and thus is optional depending on the manufacturing process used).

[0039] At 608, a dielectric layer of the stack is formed. The dielectric layer can be any suitable material formed in any suitable manner. In a particular embodiment, a thin layer of silicon dioxide is formed using CVD. At 610, a polysilicon layer of the stack is formed over (e.g., directly on top of) the dielectric layer. The polysilicon layer can be formed in any suitable manner. In a particular embodiment, a thin layer of polysilicon is formed using CVD. At 612, if the polysilicon layer is not the last layer of the stack, the process returns to 608 to form additional layers of the stack.

[0040] At 614, a hard mask is applied. The hard mask may include holes at which a channel through the stack will be formed. At 616, a dry etching material is applied. Dry etching may be accomplished in any suitable manner. For example, dry etching may include applying reactive gases, including one or more of fluorocarbons, oxygen, chlorine, boron trichloride, nitrogen, argon, helium, or other gases. In various embodiments, dry etching may include physical dry etching (e.g., applying an ion beam, an electron beam, or a photon beam), chemical dry etching, reactive ion etching, or other suitable etching techniques. The result of the dry etching may be the removal of material previously disposed in the now formed channel 110. The dry etching may extend downward to (and partially through) the etch stop layer 108. At 618, a wet etching material is applied. The wet etching may remove portions of the etch stop layer 108 from the channel 110 (which portions may have been displaced from the etch stop layer 108 during the dry etching). The wet etching material may include any one or more of hydrofluoric acid, nitric acid, water, ammonium fluoride, phosphoric acid, acetic acid, or other suitable wet etching materials.

[0041] Figure 7 An exemplary process for producing a hard mask layer using magnesium oxide (MgO) or magnesium aluminum oxide (MgAl2O4) to manufacture a memory device according to a particular embodiment is shown. The high dry etch resistance of magnesium oxide and magnesium aluminum oxide makes these materials very suitable for use as a hard mask layer. As mentioned above, these materials have high wet etch rates (which may make them unsuitable for use as an etch stop layer in some manufacturing processes, but they can be alloyed with other compounds to form a suitable etch stop layer), which can make them easy to remove after use as a mask.

[0042] CVD carbon films and carbon-doped films are currently struggling to meet the etching requirements of very high aspect ratios (i.e., very high dry etch resistance) for 3D NAND. Also, high metal content hard masks (e.g., W and W-doped carbon) can cause distortion and etch blocking due to rearrangement during dry etching.

[0043] In various embodiments, MgO or Mg z Alv O y A mixture of oxides of MgO and MgO is used to form a hard mask with a low dry etch rate. z Al v O y All have high wet etch rates, but their wet etch rates can be adjusted by alloying with high-K oxides (such as SiO2 and / or HfO2) and / or by structural modification via crystallization. z Al v O y It also has a low dry etch rate. In addition, compared with the opaque carbon hard mask, MgO and MgAlO x All are transparent, allowing direct alignment of the mask using photolithography.

[0044] The amorphous structure of magnesium aluminum oxide (e.g., MgAl2O4) has a very high wet etch rate. This has the potential benefit when using magnesium aluminum oxide as a hard mask, so that it can be easily stripped using wet etching after performing a dry etch, thereby having a low risk of contamination in the channel. If the wet etch rate of the hard mask is too high, crystallization (e.g., during the annealing stage) can alleviate this factor (i.e., after crystallization, the wet etch rate can drop). If crystallization is required, higher film stresses may result. However, high stresses are tensile, and if the dry etch selectivity is significantly improved by using magnesium aluminum oxide as a hard mask, the hard mask thickness can be greatly reduced, thereby limiting the overall impact of wafer bowing.

[0045] In various embodiments, the wet etch rate of the hard mask can also be adjusted by alloying magnesium oxide or magnesium aluminum oxide with HfO2 and / or SiO2. In a particular embodiment, the optimal composition range can be about 50% HfO2+25% MgO+25% Al2O3, but in various embodiments, any suitable ratio of HfO2, Al2O3 and / or SiO2 can be alloyed with MgO to form a hard mask layer. In various embodiments, the hard mask can include cordierite (Mg2Al4Si5O 18 ) or other magnesium aluminum silicon oxides. In various embodiments, the stress, wet etch rate and / or roughness of the hard mask layer can be adjusted by structural modification (e.g., by crystallizing the hard mask by applying heat (e.g., during an annealing phase)).

[0046] exist Figure 7 In the process of FIG. 7 , a hard mask is formed at 702. In various embodiments, MgO, Mg z Al v O y or MgO or Mg z Alv O y A hard mask can be formed by combining MgO with one or more of hafnium or silicon (e.g., by combining with hafnium oxide or silicon dioxide). The hard mask layer can be formed in any suitable manner. In a particular embodiment, a multi-cathode sputtering tool can sputter MgO with one cathode while sputtering aluminum oxide, silicon dioxide, or hafnium oxide onto a wafer using another cathode (or multiple other cathodes can each sputter one of aluminum oxide, silicon dioxide, or hafnium oxide). In another embodiment, the sputtering tool can sputter a bulk target comprising magnesium oxide premixed with one or more of aluminum, hafnium, or silicon (e.g., by their respective oxides or by other means). In yet another embodiment, any of magnesium oxide, aluminum oxide, silicon dioxide, and hafnium oxide can be premixed with one or more other compounds to form a bulk target, and the bulk target can be deposited (e.g., sputtered) simultaneously with depositing (e.g., by sputtering) one or more other compounds.

[0047] At 704, if the hard mask is to be crystallized (e.g., to reduce the wet etch rate of the hard mask), heat is applied at 706. In certain embodiments, the heat may be applied as part of an RTP spike anneal process for activating dopants in the wafer. In some embodiments, the crystallization operation is omitted.

[0048] At 708, a dry etch material is applied to form any suitable channel through the stack (e.g., via a hole in a hard mask). For example, the previously described channel 110 can be formed. As another example, a hard mask and dry etching can be used to form a via through the stack to one or more metal layers below the stack. As another example, a hard mask and dry etching can be used to form a portion of a stepped channel (e.g., during fabrication, multiple hard masks can be applied and etching of various depths can be performed to provide individual connections from above the stack to each polysilicon layer 102 (e.g., through vias) to connect to memory cells in the corresponding polysilicon layer).

[0049] Figure 6 and Figure 7 The described processes merely represent operations that may occur in a particular embodiment. In other embodiments, additional operations may be performed in the process (e.g., individual memory cells of an array may be formed). Various embodiments of the present disclosure contemplate any suitable signaling mechanism for implementing the functions described herein. Figure 6 and Figure 7 Some operations shown in the drawings may be repeated, combined, modified or deleted where appropriate. In addition, the operations may be performed in any suitable order without departing from the scope of the specific embodiments.

[0050] Figure 8 An exemplary portion of a NAND flash memory array 800 according to a particular embodiment is shown. In various embodiments, the memory chip 100 may include one or more NAND flash memory arrays. The NAND flash memory array 800 may include a plurality of non-volatile memory cells 802 arranged in columns such as a series string 804. In a particular embodiment, the cells 802 of the NAND flash memory array may be formed in a stack of polysilicon layers and dielectric layers. In various embodiments, each memory cell 802 may include a transistor with a floating gate that stores a charge indicating one or more bit values ​​stored by the memory cell 802. Other embodiments may include memory cells that employ alternative gate or charge capture technology. In the series string 804, the drains of the cells 802 (except the top cell) are all coupled to the source of another cell 802.

[0051] The array 800 also includes word lines 806 (e.g., 806A-806C). The word lines 806 can span multiple series strings 804 (e.g., the word lines can be coupled to the memory cells 802 of each series string 804) and are connected to the control gates of the memory cells 802 of a row of the array 800 and used to bias the control gates of the memory cells 802 of the row. The bit lines 808 (e.g., 808A, 808B) are each coupled to the corresponding series string 804 through a corresponding drain select gate 814 (e.g., 814A, 814B). The bit lines can also be coupled to a sensing circuit that detects the state of each cell by sensing the voltage or current of each sensed bit line 808.

[0052] Each series string of memory cells 804 is coupled to a source line 810 through a source select gate 812 and to a single bit line 808 through a drain select gate 814. The source select gate 812 is controlled by a source select gate control line 816, and the drain select gate 814 is controlled by a drain select gate control line 818. In other embodiments, multiple drain select gate control lines 818 may be used (such that one drain select gate control line may control a subset of drain select gates 814, another drain select gate control line may control a different subset of drain select gates 814, and so on). The source line 810 may be coupled to a fixed bias voltage (e.g., V SRC ). In various embodiments, V SRC Can be set to ground or positive bias (e.g., between 0 and 1.5V).

[0053] Fig. 9A block diagram of components of a computer system 900 according to certain embodiments is shown. The system 900 includes a central processing unit (CPU) 902 coupled to an external input / output (I / O) controller 904, a storage device 906, and a system memory device 907. During operation, data may be transferred between the storage device 906 or the system memory device 907 and the CPU 902. In various embodiments, certain data operations (e.g., erase, program, and read operations) involving the storage device 906 or the system memory device 907 may be managed by an operating system or other software applications executed by the processor 908.

[0054] In various embodiments, the storage device 906 includes NAND flash memory (herein, a storage device including NAND flash memory is referred to as a NAND flash storage device). In some embodiments, the storage device 906 can be a solid-state drive; a memory card; a universal serial bus (USB) flash drive; or a memory integrated into a device such as a smartphone, a camera, a media player, or other computing device. Typically, storage devices with NAND flash memory are classified by the number of bits stored in each cell of the memory. For example, a single-level cell (SLC) memory has a cell that stores one bit of data per cell, a multi-level cell (MLC) memory has a cell that stores two bits of data per cell, a triple-level cell (TLC) memory has a cell that stores three bits of data per cell, and a quad-level cell (QLC) memory has a cell that stores four bits of data per cell, but some memories may use multiple encoding schemes (e.g., MLC and TLC) on the same array or different arrays of the same device.

[0055] The storage device 906 may include any number of memories 916, and each memory 916 may include any number of memory devices 922 (e.g., 922A-922D). In a particular embodiment, the memory device 922 may be or include a semiconductor package having one or more memory chips 100 (e.g., memory chips 100A-100D). In the illustrated embodiment, the memory 916 includes memory devices 922A-922D (although memory device 922A is specifically mentioned herein, other memory devices may have any suitable characteristics of memory device 922A).

[0056] CPU 902 includes a processor 908, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SOC), or other devices that execute code (i.e., software instructions). In the illustrated embodiment, processor 908 includes two processing elements (cores 914A and 914B in the illustrated embodiment), which may include asymmetric processing elements or symmetric processing elements. However, the processor may include any number of processing elements that may be symmetric or asymmetric.

[0057] In one embodiment, a processing element refers to a hardware or logic unit that supports a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a processing unit, a context, a context unit, a logical processor, a hardware thread, a kernel, and / or any other element capable of maintaining the state of a processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code (e.g., a software thread, an operating system, an application, or other code). A physical processor (or processor socket) generally refers to an integrated circuit, which may include any number of other processing elements, such as kernels or hardware threads.

[0058] A kernel 914 may refer to a logic unit located on an integrated circuit that is capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. A hardware thread may refer to any logic unit located on an integrated circuit that is capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when specific resources are shared and other resources are dedicated to architectural states, the boundaries between the naming of hardware threads and kernels overlap. However, kernels and hardware threads are often viewed as separate logical processors by an operating system, wherein the operating system can schedule operations on each logical processor separately.

[0059] In various embodiments, a processing element may also include one or more arithmetic logic units (ALUs), floating point units (FPUs), caches, instruction pipelines, interrupt handling hardware, registers, or other hardware that facilitates the operation of the processing element.

[0060] I / O controller 910 is an integrated I / O controller that includes logic for transferring data between CPU 902 and I / O devices, which may refer to any suitable device capable of transferring data to and / or receiving data from an electronic system (e.g., CPU 902). For example, I / O devices may include audio / video (A / V) device controllers, such as graphics accelerators or audio controllers; data storage device controllers, such as flash memory devices, magnetic storage disks, or optical storage disk controllers; wireless transceivers; network processors; network interface controllers; or controllers for other input devices such as monitors, printers, mice, keyboards, or scanners; or other suitable devices. In certain embodiments, I / O devices may include storage devices 906, which may be coupled to CPU 902 via I / O controller 910.

[0061] The I / O devices may communicate with the I / O controller 910 of the CPU 902 using any suitable signaling protocol, such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel (FC), IEEE 802.3, IEEE 802.11, or other current or future signaling protocols. In certain embodiments, the I / O controller 910 and the underlying I / O devices may communicate data and commands according to a logical device interface specification such as Non-Volatile Memory Express (NVMe) (e.g., as described in one or more specifications available at www.nvmexpress.org / specifications / ) or Advanced Host Controller Interface (AHCI) (e.g., as described in one or more AHCI specifications such as Serial ATA AHCI: Specification, Revision 1.3.1, e.g., Serial ATA AHCI: Specification, Revision 1.3.1 available at http: / / www.intel.com / content / www / us / en / io / serial-ata / serial-ata-ahci-spec-rev1-3-1.html). In various embodiments, the I / O devices coupled to the I / O controller may be located off-chip (i.e., not on the same chip as the CPU 902) or may be integrated on the same chip as the CPU 902.

[0062] The CPU memory controller 912 is an integrated memory controller that includes logic for controlling the flow of data to and from one or more system memory devices 907. The CPU memory controller 912 may include logic operable to read from, write to, or request other operations from the system memory device 907. In various embodiments, the CPU memory controller 912 may receive write requests from the kernel 914 and / or the I / O controller 910, and may provide the data specified in these requests to the system memory device 907 for storage therein. The CPU memory controller 912 may also read data from the system memory device 907 and provide the read data to the I / O controller 910 or the kernel 914. During operation, the CPU memory controller 912 may issue a command including one or more addresses of the system memory device 907 in order to read data from or write data to memory (or perform other operations). In some embodiments, the CPU memory controller 912 may be implemented on the same chip as the CPU 902, while in other embodiments, the CPU memory controller 912 may be implemented on a different chip from the CPU 902. I / O controller 910 may perform similar operations for one or more storage devices 906 .

[0063] The CPU 902 may also be coupled to one or more other I / O devices via an external I / O controller 904. In certain embodiments, the external I / O controller 904 may couple a storage device 906 to the CPU 902. The external I / O controller 904 may include logic for managing data flow between one or more CPUs 902 and the I / O devices. In certain embodiments, the external I / O controller 904 is located on a motherboard along with the CPU 902. The external I / O controller 904 may exchange information with components of the CPU 902 using a point-to-point interface or other interface.

[0064] The system memory device 907 may store any suitable data, such as data used by the processor 908 to provide the functionality of the computer system 900. For example, data associated with a program executed by the kernel 914 or a file accessed by the kernel 914 may be stored in the system memory device 907. Thus, the system memory device 907 may include a system memory that stores data and / or instruction sequences executed or otherwise used by the kernel 914. In various embodiments, the system memory device 907 may store persistent data (e.g., a user's files or instruction sequences) that remains stored even after power to the system memory device 907 is removed. The system memory device 907 may be dedicated to a particular CPU 902 or shared by other devices of the computer system 900 (e.g., one or more other processors or other devices).

[0065] In various embodiments, the system memory device 907 may include memory (including any number of memory arrays), a memory device controller, and other supporting logic units (not shown). The memory array may include non-volatile memory and / or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the data state stored in the medium. Non-limiting examples of non-volatile memory may include any of the following or a combination thereof: solid-state memory (e.g., planar or 3D NAND flash memory or NOR flash memory), 3D cross-point memory, memory devices using chalcogenide phase change materials (e.g., chalcogenide glass), byte-addressable non-volatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM), bidirectional memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), various other types of non-volatile random access memory (RAM), and magnetic storage memory. In some embodiments, the 3D crosspoint memory may include a transistor-free stackable crosspoint architecture, wherein the memory cells are located at the intersection of word lines and bit lines and are individually addressable, and wherein the bit storage is based on changes in body resistance. Volatile memory is a storage medium that requires power to maintain the state of the data stored in the medium. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). A specific type of DRAM that can be used in a memory array is a synchronous dynamic random access memory (SDRAM). In some embodiments, any portion of the memory 907 that is a volatile memory may comply with JEDEC standards, including but not limited to double data rate (DDR) standards, such as DDR3, DDR4, and DDR5 or low power DDR4 (LPDDR4) and emerging standards.

[0066] The storage device 906 can store any suitable data, such as data used by the processor 908 to provide the functions of the computer system 900. For example, data associated with a program executed by the kernel 914A and 914B or a file accessed by the kernel 914A and 914B can be stored in the storage device 906. Therefore, in some embodiments, the storage device 906 can store data and / or instruction sequences executed or otherwise executed by the kernel 914A and 914B. In various embodiments, the storage device 906 can store persistent data (e.g., a user's file or software application code), and the persistent data remains stored even after the power to the storage device 906 is removed. The storage device 906 can be dedicated to the CPU 902 or shared by other devices (e.g., another processor or other device) of the computer system 900.

[0067] In the illustrated embodiment, the storage device 906 includes a storage device controller 918 and a memory 916, and the memory 916 includes four memory devices 922A-922D operable to store data, however, the storage device may include any suitable number of memory devices. The memory device 922A includes a plurality of memory cells, each of which is operable to store one or more bits. The cells of the memory device 922A may be arranged in any suitable manner, such as in rows (e.g., word lines) and columns (e.g., bit lines), three-dimensional structures, and / or other arrangements. In various embodiments, these cells may be logically grouped into banks, blocks, sub-blocks, word lines, pages, frames, bytes, or other suitable groups. In various embodiments, the memory device 922A includes one or more NAND flash memory arrays.

[0068] The memory device 922A may include any of the volatile or nonvolatile memories listed above or other suitable memories. In a particular embodiment, the memory device 922A includes a nonvolatile memory, such as a planar or 3D NAND flash memory. In a particular embodiment, the memory device 922A having a nonvolatile memory may comply with one or more standards for nonvolatile memory promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD220C, JESD223C, JESD223-1 or other suitable standards (the JEDEC standards cited herein are available at www.jedec.org). In a particular embodiment, the storage device includes a NAND flash memory that complies with one or more portions of a standard for SDRAM memory promulgated by JEDEC, such as JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM (these standards are available at www.jedec.org). These standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of the storage device that implements these standards may be referred to as a DDR-based interface. For example, a storage device 906 including a NAND flash memory may receive a command having a format that complies with a DDR-based standard and may translate the command into one or more commands that are compatible with the NAND flash memory of the storage device 906. Similarly, the storage device 906 may format the result of an operation performed on the NAND flash memory into a format that complies with a DDR-based standard before transmitting the result to the CPU 902.

[0069] In certain embodiments, the memory device 922 is a semiconductor package. In various embodiments, the semiconductor package may include a housing that contains one or more semiconductor dies (also referred to as chips) (e.g., memory chips 100A-100D). The package may also include contact pins or leads for connecting to external circuits. However, packaging is merely an exemplary form that the memory device 922 may take, because the memory device may be any suitable arrangement of one or more memory arrays and associated logic units in any suitable physical arrangement. For example, although a single physical package may include a single memory device 922, multiple memory devices 922 may reside on a single package, or the memory 922 may be dispersed across multiple packages.

[0070] The memory 916 may be embodied in one or more different physical media, such as a circuit board, a die, a disk drive, other media, or any combination thereof (or in combination with one or more packages). In a particular embodiment, the memory 916 includes a circuit board coupled to a plurality of memory devices 922, each of which includes a semiconductor package.

[0071] In various embodiments, the storage device 906 may include any suitable type of memory and is not limited to a specific speed, technology or form factor of the memory. For example, the storage device 906 may be a disk drive (e.g., a solid-state drive), a flash drive, a memory integrated with a computing device (e.g., a memory integrated on a circuit board of a computing device), a memory module (e.g., a dual in-line memory module) that can be inserted into a memory slot, or other types of storage devices. Moreover, the computer system 900 may include a variety of different types of storage devices. The storage device 906 may include any suitable interface for communicating with the CPU memory controller 912 or the I / O controller 910 using any suitable communication protocol (e.g., a DDR-based protocol, PCI, PCIe, USB, SAS, SATA, FC, system management bus (SMBus) or other suitable protocols). The storage device 906 may also include a communication interface for communicating with the CPU memory controller 912 or the I / O controller 910 according to any suitable logical device interface specification such as NVMe, AHCI or other suitable specifications. In certain embodiments, storage device 906 may include multiple communication interfaces, each of which communicates with CPU memory controller 912 and / or I / O controller 910 using a separate protocol.

[0072] The storage device controller 918 may include logic for receiving requests from the CPU 902 (e.g., via the CPU memory controller 912 or the I / O controller 910), executing the requests on the memory 916 (or its (multiple) memory devices), and providing data associated with the requests to the CPU 902 (e.g., via the CPU memory controller 912 or the I / O controller 910). The controller 918 may also be operable to detect and / or correct errors encountered during memory operations. In one embodiment, the controller 918 also tracks the number of times a particular cell (or logical grouping of cells) has been written to perform wear leveling and / or detect when cells are approaching an estimated number of times they can be reliably written. When performing wear leveling, the storage device controller 918 may evenly distribute write operations between blocks of memory in the memory 916 so that particular blocks are not written more than other blocks. In various embodiments, the controller 918 may also monitor various characteristics of the storage device 906, such as temperature or voltage, and report associated statistics to the CPU 902. The storage device controller 918 may be implemented on the same circuit board or device as the memory 916, or on a different circuit board or device than the memory 916. For example, in some environments, the storage device controller 918 may be a centralized storage controller that manages memory operations for multiple different memories 916 (which may each have the same type of memory or may be of different types) of the computer system 900 (and thus may provide the storage device controller functionality described herein to any memory coupled thereto).

[0073] In various embodiments, the storage device 906 also includes an address translation engine 920. In the illustrated embodiment, the address translation engine 920 is shown as part of the storage device controller 918, but in various embodiments, the address translation engine 920 can be separate from the storage device controller 918 and communicatively coupled to the storage device controller 918. In various embodiments, the address translation engine 920 can be integrated on the same chip or package as the storage device controller 918, or integrated on a different chip or package from the storage device controller 918.

[0074] In various embodiments, the address translation engine 920 may include a logic unit for storing and updating a mapping between a logical address space (e.g., an address space visible to a host computing device coupled to the storage device 906) and a physical address space (which may or may not be exposed to the host computing device) of the memory 916 of the storage device 906. The logical address space may expose a plurality of logical data groups physically stored on corresponding physical memory groups addressable through the physical address space of the storage device 906. The physical address of the physical address space may include any suitable information identifying a physical memory location (e.g., a location within a memory array of the memory 916) of the storage device 906, such as an identifier of the memory 916 where the physical memory location is located, an identifier of the memory device 922A where the physical memory location is located, one or more pages of the physical memory location, one or more sub-blocks of the physical memory location, one or more word lines of the physical memory location, one or more bit lines of the physical memory location, or other suitable identifiers or encodings thereof.

[0075] In various embodiments, the storage device 906 also includes a program control logic unit 924 that is operable to control a programming sequence performed when data is written to the memory 916 or a reading sequence performed when data is read from the memory 916. In various embodiments, the program control logic unit 924 may provide various voltages (or information indicating which voltages should be provided) applied to one or more memory cells, word lines, bit lines, and / or other portions of the memory array during programming and / or reading of data, perform error correction, and perform other suitable functions.

[0076] In various embodiments, the program control logic unit 924 may be integrated on the same chip as the storage device controller 918 or on a different chip from the storage device controller 918. In the illustrated embodiment, the program control logic unit 924 is shown as part of the storage device controller 918, but in various embodiments, all or a portion of the program control logic unit 924 may be separate from the storage device controller 918 and communicatively coupled to the storage device controller 918. For example, all or a portion of the program control logic unit 924 may be located on the same package or chip as the memory 916 and / or the memory devices 922A-922D.

[0077] In some embodiments, all or some elements of system 900 reside on (or are coupled to) the same circuit board (e.g., mainboard). In various embodiments, any suitable division between elements may exist. For example, the elements shown in CPU 902 may be located on a single die (i.e., on a chip) or on a package, or any element of CPU 902 may be located outside a chip or outside a package. Similarly, the elements shown in storage device 906 may be located on a single chip or on multiple chips. In various embodiments, storage device 906 and host computing device (e.g., CPU 902) may be located on the same circuit board or on the same device, and in other embodiments, storage device 906 and host computing device may be located on different circuit boards or devices.

[0078] The components of the system 900 may be coupled together in any suitable manner. For example, a bus may couple any components together. The bus may include any known interconnect, such as a multi-point bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a radio transceiver logic (GTL) bus. In various embodiments, the integrated I / O subsystem includes point-to-point multiplexing logic units between various components of the system 900 (e.g., a kernel 914, one or more CPU memory controllers 912, an I / O controller 910, an integrated I / O device, a direct memory access (DMA) logic unit (not shown), etc.). In various embodiments, the components of the computer system 900 may be coupled together through one or more networks including any number of intervening network nodes (e.g., routers, switches, or other computing devices). For example, a host computing device (e.g., CPU 902) and a storage device 906 may be communicatively coupled through a network.

[0079] Although not shown, the system 900 may use a battery and / or a power outlet connector and associated systems to receive power, use a display to output data provided by the CPU 902, or use a network interface that allows the CPU 902 to communicate over a network. In various embodiments, the battery, power outlet connector, display, and / or network interface may be communicatively coupled to the CPU 902. Other sources of power, such as renewable energy sources (e.g., solar or motion-based power), may be used.

[0080] Fig.10A horizontal cross-section of a portion of a memory chip 100 having a discontinuous etch stop layer 120 (including portions 120A and 120B) according to a particular embodiment is shown. The etch stop layer 120 may have any one or more of the characteristics of the etch stop layer 108 described above (e.g., the etch stop layer 120 may be formed using any of the compositions described above). In a particular embodiment, a plurality of holes may be formed in a dielectric layer 118 above the substrate before forming the stack. The dielectric layer 118 and the holes therein may be formed in any suitable manner (e.g., by applying one or more masks and / or etching, or by any other suitable means). Each hole is then filled with an etch stop material to form a portion of the etch stop layer (e.g., 120A or 120B). The surface on the dielectric layer 118 and the etch stop layer 120 may then be planarized (e.g., using chemical mechanical planarization), and a stack is formed over the resulting surface. In certain embodiments, the dry etch for forming the channel 110 may be stopped by the etch stop portions (e.g., 120A and 120B), and the wet etch may remove the remaining etch stop film from the channel 110. In such embodiments, if the dielectric layer 118 has a high wet etch selectivity compared to the etch stop material, the upper limit on the wet etch rate requirement may be relaxed.

[0081] Although the various embodiments described herein focus on etch stop layers and hard masks used in memory devices, the teachings of the present disclosure can be applied to etch stop layers or hard masks in any suitable semiconductor device. For example, a hard mask layer or etch stop layer can be used in conjunction with etching performed through any suitable layer (including any suitable material) of a semiconductor device. In addition, although various composition regions have been shown as "optimal" or "desirable", the novel embodiments described herein may include compositions within any shown region of a ternary phase diagram. In addition, various embodiments disclose etch stop layers or hard masks composed of specific compounds (e.g., aluminum hafnium oxide, magnesium aluminum oxide, etc.). These embodiments contemplate specific compounds that constitute any suitable portion of an etch stop layer or hard mask. For example, although an etch stop layer or hard mask may contain most of a specific compound, an etch stop layer or hard mask may also contain any suitable number of other compounds (e.g., impurities or other compounds described herein). In various embodiments, an etch stop layer or hard mask may be substantially composed of any compound listed herein (e.g., 99% or more of an etch stop layer or hard mask may be a specific compound).

[0082] A design can go through various stages from creation to simulation to manufacturing. The data representing the design can represent the design in a variety of ways. First, as useful in simulation, a hardware description language (HDL) or another functional description language can be used to represent the hardware. In addition, a circuit level model with logic and / or transistor gates can be generated at some stages of the design process. In addition, most designs reach a data level representing the physical layout of various devices in the hardware model at some stage. In the case of using conventional semiconductor manufacturing technology, the data representing the hardware model can be data specifying whether various features exist on different mask layers of a mask used to manufacture an integrated circuit. In some embodiments, such data can be stored in a database file format such as a Graphic Data System II (GDS II), an Open Artwork System Interchange Standard (OASIS) or a similar format.

[0083] In some embodiments, software-based hardware models, as well as HDL and other functional description language objects may include register transfer language (RTL) files and other examples. These objects may be machine-parseable, so that the design tool may accept HDL objects (or models), parse the HDL objects for the properties of the described hardware, and use the objects to determine the physical circuit and / or on-chip layout. The output of the design tool may be used to manufacture physical devices. For example, the design tool may use HDL objects to determine the configuration of various hardware and / or firmware elements, such as bus width, registers (including size and type), memory blocks, physical link paths, structural topology, and other properties of the system to be implemented to achieve the modeling using HDL objects. The design tool may include tools for determining the topology and structural configuration of systems on chip (SoC) and other hardware devices. In some examples, HDL objects may be used as the basis for developing models and design files, and manufacturing equipment may use these models and design files to manufacture the described hardware. In fact, the HDL objects themselves may be provided as input to the manufacturing system software to enable the described hardware to be manufactured.

[0084] In any representation of a design, the data representing the design may be stored in any form of machine-readable medium. A magnetic or optical storage device or memory such as a disk may be a machine-readable medium for storing information transmitted via light waves or radio waves that are modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying a code or design is transmitted, a new copy is made in the sense that a copy, buffering, or retransmission of the electrical signal is performed. Thus, a communications provider or network provider may store, at least temporarily, an article of manufacture embodying the techniques of an embodiment of the present disclosure, such as information encoded in a carrier wave, on a tangible machine-readable medium.

[0085] In various embodiments, a medium storing a representation of a design may be provided to a manufacturing system (e.g., a semiconductor manufacturing system capable of manufacturing integrated circuits and / or related components). The design representation may instruct the system to manufacture a device capable of performing any combination of the functions described above. For example, the design representation may instruct the system which components to manufacture, how the components should be coupled together, where the components should be placed on the device, and / or other suitable specifications regarding the device to be manufactured.

[0086] Thus, one or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, which represent various logic units within a processor, which when read by a machine causes the machine to fabricate the logic units to perform the techniques described herein. These representations, often referred to as "IP cores," may be stored on a non-transitory, tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into manufacturing machines that fabricate the logic units or processors.

[0087] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these embodiments. Embodiments of the present disclosure may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0088] Instructions may be input as application code to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the present application, a processing system includes any system having a processor (e.g., for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor).

[0089] The program code can be implemented in a high-level procedural programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly language or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In various embodiments, the language can be a compiled or interpreted language.

[0090] Embodiments of the methods, hardware, software, firmware, or code described above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable (or otherwise accessible) by a processing element. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine (e.g., a computer or electronic system). For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are distinguished from non-transitory media from which information can be received.

[0091] The instructions for programming the logic unit to perform the embodiments of the present disclosure can be stored in a memory in the system, such as a DRAM, a cache, a flash memory, or other storage devices. In addition, these instructions can be distributed over a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, but the machine-readable medium is not limited to a floppy disk, an optical disk, a compressed disk, a read-only memory (CD-ROM), a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory, or a tangible machine-readable storage device for transmitting information through the Internet by means of electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

[0092] Logic units may be used to implement any of the processes shown in the entire figures (e.g., Figure 6 or Figure 7902, storage device 906, external I / O controller 904, system memory device 907, one or more machines for manufacturing chip 100, any subcomponents thereof, or other components described herein). "Logical unit" may refer to hardware, firmware, software, and / or a combination thereof for performing one or more functions. As an example, a logical unit may include hardware, such as a microcontroller or a processor, which is associated with a non-transitory medium to store code suitable for execution by the microcontroller or the processor. Therefore, in one embodiment, the logic unit mentioned refers to hardware that is specifically configured to recognize and / or execute code stored on a non-transitory medium. In addition, in another embodiment, a logic unit is used to refer to a non-transitory medium including code that is particularly suitable for execution by a microcontroller to perform a predetermined operation. As can be inferred, in yet another embodiment, the term "logical unit" (in this example) may refer to a combination of hardware and non-transitory media. In various embodiments, the logic unit may include a microprocessor or other processing element operable to execute software instructions, a discrete logic unit such as an application specific integrated circuit (ASIC), a programmed logic device such as a field programmable gate array (FPGA), a memory device containing instructions, a combination of logic devices (e.g., as found on a printed circuit board), or other suitable hardware and / or software. The logic unit may include one or more gates or other circuit components, which may be implemented by, for example, transistors. In some embodiments, the logic unit may also be fully embodied as software. The software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a non-temporary computer-readable storage medium. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, or instruction sets and / or data in a memory device. Typically, the boundaries of logic units shown as separate generally vary and may overlap. For example, a first logic unit and a second logic unit may share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware.

[0093] In one embodiment, the phrase "to" or "configured to" is used to refer to the following operations on a device, hardware, logic unit or element: arranged, placed together, manufactured, offered for sale, imported and / or designed to perform a specified or determined task. In this example, if the device or its elements are designed, coupled and / or interconnected to perform the specified task, then the device or its elements that are not operating are still "configured to" perform the specified task. As a purely illustrative example, a logic gate can provide 0 or 1 during operation. However, a logic gate that is "configured to" provide an enable signal to a clock does not include every possible logic gate that can provide 1 or 0. Instead, a logic gate is a logic gate coupled in a certain way so that a 1 or 0 is output during operation to enable the clock. Note again that the term "configured to" used does not require operation, but focuses on the potential state of the device, hardware and / or element, where in the potential state, the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element operates.

[0094] Furthermore, in one embodiment, the phrases "can / may" and / or "operable to" are used to refer to a certain device, logic unit, hardware, and / or element being designed in such a manner that the device, logic unit, hardware, and / or element can be used in a specified manner. Note that, as described above, in one embodiment, the phrases "to", "can" or "operable to" are used to refer to a potential state of a device, logic unit, hardware, and / or element, wherein the device, logic unit, hardware, and / or element is not operating, but rather the device, logic unit, hardware, and / or element is designed in such a manner that the device can be used in a specified manner.

[0095] The value used herein includes any known representation of a number, state, logic state or binary logic state. Typically, the logic level, logic value or logic state value used is also referred to as 1 and 0, which only represent binary logic states. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one embodiment, storage units such as transistors or flash memory cells can store a single logic value or multiple logic values. However, other representations of values ​​in computer systems have been used. For example, the decimal number 10 can also be represented as a binary value 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information that can be stored in a computer system.

[0096] In addition, a state can be represented by a value or a portion of a value. As an example, a first value such as a logical 1 can represent a default state or initial state, while a second value such as a logical 0 can represent a non-default state. In addition, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value may include a high logic value, i.e., reset, and an updated value may include a low logic value, i.e., set. Note that any combination of values ​​can be used to represent any number of states.

[0097] In at least one embodiment, a device includes: an etch stop layer including one or more of hafnium, silicon, or magnesium, and aluminum oxide; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

[0098] In one embodiment, the etch stop layer comprises aluminum hafnium oxide. In one embodiment, the etch stop layer comprises aluminum hafnium silicon oxide. In one embodiment, the etch stop layer comprises aluminum magnesium hafnium oxide. In one embodiment, the etch stop layer comprises aluminum magnesium silicon oxide. In one embodiment, the device further comprises a hard mask, the hard mask comprising magnesium oxide. In one embodiment, the hard mask further comprises one or more of aluminum, silicon or hafnium. In one embodiment, the etch stop layer has a crystallization temperature greater than 1000 degrees Celsius. In one embodiment, the etch stop layer has a dry etch rate lower than the dry etch rate of Al2O3. In one embodiment, the device comprises a 3D NAND memory device. In one embodiment, the etch stop layer is a uniformly thick etch stop layer deposited over the entire surface of the wafer. In one embodiment, the etch stop layer comprises a plurality of etch stop portions, the plurality of etch stop portions being formed in holes in a dielectric layer formed on the wafer.

[0099] In at least one embodiment, a method includes: forming an etch stop layer, the etch stop layer comprising one or more of hafnium, silicon or magnesium, and aluminum oxide; depositing a plurality of layers over the etch stop layer; and forming a channel through at least some of the plurality of layers, the channel extending to the etch stop layer.

[0100] In one embodiment, the etch stop layer comprises aluminum hafnium oxide. In one embodiment, the etch stop layer comprises aluminum hafnium silicon oxide. In one embodiment, the etch stop layer comprises aluminum magnesium hafnium oxide. In one embodiment, the etch stop layer comprises aluminum magnesium silicon oxide. In one embodiment, the method further comprises forming a hard mask comprising magnesium oxide. In one embodiment, the hard mask further comprises one or more of aluminum, silicon or hafnium. In one embodiment, the etch stop layer has a crystallization temperature greater than 1000 degrees Celsius. In one embodiment, the etch stop layer has a dry etch rate lower than the dry etch rate of Al2O3. In one embodiment, at least one of the plurality of layers comprises a plurality of NAND memory cells. In one embodiment, forming the etch stop layer comprises simultaneously performing the following operations: sputtering aluminum oxide using a first cathode of a sputtering tool, and sputtering one or more of hafnium oxide, silicon dioxide or magnesium oxide using a second cathode of the sputtering tool. In one embodiment, forming the etch stop layer comprises sputtering a bulk target onto a wafer, the bulk target comprising a combination of aluminum oxide and one or more of hafnium, silicon or magnesium.

[0101] In at least one embodiment, a system includes a semiconductor package, the semiconductor package including a first memory chip, the first memory chip including: a stack, the stack including alternating first and second layers, wherein the first layers include a first conductive material and the second layers include a first dielectric material; an etch stop layer, the etch stop layer including one or more of hafnium, silicon or magnesium, and aluminum oxide; and a channel formed through the stack, the channel extending to the etch stop layer.

[0102] In one embodiment, the system further comprises a processor coupled to the semiconductor package. In one embodiment, the system further comprises one or more of a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor. In one embodiment, the etch stop layer comprises aluminum hafnium silicon oxide. In one embodiment, the etch stop layer comprises aluminum magnesium hafnium oxide.

[0103] In at least one embodiment, a system includes a module for forming an etch stop layer, the etch stop layer comprising one or more of hafnium, silicon or magnesium, and aluminum oxide; a module for depositing multiple layers above the etch stop layer; and a module for forming a channel through at least some of the multiple layers, the channel extending to the etch stop layer.

[0104] In one embodiment, forming the etch stop layer includes simultaneously sputtering aluminum oxide using a first cathode of the sputtering tool and sputtering one or more of hafnium oxide, silicon dioxide, or magnesium oxide using a second cathode of the sputtering tool. In one embodiment, forming the etch stop layer includes sputtering a bulk target onto the wafer, the bulk target comprising a combination of aluminum oxide and one or more of hafnium, silicon, or magnesium. In one embodiment, the system further includes a module for forming a hard mask over the plurality of layers, the hard mask comprising magnesium oxide. In one embodiment, the hard mask further comprises one or more of aluminum, silicon, or hafnium.

[0105] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0106] In the foregoing description, detailed descriptions have been given with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Therefore, the description and drawings are to be regarded as illustrative rather than restrictive. Furthermore, the foregoing use of embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments as well as potentially the same embodiment.

Claims

1. A device including an etch stop layer, comprising: The etch stop layer comprises aluminum magnesium hafnium oxide or aluminum magnesium silicon oxide, wherein the aluminum magnesium hafnium oxide or aluminum magnesium silicon oxide is formed by alloying magnesium oxide and aluminum oxide with hafnium oxide or silicon dioxide, wherein a wet etching rate, a dry etching rate and a crystallization temperature of the etch stop layer are adjusted by adjusting the amount of magnesium oxide, aluminum oxide, hafnium oxide or silicon dioxide; and A channel is formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

2. The device of claim 1, further comprising a hard mask comprising magnesium oxide.

3. The device according to claim 2, wherein: The hard mask also includes one or more of aluminum, silicon, or hafnium.

4. The device according to any one of claims 1 to 3, wherein: The etch stop layer has the crystallization temperature higher than 1000 degrees Celsius.

5. The device according to any one of claims 1 to 3, wherein: The etch stop layer has the dry etching rate lower than the dry etching rate of aluminum oxide.

6. The device according to any one of claims 1 to 3, wherein: The apparatus includes a 3D NAND memory device.

7. A method for forming an etch stop layer, comprising: forming the etch stop layer, the etch stop layer comprising aluminum magnesium hafnium oxide or aluminum magnesium silicon oxide, wherein the aluminum magnesium hafnium oxide or aluminum magnesium silicon oxide is formed by alloying magnesium oxide and aluminum oxide with hafnium oxide or silicon dioxide, wherein the wet etching rate, dry etching rate and crystallization temperature of the etch stop layer are adjusted by adjusting the amount of magnesium oxide, aluminum oxide, hafnium oxide or silicon dioxide; depositing a plurality of layers over the etch stop layer; and A via is formed through at least some of the plurality of layers, the via extending to the etch stop layer. The method of claim 7 , further comprising forming a hard mask comprising magnesium oxide.

9. The method according to claim 8, wherein: The hard mask also includes one or more of aluminum, silicon, or hafnium.

10. The method according to any one of claims 7 to 9, wherein: The etch stop layer has the crystallization temperature higher than 1000 degrees Celsius.

11. The method according to any one of claims 7 to 9, wherein: The etch stop layer has the dry etching rate lower than the dry etching rate of aluminum oxide.

12. The method according to any one of claims 7 to 9, wherein: At least one of the plurality of layers includes a plurality of NAND memory cells.

13. The method according to any one of claims 7 to 9, wherein: Forming the etch stop layer includes simultaneously sputtering aluminum oxide using a first cathode of a sputtering tool and sputtering magnesium oxide, and one or more of hafnium oxide or silicon dioxide using a second cathode of the sputtering tool.

14. The method according to any one of claims 7 to 9, wherein: Forming the etch stop layer includes sputtering a bulk target onto the wafer, the bulk target comprising a combination of aluminum oxide, magnesium, and one or more of hafnium or silicon.

15. A system comprising means for performing the method according to any one of claims 7-14.

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