Method and device for detecting the state of a high-voltage interlock loop, and vehicle

Abstract

A state detection method of a high-voltage interlock loop, the high-voltage interlock loop and a voltage dividing module are coupled to form a detection loop, comprising: loading a first frequency positive voltage square wave current signal in the detection loop; loading a second frequency negative voltage square wave current signal in the detection loop; detecting a first signal component of the first frequency on the voltage dividing module and outputting a first detection level and a second detection level, and detecting a second signal component of the second frequency and outputting a third detection level and a fourth detection level; determining whether the high-voltage interlock loop is abnormal according to the first detection level, the second detection level, the third detection level and the fourth detection level. The square wave current signal is used to drive the HVIL loop, and since the loop is a single closed loop without branch circuits, the current signal will not change with the length of the transmission line, there is no signal attenuation, so it has a longer transmission distance, and can meet the general platform demand of almost all vehicle types for the length of the high-voltage interlock loop.

Description

Technical Field

[0001] This invention belongs to the field of new energy vehicle technology, and in particular relates to a method, device and vehicle for detecting the state of a high-voltage interlocking loop. Background Technology

[0002] Currently, with the rapid development and popularization of new energy vehicles in China, their safety is receiving increasing attention. Since the voltage of the high-voltage systems in new energy vehicles is generally between 300V and 600V, far exceeding the safe voltage range for the human body, high-voltage interlock (HVIL) technology is widely used in the field of high-voltage safety for new energy vehicles to protect the personal safety of drivers, passengers, and maintenance personnel. The HVIL device uses low-voltage electrical signals to connect the various components of the high-voltage system (including the power battery system, high-voltage electrical equipment, high-voltage connectors, high-voltage cables, etc.) in series to form a closed loop, monitoring the integrity of the entire high-voltage system circuit in real time. When the HVIL loop is abnormally disconnected, the battery management system triggers a safety protection strategy, disconnecting the power battery system to protect vehicle occupants from electric shock.

[0003] Current high-voltage interlocking devices generally employ two technologies: analog voltage signal monitoring and digital voltage signal monitoring. Analog voltage signal monitoring determines the loop's on / off state by reading the loop voltage magnitude. However, this technology has several drawbacks: when the loop cable is long or has high resistance, there is a significant voltage drop across the loop cable, easily leading to numerical deviations in the acquired voltage signal and causing false alarms or missed alarms. Digital voltage signal monitoring typically determines the loop's on / off state by identifying the frequency and duty cycle of the PWM (Pulse Width Modulation) voltage signal. However, this monitoring scheme, using single-ended PWM voltage signal transmission, has poor anti-interference capabilities in the complex electromagnetic environment of a vehicle and is highly susceptible to common-mode interference, causing signal distortion and severely impacting the reliability of the monitoring results. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method, device and vehicle for detecting the state of a high-voltage interlock loop, aiming to solve the problem that in traditional technical solutions, voltage signals are used for loop interlock detection. When the interlock loop of the whole vehicle is too long, the loop resistance increases, resulting in a large additional voltage drop in the loop, which causes numerical deviation in the interlock detection and affects the reliability of the detection. At the same time, the voltage signal has poor anti-interference ability.

[0005] A first aspect of this invention provides a state detection method for a high-voltage interlock loop, wherein the high-voltage interlock loop is coupled with a voltage divider module to form a detection loop, and the state detection method includes:

[0006] A positive voltage square wave current signal of the first frequency is applied to the detection loop;

[0007] The first signal component of the first frequency on the voltage divider module is detected, and a first detection level and a second detection level are output.

[0008] A negative voltage square wave current signal of the second frequency is applied to the detection loop;

[0009] The second signal component of the second frequency on the voltage divider module is detected, and a third detection level and a fourth detection level are output.

[0010] The high-voltage interlock loop is determined to be abnormal based on the first detection level, the second detection level, the third detection level, and the fourth detection level.

[0011] A second aspect of this invention provides a state detection device for a high-voltage interlock loop, wherein the high-voltage interlock loop is coupled with a voltage divider module to form a detection loop, and the state detection device includes:

[0012] A first signal generator is configured to apply a positive voltage square wave current signal of a first frequency to the detection loop;

[0013] The detection unit is configured to detect a first signal component of the first frequency on the voltage divider module and output a first detection level and a second detection level.

[0014] The second signal generator is configured to apply a negative voltage square wave current signal of the second frequency to the detection loop;

[0015] The detection unit is also configured to detect a second signal component of the second frequency on the voltage divider module and output a third detection level and a fourth detection level;

[0016] The control unit is configured to determine whether the high-voltage interlock loop is abnormal based on the first detection level, the second detection level, the third detection level, and the fourth detection level.

[0017] A third aspect of the present invention provides an automobile including a high-voltage interlock loop status detection device as described above.

[0018] The aforementioned high-voltage interlock loop status detection method and device uses a square wave current signal to drive the HVIL loop. Since the loop is a single closed loop without branch loops, the current signal does not change with the transmission line length, and there is no signal attenuation. Therefore, it has a longer transmission distance, meeting the universal platform requirements for high-voltage interlock loop length in almost all vehicle models. Furthermore, using a square wave current signal to drive the HVIL loop, compared to a voltage signal, provides higher anti-interference capability and better stability, resulting in higher EMC anti-interference suppression capability and better reliability. Simultaneously, using a bipolar square wave current signal to drive the high-voltage interlock loop, due to its wider peak-to-peak amplitude of positive and negative currents, provides higher fault tolerance and robustness when determining loop on / off status compared to a unipolar square wave current signal. In addition, by implementing relevant fault detection measures on two sets of four-level signals, different fault types can be effectively identified, including loop open circuit faults, loop short circuit to power supply faults, and loop short circuit to ground faults, thereby enabling rapid fault diagnosis and saving maintenance time and costs. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a high-voltage interlocking loop status detection device provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram illustrating the implementation process of the high-voltage interlock loop status detection method provided in this embodiment of the invention.

[0022] Figure 3 for Figure 2 A schematic diagram of the implementation process of step S120 in the high-voltage interlocking loop status detection method;

[0023] Figure 4 for Figure 2 A schematic diagram of the implementation process of step S140 in the high-voltage interlock loop status detection method;

[0024] Figure 5 This is a schematic diagram of the structure of a high-voltage interlocking loop status detection device provided in another embodiment of the present invention;

[0025] Figure 6 for Figure 5 The example circuit schematic of the first embodiment of the high-voltage interlock detection circuit is shown.

[0026] Figure 7 for Figure 5 The example circuit schematic of the second embodiment of the high-voltage interlock detection circuit shown; Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] Please see Figure 1 In this embodiment of the invention, the high-voltage interlock loop 10 is coupled with a voltage divider module 110 to form a detection loop 20. The high-voltage interlock loop 10 can be connected in series with the following high-voltage electrical equipment components: high-voltage connectors of power battery systems and their manual maintenance switches, high-voltage connectors of power distribution units and their upper covers, high-voltage connectors of drive motors, high-voltage connectors of on-board chargers, high-voltage air conditioning compressors, and high-voltage DC-DC modules, etc. The high-voltage interlock loop 10 and the voltage divider module 110 are connected in series to form the detection loop 20, or the voltage divider module 110 is connected in parallel with one of the components of the high-voltage interlock loop 10 to form the detection loop 20. The voltage divider module 110 is a circuit composed of at least one of resistors, inductors, and capacitors.

[0029] Please see Figure 1 and Figure 2 The high-voltage interlocking loop status detection method provided in this embodiment of the invention includes the following steps:

[0030] Step S110: Apply a positive voltage square wave current signal of the first frequency to the detection loop 20.

[0031] Specifically, a positive voltage square wave current signal is generated using a first signal generator 120 (e.g., a current source), and then controlled by a first switch 160 to be connected to the detection loop 20. Thus, the HVIL loop is driven by a square wave current signal. Because the loop is a single closed loop with no branch loops, the current signal does not change with the transmission line length, and there is no signal attenuation. Therefore, it has a longer transmission distance, which can meet the universal platform requirements for the length of high-voltage interlock loops in almost all vehicle models.

[0032] Step S120: Detect the first signal component of the first frequency on the voltage divider module 110 and output the first detection level and the second detection level.

[0033] Specifically, the detection module 140 detects the voltage component of the positive voltage square wave current signal on the voltage divider module 110, and after preprocessing the voltage component (such as amplification, biasing, etc.), it compares it with two preset voltages to obtain two comparison results (detection levels) that can indicate the state of the high voltage interlocking loop 10.

[0034] In step S130, a negative voltage square wave current signal of the second frequency is applied to the detection loop 20.

[0035] Specifically, a negative voltage square wave current signal is generated using a second signal generator 130 and controlled to be connected to the detection loop 20 via a second switch 170. Furthermore, using a square wave current signal to drive the HVIL loop provides higher anti-interference capability and better stability compared to a voltage signal, resulting in higher EMC anti-interference suppression capability and better reliability for the system. Simultaneously, using a bipolar square wave current signal to drive the high-voltage interlock loop 10, due to its wider peak-to-peak amplitude of positive and negative currents, provides higher fault tolerance and robustness when determining the loop's on / off state compared to a unipolar square wave current signal.

[0036] Step S140: Detect the second signal component of the second frequency on the voltage divider module 110 and output the third and fourth detection levels. The process is similar to step S120. The detection module 140 detects the voltage components of the positive and negative voltage square wave current signals on the voltage divider module 110, preprocesses these voltage components (e.g., amplification, biasing), and compares them with two preset voltages to obtain two level signals that indicate the state of the high-voltage interlock loop 10.

[0037] Step S150: Determine whether the high-voltage interlock loop is abnormal based on the first detection level, the second detection level, the third detection level, and the fourth detection level. By judging the two sets of four level signals, different fault types can be effectively identified, including loop open circuit faults, loop short circuit to power supply faults, and loop short circuit to ground faults, thereby enabling rapid fault diagnosis and saving maintenance time and costs.

[0038] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. For example, steps S130 and S140 can be executed first, followed by steps S110 and S120. Furthermore, the positive voltage square wave current signal and the negative voltage square wave current signal are PWM current signals with an output current of 10–30 mA, a frequency of 20–1000 Hz, and a duty cycle of 20%–80%. Optionally, the positive voltage square wave current signal and the negative voltage square wave current signal have the same current magnitude, frequency, and duty cycle.

[0039] For a more detailed embodiment, please refer to the figure. Figure 1 and Figure 3 Step S120 includes:

[0040] Step S121: Detect and amplify the first voltage component of the positive voltage square wave current signal applied to the voltage divider module 110. In one embodiment, the detection module 140 includes a differential amplifier 142, with its two ends connected to the two ends of the voltage divider module 110. The first voltage component detected on the voltage divider module 110 is amplified and then output at the output terminal.

[0041] Step S122: Compare the amplified first voltage component with a first preset voltage and output a first detection level. In one embodiment, the detection module 140 uses a first voltage comparator 143 to compare the first voltage component with the first preset voltage and output a first comparison result.

[0042] Step S123: Compare the amplified first voltage component with a second preset voltage and output a second detection level. In one embodiment, the detection module 140 uses a second voltage comparator 144 to compare the first voltage component with the second preset voltage and output a second comparison result.

[0043] For a more detailed embodiment, please refer to Figure 1 and Figure 4 Similar to step S120, step S140 includes:

[0044] Step S141: Detect the second voltage component of the negative voltage square wave current signal applied to the voltage divider module and amplify it; the two ends of the differential amplifier 142 are connected to the two ends of the voltage divider module 110, and the second voltage component on the voltage divider module 110 is detected, amplified, and then output at the output end.

[0045] Step S142: Compare the amplified second voltage component with the first preset voltage and output the third detection level; use the first voltage comparator 143 to compare the second voltage component with the first preset voltage and output the third comparison result.

[0046] Step S143: Compare the amplified second voltage component with the second preset voltage and output the fourth detection level. Use the second voltage comparator 144 to compare the second voltage component with the second preset voltage and output the fourth comparison result.

[0047] In one embodiment, the principle for setting the second preset voltage is that when the detection loop 20 is connected to a positive voltage square wave current signal, the voltage of the first voltage component after being amplified by the differential amplifier 142 is greater than the second preset voltage and greater than 0; the principle for setting the first preset voltage is that when the detection loop 20 is connected to a negative voltage square wave current signal, the voltage of the second voltage component after being amplified by the differential amplifier 142 is less than the first preset voltage and less than 0, that is, the second preset voltage is greater than 0 and greater than the first preset voltage.

[0048] In another embodiment, a fixed positive common-mode voltage is applied to the positive and negative voltages across the voltage divider module 110 so that the voltage amplified and output by the differential amplifier 142 is always positive. In this embodiment, the second preset voltage > the first preset voltage > 0.

[0049] In a more detailed embodiment, step S150 includes: performing analog-to-digital conversion on the first detection level, the second detection level, the third detection level, and the fourth detection level to obtain corresponding digital values; generally, the controller (control unit 150) can have a built-in or external module converter to convert the detection levels into corresponding digital signals. Subsequently, a set of four digital signals converted from detection levels, obtained by applying positive and negative voltage square wave current signals to the detection loop 20 respectively, are used as the basis for determining the state of the high-voltage interlock loop 10. The digital values ​​are then matched against a preset table to determine the state of the high-voltage interlock loop. The controller matches the obtained digital signals against a pre-stored "Digital Signal-Fault State" table to determine the current state of the high-voltage interlock loop 10.

[0050] Furthermore, this invention also discloses a state detection device for a high-voltage interlocking loop, which can be applied to electric vehicles, hybrid vehicles, or electric motorcycles. Please refer to [link / reference]. Figure 5 The high-voltage interlock loop status detection device includes a voltage divider module 210 coupled with the high-voltage interlock loop 10 to form a detection loop 20, a first signal generator 220, a second signal generator 230, a detection unit 240, and a control unit 250.

[0051] The first signal generator 220 is connected to the first end of the detection loop 20 and is configured to load a positive voltage square wave current signal of the first frequency onto the detection loop 20 through the first switch 260. The second signal generator 230 is connected to the second end of the detection loop 20 and is configured to load a negative voltage square wave current signal of the second frequency onto the detection loop 20 through the second switch 270. The detection unit 240 is connected in parallel with the voltage divider module 210 and is configured to detect the first signal component of the first frequency on the voltage divider module 210 and output a first detection level and a second detection level when only the first switch 260 is connected, and to detect the second signal component of the second frequency on the voltage divider module 210 and output a third detection level and a fourth detection level when only the second switch 270 is connected. The control unit 250 is connected to the detection unit 240, the first switch 260 and the second switch 270 and is configured to control the opening and closing of the first switch 260 and the second switch 270 respectively, and determine whether the high-voltage interlocking loop 10 is abnormal based on the first detection level, the second detection level, the third detection level and the fourth detection level.

[0052] Specifically, the output terminal of the first signal generator 220 is connected to the first terminal of the detection circuit 20 (i.e., one end of the voltage divider module 210), the control terminal of the first switch 260 is connected to the first control terminal of the control unit 250, the input terminal of the first switch 260 is connected to the second terminal of the detection circuit 20, and the output terminal of the first switch 260 is grounded. When the first switch 260 is closed, the positive voltage square wave current signal generated by the first signal generator 220 will be applied to the detection circuit 20. The output terminal of the second signal generator 230 is connected to the second terminal of the detection circuit 20 (i.e., the end of the high-voltage interlock loop 10 away from the voltage divider module 210), the control terminal of the second switch 270 is connected to the second control terminal of the control unit 250, the input terminal of the second switch 270 is connected to the first terminal of the detection circuit 20, and the output terminal of the second switch 270 is grounded. When the second switch 270 is closed, the negative voltage square wave current signal generated by the second signal generator 230 will be applied to the detection circuit 20. The detection unit 240 first differentially amplifies the voltage component of the detected positive / negative voltage square wave current signal applied to the voltage divider module 210, and then compares it with two different reference voltage signals to output different comparison results (detection levels). These results are then input to the two input terminals of the control unit 250. When the high-voltage interlock loop 10 is normally connected, the control unit 250 can detect a detection level combination that meets the expectations. When the high-voltage interlock loop 10 has an abnormal connection, such as an open circuit, a short circuit to the power supply, or a short circuit to the power supply ground, the control unit 250 detects an abnormal detection level combination.

[0053] In some embodiments, the first signal generator 220 and the second signal generator 230 are current sources that output PWM current signals with a current magnitude of 10-30mA, a frequency of 20-1000Hz, and a duty cycle of 20%-80%. It is understood that the current magnitude, frequency, and duty cycle of the first signal generator 220 and the second signal generator 230 may be the same or different.

[0054] In this embodiment, please refer to Figure 6 The current source includes a first transistor T1, a second transistor T2, a first resistor R1, and a second resistor R2. The base of the first transistor T1 is connected to the emitter of the second transistor T2 and the first terminal of the first resistor R1. The collector of the first transistor T1 is connected to the first terminal of the second resistor R2 and the base of the second transistor T2. The emitter of the first transistor T1 and the second terminal of the first resistor R1 are connected to the power supply Vbat. The second terminal of the second resistor R2 is connected to the power supply ground. The collector of the second transistor T2 serves as the output terminal of the current source and is connected to the detection loop 20. In one embodiment, please refer to... Figure 6 Both transistor T1 and transistor T2 are PNP type transistors. In another embodiment, please refer to... Figure 7Both the first transistor T1 and the second transistor T2 are NPN transistors. Furthermore, the two first transistors T1 and the two second transistors T2 in the two current sources that constitute the first signal generator 220 and the second signal generator 230, respectively, have the same electrical performance parameters. For convenience, devices of the same model can be selected. The two first resistors R1 in the two current sources that constitute the first signal generator 220 and the second signal generator 230, respectively, have the same resistance value, and the two second resistors R2 also have the same resistance value.

[0055] Please see Figure 6 In one embodiment, both the first switch 260 and the second switch 270 include a third resistor R3 and a first MOSFET M1. The first end of the third resistor R3 serves as the control terminal of the switch and is connected to the control terminal of the control unit 250. The second end of the third resistor R3 is connected to the gate of the first MOSFET M1. The source of the first MOSFET M1 serves as the output terminal of the switch and is connected to the power supply ground. The drain of the first MOSFET M1 serves as the output terminal of the switch and is connected to the detection loop 20. Optionally, the two first MOSFETs M1 constituting the first switch 260 and the second switch 270 have the same electrical performance parameters and are both P-channel MOSFETs. For convenience, devices of the same type can be selected. Preferably, the two first MOSFETs M1 have hardware protection functions such as short-circuit turn-off, overload turn-off, and thermal runaway turn-off.

[0056] Please see Figure 7 In another embodiment, both the first switch 260 and the second switch 270 include a fourth resistor R4, a fifth resistor R5, a second MOSFET M2, and a third transistor T3. The first end of the fourth resistor R4 serves as the control terminal of the switch and is connected to the control terminal of the control unit 250. The second end of the fourth resistor R4 is connected to the base of the third transistor T3. The emitter of the third transistor T3 serves as the output terminal of the switch and is connected to the power supply ground. The collector of the third transistor T3 is connected to the gate of the second MOSFET M2 and the first end of the fifth resistor R5. The drain of the second MOSFET M2 is connected to the power supply Vbat along with the second end of the fifth resistor R5. The source of the second MOSFET M2 serves as the input terminal of the switch and is connected to the detection loop 20. Optionally, the two second MOSFETs M2 constituting the first switch 260 and the second switch 270 have the same electrical performance parameters and are both P-channel MOSFETs. For convenience, devices of the same type can be selected. Preferably, the two second MOSFETs M2 have hardware protection functions such as short-circuit turn-off, overload turn-off, and thermal runaway turn-off. In addition, the two third transistors T3 have the same electrical performance parameters and are both NPN transistors. For convenience, devices of the same type can be selected.

[0057] Please see Figure 5In some embodiments, the detection unit includes a differential amplifier 242, a first voltage comparator 243, and a second voltage comparator 244.

[0058] The first input terminal of the differential amplifier 242 is connected to the first terminal of the first signal generator 220 and the first terminal of the voltage divider module 210. The second input terminal of the differential amplifier 242 is connected to the first terminal of the high-voltage interlock loop 10 and the second terminal of the voltage divider module 210. The output terminal of the differential amplifier 242 is connected to the inverting input terminal of the first voltage comparator 243 and the non-inverting input terminal of the second voltage comparator 244. The non-inverting input terminal of the first voltage comparator 243 and the inverting input terminal of the second voltage comparator 244 are respectively connected to the first reference voltage REF1 and the second reference voltage REF2. The output terminal of the first voltage comparator 243 is connected to the first input terminal of the control unit 250, and the output terminal of the second voltage comparator 244 is connected to the second input terminal of the control unit 250. Optionally, the first voltage comparator 243 and the second voltage comparator 244 have the same electrical performance parameters; for convenience, devices of the same model can be selected.

[0059] The differential amplifier 242 is configured to detect and amplify a first voltage component of a positive voltage square wave current signal applied to the voltage divider module 210, and is also configured to detect and amplify a second voltage component of a negative voltage square wave current signal applied to the voltage divider module 210; the first voltage comparator 242 is configured to compare the amplified first voltage component with a first preset voltage and output a first detection level, and is also configured to compare the amplified second voltage component with the first preset voltage and output a third detection level; the second voltage comparator 243 is configured to compare the amplified first voltage component with a second preset voltage and output a second detection level, and is also configured to compare the amplified second voltage component with the second preset voltage and output a fourth detection level.

[0060] In one embodiment, please refer to Figure 6 The differential amplifier 242 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a voltage operational amplifier U1. The first terminal of the eighth resistor R8 is connected to the first terminal of the voltage divider module 210. The first terminal of the sixth resistor R6 is connected to the second terminal of the voltage divider module 210. The second terminal of the eighth resistor R8, the first terminal of the ninth resistor R9, and the non-inverting input terminal of the voltage operational amplifier U1 are connected. The second terminal of the sixth resistor R6, the first terminal of the seventh resistor R7, and the inverting input terminal of the voltage operational amplifier U1 are connected. The second terminal of the seventh resistor R7 is connected to the output terminal of the voltage operational amplifier U1. The second terminal of the ninth resistor R9 is connected to the power supply ground. The output terminal of the voltage operational amplifier U1 serves as the output terminal of the differential amplifier 242. Optionally, in this embodiment, the second reference voltage REF2 > 0 > the first reference voltage REF1.

[0061] In another implementation, please refer to Figure 7 The differential amplifier 242 also includes a bias resistor R10. The first terminal of the bias resistor R10 is connected to a positive voltage reference REF3, and the second terminal is connected to the non-inverting input of the voltage operational amplifier U1. Thus, a fixed positive common-mode voltage is biased across the voltage divider module 210, ensuring that the amplified output voltage is always positive. Optionally, in this embodiment, the second reference voltage REF5 > the first reference voltage REF4 > 0.

[0062] For further details, please refer to Figure 6 The control unit 250 performs fault detection and judgment on the high-voltage interlock loop 10 according to the preset combination relationship of the first detection level, the second detection level, the third detection level, and the fourth detection level. Specifically, in the detection unit 210, the second reference voltage REF2 is set according to the principle that when the current flowing through the voltage divider module 210 is from top to bottom, the voltage after gain by the differential amplifier 242 > the second reference voltage REF2 > 0; the first reference voltage REF1 is set according to the principle that when the current flowing through the voltage divider module 210 is from bottom to top, the voltage after gain by the differential amplifier 242 < the first reference voltage REF1 < 0.

[0063] The control unit 250 includes a processor and its peripheral circuitry. The processor can be an ECU (Electronic Control Unit, vehicle computer), a motor controller (Microcontroller Unit, MCU), or a Battery Management System (BMS), such as a microcontroller or a DSP (Digital Signal Processing) processor. Please refer to [link to relevant documentation]. Figure 5 The control unit 250 can have a built-in or external module converter 251 to convert the detection level into a corresponding digital signal. Subsequently, a set of four digital signals converted from the detection levels, obtained by applying positive and negative voltage square wave current signals to the detection loop 20 respectively, are used as the basis for determining the state of the high-voltage interlock loop 10. The processor 252 of the control unit 250 then matches the digital values ​​in a preset table to determine the state of the high-voltage interlock loop. The controller matches the obtained digital signal with a pre-stored "Digital Signal-Fault State" table in the memory 253 to determine the current state of the high-voltage interlock loop 10.

[0064] The "Digital Signal - Fault Status" table will be explained through an analysis of high-voltage interlock loop connection scenarios. Please refer to [link / reference]. Figure 6 :

[0065] 1. Analysis of normal scenario for high-voltage interlock loop 10 connection

[0066] When the first switch 260 is closed, the positive voltage square wave current signal flows from top to bottom through the voltage divider module 210. The voltage across the voltage divider module 210 is amplified by the differential amplifier 242 and outputs a positive voltage signal. The first voltage comparator 243 compares this voltage with a preset negative voltage threshold, a first reference voltage REF1. Since the positive voltage signal output by the differential amplifier 242 is greater than the preset first reference voltage REF1, the first voltage comparator 243 outputs "0", i.e., the first detection level. Similarly, since the preset second reference voltage REF2 is a positive voltage threshold, the positive voltage signal output by the differential amplifier 242 is greater than the preset second reference voltage REF2. At this time, the second voltage comparator 244 outputs "1", i.e., the second detection level.

[0067] Similarly, when the second switch 270 is closed, the negative voltage square wave current signal flows through the voltage divider module 210 in the direction of bottom to top. The differential amplifier 242 outputs a negative voltage signal, and this voltage signal is less than the first reference voltage REF1. Then the first voltage comparator 243 outputs "1", which is the third detection level. The differential amplifier 242 outputs a negative voltage signal, and this voltage signal is less than the preset second reference voltage REF2. At this time, the second voltage comparator 244 outputs "0", which is the fourth detection level. The relationship between detection levels and fault status is shown in Table 1 below.

[0068] Table 1:

[0069] First detection level Second detection level Third detection level Fourth detection level Fault status 0 1 1 0 Connection normal

[0070] 4. Analysis of the scenario of high-voltage interlocking loop 10 connection failure

[0071] Since no current flows through the voltage divider module 210 at this time, the voltage output by the differential amplifier 242 is always 0V, and the detection level output by the first voltage comparator 243 and the second voltage comparator 244 is "0", thus obtaining the relationship between the detection level and the fault state in Table 2 below.

[0072] Table 2:

[0073] First detection level Second detection level Third detection level Fourth detection level Fault status 0 0 0 0 Connection disconnection

[0074] 3. Analysis of a short circuit from high-voltage interlock loop 10 to power supply Vbat scenario

[0075] When the first switch 260 is closed, due to the short circuit of the high-voltage interlock loop 10 to the power supply Vbat, no current flows through the voltage divider module 210, so both the first and second detection levels are "0". When the second switch 270 is closed, the current flowing through the voltage divider module 210 is from bottom to top, and the third and fourth detection levels are "1" and "0" respectively, thus obtaining the relationship between the detection levels and fault status in the table below.

[0076] Table 3:

[0077] First detection level Second detection level Third detection level Fourth detection level Fault status 0 0 0 1 Short circuit to power supply Vbat

[0078] 4. Analysis of the scenario where the high-voltage interlock loop 10 is short-circuited to the power supply ground

[0079] When the first switch 260 is closed, due to the short circuit of the high-voltage interlock loop 10 to the power supply ground, the current flowing through the voltage divider module 210 is from top to bottom. Therefore, the first detection level and the second voltage detection level are "0" and "1" respectively. After executing step 104, no current flows through the voltage divider module 210, and the third detection level and the fourth voltage detection level are both "0", thus obtaining the relationship between the detection levels and the fault status in the table below.

[0080] Table 4:

[0081] First detection level Second detection level Third detection level Fourth detection level Fault status 1 0 0 0 Short circuit to power ground

[0082] Thus, by presetting Tables 1-4 above in the memory 253 of the control unit 250, the control unit 250 can accurately determine the working state of the high-voltage interlocking loop 10 based on the current detection level combination state of the system.

[0083] As can be seen, the high-voltage interlock loop state detection method and device uses a square wave current signal to drive the HVIL loop. Since the loop is a single closed loop without branch loops, the current signal does not change with the transmission line length, and there is no signal attenuation. Therefore, it has a longer transmission distance, meeting the universal platform requirements for the length of the high-voltage interlock loop 10 in almost all vehicle models. Furthermore, using a square wave current signal to drive the HVIL loop, compared to a voltage signal, provides higher anti-interference capability and better stability, resulting in higher EMC anti-interference suppression capability and better reliability for the system. Simultaneously, using a bipolar square wave current signal to drive the high-voltage interlock loop 10, due to its wider peak-to-peak amplitude of positive and negative currents, provides higher fault tolerance and robustness when determining the loop's on / off state compared to a unipolar square wave current signal. In addition, by implementing relevant fault detection measures on two sets of four-level signals, different fault types can be effectively identified, including loop open circuit faults, loop short circuit to power supply Vbat faults, loop short circuit to ground faults, etc., thereby enabling rapid fault diagnosis and saving maintenance time and costs.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for detecting the state of a high-voltage interlocking loop, characterized in that, The high-voltage interlock loop is coupled with a voltage divider module to form a detection loop, and the state detection method includes: A positive voltage square wave current signal of the first frequency is applied to the detection loop; Detecting the first signal component of the first frequency on the voltage divider module and outputting a first detection level and a second detection level includes: detecting the first voltage component of the positive voltage square wave current signal applied to the voltage divider module and amplifying it; comparing the amplified first voltage component with a first preset voltage and outputting a first detection level; comparing the amplified first voltage component with a second preset voltage and outputting a second detection level. A negative voltage square wave current signal of the second frequency is applied to the detection loop; Detecting the second signal component of the second frequency on the voltage divider module and outputting the third and fourth detection levels includes: detecting the second voltage component of the negative voltage square wave current signal applied to the voltage divider module and amplifying it; comparing the amplified second voltage component with a first preset voltage and outputting the third detection level; comparing the amplified second voltage component with a second preset voltage and outputting the fourth detection level. The high-voltage interlock loop is determined to be abnormal based on the first detection level, the second detection level, the third detection level, and the fourth detection level.

2. The state detection method as described in claim 1, characterized in that, The positive voltage square wave current signal and the negative voltage square wave current signal are PWM current signals with an output current of 10-30 mA, a frequency of 20-1000 Hz, and a duty cycle of 20%-80%.

3. The state detection method as described in claim 1 or 2, characterized in that, The positive voltage square wave current signal and the negative voltage square wave current signal have the same current magnitude, frequency, and duty cycle.

4. The state detection method as described in claim 1, characterized in that, The step of determining whether the high-voltage interlock loop is abnormal based on the first detection level, the second detection level, the third detection level, and the fourth detection level includes: The first detection level, the second detection level, the third detection level, and the fourth detection level are converted from analog to digital to obtain the corresponding digital values; The numerical values ​​are matched against a preset table to determine the status of the high-voltage interlock loop.

5. A status detection device for a high-voltage interlocking loop, characterized in that, The high-voltage interlock loop is coupled with a voltage divider module to form a detection loop, and the status detection device includes: A first signal generator is configured to apply a positive voltage square wave current signal of a first frequency to the detection loop; A detection unit is configured to detect a first signal component of the first frequency on the voltage divider module and output a first detection level and a second detection level; the detection unit includes: a differential amplifier configured to detect and amplify a first voltage component of the positive voltage square wave current signal applied to the voltage divider module; a first voltage comparator configured to compare the amplified first voltage component with a first preset voltage and output a first detection level; and a second voltage comparator configured to compare the amplified first voltage component with a second preset voltage and output a second detection level. The second signal generator is configured to apply a negative voltage square wave current signal of the second frequency to the detection loop; The detection unit is further configured to detect a second signal component of the second frequency on the voltage divider module and output a third detection level and a fourth detection level, including: the differential amplifier is further configured to detect and amplify a second voltage component of a negative voltage square wave current signal applied to the voltage divider module; the first voltage comparator is further configured to compare the amplified second voltage component with a first preset voltage and output a third detection level; the second voltage comparator is further configured to compare the amplified second voltage component with a second preset voltage and output a fourth detection level; The control unit is configured to determine whether the high-voltage interlock loop is abnormal based on the first detection level, the second detection level, the third detection level, and the fourth detection level.

6. The state detection device as described in claim 5, characterized in that, The positive voltage square wave current signal and the negative voltage square wave current signal are PWM current signals with an output current of 10-30 mA, a frequency of 20-1000 Hz, and a duty cycle of 20%-80%.

7. The state detection device as described in claim 5 or 6, characterized in that, The positive voltage square wave current signal and the negative voltage square wave current signal have the same current magnitude, frequency, and duty cycle.

8. The state detection device as described in claim 5, characterized in that, The control unit includes: An analog-to-digital converter is configured to perform analog-to-digital conversion on the first detection level, the second detection level, the third detection level, and the fourth detection level to obtain corresponding digital values; The processor is configured to match the digital values ​​in a preset table to determine the state of the high-voltage interlock loop; and The memory stores the preset table.

9. The state detection device as described in claim 5, characterized in that, The voltage divider module is a circuit composed of at least one of resistors, inductors, and capacitors.

10. A car, characterized in that, Includes the high-voltage interlock detection device as described in any one of claims 5 to 9.

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