Remote atomic operation instructions

Abstract

The disclosed embodiments relate to atomic memory operations. In one example, a method of executing an instruction atomically and with weak ordering includes: fetching, by fetch circuitry, the instruction from a code storage device, the instruction including an opcode, a source identifier, and a destination identifier; decoding, by decode circuitry, the fetched instruction; selecting, by schedule circuitry, an execution circuit among a plurality of circuits in a system; scheduling, by the schedule circuitry, execution of the decoded instruction out of order with respect to other instructions in an order selected to optimize at least one of latency, throughput, power, and performance; and executing, by data execution circuitry, the decoded instruction to: atomically read data from a location identified by the destination identifier; perform an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and write a result back to the location.

Description

Technical Field

[0001] The field of the invention relates generally to computer processor architectures, and more particularly to remote atomic operation (RAO) instructions. Background Art

[0002] An atomic memory operation is one during which a processor core can read a location, modify the location, and write the location back in what appears to be a single operation to other cores. A core can refer to a physical core in a single-threaded architecture or a logical core in a multi-threaded architecture. An atomic memory operation in a multi-core system is an operation that cannot be divided into any smaller parts or appear to be a single operation to other cores in the system. Read-modify-write is one of a class of atomic memory operations that both reads a memory location and writes a new value to the memory location as part of the same operation (at least as appears to be the same operation to other cores in the multi-core system).

[0003] Typically, performing atomic operations in a multi-core system, especially in the presence of contention among the cores, can be expensive and inefficient. Cache lines holding variables accessed atomically can be "ping-ponged" among multiple cores and multiple private caches across a shared interconnect. Coherence overhead can also limit throughput to, for example, less than one atomic operation per 100 clock cycles on a given cache line. In the case where hundreds of threads are trying to access the same line, the last thread in the line may have to wait a very long time, such as, for example, more than 25,000 clock cycles.

[0004] In addition to latency issues, cache line ping-pong places significant strain on interconnect network traffic among multiple nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which:

[0006] Figure 1 is a block diagram illustrating processing components for executing remote atomic operation instructions according to some embodiments;

[0007] Figure 2 is a flow chart of a process to be performed by a processor for executing remote atomic operation instructions according to some embodiments;

[0008] Figure 3 Various portions of a multi-core processor for executing remote atomic operation instructions according to some embodiments are shown;

[0009] Figure 4 is a flow chart of a process performed by a processor for executing a remote atomic operation instruction according to some embodiments;

[0010] Figure 5 is a block diagram of a second more specific exemplary system for executing remote atomic operation instructions according to some embodiments;

[0011] Figure 6 shows a physical memory having various memory regions mapped for executing RAO instructions at various locations according to some embodiments;

[0012] Figure 7 is a block diagram illustrating the format of a remote atomic operation instruction according to some embodiments;

[0013] Figure 8 is a block diagram illustrating the format and optional parameters of a remote atomic operation instruction according to some embodiments;

[0014] Figure 9 is a block diagram showing the execution of the RAO instruction;

[0015] Figure 10 An embodiment of hardware for processing RAO instructions is presented;

[0016] Figure 11 Shows the process of executing RAO instructions by the processor;

[0017] FIG. 12A to FIG. 12B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention;

[0018] Figure 12A is a block diagram illustrating a general vector friendly instruction format and its class A instruction template according to an embodiment of the present invention;

[0019] Figure 12B is a block diagram illustrating a general vector friendly instruction format and its Class B instruction template according to an embodiment of the present invention;

[0020] Figure 12C is a block diagram illustrating an exemplary specific vector friendly instruction format according to an embodiment of the present invention;

[0021] Figure 13 is a block diagram of a register architecture according to one embodiment of the present invention;

[0022] Figure 14A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0023] Figure 14B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention;

[0024] FIG. 15A to FIG. 15B A block diagram illustrating a more specific exemplary in-order core architecture, wherein a core is one of several logic blocks in a chip (including other cores of the same and / or different types);

[0025] Figure 15A is a block diagram of a single processor core along with its connection to the on-die interconnect network and its local subset of the Level 2 (L2) cache in accordance with an embodiment of the present invention;

[0026] Figure 15B According to an embodiment of the present invention Figure 15A An expanded view of a portion of a processor core in FIG;

[0027] Figure 16 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present disclosure;

[0028] Figures 17 to 20 is a block diagram of an exemplary computer architecture;

[0029] Figure 17 is a block diagram of a system according to one embodiment of the present invention;

[0030] Figure 18 is a block diagram of a first more specific exemplary system according to an embodiment of the present invention;

[0031] Figure 19 is a block diagram of a second more specific exemplary system according to an embodiment of the present invention;

[0032] Figure 20 is a block diagram of a system on a chip (SoC) according to an embodiment of the present invention; and

[0033] Figure 21 is a block diagram contrasting the use of a software instruction converter for converting binary instructions in a source instruction set to binary instructions in a target instruction set according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the present invention can be practiced without these specific details. In other instances, well-known circuits, structures, and technologies are not shown in detail to avoid obscuring the understanding of this specification.

[0035] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it should be understood that it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0036] Embodiments disclosed herein relate to instructions that implement high-performance atomic memory operations, even in the presence of competing memory locations shared among multiple cores in a multi-core processor. RAO instructions can be executed in various locations, such as at a core, at a private cache, at a shared cache, at a cache control circuit (10) (sometimes referred to as a cache and home agent (CHA)), at a memory controller, or at a remote core, to name a few. RAO instructions will execute on both single-socket and multi-socket systems.

[0037] Some attempts to perform atomic operations suffer from long latencies, pressure on data cache capacity, and high traffic usage of the interconnect among multiple cores. For example, as mentioned above, cache lines holding variables that are accessed atomically can be "ping-ponged" among private caches across a shared interconnect (ping-pong occurs when multiple cores are writing to the same cache line, even if they are writing to different variables in the cache line and must ping-pong back and forth across the cache line). The embodiments disclosed herein implement atomic memory operations with reduced latency and serialization.

[0038] Some attempts to perform atomic operations (also mentioned above) suffer from consistency overhead that can limit throughput. Even in the presence of little contention, some other processors force a certain number of atomic operations in a thread to be serialized. This serialization limits throughput even if shared data is not contended. The embodiments disclosed herein implement atomic memory operations with reduced serialization or throughput limitations.

[0039] Due to the poor performance of atomic memory operations, some methods try to avoid using any atomic memory operations. However, completely avoiding atomic memory operations can be problematic and often requires significant refactoring of the algorithm, often with additional instruction overhead.

[0040] Instead, one approach to avoiding atomic memory operations uses privatization: each thread maintains its own copy of the variable. The cost of updating the private copy is typically low. However, the multiple threads often need to combine their data eventually, and the overhead of performing this combining can be significant. Furthermore, when an application uses large arrays of these shared variables, maintaining many copies of the array can put a strain on cache capacity or even memory capacity. This can increase the cost of updating the private copy.

[0041] Another approach to avoiding atomic memory operations uses a single cache shared by all processors to prevent data from being moved around while executing multiple updates from different cores. However, this hardware approach is problematic for at least the following reasons: (a) it requires an atomic memory instruction to explicitly tell the hardware to execute the instruction at a cache shared by all processors; and (b) it is based on a memory model with weak ordering, as opposed to the stronger ordering of other processors.

[0042] Another hardware approach allows the processor to dynamically determine whether threads need to be serialized through a lock-protected critical section and perform serialization only when necessary. However, this approach does not provide good performance under contention and still causes serialization near atomic operations.

[0043] Implementing the solution in software can also be problematic because it requires significant changes in application parallelization (and therefore programmer effort). Software solutions also carry instruction overhead, which in some cases can be worse than existing atomic memory operations.

[0044] The embodiments described herein allow for reduced latency of atomic memory instructions (in the event of contention, by queuing the operations at a single location and performing them in place). These instructions are referred to as Remote Atomic Operation (RAO) instructions, and executing one or more of these instructions causes a specific read-modify-write operation to a memory location in an atomic manner. Further, the memory accesses performed by the RAO instructions may be weakly ordered, but built upon a more strongly ordered memory model. (As used herein, memory loads and stores in a strongly ordered model are executed in program order, while a weakly ordered model allows for some reordering of memory accesses, i.e., some type of out-of-order execution). Thus, the embodiments described herein allow for hiding the latency of atomic operations (via weakly ordered semantics).

[0045] Figure 1is a block diagram illustrating processing components for executing remote atomic operation instructions according to some embodiments. As shown, computing system 100 includes code storage device 102, fetch circuitry 104, decode circuitry 106, scheduling circuitry 108, execution circuitry 110, registers 112, memory 114, and retirement or commit circuitry 116. In operation, fetch circuitry 104 fetches instructions from code storage device 102, which may include, but is not limited to, cache memory, on-chip memory, memory on the same die as the processor, instruction registers, general registers, or system memory. In some embodiments, the format of the instructions is similar to that of the instructions described with respect to Figures 7 to 10 1 and 1. The format of the instruction format shown and discussed above is any one or more of the following. After the fetch circuit fetches the instruction, the decoding circuit 106 decodes the fetched instruction, including by parsing the opcode and various fields of the instruction. After the decoding circuit 106 decodes the instruction, the scheduling circuit 108 selects an execution circuit from multiple circuits in the computing system to execute the decoded instruction. The selected execution circuit 110 then executes the decoded instruction. When executing the instruction, the execution circuit 110 can read data from registers 112 and memory 114 and write data to the registers and memory. Registers 112 can include, but are not limited to, data registers, instruction registers, vector registers, mask registers, general registers, on-chip memory, memory located on the same die as the processor, or memory located in the same package as the processor. Memory 114 can be, but is not limited to, on-chip memory, memory located on the same die as the processor, memory located in the same package as the processor, cache memory, or system memory. After execution circuitry 110 executes an instruction, in some embodiments retirement or commit circuitry 116 retires the instruction, ensuring that the execution results are or have been written to their destinations and freeing or releasing resources for later use.

[0046] Embodiments disclosed herein provide a family of atomic memory instructions. Each of the executed atomic memory instructions detailed herein performs an atomic update operation (e.g., read-modify-write) on a memory location. Memory accesses are weakly ordered with respect to other instructions from the same thread and are similar to non-temporal (NT) stores. While such memory accesses are weakly ordered to improve performance, some embodiments may allow for a stronger form of ordering. However, the instructions do avoid traditional data hazards—read after write, write after read, and write after write dependencies—using instructions from the same thread. The instructions may be executed in various locations, such as at a processor core, at a private cache, at a shared cache, at a cache control circuit (10) (sometimes referred to as a cache and home agent (CHA)), at a memory controller, or at a remote core. In some embodiments, each instruction will perform parallel operations on elements of a vector register. In some embodiments, scalar operations are performed on general purpose registers.

[0047] Figure 2 2 is a flow chart of a process to be performed by a processor for executing a remote atomic operation instruction according to some embodiments. As shown, after starting, at 202, fetch circuitry fetches an instruction from a code storage device, the instruction including an opcode, a source identifier, and a destination identifier. In some embodiments, the instruction includes a second destination identifier. In some embodiments, the instruction includes an immediate value (constant value). At 204, the fetched instruction is decoded by decode circuitry.

[0048] At 206, the scheduling circuit selects an execution circuit from among a plurality of circuits in the system to execute the instruction, since the disclosed embodiments can execute the instruction in a variety of system locations. Figure 5 and Figure 6 and its associated description presented below in the section under the subheading "Where the RAO Instruction is Executed" describe various potential execution locations.

[0049] In some embodiments, at least one of the plurality of circuits in the system generates a heuristic indicative of the measured power and performance state, and the scheduling circuitry uses the generated heuristic to inform its selection of the execution circuit.

[0050] At 208, operands are retrieved from their registers or memory locations to be used in executing the instruction. Figure 2208 is shown using a dashed line to indicate that it is optional, at least when it is performed. In some embodiments, for example, retrieving the operand is part of decoding the instruction performed at 204. In some embodiments, retrieving the operand is part of scheduling the instruction and is performed by scheduling circuitry. In some embodiments, retrieving the operand is part of executing the instruction performed at 212 and is performed by execution circuitry.

[0051] At 210 , scheduling circuitry schedules execution of the decoded instructions out of order with respect to other instructions. Figure 2 210 is shown using dashed lines to indicate that the scheduling function is optional to the extent that it may be performed by decode circuitry, execution circuitry, rename / allocation circuitry, and / or retirement circuitry, as described with respect to FIG. Figure 4 、 Figure 12A and Figure 12B As shown and described.

[0052] The scheduling circuitry schedules the execution of decoded instructions in an order selected to optimize at least one of latency, throughput, power, and performance. For example, memory accesses to sequential memory addresses can be grouped to allow the memory accesses to be executed as a burst rather than sequentially, thereby improving throughput, power, and performance. As another example, to improve latency, memory load instructions can be moved to execute at a time much earlier than the time the loaded data is needed, thereby hiding some of the latency associated with the load. As another example of optimizing power and performance, memory store instructions can be moved to execute instructions with operands ready first before instructions waiting for operands to be ready. As another example of optimizing power, memory accesses to DRAM memory can be sorted so that accesses are grouped into the same DRAM bank, thereby minimizing the number of DRAM bank precharges required.

[0053] At 214, the instruction is retired, writing the execution results into its destination and freeing up resources for use by subsequent instructions.

[0054] In some embodiments, the execution at 212 includes: atomically reading data from the location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using source operands identified by the source identifier; and writing the result of the operation to the location identified by the destination identifier. Thus, these embodiments use the destination as both a source and a destination.

[0055] In some embodiments, the execution at 212 includes: atomically reading data from the location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation ignoring the source operand identified by the source identifier; and writing the result of the operation to the location identified by the destination identifier. Thus, these embodiments use the destination as both the source and the destination, and ignore the source.

[0056] In some embodiments, the execution at 212 includes: atomically reading data from the location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation ignoring at least a portion of the data retrieved from the destination (e.g., using a mask register to mask certain elements of a vector retrieved from the destination), using a source operand identified by the source identifier; and writing a result of the operation to the location identified by the destination identifier. Thus, these embodiments use the source and ignore at least a portion of the destination.

[0057] In some embodiments, the execution at 212 includes: atomically reading data from the location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation ignoring at least a portion of the data retrieved from the destination (e.g., ignoring certain elements of the vector retrieved from the destination) and ignoring source operands identified by the source identifier; and writing the result of the operation to the location identified by the destination identifier. Thus, these embodiments ignore at least a portion of the destination and ignore the source.

[0058] The instructions may operate on vector or scalar data as controlled by the opcode. In some embodiments, the instructions are part of a strongly-ordered instruction set. In some embodiments, the fetch circuitry, the decode circuitry, and the execution circuitry fetch, decode, and execute a plurality of strongly-ordered instructions in order according to a more strongly-ordered memory model.

[0059] Figure 3 3 is a block diagram illustrating a portion of a multi-core processor for executing RAO instructions according to some embodiments. As shown, the multi-core processor 300 includes a core cluster 302, a cache consistency protocol interface (CCPI) 312, and a cache control circuit 314. The cache consistency protocol interface (CCPI) 312 couples the core cluster 302 to the cache control circuit 314. Also shown is a snoop filter / last level cache (SF / LLC) 324, which will be used by the cache control circuit 314 to service the RAO instruction. In some embodiments, the cache control circuit 314 is referred to as a cache and home agent (CHA).

[0060] according to Figure 3In an embodiment, core cluster 302 includes circuitry 304 that includes at least a portion of a processor pipeline to be used when executing remote atomic operation instructions according to some embodiments disclosed herein. Circuitry 304 may be used, for example, to implement Figure 2 、 Figure 4 、 Figure 9 and Figure 11 That is, the circuit system 304 includes a fetch stage for fetching instructions from a code storage device, a decode stage for decoding the instructions, a dispatch stage for scheduling execution, an execute stage for performing the operations specified by the instructions, and a retirement stage for retiring the instructions.

[0061] In some embodiments, the decode stage of circuitry 304 decodes each instruction into one or more micro-operations (uOps) and stores the micro-operations in a uop queue. In some embodiments, while the uOps remain in the uop queue, the dispatch stage causes the retrieval of operands required by the uOps. In some embodiments, instructions enter the dispatch stage in program order, but the dispatch stage selects uOps out of order to send for execution. The dispatch circuitry in such embodiments bases its selection on an attempt to improve at least one of latency, throughput, power, and performance.

[0062] In some embodiments, the execution stage of circuitry 304 utilizes at least three execution stacks, each stack encapsulating a certain type of data and including one or more of an arithmetic logic unit (ALU), a shifter, and a memory request generator. In some embodiments, for example, different stacks are used for integer data, floating point data, and mixed integer and floating point simultaneous instruction multiple data (SIMD) data.

[0063] In some embodiments, the execution stage of the circuit system 304 provides multiple ports to which the scheduling circuitry issues uOps. For example, in some embodiments, the execution stage provides five ports to which uOps can be scheduled simultaneously. Thus, in some embodiments, the execution stage can simultaneously execute uOps associated with multiple threads. In some embodiments, the execution stage can simultaneously receive and process uOps associated with more than one logical processor.

[0064] In some embodiments, core cluster 302 includes a load / store unit (LSU) 306. As shown, LSU 306 includes buffers—a load buffer (LB), a store data buffer (SD), and a store buffer (SB)—for maintaining data transfers between circuitry 304 and L1 / L2 cache 308. In some embodiments, each entry in the LB buffer, the SD buffer, and the SB buffer is 64 bytes wide.

[0065] As shown, core cluster 302 includes L1 / L2 cache 308. The cache hierarchy in core cluster 302 includes a first-level instruction cache (L1ICache), a first-level data cache (L1DCache), and a second-level (L2) cache. When circuit system 304 implements multiple logical processors, the multiple logical processors share the L1DCache. The L2 cache is shared by both instructions and data. In some embodiments, the L1 data and instruction caches each have a capacity of 32kB, are 8-way set associative, and have a cache line size of 64 bytes. In some embodiments, the L1 and L2 data caches are non-blocking, so they can handle multiple simultaneous cache misses.

[0066] As shown, core cluster 302 includes a bus interface unit (BIU) 310 that, in operation, handles the transfer of data and addresses by issuing addresses, fetching instructions from code storage, reading data from ports and memory, and writing data to ports and memory.

[0067] according to Figure 3 A cache coherence protocol interface (CCPI) 312 of an embodiment provides a bidirectional data path between the core cluster 302 and the cache control circuitry 314 .

[0068] As shown, cache control circuitry 314 includes an entry 316, a request table 318, a snoop filter / last-level cache (SF / LLC) 324, an execution pipeline 322, and a home agent 320. Entry 316 communicates with cache coherence protocol interface (CCPI) 312 and buffers transactions to and from the CCPI. In some embodiments, request table 318 includes registers or static random access memory for maintaining up to 64 memory requests and their progress. In some embodiments, SF / LLC 324 includes a snoop filter for responding to snoop requests from other core clusters and a last-level cache that includes the contents of lower-level caches in core cluster 302. In other words, in some embodiments, any cache line valid in L1 / L2 cache 308 is also present in the last-level cache. In some embodiments, execution pipeline 322 enhances read-modify-write functionality by providing additional integer operations with reduced latency. In some embodiments, for example, request table 318 holds the destination address and an immediate value (constant value) to be added to the value, and then the sum is written back to the destination address.

[0069] Figure 4is a flow chart of a process performed by a processor for executing remote atomic operation instructions according to some embodiments. Process 400 is performed using, for example, Figure 3 3. After the start, at 402, an instruction is fetched from the code storage device by the fetch circuitry. The fetched instruction includes an opcode, a source identifier, a destination identifier specifying a memory location, and a second destination identifier specifying a register. At 404, the fetched instruction is decoded by the decode circuitry.

[0070] At 406, a determination is made as to whether the designation is to be weakly ordered. In some embodiments, this determination is made by scheduling circuitry. In some embodiments, for example, the scheduling circuitry accesses a page table having a plurality of entries, each entry storing a mapping between a virtual address and a physical address of an associated memory page, each entry further specifying whether to weakly order remote atomic operations on the associated memory page. In some embodiments, the RAO instruction itself specifies whether the RAO instruction is to be weakly ordered or strongly ordered, via an opcode, an opcode suffix, or an additional instruction operand. Some RAO instructions may be allowed to be weakly ordered, while other RAO instructions may be strongly ordered.

[0071] If the instructions are to be weakly ordered, then at 408, the scheduling circuitry selects an order for execution of the decoded instructions, the order being selected to optimize at least one of latency, throughput, power, and performance. For example, memory accesses to sequential memory addresses can be grouped to allow the memory accesses to be executed as a burst rather than sequentially, thereby improving throughput, power, and performance. As another example, to improve latency, memory load instructions can be moved to execute at a time much earlier than the time the loaded data is needed, thereby hiding some of the latency associated with the load. As another example of optimizing power and performance, memory store instructions can be scheduled to reference instructions with operands ready before instructions waiting for operands to be ready. As another example of optimizing power, memory accesses to DRAM memory can be sorted so that accesses are grouped into the same DRAM bank, thereby minimizing the number of DRAM bank precharges required.

[0072] At 410 , the scheduling circuitry schedules execution of the RAO instructions, either in a strong ordering or according to the order selected at 408 .

[0073] At 412, the scheduling circuitry selects circuitry within the system for executing the decoded instruction, since the disclosed embodiments can execute the instruction in a variety of system locations. Figure 5 and Figure 6 and its associated description presented below in the section under the heading "Where the RAO Instruction is Executed" describe various potential execution locations.

[0074] In some embodiments, the instruction decoded at 404 includes a hint for suggesting which circuit of the plurality of circuits is to execute the decoded instruction, wherein the hint includes at least one of an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register. For example, the instruction may include a "core" prefix or suffix to indicate that the instruction should be executed in a processor core. For example, the instruction may include a "remote" prefix or suffix to indicate that the instruction should be executed in a remote processing core. For example, the instruction may include a "PROX" prefix or suffix to indicate that the instruction should be executed by a circuit proximate to where the destination data is expected to be found (such as, for example, a private cache of a thread of a core associated with executing the RAO instruction).

[0075] At 414, the scheduling circuitry dispatches the decoded instructions to the selected execution circuitry and retires the instructions, thereby hiding subsequent latency associated with the write.

[0076] At 416, the selected execution circuit executes the instruction and causes the execution result to be written back to the memory location specified by the destination identifier and the register specified by the second destination identifier. In some embodiments, the selected execution circuit uses a write back / memory write stage 1418 ( Figure 14A ) etc. to write the execution result. In some embodiments, the selected execution circuit uses a memory unit 1470 and / or a memory access unit 1464 ( Figure 14A 、 Figure 14B ) to write the execution result back to the memory location specified by the destination identifier. In some embodiments, the selected execution circuit uses a rename / allocator unit 1452 ( Figure 14B ) and other register allocation circuits to write the execution results back to the specified registers.

[0077] At 418, the processor guards against data conflicts by preventing consumers of the identified destination register from reading erroneous values. In some embodiments, such as cache control circuitry 314 ( Figure 3 ) and other cache control circuits prevent data conflicts by maintaining a table of requests that have been retired but not yet committed, such as request table 318 ( Figure 3 ); and checking for conflicts among subsequent accesses to the same cache line or cache element awaiting debugging. In some embodiments, the plurality of circuits within the processor include at least two of the following: scheduling circuitry, rename / allocator unit 1452 ( Figure 14B ), memory unit 1470 ( Figure 14B ), (multiple) memory access units 1464 ( Figure 14B ), L2 cache unit 1476 ( Figure 14B ), decoding unit 1440 ( Figure 14B ).

[0078] The process then ends.

[0079] Where to perform RAO operations

[0080] Remote atomic operation instructions as defined in various embodiments herein may be executed in various locations in a processor, such as at one or more of the cores of a multiprocessor, at a private cache, at a shared cache, at a cache control circuitry (sometimes referred to as a cache and home agent (CHA)), at a memory controller, at a remote core, on a coprocessor, or at an accelerator. RAO instructions are used for both single-socket and multi-socket systems.

[0081] Figure 5 5 is a block diagram of an exemplary system for executing remote atomic operation instructions according to some embodiments. As shown, system 500 includes processors 570 and 580, which include integrated memory controllers ("IMC") 572 and 582, respectively, for connecting to memory 532 and memory 534, respectively. Processors 570 and 580 each include one or more processor cores 574 and 584; cache control circuitry (10) 575 and 585; last level cache (LLC) 577 and 587; and point-to-point interfaces 576, 578, 586, and 588 coupled to other components using interconnects 550, 552, and 554. System 500 further includes a chipset 590, which includes point-to-point interfaces 594 and 598 and high-performance interfaces 592 and 596 for communicating with bus 516 and optional coprocessor 538. Cache control circuitry 575 and 585 are sometimes referred to as cache and home agents (CHAs).

[0082] In some embodiments, the location where the remote atomic operation is to be performed is, for example, during process 400 at block 412 ( Figure 4 ) is selected.

[0083] In some embodiments, the execution circuit selected at 408 will reflect a static selection, eg, as designed by a hardware designer of system 500. Each of processor cores 574 and 584 may be associated with cache control circuitry (10) for executing remote atomic operation instructions.

[0084] In other words, in some embodiments, the location where the remote atomic operation instruction will be executed will be statically selected by the hardware designer, for example, by a hash function that maps the address to the cache control circuit (10).

[0085] In some embodiments, the location where the remote atomic operation instruction will be executed will be statically selected by software.

[0086] In some embodiments, the location where the remote atomic operation instructions will be executed will be statically selected, as each instruction is controlled by, for example, including an immediate operand indicating where to execute the instruction.

[0087] In some embodiments, the processor will include a software programmable control register that will be set by software to indicate where the RAO instruction should be executed.

[0088] In some embodiments, the processor will include separate software programmable control registers that will be set by software for different instructions (e.g., ADD and CMPXCHG) or different groups of instructions (e.g., integer and floating point) to indicate where the RAO instruction will be executed.

[0089] In some embodiments, the processor will include a separate software programmable control register for each different type of instruction or group of instructions, which will be set by software to indicate where the RAO instruction is to be executed.

[0090] In some embodiments, the processor will have separate control over different instructions or groups of instructions.

[0091] In some embodiments, the processor will use some information from the hardware to predict the best location to execute the RAO instruction. In such embodiments, the processor will use both information received from the hardware and controls provided by software (e.g., as part of an instruction, as a control register, or as part of a page table entry) to determine where to execute the RAO instruction. In such embodiments, the controls provided by the software are more like guidance than instructions.

[0092] In some embodiments, properties will be added to addresses (eg, in page table entries) to indicate where the RAO instruction should be executed for those addresses.

[0093] Figure 61 shows a physical memory having various memory regions mapped for executing RAO instructions at various locations according to some embodiments. As shown, physical memory 600 includes code and storage region 602 for task 1, code and storage region 604 for task 2, code and storage region 606 for task N, and region 608 for the operating system. In some embodiments, RAO instructions directed to memory addresses for tasks 1 through N will use different hardware to execute the RAO instructions. As shown, a RAO instruction with a destination identifier pointing to a memory address in region 802 for task 1 will use a processor core, e.g., Figure 5 The execution circuitry in one of the processor cores 574 in FIG. 1; the RAO instruction having a destination identifier pointing to the region 804 of Task 2 will use the cache control circuitry, e.g. Figure 5 and the RAO instruction with a destination identifier pointing to the region 606 of task N will use the execution circuit system in 10 575; Figure 5 The mapping of each memory region to the execution circuit location can be achieved by adding a page table entry that specifies where the RAO instruction for this region will be executed.

[0094] In some embodiments, performance metrics are collected and used to dynamically select where to execute RAO instructions. For example, the queue depth in the transaction ordering structure of the cache control circuitry can be used to direct RAO instructions to be executed by less heavily loaded cache control circuitry (sometimes referred to as cache and home agents). As another example, by, for example, Figure 3 Traffic statistics collected by the cache coherence protocol interface (CCPI) 312 in the Cache Coherence Protocol Interface can be used to direct RAO instructions to be executed by less loaded network nodes. As another example, at least some actual latency can be measured, and RAO instructions that experience more than a threshold amount of latency will be assigned to random execution circuits on a trial-and-error basis to improve latency. As another example, RAO instructions originating from an application will be assigned to the processing core executing the application for execution. This mapping can be achieved by adding a mapping to a page table for the memory area used by the application.

[0095] RAO instruction type

[0096] In some embodiments, executing the instructions will involve a read-modify-write, whereby the processor reads the contents of a memory location, modifies the data read, and writes the result back to the memory location.Optional parameters may be used to modify the operations performed during the modify stage.

[0097] There are at least two different classes of RAO instructions: RAO instructions whose only output is a memory location that is updated atomically, and RAO instructions that also have a destination register. There are microarchitectural implications for this difference. Within each class, there are multiple subclasses of RAO instructions.

[0098] RAO instructions whose only output is a memory location that is updated atomically can be weakly ordered; due to weak ordering, such RAO instructions are retired immediately upon issuing the operation to the memory system, without waiting for the operation to complete. On the other hand, instructions with register destinations retire after the core receives the data. For this reason, in some embodiments, instructions with register destinations have stronger ordering requirements than first-class RAO instructions.

[0099] All RAO ​​instructions take a memory destination and a general register operand. Additionally, some RAO instructions take an additional implicit operand (e.g., in RAX). The following table describes some RAO instructions with an optional second destination and an immediate (constant) operand.

[0100] Table 1 - No register destination (i.e., opcode memdest(memory destination), reg(register))

[0101]

[0102]

[0103] In some embodiments, the remote atomic operation instruction updates a memory location and also writes the result to a register.

[0104] Table 2 - Remote Atomic Operation (RAO) Instructions with Register Destination

[0105] (i.e., opcode memory destination, [register destination], [register])

[0106]

[0107]

[0108] In some embodiments, the remote atomic operation instruction is one of the following: integer addition, integer addition with threshold, integer subtraction, integer subtraction with threshold, integer saturating addition, integer subtraction with floor, logical AND, logical OR, logical XOR, floating point addition, floating point subtraction, update to minimum and update to maximum, integer swap and add, swap, compare and swap, floating point swap and add.

[0109] RAO instruction format

[0110] Reference Figures 7 to 10The format of the RAO instruction according to the embodiments disclosed herein is shown and described.

[0111] Figure 7 7 is a block diagram illustrating the format of an instruction for a remote atomic operation according to some embodiments. As shown, instruction 700 includes an opcode 702, an optional size identifier 704, a source identifier 706, a destination identifier 708, and an optional second destination identifier 710 (optional instruction fields are shown in a box with a dashed outline).

[0112] The optional size identifier 704 is shown as a separate instruction operand, but in some embodiments, it will be included in the opcode prefix or suffix "B", "W", "D", and "Q" corresponding to the size of 1 byte, 2 bytes, 4 bytes, or 8 bytes, respectively, of each source vector element. In some embodiments, the optional size identifier 704 is included in the opcode of each source vector element, such as the prefix or suffix "H", "S", "D", "Q", and "E" corresponding to the precision levels: half precision (2 bytes), single precision (4 bytes), double precision (8 bytes), and quadruple precision (16 bytes), respectively. In other embodiments, the optional size identifier 704 is an instruction parameter or operand that specifies the size and / or precision level of the source vector element. Figure 8 Display the size identifier as part of the opcode.

[0113] In some embodiments, source identifier 706 is used to specify a source vector register, such as a vector register included in a register file of a processor. Figure 11 Embodiments of a register file for a processor are further described below in conjunction with its associated description.In some embodiments, source identifier 706 is used to identify a memory location.

[0114] The destination identifier 708 and the optional second destination identifier 710 identify two locations: a vector register of a processor's register file or a memory location, to which the execution results are to be written according to some embodiments disclosed herein.

[0115] Figure 8 8 is a block diagram illustrating the format and optional parameters of a remote atomic operation instruction according to some embodiments. As shown, instruction 800 includes an opcode 802 , an optional size identifier 804 , a source identifier 806 , a destination identifier 808 , and an optional second destination identifier 810 .

[0116] In some embodiments, the optional size identifier 804 is included in the opcode for each source vector element, for example as a prefix or suffix "B", "W", "D", and "Q" corresponding to a size of 1 byte, 2 bytes, 4 bytes, or 8 bytes, respectively. In some embodiments, the optional size identifier 804 is included in the opcode prefix or suffix "H", "S", "D", "Q", and "E" corresponding to the precision levels of half precision (2 bytes), single precision (4 bytes), double precision (8 bytes), and quadruple precision (16 bytes), respectively, for each source vector element. In other embodiments, the optional size identifier 804 is an instruction parameter or operand that specifies the size and / or precision level of the source vector element.

[0117] In some embodiments, source identifier 806 is used to specify a source vector register, such as a vector register included in a register file of a processor. Figure 11 The source identifier 806 is used to identify a memory location.

[0118] The destination identifier 808 and the optional second destination identifier 810 are used to identify two locations: a vector register of a processor's register file or a memory location, to which the execution results are to be written, according to some embodiments.

[0119] The format of instruction 800 may specify optional parameters, some examples of which are shown as, but not limited to, mathematical operations 812 (e.g., addition, subtraction, division, multiplication, modulus, etc.), logical operations 814 (e.g., AND, OR, NAND, NOR, XOR, XOR, CMP, etc.), swaps 816, thresholds 818, and floor 820. In some embodiments, these optional parameters are included as part of the opcode, perhaps separated by underscores. In other embodiments, these parameters are separate operands or instruction fields.

[0120] In some embodiments, executing the instructions will involve a read-modify-write, whereby the processor reads the contents of a memory location, modifies the data read, and writes the result back to the memory location.The aforementioned optional parameters may be used to modify the operations performed during the modify stage.

[0121] For example, the opcode modifier math operation 812 may be _ADD_, in which case the processor reads the data at the location identified by the destination identifier 808, adds the data at the location identified by the source identifier 806, and writes the result back to the location identified by the destination identifier 808; and if the instruction includes an optional second destination identifier 810, the processor also writes the result to the location identified by the optional second destination identifier 810, which may be a register.

[0122] RAOOPMEMREG instruction

[0123] Example Implementation

[0124] Embodiments of the RAOOPMEMREG instruction for improving computing performance are described herein. Specifically, execution of the RAOOPMEMREG instruction can be weakly ordered, can be performed by multiple circuits within a processor, and causes the processor to atomically read data from a memory location, perform an operation on the data as specified by an opcode, and write the result of the operation back to a location identified by a destination identifier.

[0125] Figure 9 902 includes fields for an opcode 904 (e.g., the mnemonic "RAOOPMEMREG*"), a first destination operand (DST1 906) for specifying a memory location, a second destination operand (DST2 908) for specifying a register, and a source identifier (SRC 910) for specifying a source location 912. As shown, opcode 904 RAOOPMEMREG* includes an asterisk ("*"), which represents a suffix or prefix that can be added to the opcode to control the operation of the instruction.

[0126] In some embodiments, DST1 specifies the memory address of a cache line residing somewhere in the memory hierarchy: for example, in the L1 cache, in the L2 cache, in the last level cache (LLC), or in memory. DST2 specifies a register in the register architecture, for example, a general register, a vector register, or Figure 13 In some embodiments, the source identifier SRC 910 identifies a register that holds an operand to be used in an operation. In some embodiments, the source identifier SRC 910 identifies a memory location.

[0127] As shown, the RAOOPMEMREG* instruction can operate on scalars or vectors, but is not limited thereto. In some embodiments, DST1 906, DST2 908, and SRC 910 identify scalar data in integer format or floating point format. In some embodiments, DST1 906, DST2 908, and SRC 910 identify vector data to be operated on in parallel by parallel hardware.

[0128] In response to an instruction having an opcode 904 equal to RAOOPMEMREG*, the execution circuit system 916 first reads the data from the memory destination 914, then performs an operation (OP 918) on the data and the contents of the source location 912, and again writes the result of the operation back to the memory destination and also to the register destination 920. Figure 9 The execution order of the RAOOPMEMREG instruction is illustrated using numbered circles 1, 2, and 3 shown in the order of execution.

[0129] Example Hardware for Executing the RAOOPMEMREG Instruction

[0130] Figure 10 An embodiment of hardware for processing RAO instructions is shown. As shown, a storage device 1003 stores a RAOOPMEMREG instruction 1001 to be executed.

[0131] The instruction is received by decoding circuitry 1005. For example, decoding circuitry 1005 receives this instruction from fetch logic / circuitry. Instruction 1001 includes fields for: opcode 904, a memory identifier for specifying a memory destination, a destination register identifier for specifying a register destination, and a source identifier for specifying a source location. Decoding circuitry 1005 decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be executed by execution circuitry (e.g., execution circuitry 1009 or 916). Decoding circuitry 1005 also decodes the instruction prefix (if used).

[0132] In some embodiments, the register renaming, register allocation and / or scheduling circuitry 1007 provides one or more of the following functions: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in some embodiments, a register alias table); 2) assigning status bits and flags to decoded instructions; and 3) scheduling decoded instructions for execution by the execution circuitry outside of the instruction pool (e.g., in some embodiments, using a reservation station).

[0133] Registers (register file) and / or memory 1008 store data as operands for instructions to be operated on by the execution circuitry.Exemplary register types include packed data registers, general purpose registers, and floating point registers.

[0134] The execution circuitry 1009 executes the decoded RAOOPMEMREG instruction. Figure 9Rather, an embodiment of execution circuitry is shown and described, and is one embodiment of execution circuitry 1009. Write-back (retirement) circuitry 1011 commits the results of executing a decoded RAOOPMEMREG instruction.

[0135] Example format of the RAOOPMEMREG instruction

[0136] In some embodiments, retirement / write-back circuitry architecturally commits the destination register into a register or memory and retires the instruction.

[0137] An embodiment of the format of the RAOOPMEMREG instruction is OPCODE, MEMDST, REGDST, and SRC. In some embodiments, RAOOPMEMREG{B / W / D / Q} is the opcode mnemonic for the instruction. SRCREG is a field used to identify the packed data source register operand, and DSTREG is a field used to identify the packed data destination register operand.

[0138] In some embodiments, the OPCODE field is a full opcode field, such as full opcode field 1274 (FIG. 12) or an actual opcode field such as 1230 (FIG. 12), the MEMDST field is, the SRCREG field is a Reg field such as REG 1244 (FIG. 12), and the DSTREG field is an R / M field such as 1246 (FIG. 12).

[0139] In some embodiments, the RAOOPMEMREG instruction includes a field for writing a mask register operand (k) (e.g., RAOOPMEMREG{k}DSTREG, SRC1, SRC2). The write mask is used to conditionally control per-element operations and result updates. According to an embodiment, the write mask uses a merge and zero mask. Instructions encoded with a predicate (write mask, write mask, or k register) operand use this operand to conditionally control per-element calculation operations and result updates to the destination operand. The predicate operand is called an opmask (write mask) register. In some embodiments, opmask is a set of architectural registers with a size of 64 bits. Note that, based on this set of architectural registers, only k1 to k7 can be addressed as predicate operands. k0 can be used as a conventional source or destination, but cannot be encoded as a predicate operand. Also note that predicate operands can be used to implement memory fault suppression for some instructions with memory operands (source or destination). As a predicate operand, the opmask register contains one bit for managing operations / updates on each data element of a vector register. Typically, the opmask register can support instructions with multiple element sizes: single-precision floating point (float32), integer doubleword (int32), double-precision floating point (float64), and integer quadword (int64). The opmask register's length, MAX_KL, is sufficient to handle up to 64 elements, or 64 bits, with one bit per element. For a given vector length, each instruction accesses only the number of least significant mask bits required based on its data type.

[0140] The opmask register affects instructions at a per-element granularity. Therefore, any numeric or non-numeric operation on each data element and any per-element update of intermediate results to the destination operand are based on the corresponding bit of the opmask register. In most embodiments, the opmask acting as this operand is subject to the following properties: 1) if the corresponding opmask bit is not set, the operation of the instruction is not performed on the element (this implies that operations on masked-off elements do not cause exceptions or violations, and therefore, no exception flags are updated due to masked-off operations); 2) if the corresponding write mask bit is not set, the destination element is not updated with the result of the operation; instead, the destination element must be retained (merge mask) or it must be zeroed (zero mask); and 3) for some instructions with memory operands, memory faults are suppressed for elements with mask bit 0. Note that since the mask effectively provides merging behavior to the vector register destination, this feature provides a general construct to implement control flow prediction. As an alternative, masks can be used for zeroing instead of merging, so that masked elements are updated to 0 instead of retaining their old values. The zeroing behavior is provided to remove the implicit dependency on old values ​​when they are not needed.

[0141] In one embodiment, the encoding of an instruction includes a scale-index-base (SIB) type memory addressing operand that indirectly identifies a plurality of indexed destination locations in memory. In one embodiment, the SIB type memory operand may include an encoding that identifies a base address register. The contents of the base address register may represent a base address in memory from which the address of a particular destination location in memory is calculated. For example, the base address may be the address of a first location in a batch of potential destination locations for an extend vector instruction. In one embodiment, the SIB type memory operand may include an encoding that identifies an index register. Each element of the index register may specify an index or offset value that may be used to calculate the address of a corresponding destination location within the batch of potential locations based on the base address. In one embodiment, the SIB type memory operand may include an encoding that specifies a scale factor to be applied to each index value when calculating the corresponding destination address. For example, if a scale factor value of four is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to calculate the destination address.

[0142] In one embodiment, a SIB-type memory operand of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements each having a 32-bit index value. The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, a SIB-type memory operand of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements each having a 64-bit index value. The vector index register may be a 128-bit register (eg, XMM) register (vm64x), a 256-bit (eg, YMM) register (vm64y), or a 512-bit (eg, ZMM) register (vm64z).

[0143] Example Method of Executing the RAOOPMEMREG Instruction

[0144] Figure 11 An embodiment of a method for executing a RAO instruction performed by a processor is shown. For example, Figure 10 The processor components (such as the pipeline described in detail below) execute this method.

[0145] At 1101, an instruction is retrieved. For example, a RAOOPMEMREG instruction is retrieved. The RAOOPMEMREG instruction includes fields for an opcode, a first destination operand identifying a memory location, a second destination operand specifying a source, and a source operand identifying a source. In some embodiments, the instruction further includes a field for a write mask. In some embodiments, the instruction is retrieved from an instruction cache. The destination operand specifies a packed data vector register. The opcode of the RAOOPMEMREG instruction indicates that vector register elements are to be broadcast.

[0146] The fetched instruction is decoded at 1103. For example, the fetched RAOOPMEMREG instruction is decoded by the decoding circuitry as described in detail herein.

[0147] Decoded instructions are dispatched (as needed).

[0148] At 1107, the decoded instruction is executed by the instruction circuitry (e.g., 916 or 1009). For the RAOOPMEMREG instruction, execution causes the execution circuitry to read data from the destination memory location, perform the operation using the data and the source register as operands, and write the result of the operation back to the destination memory location. For example, in one embodiment, the execution circuitry performs a read-modify-write to read a scalar value stored in memory, add the value stored in the register to the scalar value, and write it back to the memory location. In another embodiment, the execution circuitry performs a read-modify-write to read a vector from memory, multiply each element in the vector by the value stored in the general register, and write the vector back to memory. In another embodiment, the execution circuitry performs a read-modify-write to read a vector from memory, compare the vector to a vector stored in a vector register to identify the maximum value of each element, and write the resulting vector back to the memory location, wherein each element of the resulting vector is set to the maximum value of the previous contents of the vector in memory and the vector in the vector register.

[0149] In some embodiments, at 1109, the instruction is committed or retired.

[0150] instruction set

[0151] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify, among other things, the operation to be performed (opcode) and the operand(s) on which the operation is to be performed. Some instruction formats are further broken down by the definition of instruction templates (or subformats). For example, the instruction templates for a given instruction format may be defined as having different subsets of the fields of that instruction format (the fields included are generally in the same order, but at least some fields have different bit positions because fewer fields are included), and / or as having given fields interpreted in different ways. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, according to a given one of the instruction templates for that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, the specific instruction format including an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the ADD instruction appearing in the instruction stream will have specific content in the operand field for selecting a specific operand.

[0152] Example instruction format

[0153] The embodiments of the instruction(s) described herein can be implemented in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. The embodiments of the instruction(s) can be executed on such systems, architectures, and pipelines, but are not limited to the embodiments described in detail.

[0154] VEX instruction format

[0155] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 128 bits. The use of the VEX prefix provides a syntax for three operands (or more). For example, the previous two operand instructions performed an operation such as A=A+B, which overwrote the source operand. Using the VEX prefix allows operands to perform non-destructive operations such as A=B+C.

[0156] FIG12 shows an AVX instruction format including a VEX prefix 1202 , an actual opcode field 1230 , a Mod R / M byte 1240 , a SIB byte 1250 , a shift field 1262 , and an IMM8 1272 . Figure 12B It shows which fields in FIG. 12 make up the complete opcode field 1274 and base operation field 1242 . Figure 12C It shows which fields make up the register index field 1244 in FIG. 12 .

[0157] The VEX prefix (bytes 0-2) 1202 is encoded in three bytes. The first byte is the format field 1240 (VEX byte 0, bits [7:0]), which contains a clear C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include multiple bit fields that provide specific capabilities. Specifically, the REX field 1205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bit [7] - R), the VEX.X bit field (VEX byte 1, bit [6] - X), and the VEX.B bit field (VEX byte 1, bit [5] - B). The other fields of the instruction encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, so that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B.

[00105] The opcode map field 1215 (VEX byte 1, bits [4:0] - mmmmm) includes content for encoding the implied leading opcode byte. The W field 1264 (VEX byte 2, bits [7] - W) is denoted by the symbol VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 1220 (VEX byte 2, bits [6:3] - vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1's complement) form and is valid for instructions with 2 or more source operands; 2) VEX.vvvv encodes the destination register operand, specified in 1's complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. If the VEX.L 1268 size field (VEX byte 2, bit [2]-L) = 0, then VEX.L represents a 128-bit vector; if VEX.L = 1, then VEX.L represents a 256-bit vector. The prefix encoding field 1225 (VEX byte 2, bits [1:0]-pp) provides additional bits for the base address operation field.

[0158] The actual opcode field 1230 (byte 3) is also called the opcode byte. A portion of the opcode is specified in this field.

[0159] The MOD R / M field 1240 (byte 4) includes a MOD field 1242 (bits [7-6]), a Reg field 1244 (bits [5-3]), and an R / M field 1246 (bits [2-0]). The Reg field 1244 may be used to encode a destination register operand or a source register operand (Rrrr's rrr), or it may be treated as an opcode extension and not used to encode any instruction operand. The R / M field 1246 may be used to encode an instruction operand that references a memory address, or it may be used to encode a destination register operand or a source register operand.

[0160] Scale, Index, Base (SIB) - The contents of the scale field 1250 (byte 5) include SS 1252 (bits [7-6]) used for memory address generation. The contents of SIB.xxx 1254 (bits [5-3]) and SIB.bbb 1256 (bits [2-0]) have been previously referenced for register indexes Xxxx and Bbbb.

[0161] The shift field 1262 and the immediate field (IMM8) 1272 contain data.

[0162] Exemplary Register Architecture

[0163] Figure 13 is a block diagram of a register architecture 1300 according to one embodiment of the present invention. In the embodiment shown, there are 32 512-bit wide vector registers 1310; these registers are referenced as zmm0 through zmm31. The lower-order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower-order 128 bits of the lower 16 zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0164] General purpose registers 1325 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0165] A scalar floating-point stack register file (x87 stack) 1345, on which an MMX packed integer flat register file 1350 is overlaid—in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; while MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between MMX and XMM registers.

[0166] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0167] Exemplary Core Architectures, Processors, and Computer Architectures

[0168] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic or as dedicated cores, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip, which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor(s) described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture. Detailed herein are circuits (units) including exemplary cores, processors, etc.

[0169] Exemplary Core Architecture

[0170] In-order and out-of-order core block diagram

[0171] Figure 14A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to various embodiments of the present invention. Figure 14B is a block diagram illustrating an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention. Figures 14A-14B The solid-line boxes in show the in-order pipeline and in-order core, while the optional addition of dashed-line boxes shows the register-renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0172] exist Figure 14A, the processor pipeline 1400 includes a fetch stage 1402, a length decode stage 1404, a decode stage 1406, an allocation stage 1408, a rename stage 1410, a schedule (also known as dispatch or issue) stage 1412, a register read / memory read stage 1414, an execute stage 1416, a write back / memory write stage 1418, an exception handling stage 1422, and a commit stage 1424.

[0173] Figure 14B A processor core 1490 is shown, comprising a front end unit 1430 coupled to an execution engine unit 1450, and both the front end unit 1430 and the execution engine unit 1450 are coupled to a memory unit 1470. The core 1490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 1490 may be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0174] Front end unit 1430 includes a branch prediction unit 1432, which is coupled to an instruction cache unit 1434, which is coupled to an instruction translation lookaside buffer (TLB) 1436, which is coupled to an instruction fetch unit 1438, which is coupled to a decode unit 1440. Decode unit 1440 (or decoder) can decode an instruction and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, reflect, or derived from the original instruction. Decode unit 1440 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, core 1490 includes a microcode ROM or other medium (e.g., in decode unit 1440 or otherwise within front end unit 1430) that stores microcode for certain macroinstructions. The decode unit 1440 is coupled to the rename / allocator unit 1452 in the execution engine unit 1450 .

[0175] Execution engine unit 1450 includes a rename / allocator unit 1452, which is coupled to a retirement unit 1454 and a set of one or more scheduler units 1456. Scheduler unit(s) 1456 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. Scheduler unit(s) 1456 are coupled to physical register file(s) units 1458. Each of physical register file(s) units 1458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating point, packed integers, packed floating point, vector integers, vector floating point, state (e.g., an instruction pointer, which is the address of the next instruction to be executed), and the like. In one embodiment, physical register file(s) units 1458 include a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. Physical register file(s) units 1458 are overlapped by retirement units 1454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using reorder buffer(s) and retirement register file(s); using future files(s), history buffer(s), retirement register file(s); using register maps and register pools, etc.). Retirement units 1454 and physical register file(s) units 1458 are coupled to execution cluster(s) 1460. Execution cluster(s) 1460 include a set of one or more execution units 1462 and a set of one or more memory access units 1464. Execution units 1462 can perform various operations (e.g., shifts, additions, subtractions, multiplications) and can operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler unit(s) 1456, physical register file(s) 1458, and execution cluster(s) 1460 are shown as potentially multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler unit, physical register file(s) and / or execution cluster—and in the case of separate memory access pipelines, certain embodiments are implemented in which only the execution cluster of that pipeline has memory access unit(s) 1464). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order.

[0176] A set of memory access units 1464 is coupled to a memory unit 1470, which includes a data TLB unit 1472, which is coupled to a data cache unit 1474, which is coupled to a level 2 (L2) cache unit 1476. In one exemplary embodiment, the memory access unit 1464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1472 in the memory unit 1470. The instruction cache unit 1434 is also coupled to a level 2 (L2) cache unit 1476 in the memory unit 1470. The L2 cache unit 1476 is coupled to one or more other levels of cache and ultimately to main memory.

[0177] As an example, the exemplary register renaming out-of-order issue / execution core architecture may implement the pipeline 1400 as follows: 1) instruction fetch 1438 executes the fetch stage 1402 and the length decode stage 1404; 2) the decode unit 1440 executes the decode stage 1406; 3) the rename / allocator unit 1452 executes the allocate stage 1408 and the rename stage 1410; 4) (multiple) scheduler units 1456 execute the schedule stage 1412; 5) (multiple) physical register file units 1458 and memory units 1470 execute the register read / memory read stage 1414; the execution cluster 1460 executes the execute stage 1416; 6) the memory unit 1470 and the (multiple) physical register file units 1458 execute the write back / memory write stage 1418; 7) each unit may be involved in the exception handling stage 1422; and 8) the retirement unit 1454 and the (multiple) physical register file units 1458 execute the commit stage 1424.

[0178] Core 1490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set from MIPS Technologies, Inc. of Sunnyvale, California; the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, California (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 1490 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby enabling operations used by many multimedia applications to be performed using packed data.

[0179] It should be understood that a core may support multithreading (executing two or more sets of operations or threads in parallel) and that this multithreading may be accomplished in a variety of ways, including time-shared multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-shared fetch and decode and subsequent operations such as Hyper-Threading (Simultaneous Multithreading).

[0180] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the embodiment of the processor shown also includes separate instruction and data cache units 1434 / 1474 and a shared L2 cache unit 1476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a first level (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0181] Specific exemplary in-order core architecture

[0182] Figures 15A-15B A block diagram showing a more specific exemplary in-order core architecture, which would be one logic block among several logic blocks in a chip (including other cores of the same and / or different types). Depending on the application, the logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0183] Figure 15A 15 is a block diagram of a single processor core and its connection to a ring network 1502 (e.g., an on-die interconnect network) and its local subset 1504 of a level 2 (L2) cache according to an embodiment of the present invention. In one embodiment, the instruction decoder 1500 supports the x86 instruction set with the packed data instruction set extension. The L1 cache 1506 allows low-latency access to cache memory in the scalar and vector units. Although in one embodiment (to simplify the design), the scalar unit 1508 and the vector unit 1510 use separate register sets (scalar registers 1512 and vector registers 1514, respectively), and data transferred between these registers is written to memory and then read back from the level 1 (L1) cache 1506, alternative embodiments of the present invention may use a different approach (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0184] The local subset 1504 of the L2 cache is part of the global L2 cache, which is divided into multiple separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 1504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 1504 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1504 and flushed from other subsets when necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1012 bits wide in each direction.

[0185] Figure 15B According to an embodiment of the present invention Figure 15A An expanded view of a portion of a processor core in FIG. Figure 15B Includes the L1 data cache 1506A portion of the L1 cache 1504, as well as more details about the vector unit 1510 and vector registers 1514. Specifically, the vector unit 1510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 1528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports blending of register inputs through blending unit 1520, supports numerical conversion through numerical conversion units 1522A-B, and supports copying of memory inputs through copy unit 1524.

[0186] Processor with integrated memory controller and graphics device

[0187] Figure 16 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention. Figure 16 The solid-line box in the figure shows a processor 1600 having a single core 1602A, a system agent 1610, a set 1616 of one or more bus controller units, while the optional addition of the dashed-line box shows an alternative processor 1600 having multiple cores 1602A-N, a set 1614 of one or more integrated memory controller units in the system agent unit 1610, and dedicated logic 1608.

[0188] Thus, different implementations of processor 1600 may include: 1) a CPU, wherein specialized logic 1608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 1602A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, wherein cores 1602A-N are a large number of specialized cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 1602A-N are a large number of general-purpose in-order cores. Thus, processor 1600 may be a general-purpose processor, a coprocessor, or a specialized processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-integrated-core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. Processor 1600 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0189] The memory hierarchy includes one or more cache levels within cores 1404A-N, a set of one or more shared cache units 1606, and external memory (not shown) coupled to a set of integrated memory controller units 1614. The set of shared cache units 1606 may include one or more intermediate levels of cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 1612 interconnects the integrated graphics logic 1608, the set of shared cache units 1606, and the system agent unit 1610 / integrated memory controller unit(s) 1614, alternative embodiments may use any number of well-known techniques to interconnect such units. In one embodiment, coherency is maintained between the one or more cache units 1606 and the cores 1602A-N.

[0190] In some embodiments, one or more cores 1602A-N may be multithreaded. System agent 1610 includes components that coordinate and operate cores 1602A-N. System agent unit 1610 may include, for example, a power control unit (PCU) and a display unit. The PCU may include or may include the logic and components required to regulate the power state of cores 1602A-N and integrated graphics logic 1608. The display unit is used to drive one or more externally connected displays.

[0191] The cores 1602A-N may be homogeneous or heterogeneous with respect to architectural instruction sets; that is, two or more of the cores 1602A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0192] Exemplary Computer Architecture

[0193] Figure 17-20 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network appliances, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can include a processor and / or other execution logic as disclosed herein are generally suitable.

[0194] Now refer to Figure 17 , a block diagram of a system 1700 according to one embodiment of the present invention is shown. System 1700 may include one or more processors 1710, 1715 coupled to a controller hub 1720. In one embodiment, controller hub 1720 includes a graphics memory controller hub (GMCH) 1790 and an input / output hub (IOH) 1750 (which may be on separate chips); GMCH 1790 includes memory and a graphics controller, to which memory 1740 and a coprocessor 1745 are coupled; and IOH 1750 couples input / output (I / O) devices 1760 to GMCH 1790. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described herein), with memory 1740 and coprocessor 1745 coupled directly to processor 1710, and controller hub 1720 and IOH 1750 being on a single chip.

[0195] The optional addition of processor 1715 is Figure 17 Each processor 1710 , 1715 may include one or more of the processing cores described herein and may be a version of processor 1600 .

[0196] The memory 1740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1720 communicates with the processor(s) 1710, 1715 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface, or similar connection 1795.

[0197] In one embodiment, coprocessor 1745 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 1720 may include an integrated graphics accelerator.

[0198] There may be various differences between the physical resources 1710 , 1715 in terms of a range of quality metrics including architectural, microarchitectural, thermal, and power consumption characteristics.

[0199] In one embodiment, processor 1710 executes instructions that control general types of data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 1710 recognizes these coprocessor instructions as being of a type that should be executed by attached coprocessor 1745. Accordingly, processor 1710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1745 over a coprocessor bus or other interconnect. Coprocessor(s) 1745 accept and execute the received coprocessor instructions.

[0200] Now see Figure 18 , shown is a block diagram of a first more specific exemplary system 1800 according to an embodiment of the present invention. Figure 18 As shown in FIG, multiprocessor system 1800 is a point-to-point interconnect system and includes a first processor 1870 and a second processor 1880 coupled via a point-to-point interconnect 1850. Each of processors 1870 and 1880 may be a version of processor 1600. In one embodiment of the invention, processors 1870 and 1880 are processors 1810 and 1715, respectively, and coprocessor 1838 is coprocessor 1745. In another embodiment, processors 1870 and 1880 are processor 1710 and coprocessor 1745, respectively.

[0201] Processors 1870 and 1880 are shown as including integrated memory controller (IMC) units 1872 and 1882, respectively. Processor 1870 also includes point-to-point (PP) interfaces 1876 and 1878 as part of its bus controller unit; similarly, second processor 1880 includes PP interfaces 1886 and 1888. Processors 1870, 1880 can exchange information via PP interface 1850 using point-to-point (PP) interface circuits 1878, 1888. Figure 18 As shown in FIG, IMCs 1872 and 1882 couple the processors to respective memories, namely, memory 1832 and memory 1834, which may be portions of main memory locally attached to the respective processors.

[0202] Processors 1870, 1880 may each exchange information with a chipset 1890 via respective PP interfaces 1852, 1854 using point-to-point interface circuits 1876, 1894, 1886, 1898. Chipset 1890 may optionally exchange information with a coprocessor 1838 via a high-performance interface 1839. In one embodiment, coprocessor 1838 is a special-purpose processor such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0203] A shared cache (not shown) may be included in either processor, or external to both processors but connected to the processors via the PP interconnect, such that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0204] Chipset 1890 may be coupled to first bus 1816 via interface 1896. In one embodiment, first bus 1816 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another I / O interconnect bus, although the scope of the invention is not limited in this regard.

[0205] like Figure 18 , various I / O devices 1814 may be coupled to the first bus 1816, along with a bus bridge 1818 that couples the first bus 1816 to a second bus 1820. In one embodiment, one or more additional processors 1815, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 1816. In one embodiment, the second bus 1820 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 1820, including, for example, a keyboard and / or mouse 1822, communication devices 1827, and a storage unit 1828, such as a disk drive or other mass storage device, which may include instructions / code and data 1830. Additionally, an audio I / O 1824 may be coupled to the second bus 1820. Note that other architectures are possible. For example, instead of Figure 18 Instead of a point-to-point architecture, the system can implement a multi-drop bus or other such architecture.

[0206] Now refer to Figure 19 , shown is a block diagram of a second more specific exemplary system 1700 according to an embodiment of the present invention. Figure 18 and 19Similar elements in the same reference numerals are used, and Figure 19 Omitted Figure 18 Some aspects of Figure 19 other aspects.

[0207] Figure 19 Processors 1870, 1880 are shown as including integrated memory and I / O control logic ("CL") 1872 and 1882, respectively. Thus, CL 1872, 1882 includes an integrated memory controller unit and includes I / O control logic. Figure 19 Not only are memories 1832, 1834 shown coupled to the CLs 1872, 1882, but I / O devices 1914 are also shown coupled to the control logic 1872, 1882. Legacy I / O devices 1715 are coupled to the chipset 1890.

[0208] Now refer to Figure 20 , shown is a block diagram of a system on a chip (SoC) 1800 according to an embodiment of the present invention. Figure 16 Similar elements in the FIGURE 1 use similar reference numerals. In addition, the dashed boxes are optional features on more advanced SoCs. Figure 20 , interconnect unit(s) 2002 are coupled to: application processor 1810, which includes a set of one or more cores 1602A-N, cache units 1604A-N, and shared cache unit(s) 1606; system agent unit 1610; bus controller unit(s) 1616; integrated memory controller unit(s) 1614; one or more coprocessors 2020, which may include integrated graphics logic, image processors, audio processors, and video processors; static random access memory (SRAM) unit 2030; direct memory access (DMA) unit 2032; and display unit 2040 for coupling to one or more external displays. In one embodiment, coprocessor(s) 2020 include special-purpose processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, or embedded processors, among others.

[0209] The various embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0210] Program code (such as Figure 18The code 1830 shown in FIG. 1 is applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0211] The program code can be implemented in a high-level process-oriented programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0212] One or more aspects of at least one embodiment may be implemented as representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, causes the machine to fabricate logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into fabrication machines that actually manufacture the logic or processor.

[0213] Such machine-readable storage media may include, but are not limited to, a non-transitory, tangible arrangement of an article of manufacture manufactured or formed by a machine or apparatus, including storage media such as a hard disk; any other type of disk, including a floppy disk, an optical disk, a compact disk read only memory (CD-ROM), a compact disk rewritable (CD-RW), and a magneto-optical disk; a semiconductor device, such as a read-only memory (ROM), a random access memory (RAM) such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), flash memory, an electrically erasable programmable read-only memory (EEPROM); a phase change memory (PCM); a magnetic or optical card; or any other type of medium suitable for storing electronic instructions.

[0214] Therefore, embodiments of the present invention also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. These embodiments are also referred to as program products.

[0215] Simulation (including binary conversion, code deformation, etc.)

[0216] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may transform (e.g., using static binary transformation, dynamic binary transformation including dynamic compilation), morph, emulate, or otherwise convert an instruction into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on-processor, off-processor, or partially on-processor and partially off-processor.

[0217] Figure 21 1 is a block diagram illustrating a method for converting binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 21 It is shown that a program in a high-level language 2102 can be compiled using a first compiler 2104 to generate a first binary code (e.g., x86) 2106 that can be natively executed by a processor 2116 having at least one first instruction set core. In some embodiments, the processor 2116 having at least one first instruction set core represents any processor that performs substantially the same functionality as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of the Intel x86 instruction set core, or 2) an object code version of an application or other software that is targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 2104 represents a compiler that can be operated to generate binary code 2106 (e.g., object code) of the first instruction set that can be executed on the processor 2116 having at least one first instruction set core with or without additional linking processing. Similarly, Figure 21It is shown that an alternative instruction set compiler 2108 can be used to compile a program in a high-level language 2102 to generate alternative instruction set binary code 2110 that can be natively executed by a processor 2114 that does not have at least one first instruction set core (e.g., a processor that has a core that executes the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Inc. of Sunnyvale, California). An instruction converter 2112 is used to convert the first binary code 2106 into code that can be natively executed by the processor 2114 that does not have the first instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 2110 because an instruction converter that can do so is difficult to manufacture; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Therefore, the instruction converter 2112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 2106 through simulation, emulation, or any other process.

[0218] Further examples

[0219] Example 1 provides a method for executing instructions atomically and in a weak order, the method comprising: fetching the instruction from a code storage device by a fetch circuit system, the instruction comprising an opcode, a source identifier, and a destination identifier; decoding the fetched instruction by a decode circuit system, and executing the decoded instruction out of order with respect to other instructions in an order selected to optimize at least one of latency, throughput, power, and performance by an execution circuit system, wherein the execution comprises: atomically reading data from a location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and writing a result of the operation to the location identified by the destination identifier.

[0220] Example 2 includes the substance of the exemplary method as described in Example 1, wherein the execution circuit system is part of one or more circuits within a processor, the plurality of circuits comprising: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; a memory controller for controlling memory accesses from two or more of the multiple cores; and at least one cache control circuit coupled to at least one of the multiple cores, sometimes referred to as a cache and home agent (CHA).

[0221] Example 3 includes the substance of the exemplary method of Example 2, wherein the method further comprises: selecting, by the scheduling circuit, an execution circuit from one of the plurality of circuits to execute the instruction, wherein at least one of the plurality of circuits is used to generate a heuristic indicating a measured power and performance state, and wherein the scheduling circuit uses the heuristic to select the execution circuit.

[0222] Example 4 includes the substance of the example method of Example 3, wherein the plurality of circuits further comprises at least one of a coprocessor and a hardware accelerator.

[0223] Example 5 includes the substance of the exemplary method as described in Example 4, wherein the instruction further includes a hint for suggesting which circuit of the multiple circuits is to execute the decoded instruction, wherein the hint includes at least one of the following: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

[0224] Example 6 includes the substance of the exemplary method of Example 1, wherein the operation is one of a plurality of operations including at least integer addition, integer subtraction, integer swap and add, floating point addition, floating point subtraction, and floating point swap and add.

[0225] Example 7 includes the substance of the exemplary method as described in Example 1, wherein the operation is one of a plurality of operations including at least: saturated addition, addition with threshold, subtraction with floor, subtraction with threshold, logical operation, swap, compare and swap, update to minimum, update to minimum and swap, update to maximum, and update to maximum and swap.

[0226] Example 8 includes the substance of the exemplary method of any one of Examples 1 to 7, wherein the fetch circuit system, the decode circuit system, and the execution circuit system are further used to fetch, decode, and execute multiple strongly ordered instructions in order according to a stronger ordered memory model.

[0227] Example 9 includes the substance of the exemplary method of any one of Examples 1 to 7, wherein the instruction includes a second destination identifier for identifying a register, and wherein the execution circuit system is further for writing the result of the operation to the register.

[0228] Example 10 includes the substance of the exemplary method as described in any one of Examples 1 to 7, further including a page table having multiple page table entries, each page table entry being used to store a mapping between a virtual address and a physical address of an associated memory page, wherein each page table entry is further used to specify whether remote atomic operations of the associated memory page are weakly ordered.

[0229] Example 11 provides a system for executing instructions atomically and in a weak order, the system comprising: a memory and a processor, the processor comprising: a fetch circuit system for fetching the instruction from a code storage device, the instruction comprising an opcode, a source identifier, and a destination identifier; a decoding circuit system for decoding the fetched instruction; and an execution circuit system for executing the decoded instruction out of order with respect to other instructions in an order selected to optimize at least one of latency, throughput, power, and performance, wherein the execution comprises: atomically reading data from a location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and writing a result of the operation to the location identified by the destination identifier.

[0230] Example 12 includes the substance of the exemplary system as described in Example 11, wherein the execution circuit system is part of one or more circuits within the processor, the plurality of circuits comprising: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; a memory controller for controlling memory accesses from two or more of the multiple cores; and at least one cache control circuit coupled to at least one of the multiple cores.

[0231] Example 13 includes the substance of the exemplary system of Example 12, wherein the processor further comprises a scheduling circuit for selecting an execution circuit among the plurality of circuits for executing the instruction, wherein at least one of the plurality of circuits is for generating a heuristic indicating a measured power and performance state, and wherein the scheduling circuit uses the heuristic to select the execution circuit.

[0232] Example 14 includes the substance of the example system of Example 13, wherein the plurality of circuits further comprises at least one of a coprocessor and a hardware accelerator.

[0233] Example 15 includes the substance of the exemplary system as described in Example 14, wherein the instruction further includes a hint for suggesting which circuit of the plurality of circuits is to execute the decoded instruction, wherein the hint includes at least one of the following: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

[0234] Example 16 includes the substance of the example system of Example 11, wherein the operation is one of a plurality of operations including at least integer addition, integer subtraction, integer swap and add, floating point addition, floating point subtraction, and floating point swap and add.

[0235] Example 17 includes the substance of the exemplary system of Example 11, wherein the operation is one of a plurality of operations including at least: saturated addition, addition with threshold, subtraction with floor, subtraction with threshold, logical operation, swap, compare and swap, update to minimum, update to minimum and swap, update to maximum, and update to maximum and swap.

[0236] Example 18 includes the substance of the exemplary system of any one of Examples 11 to 17, wherein the fetch circuitry, the decode circuitry, and the execute circuitry are further operable to fetch, decode, and execute a plurality of strongly-ordered instructions in order according to a stronger-ordered memory model.

[0237] Example 19 includes the substance of the exemplary system of any one of Examples 11 to 17, wherein the instruction includes a second destination identifier for identifying a register, and wherein the execution circuit system is further for writing the result of the operation to the register.

[0238] Example 20 includes the essence of the exemplary system as described in any of Examples 11 to 17, further including a page table having multiple page table entries, each page table entry being used to store a mapping between a virtual address and a physical address of an associated memory page, wherein each page table entry is further used to specify whether remote atomic operations of the associated memory page are weakly ordered.

[0239] Example 21 provides a device for executing instructions atomically and in a weak order, the device comprising: a device for retrieving the instruction from a code storage device, the instruction comprising an opcode, a source identifier, and a destination identifier; a device for decoding the retrieved instruction; and a device for executing the decoded instruction out of order with respect to other instructions in a certain order, the order being selected to optimize at least one of latency, throughput, power, and performance, wherein the execution comprises: atomically reading data from a location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and writing a result of the operation to the location identified by the destination identifier.

[0240] Example 22 includes the substance of the exemplary device as described in Example 21, wherein the means for executing is part of one or more circuits within the device, the plurality of circuits comprising: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; a memory controller for controlling memory accesses from two or more of the multiple cores; and at least one cache control circuit coupled to at least one of the multiple cores.

[0241] Example 23 includes the substance of the exemplary apparatus of Example 22, further comprising means for selecting an execution circuit from one of the plurality of circuits for executing the instruction, wherein at least one of the plurality of circuits is for generating a heuristic indicative of a measured power and performance state, and wherein the means for selecting uses the heuristic to select the execution circuit.

[0242] Example 24 includes the substance of the exemplary apparatus of Example 23, wherein the plurality of circuits further comprises at least one of a co-processor and a hardware accelerator.

[0243] Example 25 includes the substance of the exemplary apparatus of Example 24, wherein the instruction further comprises a hint for suggesting which of the plurality of circuits is to execute the decoded instruction, wherein the hint comprises at least one of: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

[0244] Example 26 includes the substance of the example apparatus of Example 21, wherein the operation is one of a plurality of operations including at least integer addition, integer subtraction, integer swap and add, floating point addition, floating point subtraction, and floating point swap and add.

[0245] Example 27 includes the substance of the exemplary apparatus of Example 21, wherein the operation is one of a plurality of operations including at least: saturated addition, addition with a threshold, subtraction with a floor, subtraction with a threshold, a logical operation, a swap, a compare and swap, an update to a minimum value, an update to a minimum value and swap, an update to a maximum value, and an update to a maximum value and swap.

[0246] Example 28 includes the substance of the exemplary apparatus of any one of Examples 21 to 27, wherein the means for fetching, the means for decoding, and the means for executing are further configured to fetch, decode, and execute a plurality of strongly ordered instructions in order according to a stronger ordered memory model.

[0247] Example 29 includes the substance of the exemplary apparatus of any one of Examples 21 to 27, wherein the instruction includes a second destination identifier for identifying a register, and wherein the means for executing is further for writing the result of the operation to the register.

[0248] Example 30 includes the substance of an exemplary device as described in any of Examples 21 to 27, further including a page table having multiple page table entries, each page table entry being used to store a mapping between a virtual address and a physical address of an associated memory page, wherein each page table entry is further used to specify whether remote atomic operations of the associated memory page are weakly ordered.

[0249] Example 31 provides a non-transitory machine-readable medium containing instructions that, when executed by a processor, cause the processor to: fetch the instruction from a code storage device by a fetch circuit system, the instruction including an opcode, a source identifier, and a destination identifier; decode the fetched instruction by a decoding circuit system, and execute the decoded instruction out of order with respect to other instructions by an execution circuit system in an order selected to optimize at least one of latency, throughput, power, and performance, wherein the execution includes: atomically reading data from a location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and writing a result of the operation to the location identified by the destination identifier.

[0250] Example 32 includes the substance of the exemplary non-transitory machine-readable medium as described in Example 31, wherein the execution circuit system is part of one or more circuits within the processor, the plurality of circuits comprising: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; a memory controller for controlling memory accesses from two or more of the multiple cores; and at least one cache control circuit coupled to at least one of the multiple cores.

[0251] Example 33 includes the substance of the exemplary non-transitory machine-readable medium of Example 32, wherein the processor is further configured to select, by a scheduling circuit, an execution circuit from one of the plurality of circuits for executing the instruction, wherein at least one of the plurality of circuits is configured to generate a heuristic indicating a measured power and performance state, and wherein the scheduling circuit uses the heuristic to select the execution circuit.

[0252] Example 34 includes the substance of the example non-transitory machine-readable medium of Example 33, wherein the plurality of circuits further comprises at least one of a coprocessor and a hardware accelerator.

[0253] Example 35 includes the substance of the exemplary non-transitory machine-readable medium of Example 34, wherein the instruction further includes a hint for suggesting which of the multiple circuits is to execute the decoded instruction, wherein the hint includes at least one of the following: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

[0254] Example 36 includes the substance of the exemplary non-transitory machine-readable medium as described in Example 31, wherein the operation is one of a plurality of operations including at least the following: integer addition, integer subtraction, integer swap and add, floating point addition, floating point subtraction, and floating point swap and add.

[0255] Example 37 includes the substance of the exemplary non-transitory machine-readable medium as described in Example 31, wherein the operation is one of a plurality of operations including at least: saturated addition, addition with threshold, subtraction with floor, subtraction with threshold, logical operation, swap, compare and swap, update to minimum, update to minimum and swap, update to maximum, and update to maximum and swap.

[0256] Example 38 includes the substance of an exemplary non-transitory machine-readable medium as described in any of Examples 31 to 37, wherein the fetch circuit system, the decode circuit system and the execution circuit system are further used to fetch, decode and execute multiple strongly ordered instructions in order according to a stronger ordered memory model.

[0257] Example 39 includes the substance of an exemplary non-transitory machine-readable medium as described in any of Examples 31 to 37, wherein the instruction includes a second destination identifier for identifying a register, and wherein the execution circuit system is further used to write the result of the operation to the register.

[0258] Example 40 includes the substantial contents of an exemplary non-transitory machine-readable medium as described in any one of Examples 31 to 37, further comprising a page table having a plurality of page table entries, each page table entry being used to store a mapping between a virtual address and a physical address of an associated memory page, wherein each page table entry is further used to specify whether remote atomic operations for the associated memory page are to be weakly ordered.

[0259] Example 41 provides a processor for executing instructions atomically and in a weak order, the processor comprising: a fetch circuit system for fetching the instruction from a code storage device, the instruction comprising an opcode, a source identifier, and a destination identifier; a decoding circuit system for decoding the fetched instruction; and an execution circuit system for executing the decoded instruction out of order with respect to other instructions in an order selected to optimize at least one of latency, throughput, power, and performance, wherein the execution comprises: atomically reading data from a location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and writing a result of the operation to the location identified by the destination identifier.

[0260] Example 42 includes the substance of the exemplary processor as described in Example 41, wherein the execution circuit system is part of one or more circuits within the processor, the plurality of circuits comprising: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; a memory controller for controlling memory accesses from two or more of the multiple cores; and at least one cache control circuit coupled to at least one of the multiple cores.

[0261] Example 43 includes the substance of the example processor of Example 42, wherein the processor further comprises a scheduling circuit for selecting an execution circuit among the plurality of circuits for executing the instruction, wherein at least one of the plurality of circuits is for generating a heuristic indicating a measured power and performance state, and wherein the scheduling circuit uses the heuristic to select the execution circuit.

[0262] Example 44 includes the substance of the example processor of Example 43, wherein the plurality of circuits further comprises at least one of a coprocessor and a hardware accelerator.

[0263] Example 45 includes the substance of the example processor of Example 44, wherein the instruction further comprises a hint for suggesting which of the plurality of circuits is to execute the decoded instruction, wherein the hint comprises at least one of: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

[0264] Example 46 includes the substance of the example processor of Example 41, wherein the operation is one of a plurality of operations including at least integer addition, integer subtraction, integer swap and add, floating point addition, floating point subtraction, and floating point swap and add.

[0265] Example 47 includes the substance of the example processor of Example 41, wherein the operation is one of a plurality of operations including at least: saturated addition, addition with threshold, subtraction with floor, subtraction with threshold, logical operation, swap, compare and swap, update to minimum, update to minimum and swap, update to maximum, and update to maximum and swap.

[0266] Example 48 includes the substance of the exemplary processor of any one of Examples 41 to 47, wherein the fetch circuit system, the decode circuit system, and the execution circuit system are further used to fetch, decode, and execute multiple strongly ordered instructions in order according to a stronger ordered memory model.

[0267] Example 49 includes the substance of the example processor of any one of Examples 41 to 47, wherein the instruction includes a second destination identifier for identifying a register, and wherein the execution circuit system is further for writing the result of the operation to the register.

[0268] Example 50 includes the substance of an exemplary processor as described in any of Examples 41 to 47, further including a page table having multiple page table entries, each page table entry being used to store a mapping between a virtual address and a physical address of an associated memory page, wherein each page table entry is further used to specify whether remote atomic operations of the associated memory page are weakly ordered.

[0269] Example 51 provides a device for executing instructions atomically and in a weak order, the device comprising: a fetch circuit system for fetching the instruction from a code storage device, the instruction comprising an opcode, a source identifier, and a destination identifier; a decoding circuit system for decoding the fetched instruction; and an execution circuit system for executing the decoded instruction out of order with respect to other instructions in an order selected to optimize at least one of latency, throughput, power, and performance, wherein the execution comprises: atomically reading data from a location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier; and writing the result of the operation to the location identified by the destination identifier.

[0270] Example 52 includes the substance of the exemplary device as described in Example 51, wherein the execution circuit system is part of one or more circuits within the device, the plurality of circuits comprising: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; a memory controller for controlling memory accesses from two or more of the multiple cores; and at least one cache control circuit coupled to at least one of the multiple cores.

[0271] Example 53 includes the substance of the exemplary apparatus of Example 52, wherein the apparatus further comprises a scheduling circuit for selecting an execution circuit from one of the plurality of circuits for executing the instruction, wherein at least one of the plurality of circuits is for generating a heuristic indicating a measured power and performance state, and wherein the scheduling circuit uses the heuristic to select the execution circuit.

[0272] Example 54 includes the substance of the exemplary apparatus of Example 53, wherein the plurality of circuits further comprises at least one of a coprocessor and a hardware accelerator.

[0273] Example 55 includes the substance of the exemplary apparatus of Example 54, wherein the instruction further comprises a hint for suggesting which of the plurality of circuits is to execute the decoded instruction, wherein the hint comprises at least one of: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

[0274] Example 56 includes the substance of the exemplary apparatus of Example 51, wherein the operation is one of a plurality of operations including at least integer addition, integer subtraction, integer swap and add, floating point addition, floating point subtraction, and floating point swap and add.

[0275] Example 57 includes the substance of the exemplary apparatus of Example 51, wherein the operation is one of a plurality of operations including at least: saturated addition, addition with a threshold, subtraction with a floor, subtraction with a threshold, a logical operation, a swap, a compare and swap, an update to a minimum value, an update to a minimum value and swap, an update to a maximum value, and an update to a maximum value and swap.

[0276] Example 58 includes the substance of the exemplary processor device as described in any of Examples 51 to 57, wherein the fetch circuit system, the decode circuit system and the execution circuit system are further used to fetch, decode and execute multiple strongly ordered instructions in order according to a stronger ordered memory model.

[0277] Example 59 includes the substance of the exemplary apparatus of any one of Examples 51 to 57, wherein the instruction includes a second destination identifier for identifying a register, and wherein the execution circuit system is further for writing the result of the operation to the register.

[0278] Example 60 includes the substance of an exemplary device as described in any of Examples 51 to 57, further including a page table having multiple page table entries, each page table entry being used to store a mapping between a virtual address and a physical address of an associated memory page, wherein each page table entry is further used to specify whether remote atomic operations of the associated memory page are weakly ordered.

Claims

1. A processor, comprising: fetch circuitry for fetching an instruction from a code storage device, the instruction including an opcode, a source identifier, and a destination identifier; A decoding circuit system for decoding the fetched instruction; as well as a scheduling circuit, configured to select an execution circuit for executing the instruction from among a plurality of circuits in the system; wherein the execution circuitry is to execute the decoded instruction, wherein the execution comprises: atomically reading data from the location identified by the destination identifier; performing an operation on the data as specified by the opcode, the operation using source operands identified by the source identifier; and writing a result of the operation back to the location identified by the destination identifier, wherein the instruction has an out-of-order ordering requirement for memory loads and stores when the location is not a register and has an in-order ordering requirement for memory loads and stores when the location is a destination register.

2. The processor of claim 1, wherein: The execution circuit is part of one or more circuits within the processor, the one or more circuits within the processor including: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache to be shared among two or more of the multiple cores; and a memory controller for controlling memory access from two or more of the multiple cores.

3. The processor of claim 1, wherein: The scheduling circuitry selects the execution circuit among the plurality of circuits, wherein at least one of the plurality of circuits generates a heuristic indicative of a measured power and performance state, and wherein the scheduling circuitry uses the heuristic to select the location.

4. The processor of claim 3, wherein: The plurality of circuits further include at least one of a co-processor and a hardware accelerator.

5. The processor according to any one of claims 1 to 4, wherein: The instruction further includes a hint for suggesting which of the plurality of circuits is to be selected to execute the decoded instruction, wherein the hint includes one of: an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

6. The processor according to any one of claims 1 to 4, wherein: The instruction is one of integer add, integer subtract, integer saturating add, integer subtract with floor, logical AND, logical OR, logical exclusive OR, floating point add, floating point subtract, update to minimum, update to maximum, integer add with threshold, integer subtract with threshold, integer swap and add, swap, compare and swap, floating point swap and add, update to minimum, and update to maximum.

7. A method for executing an instruction, the method comprising: fetching, by the fetch circuitry, the instruction from the code storage device, the instruction including an opcode, a source identifier, and a destination identifier; The fetched instruction is decoded by a decoding circuit system; The scheduling circuit selects an execution circuit from among multiple circuits in the system; scheduling, by the scheduling circuitry, execution of the decoded instructions; as well as executing, by the execution circuitry, the decoded instruction to: atomically read data from the location identified by the destination identifier; Perform an operation on the data as specified by the opcode, the operation using a source operand identified by the source identifier, and write a result of the operation back to the location, wherein the instruction has an out-of-order ordering requirement for memory loads and stores when the location is not a register and has an in-order ordering requirement for memory loads and stores when the location is a destination register.

8. The method of claim 7, wherein: The execution circuit is part of one or more circuits within a processor, the one or more circuits within the processor including: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache shared among two or more of the multiple cores; and a memory controller for controlling memory access from two or more of the multiple cores.

9. The method of claim 8, wherein: At least one of the plurality of circuits in the system generates a heuristic related to measured power and performance, and wherein the method further comprises using, by the scheduling circuitry, the generated heuristic to inform its selection of the execution circuitry.

10. The method of claim 9, wherein: The plurality of circuits includes at least one of a co-processor and a hardware accelerator.

11. The method according to claim 10, wherein: The instruction further includes a hint for suggesting which of the plurality of circuits is to be selected to execute the decoded instruction, wherein the hint includes at least one of an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

12. The method of claim 7, wherein: The instruction is one of integer addition, integer addition with threshold, integer subtraction; integer subtraction with threshold, integer saturating addition, integer subtraction with floor, logical AND, logical OR, logical XOR, floating point addition, floating point subtraction, update to minimum and update to maximum, integer swap and add, swap, compare and swap, and floating point swap and add.

13. The method of claim 7, wherein: The instruction includes a second destination identifier for identifying the destination register, and the method further includes writing a result of the operation to the destination register.

14. The method according to any one of claims 7 to 13, wherein The instruction includes a second destination identifier for identifying a register, and the method further includes writing the result of the operation into the register.

15. The method of any one of claims 7 to 13, further comprising: A page table having a plurality of entries is accessed by the scheduling circuitry, each entry storing a mapping between a virtual address and a physical address of an associated memory page, wherein each entry further specifies whether remote atomic operations for the associated memory page are weakly ordered.

16. A system for executing instructions, the system comprising: Memory; means for retrieving said instruction from a code storage device, said instruction comprising an opcode, a source identifier, and a destination identifier; means for decoding the fetched instruction; means for selecting an executing circuit among a plurality of circuits in said system; as well as means for scheduling execution of the decoded instructions; wherein the execution circuitry is to execute the decoded instruction to: atomically read data from the location in the memory identified by the destination identifier; perform an operation on the data as specified by the opcode, the operation using source operands identified by the source identifier; and write a result of the operation back to the location, wherein the instruction has an out-of-order ordering requirement for memory loads and stores when the location is not a register and has an in-order ordering requirement for memory loads and stores when the location is a destination register.

17. The system of claim 16, wherein: The execution circuit is part of one or more circuits within the system, the one or more circuits within the system including: at least multiple cores; a private cache controller for controlling a private cache of at least one of the multiple cores; a shared cache controller for controlling a cache shared among two or more of the multiple cores; and a memory controller for controlling memory access from two or more of the multiple cores.

18. The system of claim 17, further comprising means for selecting an execution circuit among the plurality of circuits for executing the instruction, wherein At least one of the plurality of circuits is configured to generate a heuristic indicative of a measured power and performance state, and wherein the means for selecting selects the execution circuit using the heuristic.

19. The system of claim 18, wherein: The plurality of circuits further include at least one of a co-processor and a hardware accelerator.

20. The system of claim 19, wherein: The instruction further includes a hint for suggesting which of the plurality of circuits is to be selected to execute the decoded instruction, wherein the hint includes at least one of an opcode prefix, an opcode suffix, an immediate value, and a register identifier for identifying a register.

21. A machine-readable medium comprising code which, when executed, causes a machine to perform the method of any one of claims 7 to 15.

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