Fault Detection

Abstract

The present disclosure relates to fault detection. A vehicle includes an inverter having a power bus, the power bus including a contactor, the contactor being operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery. The vehicle includes a controller configured to energize a first gate of the inverter. The energization is responsive to the voltage exceeding a threshold. The controller is configured to detect a current between a first phase associated with the first gate and the bus based on a voltage drop associated with the voltage.

Description

Technical Field

[0001] The present disclosure relates to fault detection of inverters and electric machines. Background Art

[0002] Faults can occur in the inverter and motor system. For example, a short circuit can form between the power bus and the phase leads. A short circuit can also form between phases. Similarly, an open circuit can form between phases or between the power bus and the phase leads. Summary of the invention

[0003] A vehicle includes an inverter having a power bus, the power bus including a contactor operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery. The vehicle includes a controller configured to energize a first gate of the inverter. The energization is responsive to the voltage exceeding a threshold. The controller is configured to detect a current between a first phase associated with the first gate and the bus based on a voltage drop associated with the voltage.

[0004] A vehicle includes an inverter having a bus including contactors operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery. The vehicle includes a controller configured to energize a first gate pair of the inverter in response to the voltage reaching an operating platform, and indicate a fault in response to an absence of current flowing through a phase associated with the first gate pair.

[0005] According to one embodiment of the invention, the gate is powered on for a duration and then powered off.

[0006] According to an embodiment of the present invention, the controller is further configured to: energize a second gate of the inverter during the duration, and detect a current between a first phase associated with the first gate and a second phase associated with the second gate.

[0007] According to an embodiment of the present invention, the controller is further configured to: energize a second gate of the inverter after the duration, and detect a current between a second phase associated with the second gate and the bus.

[0008] According to one embodiment of the present invention, the controller is further configured to: energize the second gate of the inverter during the duration and de-energize the second gate after the duration expires, and detect the current between the second phase associated with the second gate and the bus and the current between the first phase and the second phase associated with the first gate.

[0009] A vehicle includes an inverter having a bus, the bus including a contactor operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery. The vehicle includes a controller configured to energize a first gate pair of the inverter. The energization is responsive to the voltage reaching an operating platform. The controller is configured to indicate a fault. The fault may be indicated in response to an absence of current flowing through a phase associated with the first gate pair.

[0010] According to the present invention, a vehicle is provided, the vehicle comprising: an inverter having a bus including a contactor, the contactor being operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery; and a controller configured to: energize a first gate of the inverter in response to the voltage exceeding a threshold value, and detect a current between the first phase and the bus based on a phase current of a first phase associated with the first gate exceeding a predetermined threshold value. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of an inverter for a motor;

[0012] Figure 2A is a schematic diagram of an inverter for a motor having a bus-to-phase fault;

[0013] Figure 2B is a schematic diagram of an inverter for a motor having a phase-to-phase fault;

[0014] Figure 2C is a schematic diagram of an inverter for a motor having an open circuit fault;

[0015] Figure 3A is a graph depicting the short circuit and falling bus voltage measured through a closed switch;

[0016] Figure 3B is a graph depicting the normal behavior of the bus voltage after closing the switch;

[0017] Figure 4 is a graph depicting the inverter switching sequence for detecting a fault;

[0018] Figure 5 is a graph depicting a switch energization sequence with overlapping energization durations for detecting multiple faults;

[0019] Fig. 6A is a graph depicting the switch energization sequence used to detect a short circuit and indicating normal current changes;

[0020] Figure 6B is a graph depicting a switch energization sequence for detecting a short circuit and indicating abnormal current changes;

[0021] Fig. 7A is a graph depicting the switch energization sequence used to detect an open circuit and indicating normal current changes;

[0022] Figure 7B is a graph depicting a switch energization sequence for detecting an open circuit and indicating abnormal current changes;

[0023] Figure 8 is a graph depicting switch energization timing relative to DC link capacitor voltage;

[0024] Fig. 9 is an algorithm for detecting short circuits and open circuits. DETAILED DESCRIPTION

[0025] Embodiments of the present disclosure are described herein. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various and alternative forms. The drawings need not be drawn to scale; some features may be exaggerated or minimized to show the details of a particular component. Therefore, the specific structural and functional details disclosed herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art to utilize the present invention in various forms. As will be understood by those of ordinary skill in the art, the various features shown and described with reference to any of the figures may be combined with the features shown in one or more other figures to produce embodiments that are not explicitly shown or described. The combination of features shown provides representative embodiments for typical applications. However, various combinations and variations of features consistent with the teachings of the present disclosure may be desired for specific applications or embodiments.

[0026] A controller is used to energize the gates of the inverter switches to generate the waveform used by the motor. Single-phase or multi-phase inverter and motor systems are susceptible to faults between the individual phases and the power bus. Short circuit faults may occur between phases or between a phase and the power bus. In addition, open circuit faults may occur in one or more phases. Detecting faults at full power bus power may result in increased damage to the drive system circuitry.

[0027] The contactor can be used to direct current through the resistive element or resistor to precharge the capacitive element or DC link capacitor. The contactor can be a relay or other switch for selectively connecting the precharge circuit to the normal operating circuit. During vehicle startup, the precharge circuit can be used to control the charging of the capacitive element or DC link capacitor. The resistive element can be any resistive component (e.g., a resistor, a resistance wire). The resistance of the resistive element can be predetermined. The capacitive element can be a DC link capacitor for smoothing bus power supply voltage fluctuations.

[0028] Reference Figure 1, an electric drive system 100 for a vehicle is shown. The electric drive system 100 includes a network of switches having gates 114, 116, 118, 120, 122, and 124 forming an inverter 102. Each switch pair (e.g., S1 and S2) forms an output phase (i.e., V a 、V b 、V c ). The output phase drives the motor 130. The rails 126 and 128 of the power bus voltage 204 provide direct current to the switch. The power bus voltage 204 is powered by a DC energy source or a battery 110. Any type of DC power source can be used. The power bus voltage 204 has a resistive element 108 and a capacitive element 112. Under normal operation, the main contactor 104 is closed to provide full power availability to the power bus voltage 204, and the pre-charge contactor 106 is open. Under pre-charge operation, the main contactor 104 is open and the pre-charge contactor 106 is closed. During the pre-charge operation, the battery power is limited by the resistive element 108 to slowly charge the DC link capacitor 112.

[0029] Reference FIG. 2A to FIG. 2C , showing a fault. Figure 2A shows the power bus and output phase V a An example of a short circuit fault 140 between the power bus and the phases or a fault caused internally by the inverter switches. Figure 2B shows the output phase V a and output phase V b An example of a phase-to-phase short circuit fault 142 between phases. Figure 2C The motor 130 and the phase leads V are shown a An example of an open circuit fault 144 between.

[0030] Reference Figure 3A and Figure 3B , graph 200 depicts the behavior of the abnormal power bus voltage 204 indicating a short circuit fault, and graph 220 depicts the behavior of the normal power bus voltage 204 indicating the absence of a short circuit fault. As an example, during the pre-charge cycle of the DC link capacitor 112, the gate 114 of S1 is at t R edge (e.g., rising and power-on) and t F The pre-charge cycle may have a voltage plateau 206 of the power bus voltage 204. At t0, the pre-charge contactor 106 is closed to increase the power bus voltage 204. At t R , the gate 114 of S1 is energized by the gate driver of the controller. F, the gate 114 of S1 is de-energized by the gate driver of the controller. Under normal operation, the power bus voltage 204 will not substantially drop in response to the energization of the gate 114. If there is a short circuit fault (e.g., a short circuit of the output of phase A to the negative DC bus 128 or switch S2 is in a short circuit fault condition), the power bus voltage 204 will drop a voltage drop greater than the expected voltage drop 208. The threshold 208 may be based on the voltage 204 when the gate 114 is energized. If the voltage drop is greater than the threshold 208, a fault indication is provided.

[0031] Figure 4 3 is a timing diagram 300 including a switch gate energization interval. After the pre-charge contactor is closed at t0, the controller is configured to energize gates 114, 116, 118, 120, 122, and 124 of inverter 102. Figure 2A As discussed, to test for a short circuit fault, the switches are energized in sequence to detect a short circuit from the bus 204 to the phase during the time period 302. Additionally, the gates 114, 116, 118, 120, 122, and 124 of the inverter 102 are energized in switch pairs to test for a phase-to-phase short circuit fault during the time period 304. The controller may be configured to test for a phase-to-phase fault or a phase-to-bus fault in the reverse order.

[0032] Figure 5 4 is a timing diagram 400 including a gate energization interval. After the pre-charge contactor is closed at t0, the controller is configured to energize gates 114, 116, 118, 120, 122, and 124 of inverter 102. As shown, Figure 4The phase-to-phase fault detection test time period 302 and the phase-to-bus fault detection test time period 304 can be combined. The timing diagram 400 depicts an overlapping gate energization sequence for testing both phase-to-phase faults and phase-to-bus faults without delays or pauses. The gate 114 of S1 is energized during the duration 402 and the duration 404, and the gate 120 of S4 is energized during the duration 404 and the duration 406. During the duration 402, a bus-to-phase short circuit associated with S1 is detected. During the duration 404, a phase-to-phase short circuit associated with S1 and S4 is detected. During the duration 406, a bus-to-phase short circuit associated with S4 is detected. The gate 118 of S3 is energized during the duration 408 and the duration 410, and the gate 124 of S6 is energized during the duration 410 and the duration 412. During the duration 408, a bus-to-phase short circuit associated with S3 is detected. During duration 410, a phase-to-phase short circuit associated with S3 and S6 is detected. During duration 412, a bus-to-phase short circuit associated with S6 is detected. Gate 116 of S2 is energized during duration 414 and duration 416, and gate 122 of S5 is energized during duration 416 and duration 418. During duration 414, a bus-to-phase short circuit associated with S2 is detected. During duration 416, a phase-to-phase short circuit associated with S5 and S2 is detected. During duration 418, a bus-to-phase short circuit associated with S5 is detected.

[0033] Fig. 6A and Figure 6B A normal timing diagram 500 and an abnormal timing diagram 520 are depicted. The timing diagram 500 and the timing diagram 520 are related to the switching power-on interval. Figure 4 Similarly. Although applicable to bus-to-phase short circuit detection, as shown, gates 114, 116, 118, 120, 122, and 124 of inverter 102 are energized in the form of switch pairs to test for phase-to-phase short circuit faults during duration 508, duration 510, and duration 512 after the pre-charge contactor is closed. The fault is detected by the increased current from the controller output current 502, 504, and 506 through each phase. If the current threshold 522 is exceeded, a fault indication can be provided.

[0034] Fig. 7A and Figure 7B A normal timing diagram 600 and an abnormal timing diagram 620 are depicted. The timing diagram 600 and the timing diagram 620 are related to the switch power-on interval. Figure 4Similarly. Although applicable to bus-to-phase short circuit detection, as shown, the gates 114, 116, 118, 120, 122, and 124 of the inverter 102 are energized in the form of switch pairs to test for phase-to-phase open circuit faults during duration 608, duration 610, and duration 612 after the pre-charge contactor is closed. The open circuit fault is shown as a dotted line. When both switches (e.g., S1 and S2) associated with a given phase that are switched in pairs do not conduct current, phase 602, phase 604, and phase 606 can be identified as including an open circuit fault. For example, the gates 114 and 120 associated with S1 and S4 are energized together, and the gates 116 and 122 associated with S2 and S5 are energized together. The condition that there is no current conduction when the two pairs of switches are each energized indicates that a phase i has occurred. a 602. Any combination of gates or switches can be energized with any detection method and scheme to achieve the same results. As a non-limiting example, S1 can be paired with S6, and S2 can be paired with S3 to identify similar open circuit faults and short circuit faults in a similar manner. The order of energization can be adjusted to improve efficiency or address other factors (e.g., heat dissipation).

[0035] Figure 8 A graph 700 is included with the fault detection times 200 and 600. The short circuit detection time 200 may be after the pre-charge circuit contactor 106 is closed at t0 and at the voltage V c 204 occurs before the operating platform 206 is reached. The open circuit fault detection time 600 can be after the pre-charge circuit contactor 106 is closed at t0 and the voltage V c 204 occurs after reaching the operating platform 206. At time 702, the main contactor is closed to directly access the voltage source 110. The open circuit fault detection time 600 may occur after the main contactor 104 is closed at time 702 and the voltage V c 204 occurs after reaching the operating platform 206 .

[0036] Fig. 9 A flowchart 800 is included that depicts an example algorithm for implementing the teachings of the present disclosure. At step 802, processing begins. At step 804, the inverter controller 101 receives a command to close the pre-charge contactor 106. At step 806, the inverter controller 101 closes the pre-charge contactor 106. As V c 204 increases, monitoring the voltage until V c 204 exceeds the short-circuit test threshold. cAfter 204 exceeds the threshold, at step 810, short circuit detection 200 is performed. The short circuit detection method can be a voltage detection method or a current detection method. The threshold can be based on a sensor threshold for determining a voltage drop or current value to eliminate false positives or negatives. The controller 101 can c 204 monitors until V c 204 until the open circuit detection threshold is exceeded. The open circuit threshold may be greater than or less than the short circuit threshold, and the open circuit detection may be performed before or after the short circuit detection. c When 204 exceeds the open circuit detection threshold, the open circuit detection process 600 is executed at step 814. c When the pre-charging contactor 106 reaches the platform 206, the controller 101 determines that the pre-charging is finished at step 816. At step 818, the controller 101 opens the pre-charging contactor 106 and closes the main contactor 104. After the main contactor 104 is closed, the controller 101 may run the open circuit detection 600 at step 820. The inverter system controller (ISC) may be run at operation 822.

[0037] The words used in the specification are descriptive words rather than restrictive words, and it should be understood that various changes can be made without departing from the spirit and scope of the present disclosure. As previously mentioned, the features of each embodiment can be combined to form further embodiments of the present invention that may not be clearly described or shown. Although for one or more desired characteristics, each embodiment may have been described as providing advantages or being superior to other embodiments or the implementation of the prior art, it will be appreciated by those of ordinary skill in the art that, according to specific application and implementation, one or more features or characteristics can be compromised to achieve the desired overall system properties. These attributes may include but are not limited to cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, maintainability, weight, manufacturability, ease of assembly, etc. Therefore, the embodiment described as being inferior to other embodiments or the implementation of the prior art in one or more characteristics is not outside the scope of the present disclosure, and can be expected to be used for specific applications.

Claims

1. A vehicle comprising: an inverter having a power bus including a contactor operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery; A controller is configured to: in response to the voltage exceeding a threshold, energize a first gate of the inverter for a duration, and detect a current between a first phase associated with the first gate and the bus based on a voltage drop associated with the voltage, wherein a starting time point of the duration is defined by the threshold.

2. The vehicle according to claim 1, wherein: The end time of the time period is defined by the expected voltage drop.

3. The vehicle according to claim 2, wherein: The controller is further configured to energize a second gate of the inverter during the duration and detect a current between a first phase associated with the first gate and a second phase associated with the second gate based on a voltage drop associated with the voltage.

4. The vehicle according to claim 2, wherein: The controller is further configured to energize a second gate of the inverter after the duration and detect a current between a second phase associated with the second gate and the bus based on a voltage drop associated with the voltage.

5. The vehicle according to claim 2, wherein: The controller is further configured to energize a second gate of the inverter during the duration and deenergize the second gate after expiration of the duration, and detect a current between a second phase associated with the second gate and the bus and a current between a first phase associated with the first gate and a second phase.

6. The vehicle of claim 1, wherein: The controller is further configured to energize a first gate pair of the inverter in response to the voltage reaching an operating plateau, and indicate a fault in response to an absence of current flowing through a phase associated with the first gate pair.

7. The vehicle of claim 6, wherein: The first gate pair includes gates from different phases of an inverter.

8. The vehicle of claim 6, wherein: The controller is also configured to energize a second gate pair and a third gate pair of the inverter, and in response to an absence of current flowing through any two gate pairs of the first gate pair, the second gate pair, or the third gate pair, indicate a phase of an open circuit fault based on a common phase associated with the any two gate pairs.

9. The vehicle of claim 6, wherein: The first gate pair is energized after the contactor is opened and the main switch is closed.

10. A vehicle comprising: an inverter having a bus including contactors operable to conduct current through a resistive element connected to a capacitive element having a voltage provided by a battery; A controller is configured to: in response to the voltage exceeding a threshold, energize a first gate of the inverter for a duration and detect a current between a first phase associated with the first gate and the bus, wherein a starting time point of the duration is defined by the threshold; energize a first gate pair of the inverter in response to the voltage reaching an operating platform, and indicate a fault in response to the absence of current flowing through a phase associated with the first gate pair.

11. The vehicle of claim 10, wherein: The first gate pair includes gates from different phases of an inverter.

12. The vehicle of claim 10, wherein: The controller is also configured to energize a second gate pair and a third gate pair of the inverter, and in response to an absence of current flowing through any two gate pairs of the first gate pair, the second gate pair, or the third gate pair, indicate a phase of an open circuit fault based on a common phase associated with the any two gate pairs.

13. The vehicle of claim 10, wherein: The first gate pair is energized after the contactor is opened and the main switch is closed.

14. The vehicle of claim 10, wherein: The end time of the time period is defined by the expected voltage drop.

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