Techniques for providing cache coherency based on cache type

Abstract

Techniques and apparatuses for managing cache coherency for different types of cache memory are described. In one embodiment, an apparatus can include at least one processor, at least one cache memory, and logic, at least a portion of which is included in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache state of the memory operation request, the cache state to indicate one of a large cache state or a small cache state, execute the memory operation request via small cache coherency processing in response to the cache state being the small cache state, and execute the memory operation request via large cache coherency processing in response to the cache state being the large cache state. Other embodiments are described and claimed.

Description

Technical Field

[0001] The embodiments described herein generally relate to information processing, and more specifically, to providing cache coherency techniques within computing systems that support different types of caches. Background Technology

[0002] A computing system typically comprises various components coupled together to interoperate and perform various processing functions under the control of a central processing unit (usually called a central processing unit (CPU)). Most systems also include a collection of elements such as processors, processor cores (or “cores”), accelerators, memory devices, peripherals, dedicated processing units, and additional semiconductor devices that can be used as system memory to provide storage for information used by the processing units. In many systems, multiple memories may exist, each of which may be associated with a given element (such as a core or accelerator), which may operate as local memory or cache for the corresponding element. Local caches may be formed from different types of memory devices distinguished by size, speed, or other operating characteristics.

[0003] To maintain data consistency across systems, cache consensus protocols can be implemented, such as snooping-based protocols, directory-based protocols, combinations thereof, and / or variations thereof. Each form of consensus protocol may operate differently depending on the operational characteristics of the local caches of system components. For example, a consensus protocol may operate efficiently for a specific cache type, but may be less efficient or even ineffective for other cache types. Attached Figure Description

[0004] Figure 1 An embodiment of the first operating environment is shown.

[0005] Figure 2 An embodiment of the first logic flow is shown.

[0006] Figure 3 An embodiment of the second logic flow is shown.

[0007] Figure 4 An embodiment of the second operating environment is shown.

[0008] Figure 5 An embodiment of the third operating environment is shown.

[0009] Figure 6 An example of a third logic flow is shown.

[0010] Figure 7 An example of the fourth logic flow is shown.

[0011] Figure 8 An example of a storage medium is shown.

[0012] Figure 9 An example of a computing architecture is shown. Detailed Implementation

[0013] Various embodiments can generally relate to techniques for providing at least one cache coherence process among multiple components within a processing system. In some embodiments, the cache coherence process may operate within a multi-component (e.g., multi-chip) computing environment to track cache lines that "belong" to an additional memory of a first component (e.g., a first chip) when cached on a second component (e.g., a second chip). In some embodiments, the first chip may include a processor chip and others. In various embodiments, the second chip may include a processor chip, an accelerator chip, etc.

[0014] In some embodiments, the plurality of components may include processors, such as a central processing unit (CPU), a processor die (including, for example, a multi-chip processor die), a processor core (or “core”), an accelerator, an input / output (I / O) device, a smart I / O device, a memory device, combinations thereof, and / or the like. In some embodiments, at least a portion of the plurality of components may include and / or be operatively coupled to memory (“local memory,” “cache,” or “cache”). Based on one or more cache characteristics, the cache of the plurality of components may include one or more cache types. Non-limiting examples of cache characteristics may include size, speed, location, associated components, usage, etc. The cache type of the cache may affect the operation of at least one cache coherence process that interacts with the cache. For example, the at least one cache coherence process may include a first cache coherence process that operates efficiently with a first cache type but inefficiently with a second cache coherence process.

[0015] In some embodiments, the cache type may be based on the size of the cache. For example, the cache may be specified as one of a “giant cache type” or a “small cache type.” In some embodiments, a small cache type may include a cache having a memory size typical of a cache used in a processor core, while a giant cache type may include a cache having a size larger than a typical cache used in a processor core or some other size threshold. In various embodiments, a small cache type may have a memory size in the range of 1 to 10 megabytes (MB), while a giant cache type may have a memory size in the range of 10-100 MB or gigabytes (GB). In various embodiments, a small cache type may have a memory size of approximately less than 2 MB to approximately 12 MB. In some embodiments, a small cache type may have a memory size of approximately 500 kilobytes (KB), 1 MB, 2 MB, 4 MB, 6 MB, 8 MB, 10 MB, 12 MB, 16 MB, and a range and values ​​between any two of these values ​​(including the endpoints). In various embodiments, a giant cache type may have a memory size greater than approximately 10 MB to greater than approximately 10 GB. In some embodiments, the jumbo cache type may have a memory size of approximately 10MB, 20MB, 30MB, 40MB, 50MB, 100MB, 200MB, 500MB, 1GB, 5GB, 10GB, 25GB, 50GB, 100GB, 500GB, and a range of values ​​(including endpoints) between any two of these values. Embodiments are not limited to this context.

[0016] Typically, the memory size of small cache types and massive cache types can depend on the operating characteristics of the respective system, including any cache coherence processing. Generally, as described in more detail below, some cache coherence processes, or portions thereof, operate efficiently for small cache types, while some cache coherence processes, or portions thereof, operate inefficiently (or not at all) for massive cache types. For example, in a first system using a first cache coherence protocol, a massive cache type may have a memory size of approximately 500 MB, while in a second system using a second cache coherence protocol, a massive cache type may have a memory size of approximately 10 GB. In some embodiments, for example, the impact of cache memory size on the operating characteristics of cache coherence processing (e.g., snooping latency) can distinguish between small cache types and massive cache types.

[0017] For snoop-based cache coherence protocols, the snooping latency of jumbo cache types (e.g., accelerators or smart I / O devices) can be very high compared to the small cache types of the processor core. Therefore, jumbo cache types can be associated with "high snooping latency," and small cache types can be associated with "low snooping latency." If an agent with a jumbo cache type is treated as a conventional coherence agent, standard cache coherence mechanisms can cause the snooping latency of the agent associated with the jumbo cache type to become a limiter on memory read latency, as seen in the processor core, for example. Therefore, standard cache coherence mechanisms for jumbo cache types typically have a significant negative impact on processor performance.

[0018] Conventional software-based techniques using standard cache coherency mechanisms for jumbo cache types typically involve managing data at a low-granularity level. For example, data might be managed at the page level, where the cached data page might need to be deallocated from the page table seen by the processor core at the coherency broker. Additionally, some operations, such as page table reversal, might be required when a page is returned from the cache to host memory. Therefore, such conventional software-based techniques for providing cache coherency for jumbo caches are highly inefficient and provide poor performance.

[0019] For snooping-based cache coherence systems employing small caches, snooping filters based on random access memory (RAM), such as static RAM (SRAM), can be implemented on the processor die for the purpose of a dedicated coherence agent. However, SRAM-based snooping filters cannot be applied to large caches due to the size of the snooping filter required to map such a massive cache. For example, such a snooping filter would consume an unacceptably large percentage of the available area and power of the processor die.

[0020] Therefore, some embodiments provide techniques for supporting cache consistency processing for jumbo cache types. In some embodiments, cache consistency processing may include snoop-based consistency processing, directory-based consistency processing, combinations thereof, and / or variations thereof. In various embodiments, cache consistency processing may provide multiple consistency streams capable of supporting small cache types and jumbo cache types within the same or related architecture. For example, in some embodiments, cache consistency processing may extend the state tracked in a consistency directory (e.g., an in-memory server consistency directory) to track multiple agents, rather than a single agent class as provided by conventional techniques. In various embodiments, multiple agents may include agents for jumbo cache types (or high snoop latency) (“high-latency agents”) and / or agents for small cache types (or low snoop latency) (“low-latency agents”). Agents, for example, processor cores with small cache types may use low-latency directory bits to track consistency, while agents with jumbo cache types may use high-latency directory bits to track consistency. In various embodiments, agents may specify which type of agent to use for a particular request. In this way, the agent can implement both massive cache types (or high snooping latency) and small cache types (or low snooping latency). Therefore, in some embodiments, consistency for massive cache types can be tracked at least partially in hardware without the resource-intensive paging-related software activity required by software-based solutions. Thus, in some embodiments, the system can achieve improved cache consistency performance for massive cache types. For example, some embodiments can improve cache consistency performance for computationally intensive logic devices (e.g., those operating on computations with a data footprint greater than their attached memory capacity), such as compute accelerators (e.g., graphics processing units (GPUs)) and / or high-gate-count field-programmable gate arrays (FPGAs).

[0021] Figure 1 Examples of operating environments 100, which may represent various embodiments, are shown. Figure 1The operating environment 100 depicted may include a device 105 having a processing unit 120 (e.g., a central processing unit (CPU)). In some embodiments, the processing unit 120 may be implemented on a system-on-a-chip (SoC). In some embodiments, the processing unit 120 may be implemented as a standalone processor die. The processing unit 120 may include one or more processing cores 122a-n, such as 1, 2, 4, 6, 8, 10, 12, or 16 processing cores. Embodiments are not limited to this context. The processing unit 120 may include any type of computing element, such as, but not limited to, a microprocessor, microcontroller, complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, virtual processor (e.g., VCPU), or any other type of processor or processing circuitry. In some embodiments, the processing unit 120 may be available from Santa Clara, California. The company received One or more processors in a processor family, such as Processor. Despite Figure 1 Only one processing unit 120 is depicted, but the device may include multiple processing units.

[0022] Each of the processor cores 122a-n can be connected to the router block 160 via internal interconnect 112. The router block 160 and internal interconnect 112 can typically represent various circuits supporting communication between components in the processing unit 120, including buses, serial point-to-point links, interconnect structures, and / or the like. Further details of this connection are not shown to avoid obscuring the details of the operating environment 100.

[0023] Non-limiting examples of supported communication protocols may include the Peripheral Component Interconnect (PCI) protocol, the Fast Peripheral Component Interconnect (PCIe or PCI-E) protocol, the Universal Serial Bus (USB) protocol, the Serial Peripheral Interface (SPI) protocol, and the Serial AT Accessory (SATA) protocol. QuickPath Interconnect (QPI) protocol, UltraPath Interconnect (UPI) protocol, Optimize Accelerator Protocol (OAP) Accelerator Link (IAL), In-Device Interconnect (IDI) Protocol, On-Chip Scalable Architecture (IOSF) protocol, Scalable Memory Interconnect (SMI) protocol, SMI 3, etc. In some embodiments, link 115 may support in-device protocols (e.g., IDI) and memory interconnect protocols (e.g., SMI3). In various embodiments, link 115 may support in-device protocols (e.g., IDI), memory interconnect protocols (e.g., SMI3), and architecture-based protocols (e.g., IOSF).

[0024] like Figure 1 As shown, processing unit 120 can be communicatively coupled to logic device 180. In various embodiments, logic device 180 may include hardware devices. In some embodiments, logic device 180 may be implemented using hardware, software, or a combination thereof. In various embodiments, logic device 180 may include an accelerator. In some embodiments, logic device 180 may include a hardware accelerator. In various embodiments, logic device 180 may include I / O devices, such as smart I / O devices. In some embodiments, processing unit 120 may be coupled to multiple logic devices. Although accelerators and smart I / O devices can be used as example logic device 180, embodiments are not limited thereto, as logic device 180 may include any type of device, processor (e.g., graphics processing unit (GPU)), logic unit, circuit, integrated circuit, application-specific integrated circuit (ASIC), FPGA, memory unit, computing unit, and / or similar devices capable of operating according to some embodiments. For example, in a multi-chip configuration, logic device 180 may include processing units that are the same as, similar to, or substantially similar to processing unit 120.

[0025] Logic device 180 may include a coherence agent 140n and one or more caches 184a-n, or be associated with a coherence agent 140n and one or more caches 184a-n. In some embodiments, at least one of the caches 184a-n may include a jumbo cache type. In various embodiments, the coherence agent 140a-n may reside on the same processor die as the coherence structure 130 (e.g., coherence agent 140a) or on an accompanying die coupled to the processor die, for example via a multi-chip package (MCP) or other external package link (e.g., coherence agent 140n).

[0026] like Figure 1As shown, processing unit 120 may include local caches configured in a hierarchical structure, such as level caches 124a-n and a last-level cache (LLC) 126. Typically, the cache closest to processor cores 122a-n has the lowest latency and smallest size, and the caches become larger but have higher latency the further away from processor cores 122a-n. For example, cores 122a-n may include caches 124a-n, which can be used as a level 1 cache (L1) or a combination of L1 and L2 caches (L2). Caches 124a-n or portions thereof within cores 122a-n may be "private" to each processor core 122a-n. In the context of operating environment 100, the highest-level cache is LLC 126. For example, if L1 and L2 caches are also used, the LLC 126 for a given core 122a-n may include a level 3 (L3) cache, or if the only other cache is an L1 cache, the LLC 126 for a given core 122a-n may include an L2-type cache. Because cache memory can be extended to higher levels of cache, the embodiments are not limited to this context.

[0027] Each of the processor cores 122a-n can also be connected to LLC 126. LLC 126 is described as... Figure 1 A single logical block within; however, components associated with LLC 126 may be distributed across processing unit 120 rather than implemented as a single monolithic block or box. In some embodiments, caches 124a-n and / or one or more of LLC 126 may include small cache types. In some embodiments, caches 124a-n and / or one or more of LLC 126 may include jumbo cache types. In various embodiments, caches 124a-n and LLC 126 may include small cache types, and at least one of caches 184a-n may include jumbo cache types. Therefore, processing unit 120 may include a local cache with a hierarchical structure formed by a private cache implemented within each of processor cores 122a-n via caches 124a-n and LLC 126 implemented as a hierarchical layer between the private core cache and system memory 156.

[0028] In various embodiments, LLC 126 can be implemented as a single block or box (e.g., shared on each of processor cores 122a-n) or a set of peer LLCs (e.g., shared on a subset of processor cores 122a-n). Each LLC 126 can be implemented as a distributed set of monolithic agents or "sharded" agents. Each monolithic LLC or sharded LLC agent may include or be associated with a core / LLC consistency agent 114a-n configured to co-operate with cache consistency logic in each of the processor cores 122a-n associated with a given LLC peer of LLC 126. In some embodiments, the core / LLC consistency agent 114a-n can provide consistency processing operable to maintain cache consistency between the LLC peer and the associated processor cores 122a-n. In various embodiments, the core / LLC coherence agents 114a-n can provide cache coherence processing capable of operating to track cache lines stored in the LLC data array of LLC 126 by notification from the LLC tag repository and to track cache lines stored in the associated processor cores 122a-n caches 124a-n by notification from the sniffer filter (SF) tag repository (e.g., at a 64B granularity). LLC tags and / or SF tags can be implemented using various types of memory, such as SRAM on the processor die of processing unit 120. Typically, a typical implementation of a high-core-count processor in a 10nm silicon processor chip (e.g., 30-50 cores) may include approximately 100MB of LLC storage split across multiple LLC peers, and approximately 100MB of core-private cache split across the cores (in one example, a private cache providing approximately 1.5-2MB of private cache per core for 30-50 cores).

[0029] Processing unit 120 may include cache agent 128 and / or coherence agents 140a-n. In some embodiments, coherence agents 140a-n may include LLC / memory coherence agents between a set of LLC peers disposed on a chip and system memory 126. The LLC / memory coherence agents can provide cache coherence processing, operable to maintain cache coherence among LLC peers of LLC 126, etc. The coherence processing provided by the LLC / memory coherence agents can be notified via cache state, equivalent to the state captured by the LLC tag repository and the SF tag repository of the LLC peers of the processing chip of processing unit 120.

[0030] like Figure 1As shown, in some embodiments, at least a portion of cache agent 128 and / or consistency agents 140a-n may be coupled to consistency structure 130, which may include various components such as memory 134, storage devices (e.g., registers), interfaces, and cache consistency controller 132. In various embodiments, at least a portion of cache agent 128 may be coupled to consistency agents 140a-n without using consistency structure 130. During normal operation, consistency structure 130 may route traffic between system agents. Traffic may include snooping in response to cache requests. In some embodiments, consistency structure 130 may act as a primary on-chip interconnect between multiple different agents (e.g., cache agent 128 and / or consistency agents 140a-n) and other components. In various embodiments, consistency structure 130 may include logic operable to implement consistency and ordering on a structure within processing unit 120 based on cache consistency processing. In addition, the consistency structure 130 can perform end-to-end routing of packets and / or other data, and can also handle all associated functions such as network fairness, deadlock avoidance, traffic modulation, and other interconnection functions for the agents of the processing unit 120.

[0031] In some embodiments, cache agent 128 may be responsible for managing data transfer between cores 122a-n and / or logical devices 180 and shared caches 126 and / or caches 184a-n. Cache agent 128 is also responsible for maintaining cache coherency between cores 122a-n and logical devices 180 within a single slot (e.g., within processing unit 120). This may include generating snoop content and collecting snoop responses from cores 122a-n according to a cache coherency protocol (such as MESI, MOSI, MOESI, or MESIF). Multiple cache agents 128 may be assigned to manage different subsets of the shared cache 126.

[0032] Cache agent 128 may include any agent capable of caching one or more cache blocks. For example, cores 122a-n may be cache agents, and caches 124a-n may also be cache agents. Consistency structure 130 and / or cache consistency controller 132 may facilitate consistency communication within device 105. Consistency communication may be supported within device 105 during the address, response, and data phases of a transaction. Typically, a transaction is initiated by sending the address of the transaction along with a command indicating which transaction is being initiated, and various other control information during the address phase. Consistency agents 140a-n use the response phase to maintain cache consistency. Each consistency agent 140a-n may respond with an indication of the status of the cache block addressed by the address, and may also retry transactions that cannot determine a consistent response. Retrieved transactions are cancelled, and the initiating agent may retry them later. The order of successful (non-retrieved) address phases may establish the order of transactions for consistency purposes (e.g., according to a sequential consistency model). Data for a transaction is sent during the data phase. Some transactions may not include a data phase. For example, certain transactions may be used solely to establish changes in the consistent state of cache blocks. Typically, the consistent state of a cache block defines the permitted operations (e.g., reads, writes, etc.) that a cache broker can perform on the cache block. Common consistency state schemes include MESI, MOESI, and variations thereof.

[0033] Coherence agents 140a-n (one or more of which may be referred to as "home" agents) may be connected to memory controller 150. In some embodiments, cache agent 128, one or more of home agents 140a-n, and memory controller 150 may work together to manage access to system memory 156. The actual physical memory of memory 156 may be stored on one or more memory modules (not shown) and accessed from memory controller 150 via a memory interface. For example, in one embodiment, the memory interface may include one or more double data rate (DDR) interfaces, such as DDR3-type (DDR3) interfaces. In some embodiments, memory controller 150 may include a RAM (e.g., dynamic RAM (DRAM)) memory controller.

[0034] Coherence agents 140a-n can interact with cache agent 128 to manage cache line usage by various memory consumers (e.g., processor cores 122a-n, logic devices 180, etc.). Specifically, coherence agents 140a-n and cache agent 128 (alone or via coherence structure 130) can support a coherent memory scheme in which memory can be shared coherently without data corruption. To support this functionality, coherence agents 140a-n and cache agent 128 access and update cache line usage data stored in directory 152 (see, for example...). Figure 5 The data is logically depicted in the memory controller 150 (e.g., the part of the logic adopted by the memory controller 150 relates to the use of the data in the directory 152), but its data may be stored in the system memory 156.

[0035] The cache memory in device 105 can be kept consistent using various cache memory consistency protocols, such as snooping-based protocols, directory-based protocols, combinations thereof, and / or combinations thereof. These cache memory consistency protocols include MESI, MOSI, MOESI, MESIF, Directory Assisted Snooping (DAS), I / O Directory Cache (IODC), Home Snooping, Early Snooping, Snooping with Directory and Opportunity Snooping Broadcasts, On-Die Clustering, and / or the like. Typically, a system memory address can be associated with a specific location in the system. This location is often referred to as the “home node” of the memory address. In a directory-based protocol, cache agent 128 can send a request (e.g., via consistency structure 130) to the home node to access a memory address associated with a consistency agent (or home agent) 140a-n. Cache agent 128 is then responsible for ensuring that the latest copy of the requested data is returned to the requester from the memory 156 or cache agent 128 that owns the requested data. For example, if the request is for an exclusive copy, the consistency broker 140a-n can also be responsible for invalidating data copies at other cache brokers 128. For these purposes, the consistency broker 140a-n can typically snoop on each cache broker 128 or rely on directory 152 to track a set of cache brokers 128 on which data may reside.

[0036] In some embodiments, apparatus 105 may use cache coherence processing to provide coherence. Cache coherence processing may include multiple cache coherence protocols, functions, data streams, and / or the like. In various embodiments, cache coherence processing may include a directory-based cache coherence protocol. In a directory-based cache coherence protocol, agents protecting the memory (such as coherence agents 140a-n (or home agents)) collectively maintain a directory 152 that tracks where and in what state each cache line is cached in the system. A cache agent 128 attempting to retrieve a cache line may send a request to coherence agents 140a-n (e.g., via coherence structure 130), which performs a lookup in directory 152 and sends a message (typically referred to as a snooping message) to only those cache agents 128 that indicate directory 152 may have a cache copy of the cache line.

[0037] Directory 152 may store directory information (or consistency information). Memory controller 150 and / or cache consistency controller 132 may maintain the directory state of each line in memory within directory 152. In response to some transaction, the directory state of a corresponding line may change. Memory controller 150 and / or cache consistency controller 132 may update a record identifying the current directory state of each line in memory. In some cases, memory controller 150 and / or cache consistency controller 132 may receive data from consistency brokers 140a-n indicating changes to the directory state of a memory line. In other instances, memory controller 150 and / or cache consistency controller 132 may include logic for automatically updating the directory state based on the nature of a corresponding request (e.g., no host indication of change). In various embodiments, a directory read is performed using a requested address to determine whether the requested address hits or misses in directory 152, and if the memory address hits, the consistency state of the target memory block is determined. Directory information, which may include a directory state for each cache line in the system, may be returned by directory 152 in subsequent cycles.

[0038] In various embodiments, directory information may include bits or other data, such as information stored in the error correction code (ECC) bits of the memory entry corresponding to the requested data. In some embodiments, directory information may include 2 bits encoded as: invalid - no cache copy, clean - a clean copy cached in the memory location, dirty - a dirty copy cached in the memory location, and unused. In various embodiments, directory information may include two sets of two-bit directory status. In some embodiments, directory information may include 2 or 4 bits stored with the data, for example, as part of the ECC bits. The number of bits for directory 152 entries may include 2 bits, 4 bits, 6 bits, 8 bits, 10 bits, 12 bits, 16 bits, 20 bits, 32 bits, and any value or range between any two of these values ​​(including endpoints). In some embodiments, directory information may include various fields. Non-limiting examples of fields may include: a tag field that identifies the actual address of the memory block held in the corresponding cache line, a status field that indicates the consistency status of the cache line, containment bits that indicate whether the memory block is held in the associated L1 cache, and cache status information. In some embodiments, the directory may include status (or status information) to identify an exact cache with a copy of the data (if only one copy exists); a specific set of cache proxies (where copies of the data can be found); status (or status information) indicating the number of copies (e.g., 1 copy, 2 copies, multiple copies, and / or the like); and / or an indicator for the type of cache proxygent.

[0039] In some embodiments, the directory information may include cache state or cache state information. In some embodiments, the cache state information may indicate the type of memory operation, cache coherence processing, coherence operation, etc. For example, the cache state information may indicate whether cache coherence processing supports jumbo cache types, small cache types, and / or the like. In this way, directory 152 may support coherence tracking for multiple types of agents (e.g., coherence agents or home agents). Non-limiting classes of agents include jumbo cache agents (high-latency agents) that operate to support coherence for jumbo cache types and small cache agents (low-latency agents) that operate to support coherence for small cache types. In some embodiments, jumbo cache agents and / or small cache agents may include coherence agents 140a-n (or home agents). In various embodiments, cache coherence processing may include small cache coherence processing and jumbo cache coherence processing. In response to a cache state indicating a small cache state, device 105 or a component thereof may follow small cache coherence processing, and device 105 or a component thereof may follow jumbo cache coherence processing in response to a cache state indicating a jumbo cache state.

[0040] In some embodiments, a jumbo cache proxy may include a consistency proxy 140a-n that is a proxy operation of a jumbo cache type. For example, consistency proxy 140n may be a jumbo cache proxy for a jumbo cache of logical device 180. In another example, consistency proxy 140a may be a small cache proxy for a small cache (e.g., cache 124a) of core 122a. In some embodiments, processing unit 120 may include a jumbo cache. In some embodiments, logical device 180 may include a jumbo cache. In some embodiments, processing unit 120 and logical device 180 may include a jumbo cache. The embodiments are not limited to this context.

[0041] In various embodiments, cache state information may include or use additional directory bits for each directory entry to encode the cache state of each directory entry (e.g., small cache state or jumbo cache state). For example, cache state information may include 2 additional directory bits for each directory entry to provide a 2-bit directory encoding field for each proxy class of each directory entry. In some embodiments, 4 bits or encoding (e.g., from conventional...) The catalog encoding tracks the state of the giant cache, the 2-bit encoding tracks the state of the small cache, and the remaining bits or encoding tracks the "uncached" state.

[0042] In some embodiments, device 105 may be arranged in a multi-chip (or multi-socket) configuration, for example, where logic device 180 is the same as, similar to, or substantially similar to processing unit 120, a processor, processing unit, processor die, CPU, etc. In some embodiments, logic device 180 may be or may include multiple accompanying processor dies, such as two, four, or eight dies. In some embodiments where the logic device is an accompanying processor die, all processor-local groups of peer LLCs may be combined to create a single large group of LLC peers across all chips. In such embodiments, an LLC / memory coherence agent may be responsible for maintaining consistency among all peers using cache coherence processing according to some embodiments. For example, according to some embodiments, the LLC / memory coherence agent may use UPI, UPI-based, or UPI-derived cache coherence processing.

[0043] In a multi-chip configuration, the LLC / memory coherence agent (or the cache coherence process performed therefrom) needs to be notified with the same or similar information as described above via equivalents of LLC tags and SF tags. However, in a multi-chip configuration, each cache coherence process on each LLC / memory coherence agent on each chip needs to be notified in the configuration via equivalents of LLC states and SF states on each chip.

[0044] In a conventional system, if each chip in a multi-chip system includes a tag repository for each of the other chips, the size of the total tag repository per chip can grow by a factor of up to 8 (for an 8-processor die architecture) and force the chip to increase or decrease the amount of SRAM available for cache (and increase overhead power per chip). Furthermore, in terms of scalability, if a chip is built to support up to 8-chip configurations but is also used in 2- and 4-chip configurations, half or three-quarters of the aggregated tag state (and associated regions) will be wasted in the 4-chip and 2-chip configurations, respectively (e.g., not used for caching or other functional purposes).

[0045] Due to these scalability and cost issues, most solutions known in the art employ various approaches, such as tag (directory) caching, coarse-grained consistency, and full directory caching. In tag caching, each chip maintains a relatively small cache of the tag state of its peer LLCs. Tag caching addresses some aspects of cost and scalability issues but limits the amount of data that can be cached on other chips and restricts performance, while also requiring additional tag state on the processor chip. In coarse-grained consistency, for example, 1KB cache lines can be used instead of the 64B used between LLCs and cores to maintain consistency between peer LLCs. In this model, cache misses are more expensive (the entire 1KB data block must be moved), and the chance of cache conflicts (hotspot sets) is much greater. Both of these phenomena impose a performance burden while still requiring an on-die trace structure, albeit a scaled-down one. In the full directory scheme, trace state is stored in DRAM memory on a per-memory-line basis (as opposed to a per-cache-line basis). This solution adds memory read latency to certain streams to allow access to trace states and has some performance impact, but does not require additional on-die structures, allows caching at a 64-bit granularity, and does not limit the amount of data cached alongside the processor die. In some embodiments, the device can represent the tag state of the accompanying chips (such as 1 to 7 accompanying chips) in the form of using a single directory state to implement a full directory cache.

[0046] As described above, in some embodiments, logic device 180 may be an accelerator, an accelerator chip, an accelerator die, etc. When logic device 180 is a companion die in the form of a coherence accelerator die, the die may be attached to the cache hierarchy in the manner of processor cores 122a-n, participate in cache coherence processing managed by core / LLC coherence agents 114a-n, and have its cache lines tracked in the same snooping filters as the cores 122a-n of the processor chip. This is advantageous because it allows the coherence accelerator to utilize the processor LLC (or an LLC peer) and it allows the processor's core snooping filters to also be used to filter snooping to the accelerator, which may be particularly advantageous when the accelerator device has poor snooping latency.

[0047] The above arrangement works well when the accelerator cache (e.g., logic device 180 cache 184a-n) is on the same order of magnitude as the processor core 122a-n cache 124a-n. In this case, each accelerator attachment point requires a certain number of snoop filter capacities, similar to the snoop filter capacities of adding a single core to the SF of an associated LLC peer. This is a relatively small adder and presents a relatively low cost across the chip. However, when the accelerator cache is an order of magnitude larger than the processor core cache (e.g., 10MB), such a configuration can become problematic, similar to the problems of multi-socket systems, and may become inoperable or essentially inoperable when the accelerator cache grows by several orders of magnitude (e.g., 10GB), which has become possible with the advent of memory technologies such as multichannel DRAM (MCDRAM) and high-bandwidth memory (HBM).

[0048] Therefore, according to some embodiments, device 105 and / or its components can be configured to operate cache coherence processing, wherein the cache coherence processing is operable to address problems such as providing coherence state tracking for chips / agents that are coupled to a cache hierarchy at the Core / LLC coherence agent level and whose caches are too large to be tracked in the SF of the associated LLC peer, and others. For example, the cache coherence processing according to some embodiments may use a mechanism employed by LLC / memory coherence agents in a full catalog or full catalog-based scheme with a second field for a full catalog in memory, wherein the first field tracks the cache of memory rows in the LLC peer to notify the LLC / memory coherence agent, and the second field tracks the cache of the accelerator agent to notify the core / LLC coherence agent. In various embodiments, one of each type of field may be included such that all LLC peers on all accompanying processor chips are tracked by a single instance of the first field type, and all accelerators of all accompanying processors attached to a multiprocessor chip system are tracked by a single instance of the second field type. In some embodiments, N for each field type can be implemented such that each instance of each field type can be precisely mapped to a logical device 180 (e.g., exactly one accompanying processor chip, peer LLC, and / or accelerator chip).

[0049] This includes one or more logical flows representing exemplary methods for performing novel aspects of the disclosed architecture. While for the purpose of illustrative simplicity, one or more methods shown herein are illustrated and described as a series of actions, those skilled in the art will understand and appreciate that these methods are not limited to a specific order of actions. Accordingly, some actions may occur in a different order and / or concurrently with other actions shown and described herein. For example, those skilled in the art will understand and appreciate that methods may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Furthermore, not all actions shown in the methods may be necessary for a novel implementation.

[0050] The logic flow can be implemented using software, firmware, hardware, or any combination thereof. In software and firmware embodiments, the logic flow can be implemented by computer-executable instructions stored on a non-transitory computer-readable medium or a machine-readable medium (e.g., optical, magnetic, or semiconductor storage devices). Embodiments are not limited to this context.

[0051] Figure 2 An embodiment of logic flow 200 is illustrated. Logic flow 200 may represent some or all of the operations performed by one or more embodiments described herein (e.g., devices 105, 405, and / or 505 and / or components thereof). In some embodiments, logic flow 200 may represent some or all of the operations for a single-processor core read request on a multiprocessor chip.

[0052] like Figure 2 As shown, logical flow 200 can issue a read at box 202. For example, one of cores 122a-n can issue a data read. At box 204, logical flow 200 can look up the tag for the read. For example, the read procedure can use a core / LLC memory coherence agent to look up the LLC and SF tags. At box 206, logical flow 200 can determine if a usable copy of the data exists. For example, the core / LLC memory coherence agent can determine whether a copy of the line cache exists in the LLC peer or slave processor core based on the LLC tag and SF tag. If logical flow 200 determines at box 206 that a usable copy of the data exists, logical flow 200 can return the data at box 216.

[0053] If logic flow 200 determines at box 206 that a usable copy of the data exists, then logic flow 200 may issue a read to memory at box 210. For example, a core / LLC memory coherence agent may issue a read to DRAM. At box 212, logic flow 200 may return the memory row and trace field. For example, DRAM may return the memory row of data and the complete catalog trace field. At box 214, logic flow 200 may determine whether a copy of the data is available in the accompanying chip. For example, the complete catalog field may indicate that the accompanying processor chip may have a copy of the memory row. If logic flow 200 determines at box 214 that a copy of the data is available in the accompanying chip, then logic flow 200 may issue a snoop to all processor chips at box 220. For example, an LLC / memory coherence agent may issue a snoop to all accompanying processor chips. If logic flow 200 determines at box 214 that a copy of the data is not available in the accompanying chip, then logic flow 200 may return the data to the requesting core at box 216 and update the fields and tags at box 218. For example, the full directory, LLC tag, and SF tag can be updated to record that the memory line is now cached at the request core.

[0054] Figure 3 An embodiment of logic flow 300 is illustrated. Logic flow 300 may represent some or all of the operations performed by one or more embodiments described herein (e.g., devices 105, 405, and / or 505 and / or components thereof). In some embodiments, logic flow 300 may represent some or all of the operations for a single-processor core read request of a multiprocessor chip including at least one accelerator chip.

[0055] like Figure 3 As shown, logical flow 300 can issue a read at block 302. For example, one of cores 122a-n can issue a data read. At block 304, logical flow 300 can look up the tag for the read. For example, the read procedure can use a core / LLC memory coherence agent to look up the LLC and SF tags. At block 306, logical flow 300 can determine if a usable copy of the data exists. For example, the core / LLC memory coherence agent can determine whether a copy of the line cache exists in the LLC peer or slave processor core based on the LLC tag and SF tag. If logical flow 300 determines at block 306 that a usable copy of the data exists, logical flow 300 can return the data at block 322.

[0056] If logic flow 300 determines at block 306 that a usable copy of the data exists, then logic flow 300 may issue a read to memory at block 310. For example, the core / LLC memory coherence agent may issue a read to DRAM. At block 312, logic flow 300 may return the memory row and trace field. For example, DRAM may return the memory row of data and the complete catalog trace field. At block 314, logic flow 300 may determine whether a copy of the data is available in the accompanying chip. For example, the complete catalog field may indicate that the accompanying processor chip can have a copy of the memory row. If logic flow 300 determines at block 314 that a copy of the data is available in the accompanying chip, then logic flow 300 may issue a snoop to all processor chips at block 315. For example, the LLC / memory coherence agent may issue a snoop to all accompanying processor chips. If logic flow 300 determines at block 314 that a copy of the data is not available in the accompanying chip, then logic flow 300 may determine at block 318 whether a copy of the data is available in the accelerator chip. If logic flow 300 determines at block 318 that a copy of the data is available in the accelerator chip, then logic flow 300 can send a snooping request to all accelerator chips at block 320. If logic flow 200 determines at block 314 that a copy of the data is not available in the accompanying processor chip and at block 314 that a copy of the data is not available in the accompanying accelerator chip, then logic flow 300 can return the data to the requesting core at block 322 and update the fields and labels at block 324.

[0057] Figure 4 An example of an operating environment 400, which may represent various embodiments, is shown. Figure 4 The operating environment 400 depicted may include a device 405 having a processing unit 420 and a logic device 480. In some embodiments, the processing unit may be a CPU and / or may be implemented as a System-on-a-Chip (SoC). In various embodiments, the logic device 480 may include an accelerator, an I / O device, a smart I / O device, etc. The logic device 480 may include attached or directly attached memory. In various embodiments, the logic device 480 may use at least a portion of the directly attached memory as one or more caches. For example, the logic device 480 may include and / or be operatively coupled to directly attached memory capable of operating as one or more caches (e.g., small cache 484a and / or jumbo cache 484b). In some embodiments, small cache 484a may include a small cache, while jumbo cache 484b may include a jumbo cache.

[0058] Logic device 480 may be coupled to processing unit 420 via one or more interfaces, including but not limited to a consistency interface or bus (e.g., “request bus”) 406. In some embodiments, logic device 480 may be directly coupled to processing unit via bus 406. In various embodiments, logic device 480 may be coupled to processing unit 420 via bus 406 through a consistency structure (e.g., consistency structure 130). In some embodiments, logic device 480 may communicate with consistency controller 422 of processing unit 420. Consistency controller 422 may include various components to implement cache consistency within device 405. For example, consistency controller 422 may include home agent 428, consistency engine 424, snoop filter 426 (or directory), and / or the like. Processing unit 420 may include request processing agent 430 configured to process memory operation requests from logic device 480 or other elements (e.g., cache agent 128). In some embodiments, request processing agent 430 may be a component of consistency structure (e.g., consistency structure 130), for example, operating as an interface to link 406. Typically, a memory operation request may include a request to the processing unit 420 for performing a memory operation (e.g., reading, writing, etc.).

[0059] In some embodiments, when a request for a memory operation arrives at the consistency controller 422, the consistency engine 424 can determine the location to forward the request. A memory operation can typically refer to a transaction that requires access to host memory 456 or any caches 484a, 484b and / or processing unit caches (not shown). In some embodiments, host memory 456 may include directory 452. The consistency engine 424 can perform a lookup in snoop filter 426 or directory 452 to determine whether snoop filter 426 or directory 452 has directory information for the requested line. In some embodiments, snoop filter 426 may be a “sparse” or “partial” directory operable to maintain a portion of the directory (e.g., a portion of directory 452). For example, directory information in snoop filter 426 may track all caches in the system, while directory 452 may track the entire or substantially the entire physical address space in the system. For example, the directory information in snooping filter 426 can indicate a cache (such as caches 484a, 484b, caches 124a-n, cache 126, etc.) that has a copy of the cache block associated with a memory operation request. Generally, snooping filters can be used to avoid sending unnecessary snooping traffic, thereby removing snooping traffic from the critical path and reducing traffic and cache activity throughout the system. In various embodiments, snooping filter 426 and / or directory 452 can be an array organized in a set-associative manner, where each entry can contain one or more valid bits (depending on configuration – row-based or region-based), a proxy class bit, and a tag field. In one embodiment, the valid bits indicate whether the corresponding entry has valid information, and the proxy status bit is used to indicate whether the cache line exists in the corresponding cache proxy, and the tag field is used to store the tag of the cache line. In one embodiment, the proxy class bit is configured to indicate the proxy class associated with the cache line and / or memory operation.

[0060] If the snoop filter 426 and / or directory 452 has directory information, the consistency engine 424 forwards the request to the cache with the current copy of the row based on the row's presence vector. If a transaction might potentially change the state of the requested row, the consistency engine 424 updates the directory information in the snoop filter 426 and / or directory 452 to reflect these changes. If the snoop filter 426 and / or directory 452 does not have information for the row, the consistency engine 424 may add an entry to the snoop filter 426 and / or directory 452 to record the directory information for the requested row. In some embodiments, the directory information may include cache state information indicating the type of memory operation, cache coherence processing, coherence operation, etc. For example, the cache state information may indicate whether the cache coherence processing supports jumbo cache types, small cache types, and / or the like. In some embodiments, the logic device 480 and / or the consistency controller 422 are operable to specify cache state information associated with entries in the snoop filter 426 and / or directory 452. For example, entries in the snooping filter 426 and / or directory 452 associated with cache lines of small cache 484a may include cache status information indicating the state of the small cache. In another example, entries in the snooping filter 426 and / or directory 452 associated with cache lines of jumbo cache 484b may include cache status information indicating the state of the jumbo cache. In this way, logic device 480, combined with coherence controller 422, can support both small cache 484a and jumbo cache 484b using the same hardware and / or software architecture.

[0061] In some embodiments, memory requests (as a request bus) from logic device 480 may include and / or define a proxy class qualifier. In various embodiments, the proxy class qualifier on bus 406 during a read or write request from logic device 480 may specify which of two levels of consistency support the logic device requires for a particular request, including jumbo cache type support or small cache type support. Therefore, in various embodiments, memory operation requests generated by logic device 480, processor cores (e.g., processor cores 122a-n), cache proxies 128, and / or other elements may include a proxy class qualifier configured to specify the proxy class for a particular memory operation. In some embodiments, the element sending the memory request (e.g., logic device 480, e.g., operating as an accelerator, I / O device, etc.) may modulate the activity class on a request-by-request basis, allowing a single logic device 480 to employ one or more small caches and one or more jumbo caches.

[0062] In some embodiments, a data requester (e.g., logic device 480) can send a data request via bus 406. The data request may include data request information such as data, memory address, cache status information, etc. In various embodiments, cache status information may indicate the proxy class associated with the request, such as whether the request is associated with a jumbo cache state or a mini cache state. For example, a memory request from logic device 480 associated with mini cache 484a may include cache status information indicating a mini cache state, and a memory request from logic device 480 associated with jumbo cache 484b may include cache status information indicating a jumbo cache state.

[0063] Request processing agent 430 may receive or otherwise access memory requests and determine cache state information from the memory requests. In some embodiments, in response to a request indicating a small cache state, request processing agent 430 may execute, cause to execute, and / or instruct consistency controller 422 to operate small cache consistency processing, for example, using a flow that invokes or uses the die-on snoop filter 426 of processing unit 420 and a directory field associated with the small cache state. In various embodiments, in response to a request indicating a jumbo cache state, request processing agent 430 may execute, cause to execute, and / or instruct consistency controller 422 to operate jumbo cache consistency processing, instructing consistency controller 422 to use a flow that invokes a directory field associated with the jumbo cache state (e.g., with directory 452).

[0064] In some embodiments, in response to a directory state for accessing cache lines, the consistency controller 422 may forward a snooping message directly to logic device 480 in response to determining a jumbo cache state associated with a memory operation (and therefore a jumbo cache consistency process is active), the jumbo cache state indicating that logic device 480 may have a cache copy of the associated cache line. In various embodiments, in response to a directory state for accessing cache lines, when a small cache state indicates that a small cache agent may have a cache copy of the cache line associated with a memory operation (and therefore a small cache consistency process is active), the consistency controller 422 may forward a snooping message directly to the on-die processor snooping filter 426. In some embodiments, if the on-die snooping filter indicates that logic device 480 may have a cache copy of the cache line associated with a memory operation, the consistency controller 422 at the on-die snooping filter 426 may forward the snooping to logic device 480.

[0065] Figure 5An example of an operating environment 500, which may represent various embodiments, is shown. Figure 5 The operating environment 500 depicted may include a device 505 having a system memory 510 with a storage directory 520. The directory 520 may include one or more entries 530a-n. In some embodiments, each entry 530a-n may correspond to a data cache line stored in a cache (e.g., caches 124a-n, LLC 126, caches 184a-n, and / or the like) of the device 505. Each entry 530a-n may include directory information such as cache line information 540a-n (e.g., indicating the cache line and / or physical memory address associated with entry 530a-n), consistency status 542a-n (e.g., invalid, locked, owned, modified, exclusive, shared, forwarded, etc.), and / or cache status 544a-n. In various embodiments, cache status 544a-n may indicate whether cache entry 530a-n is associated with a small cache status (and therefore, a small cache type) or a large cache status (and therefore, a large cache type).

[0066] In some embodiments, for each memory operation, a consistency controller (such as consistency controller 422) may access entries 530a-n of directory 520 to determine the cache state. For example, the consistency controller may determine the cache state to perform a corresponding cache consistency process. For instance, for a read operation, in response to determining that cache state 544a-n is a jumbo cache state, the consistency controller may perform a jumbo cache consistency process, and in response to determining that cache state 544a-n is a min cache state, the consistency controller may perform a min cache consistency process. In another instance, for a write operation, the cache state may be determined based on a memory operation request, and if no previous entry exists for the associated cache line, the corresponding cache state 544a-n may be written to a new entry 530a-n, or the cache state 544a-n may be updated to correspond to the cache state specified in the memory operation request.

[0067] This includes one or more logical flows representing exemplary methods for performing novel aspects of the disclosed architecture. While for the purpose of illustrative simplicity, one or more methods shown herein are illustrated and described as a series of actions, those skilled in the art will understand and appreciate that these methods are not limited to a specific order of actions. Accordingly, some actions may occur in a different order and / or concurrently with other actions shown and described herein. For example, those skilled in the art will understand and appreciate that methods may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Furthermore, not all actions shown in the methods may be necessary for a novel implementation.

[0068] The logic flow can be implemented using software, firmware, hardware, or any combination thereof. In software and firmware embodiments, the logic flow can be implemented by computer-executable instructions stored on a non-transitory computer-readable medium or a machine-readable medium (e.g., optical, magnetic, or semiconductor storage devices). Embodiments are not limited to this context.

[0069] Figure 6 An embodiment of logical flow 600 is illustrated. Logical flow 600 may represent some or all of the operations performed by one or more embodiments described herein, such as devices 105, 405, and / or 605. In some embodiments, logical flow 600 may represent some or all of the operations for cache coherency processing according to some embodiments.

[0070] like Figure 6 As shown, at block 602, logic flow 600 may receive memory operation requests. For example, request processing agent 430 may receive or otherwise access memory requests and determine cache state information from the memory requests. At block 604, logic flow 600 may determine the cache state associated with the memory operation request. For example, request processing agent 430 may determine whether the memory operation request is associated with a jumbo cache state or a mini cache state. In various embodiments, a proxy class qualifier on bus 406 during a read request or write request from logic device 480 may specify which of two levels of consistency support the logic device requires for a particular request, including jumbo cache type support or mini cache type support. In various embodiments, memory operation requests generated by logic device 480, processor cores (e.g., processor cores 122a-n), cache agents 128, and / or other elements may include a proxy class qualifier configured to specify the proxy class to be used for a particular memory operation.

[0071] If determination block 606 determines that the cache state is a small cache state, then logic flow 600 can invoke the snoop filter at block 608 and use the directory field associated with the small cache state. For example, for a request indicating a small cache state, request processing agent 430 can instruct consistency controller 422 to operate using a flow that invokes the on-die snoop filter 426 of processing unit 420 and the directory field associated with the small cache state.

[0072] If determination box 606 determines that the cache state is a jumbo cache state, then logic flow 600 can invoke the directory field associated with the jumbo cache state. For example, for a request indicating a jumbo cache state, request processing agent 430 can instruct consistency controller 422 to operate using a flow that invokes the directory field associated with the jumbo cache state (e.g., with directory 452).

[0073] Figure 7 An embodiment of logic flow 700 is illustrated. Logic flow 700 may represent some or all of the operations performed by one or more embodiments described herein (e.g., devices 105, 405, and / or 505). In some embodiments, logic flow 700 may represent some or all of the operations for cache coherency processing according to some embodiments.

[0074] like Figure 7As shown, logic flow 700 can determine the cache state associated with cache line access at block 702. For example, in some embodiments, for each memory operation, a consistency controller (such as consistency controller 422) can access entries 530a-n of directory 520 to determine the cache state. If determination block 704 determines that the cache state is a small cache state, logic flow 700 can determine at block 706 whether the small cache agent can have a cache copy of the cache line associated with the memory operation. If the small cache agent has a copy of the cache line as indicated by determination block 706, a snooping message can be forwarded to a snooping filter at block 708. For example, in response to the directory state for accessing a cache line, when the small cache state indicates that the small cache agent can have a cache copy of the cache line associated with the memory operation, consistency controller 422 can directly forward the snooping message to on-die processor snooping filter 426. If the snooping filter at determination box 712 indicates that the jumbo cache agent of the logic device may have a cache copy of the cache line associated with the memory operation, then the snooping message can be forwarded to the logic device at box 714. For example, if the on-die snooping filter indicates that the logic device 480 may have a cache copy of the cache line associated with the memory operation, then the consistency controller 422 at on-die snooping filter 426 may forward the snooping content to the logic device 480.

[0075] If determination block 704 determines that the cache state is a jumbo cache state, then logic flow 700 may determine at determination block 712 whether the logic device cache (e.g., a jumbo cache device) can have a cache copy of the cache line associated with a memory operation. If logic flow 700 determines at block 712 that the logic device cache can have a cache copy of the cache line, then logic flow 700 may forward the snooping message to the logic device at block 714. For example, if an on-die snooping filter indicates that logic device 480 can have a cache copy of the cache line associated with a memory operation, then the consistency controller 422 at on-die snooping filter 426 may forward the snooping content to logic device 480.

[0076] Figure 8An example of storage medium 800 is shown. Storage medium 800 may include an article of manufacture. In some examples, storage medium 800 may include any non-transitory computer-readable or machine-readable medium, such as optical, magnetic, or semiconductor memory. Storage medium 800 may store various types of computer-executable instructions, such as instructions for implementing logic flows 100, 200, 600, and / or logic flow 700. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and so on. The examples are not limited to this context.

[0077] Figure 9 An embodiment of an exemplary computing architecture 900 suitable for implementing the various embodiments described above is illustrated. In various embodiments, the computing architecture 900 may include or be implemented as part of an electronic device. In some embodiments, the computing architecture 900 may represent, for example, devices 105, 405, and / or 505. The embodiments are not limited to this context.

[0078] As used herein, the terms “system,” “component,” and “module” are intended to refer to computer-related entities that can be hardware, a combination of hardware and software, software, or software in execution, examples of which are provided by the exemplary computing architecture 900. For example, a component can be, but is not limited to, a process running on a processor, a processor, a hard disk drive, multiple storage drives (of optical and / or magnetic storage media), an object, an executable file, an executing thread, a program, and / or a computer. For example, an application running on a server and the server itself can both be components. One or more components may reside within a process and / or an executing thread, and components may reside on a single computer and / or be distributed across two or more computers. Furthermore, components can communicatively couple with each other to coordinate operation via various types of communication media. Coordination may involve one-way or two-way exchange of information. For example, components may transmit information in the form of signals transmitted via a communication medium. This information can be implemented as signals assigned to various signal lines. In such an assignment, each message is a signal. However, other embodiments may optionally use data messages. Such data messages can be sent via various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

[0079] The computing architecture 900 includes various common computing elements, such as one or more processors, multi-core processors, coprocessors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, sound cards, multimedia input / output (I / O) components, power supplies, etc. However, embodiments are not limited to those implemented by the computing architecture 900.

[0080] like Figure 9 As shown, the computing architecture 900 includes a processing unit 904, a system memory 906, and a system bus 999. The processing unit 904 can be any of a variety of commercially available processors, including but not limited to... and processor; Application, embedded, and security processors; and and Processors; IBM and Cell processor; Core(2) and Processors; and similar processors. Dual microprocessors, multi-core processors, and other multiprocessor architectures can also be used as processing units 904.

[0081] System bus 999 provides interfaces for system components, including but not limited to the interface from system memory 906 to processing unit 904. System bus 999 can be any of several types of bus architectures, which can be further interconnected to memory buses (with or without memory controllers), peripheral buses, and local buses using any of a variety of commercial bus architectures. Interface adapters can be connected to system bus 999 via slot architectures. Exemplary slot architectures may include, but are not limited to, Accelerated Graphics Port (AGP), Card Bus, (Extended) Industry Standard Architecture ((E)ISA), Micro Channel Architecture (MCA), NuBus, Peripheral Component Interconnect (Extended) (PCI(X)), Fast PCI, PCMCIA, etc.

[0082] System memory 906 may include various types of computer-readable storage media in the form of one or more higher-speed memory cells, such as read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), dual data rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory such as ferroelectric polymer memory, bidirectional memory, phase-change or ferroelectric memory, silicon oxide nitride oxide silicon (SONOS) memory, magnetic cards or optical cards, device arrays such as redundant array of independent disks (RAID) drives, solid-state memory devices (e.g., USB storage, solid-state drives (SSDs)), and any other type of storage media suitable for storing information. Figure 9 In the illustrated embodiment, system memory 906 may include non-volatile memory 910 and / or volatile memory 912. The Basic Input / Output System (BIOS) may be stored in non-volatile memory 910.

[0083] Computer 902 may include various types of computer-readable storage media in the form of one or more lower-speed memory cells, including internal (or external) hard disk drive (HDD) 914, magnetic floppy disk drive (FDD) 916 for reading from or writing to removable disk 919, and optical disc drive 920 for reading from or writing to removable optical disc 922 (e.g., CD-ROM or DVD). HDD 914, FDD 916, and optical disc drive 920 may be connected to system bus 999 via HDD interface 924, FDD interface 926, and optical drive interface 929, respectively. HDD interface 924 for external drive implementation may include at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies.

[0084] Drives and associated computer-readable media provide volatile and / or non-volatile storage of data, data structures, computer-executable instructions, etc. For example, multiple program modules may be stored in drive and memory units 910, 912, including an operating system 930, one or more application programs 932, other program modules 934, and program data 936. In one embodiment, one or more application programs 932, other program modules 934, and program data 936 may include various applications and / or components, such as devices 105, 305, 405, and / or 505.

[0085] Users can input commands and information into computer 902 through one or more wired / wireless input devices (e.g., keyboard 938 and pointing devices such as mouse 940). Other input devices may include microphones, infrared (IR) remote controls, radio frequency (RF) remote controls, game controllers, styluses, card readers, dongles, fingerprint readers, gloves, drawing tablets, joysticks, keyboards, retinal readers, touchscreens (e.g., capacitive, resistive, etc.), trackballs, touchpads, sensors, pointers, etc. These and other input devices are typically connected to processing unit 904 via input device interface 942 coupled to system bus 999, but may be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, etc.

[0086] Monitor 944 or other types of display devices are also connected to system bus 999 via an interface such as video adapter 946. Monitor 944 can be internal or external to computer 902. In addition to monitor 944, computers typically include other peripheral output devices such as speakers, printers, etc.

[0087] Computer 902 can operate in a networked environment using logical connections to one or more remote computers (such as remote computer 948) via wired and / or wireless communications. Remote computer 948 can be a workstation, server computer, router, personal computer, laptop computer, microprocessor-based entertainment device, peer-to-peer device, or other common network node, and typically includes many or all of the elements described relative to computer 902, although for simplicity only memory / storage device 950 is shown. The depicted logical connections include wired / wireless connections to a local area network (LAN) 952 and / or a larger network (e.g., a wide area network (WAN) 954). Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to global communication networks, such as the Internet.

[0088] When used in a LAN networking environment, computer 902 connects to LAN 952 via a wired and / or wireless communication network interface or adapter 956. Adapter 956 facilitates wired and / or wireless communication to LAN 952 and may also include a wireless access point configured thereon for communication with the wireless functionality of adapter 956.

[0089] When used in a WAN networking environment, computer 902 may include modem 959, or a communication server connected to WAN 954, or other means for establishing communication via WAN 954 (e.g., via the Internet). Modem 959, which may be internal or external and wired and / or wireless, is connected to system bus 999 via input device interface 942. In a networking environment, program modules depicted relative to computer 902 or parts thereof may be stored in remote memory / storage device 950. It will be appreciated that the network connections shown are exemplary and other means of establishing communication links between computers may be used.

[0090] Computer 902 is operable to communicate with wired and wireless devices or entities using IEEE 902 family of standards, such as wireless devices operable in wireless communication (e.g., IEEE 802.16 air modulation techniques). This includes at least Wi-Fi (or Wireless Fidelity), WiMax, and Bluetooth. TM Wireless technologies, etc. Therefore, this communication can be a predefined structure like a traditional network, or simply self-organizing communication between at least two devices. Wi-Fi networks use radio technology called IEEE 802.11x (a, b, g, n, etc.) to provide secure, reliable, and fast wireless connections. Wi-Fi networks can be used to connect computers to each other, to the Internet, and to wired networks (which use IEEE 802.3 related media and functions).

[0091] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium, the representative instructions representing various logics within a processor, which, when read by a machine, cause the machine to manufacture the logic to perform the techniques described herein. This representation, referred to as an "IP core," can be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually manufacture the logic or processor. Some embodiments can be implemented, for example, using a machine-readable medium or article that can store instructions or a set of instructions, which, if executed by a machine, can cause the machine to perform the methods and / or operations according to the embodiments. Such a machine can include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, etc., and can be implemented using any suitable combination of hardware and / or software. Machine-readable media or articles may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and / or storage unit, such as memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard disk, floppy disk, optical disc read-only memory (CD-ROM), recordable optical disc (CD-R), rewritable optical disc (CD-RW), optical disc, magnetic media, magneto-optical media, removable memory cards or disks, various types of digital universal discs (DVDs), magnetic tape, cassette tape, etc. Instructions may include any suitable type of code implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc.

[0092] Example 1 is an apparatus including at least one processor, at least one cache memory, and logic, at least a portion of which is included in hardware. The logic is configured to receive a memory operation request associated with the at least one cache memory, determine a cache state of the memory operation request, the cache state indicating either a jumbo cache state or a mini cache state, execute the memory operation request via a mini cache coherence process in response to determining that the cache state is a mini cache state, and execute the memory operation request via a jumbo cache coherence process in response to determining that the cache state is a mini cache state.

[0093] Example 2 is an apparatus of Example 1, wherein the at least one cache memory includes at least one small cache and at least one large cache.

[0094] Example 3 is an apparatus of Example 1, wherein the at least one cache memory includes at least one jumbo cache having a memory size greater than 1 gigabyte (GB).

[0095] Example 4 is an apparatus of Example 1, wherein the at least one cache memory includes at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

[0096] Example 5 is an apparatus of Example 1, and further includes a logic device to which the at least one cache memory is operatively coupled.

[0097] Example 6 is an apparatus of Example 1, and further includes an accelerator, wherein the at least one cache memory is operatively coupled to the accelerator.

[0098] Example 7 is an apparatus of Example 1, and further includes a system memory storing a directory, the directory including cache status information for indicating whether the at least one cache memory is a jumbo cache or a mini cache.

[0099] Example 8 is an apparatus of Example 1, and further includes a consistency controller with a snooping filter, the snooping filter including cache status information for indicating whether at least one cache memory is a giant cache or a small cache.

[0100] Example 9 is a device of Example 1, which is used to specify the cache state of a memory operation request via a proxy class qualifier of the memory operation request.

[0101] Example 10 is a device of Example 1, which is used to perform small cache coherency processing using a snooping filter.

[0102] Example 11 is a device of Example 1, which is used to perform massive cache consistency processing using directory fields.

[0103] Example 12 is an apparatus of Example 1, wherein the memory operation request includes a request for accessing a cache line, the cache state being indicated by a copy of the cache line stored in a small cache broker.

[0104] Example 13 is an apparatus of Example 1, wherein the memory operation request includes a request for accessing a cache line, the cache state indicating the jumbo cache state based on a copy of the cache line stored in a jumbo cache broker.

[0105] Example 14 is a system comprising the apparatus according to any one of claims 1-13 and at least one transceiver.

[0106] Example 15 is a method comprising: receiving a memory operation request associated with at least one cache memory; determining a cache state of the memory operation request, the cache state indicating either a jumbo cache state or a small cache state; executing the memory operation request via a small cache coherence process in response to the cache state being a small cache state; and executing the memory operation request via a jumbo cache coherence process in response to the cache state being a jumbo cache state.

[0107] Example 16 is the method of Example 15, wherein the at least one cache memory includes at least one small cache and at least one large cache.

[0108] Example 17 is the method of Example 15, wherein the at least one cache memory includes at least one jumbo cache having a memory size greater than 1 gigabyte (GB).

[0109] Example 18 is a method of Example 15, wherein the at least one cache memory includes at least one small cache memory having a memory size of less than or equal to 10 megabytes (MB).

[0110] Example 19 is a method of Example 15, wherein the at least one cache memory is operatively coupled to a logical device of a computing device.

[0111] Example 20 is a method of Example 15, wherein the at least one cache memory is operatively coupled to an accelerator of a computing device.

[0112] Example 21 is a method of Example 15, which includes storing a directory containing cache state information used to indicate whether at least one cache is a giant cache or a small cache.

[0113] Example 22 is a method of Example 15, and further includes providing a snooping filter stored in a consistency controller of a computing device, the snooping filter including cache status information for indicating whether at least one cache memory is a giant cache or a small cache.

[0114] Example 23 is a method of Example 15, which includes specifying the cache state of a memory operation request via a proxy class qualifier for the memory operation request.

[0115] Example 24 is a method of Example 15, which includes using a snooping filter to perform small cache consistency processing.

[0116] Example 25 is a method of Example 15 that includes using a directory field to perform massive cache consistency processing.

[0117] Example 26 is the method of Example 15, wherein the memory operation request includes a request for accessing a cache line, the cache state being indicated by a copy of the cache line stored in a small cache broker.

[0118] Example 27 is the method of Example 15, where the memory operation request includes a request to access a cache line, and the cache state is indicated by a copy of the cache line stored in a jumbo cache broker.

[0119] Example 28 is a computer-readable storage medium storing instructions for execution by processing circuitry of a computing device, the instructions for causing the computing device to receive a memory operation request associated with at least one cache memory, determining a cache state of the memory operation request indicating either a jumbo cache state or a mini cache state, executing the memory operation request via mini cache coherence processing in response to determining that the cache state is a mini cache state, and executing the memory operation request via jumbo cache coherence processing in response to determining that the cache state is a jumbo cache state.

[0120] Example 29 is a computer-readable storage medium of Example 28, wherein the at least one cache memory includes at least one small cache and at least one large cache.

[0121] Example 30 is a computer-readable storage medium of Example 28, wherein the at least one cache memory includes at least one jumbo cache having a memory size greater than 1 gigabyte (GB).

[0122] Example 31 is a computer-readable storage medium of Example 28, wherein the at least one cache memory includes at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

[0123] Example 32 is a computer-readable storage medium of Example 28, the at least one cache memory being operatively coupled to a logical device of a computing device.

[0124] Example 33 is a computer-readable storage medium of Example 28, wherein the at least one cache memory is operatively coupled to an accelerator of a computing device.

[0125] Example 34 is a computer-readable storage medium of Example 28, the instructions being configured to cause a computing device to store a directory including cache status information, the cache status information being configured to indicate whether at least one cache is a jumbo cache or a mini cache.

[0126] Example 35 is a computer-readable storage medium of Example 28, the instructions being configured to enable a computing device to provide a snooping filter stored in a consistency controller of the computing device, the snooping filter including cache status information for indicating whether at least one cache is a jumbo cache or a mini cache.

[0127] Example 36 is a computer-readable storage medium of Example 28, the instructions being used to cause a computing device to specify the cache state of a memory operation request via a proxy class qualifier of the memory operation request.

[0128] Example 37 is a computer-readable storage medium of Example 28, which is used to enable a computing device to perform small cache coherency processing using a snooping filter.

[0129] Example 38 is a computer-readable storage medium of Example 28, which is used to enable a computing device to perform massive cache coherency processing using a directory field.

[0130] Example 39 is a computer-readable storage medium of Example 28, wherein a memory operation request includes a request for accessing a cache line, and the cache state is indicated by a copy of the cache line stored in a small cache broker.

[0131] Example 40 is a computer-readable storage medium of Example 28, wherein a memory operation request includes a request for accessing a cache line, and the cache state is indicated in a jumbo cache broker based on a copy of the cache line.

[0132] Example 41 is an apparatus including at least one cache memory unit and a memory operation management unit for receiving a memory operation request associated with at least one cache memory, determining a cache state of the memory operation request, the cache state indicating either a jumbo cache state or a mini cache state, executing the memory operation request via mini cache coherence processing in response to determining that the cache state is a mini cache state, and executing the memory operation request via jumbo cache coherence processing in response to determining that the cache state is a jumbo cache state.

[0133] Example 42 is an apparatus of Example 41, wherein the at least one cache memory includes at least one small cache and at least one large cache.

[0134] Example 43 is an apparatus of Example 41, wherein the at least one cache memory includes at least one jumbo cache having a memory size greater than 1 gigabyte (GB).

[0135] Example 44 is an apparatus of Example 41, wherein the at least one cache memory includes at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

[0136] Example 45 is an apparatus of Example 41, and further includes a logic device unit, wherein the at least one cache memory unit is operatively coupled to the logic device unit.

[0137] Example 46 is an apparatus of Example 41, and further includes an accelerator unit, wherein the at least one cache memory unit is operatively connected to the accelerator unit.

[0138] Example 47 is an apparatus of Example 41, and further includes a system memory unit that stores a directory including cache status information used to indicate whether at least one cache memory unit is a jumbo cache or a mini cache.

[0139] Example 48 is an apparatus of Example 41, and further includes a consistency controller unit with a snooping filter, the snooping filter including cache status information for indicating whether at least one cache memory unit is a giant cache or a small cache.

[0140] Example 49 is an apparatus of Example 41, in which the memory operation management unit is used to specify the cache state of a memory operation request via a proxy class qualifier of the memory operation request.

[0141] Example 50 is a device of Example 41, in which a memory operation management unit is used to perform small cache coherency processing using a snooping filter.

[0142] Example 51 is an apparatus of Example 41, in which a memory operation management unit is used to perform massive cache coherency processing using a directory field.

[0143] Example 52 is an apparatus of Example 41, wherein a memory operation request includes a request for accessing a cache line, and the cache state is indicated by a copy of the cache line stored in a small cache broker.

[0144] Example 53 is an apparatus of Example 41, wherein a memory operation request includes a request for accessing a cache line, and the cache state is indicated by a copy of the cache line stored in a jumbo cache broker.

[0145] Example 54 is a system comprising the apparatus according to any one of claims 41-53 and at least one transceiver.

[0146] It should be noted that the methods described herein need not be performed in the order described or in any particular order. Furthermore, the various activities described with respect to the methods identified herein can be performed serially or in parallel.

[0147] While specific embodiments have been illustrated and described herein, it should be understood that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all modifications or variations of the various embodiments. It should be understood that the above description is illustrative and not restrictive. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will be apparent to those skilled in the art upon reading the foregoing description. Therefore, the scope of the various embodiments includes any other applications in which the above compositions, structures, and methods are used.

[0148] It is important to emphasize that this abstract of the disclosure is provided to comply with the requirements of Section 1.72(b) of 37 C.FR, and is intended to facilitate the reader's rapid determination of the nature of the technical disclosure. It should be understood that it is not intended to be construed as limiting the scope or meaning of the claims. Furthermore, as can be seen in the foregoing detailed description, various features are combined in one embodiment for the purpose of simplifying the disclosure. The method of the disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than expressly recited in each claim. Rather, as reflected in the following claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are thereby incorporated into the detailed description, wherein each claim is itself a separate preferred embodiment. In the appended claims, the terms “including” and “in which” are used as concise English equivalents of the respective terms “comprising” and “wherein”. Furthermore, the terms “first,” “second,” “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0149] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. A computing device comprising: at least one processor; at least one cache memory; and logic, at least a portion of which is included in hardware, to: receive a memory operation request associated with the at least one cache memory, determine a cache state of the memory operation request, the cache state indicating one of a small cache state or a large cache state, in response to determining that the cache state is a small cache state, perform the memory operation request via small cache coherency processing, and in response to determining that the cache state is a large cache state, perform the memory operation request via large cache coherency processing.

2. The computing device of claim 1, the at least one cache memory comprising at least one small cache and at least one large cache.

3. The computing device of claim 1, the at least one cache memory comprising at least one large cache having a memory size greater than 1 gigabyte (GB).

4. The computing device of claim 1, the at least one cache memory comprising at least one small cache having a memory size less than or equal to 10 megabytes (MB).

5. The computing device of claim 1, further comprising a logic device, the at least one cache memory operatively coupled to the logic device.

6. The computing device of claim 1, further comprising an accelerator, the at least one cache memory operatively coupled to the accelerator.

7. The computing device of any one of claims 1 to 6, further comprising a system memory storing a directory including cache state information to indicate whether the at least one cache memory is a large cache or a small cache.

8. The computing device of any one of claims 1 to 6, further comprising a coherency controller having a snoop filter including cache state information to indicate whether the at least one cache memory is a large cache or a small cache.

9. The computing device of any one of claims 1 to 6, the logic to specify the cache state of the memory operation request via a proxy class qualifier of the memory operation request.

10. The computing device of any one of claims 1 to 6, the logic to perform the small cache coherency processing using a snoop filter.

11. The computing device of any one of claims 1 to 6, the logic to perform the large cache coherency processing using a directory field.

12. The computing device of any one of claims 1 to 6, the memory operation request comprising a request to access a cache line, the cache state indicating the small cache state based on a copy of the cache line being stored in a small cache proxy. ​ 13. The computing device according to any one of claims 1 to 6, wherein the memory operation request includes a request to access a cache line, and the cache state indicates the jumbo cache state based on a copy of the cache line being stored in a jumbo cache broker.

14. A method for processing a memory operation request, comprising: Receive a memory operation request associated with at least one cache memory of the computing device; Determine the cache state of the memory operation request, wherein the cache state indicates either a giant cache state or a small cache state; In response to the cache state being a small cache state, the memory operation request is executed via small cache coherence processing; and In response to the cache state being a jumbo cache state, the memory operation request is executed via jumbo cache coherency processing.

15. The method of claim 14, wherein the at least one cache memory comprises at least one small cache and at least one large cache.

16. The method of claim 14, wherein the at least one cache memory comprises at least one gigabyte (GB) memory size.

17. The method of claim 14, wherein the at least one cache memory comprises at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

18. The method of claim 14, wherein the at least one cache memory is operatively coupled to a logic device of the computing device.

19. The method of claim 14, wherein the at least one cache memory is operatively coupled to an accelerator of the computing device.

20. The method according to any one of claims 14-19, comprising storing a directory including cache status information, the cache status information being used to indicate whether the at least one cache memory is a jumbo cache or a mini cache.

21. The method of any one of claims 14 to 19, further comprising providing a snooping filter stored in a consistency controller of the computing device, the snooping filter including cache status information for indicating whether the at least one cache memory is a giant cache or a small cache.

22. The method of any one of claims 14 to 19, further comprising specifying the cache state of the memory operation request via a proxy class qualifier of the memory operation request.

23. The method according to any one of claims 14 to 19, comprising using a snooping filter to perform the small cache coherency processing.

24. The method of any one of claims 14 to 19, comprising using a directory field to perform the massive cache consistency processing.

25. The method of any one of claims 14 to 19, wherein the memory operation request includes a request for accessing a cache line, and the cache state indicates the mini-cache state based on a copy of the cache line being stored in a mini-cache agent.

26. A computer-readable storage medium having instructions stored thereon, which, when executed by a processor, cause the processor to perform the method according to any one of claims 14-25.

27. A computer program product comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 14-25.

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