Method and apparatus for profile-guided graphics processing optimization

Abstract

An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus includes: a graphics processor for processing graphics commands in response to execution of an application; a profile store for storing graphics execution profile data associated with one or more graphics workloads; and a profile manager for reading the profile data when one of the graphics workloads is detected during execution of the application and for configuring the graphics processor according to the profile data.

Description

Background Art Technical Field

[0001] The present invention generally relates to the field of graphics processors. More particularly, the present invention relates to an apparatus and method for profile-guided graphics processing optimization.

[0002] Related technical description

[0003] There are many opportunities to improve the performance of 3D applications running on modern GPUs by changing the configuration of the underlying system or changing the way the workload is executed on the GPU during execution. Unfortunately, implementing solutions for many of these opportunities is impractical. This is because utilizing them requires an impractical amount of foresight related to how the workload will behave in the future, or requires a large amount of real-time information related to how the workload is currently performing, as well as a large amount of processing work performed on that data. Due to the impracticality of perfect foresight and the real-time measurement of a large number of characteristics in current systems, these opportunities have not yet been realized.

[0004] Many problems that are not currently optimally addressed fit these characteristics, including by way of example and not limitation:

[0005] -Shader Single Instruction Multiple Data (SIMD) dispatch width

[0006] -Frequency balancing in power-constrained environments

[0007] - Resource cacheability

[0008] -Cache and register configuration

[0009] -Execution Unit (EU) thread count vs. per-thread registers

[0010] - Many others

[0011] In the past, this problem has been poorly addressed by configuring the system in a single way to perform as efficiently as possible across a wide range of workloads. This results in average performance, meaning that sometimes the configuration is acceptable, but sometimes it is poor relative to the optimal configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

[0013] Figure 1 is a block diagram of an embodiment of a computer system having a processor with one or more processor cores and a graphics processor;

[0014] Figure 2is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;

[0015] Figure 3 is a block diagram of one embodiment of a graphics processor, which may be a discrete graphics processing unit or may be an integrated graphics processor with multiple processing cores;

[0016] Figure 4 is a block diagram of an embodiment of a graphics processing engine for a graphics processor;

[0017] Figure 5 is a block diagram of another embodiment of a graphics processor;

[0018] Figure 6 is a block diagram of thread execution logic comprising an array of processing elements;

[0019] Figure 7 shows a graphics processor execution unit instruction format according to an embodiment;

[0020] Figure 8 is a block diagram of another embodiment of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline.

[0021] Figure 9A is a block diagram illustrating a graphics processor command format according to an embodiment;

[0022] Figure 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment;

[0023] Figure 10 An exemplary graphics software architecture for a data processing system according to an embodiment is shown;

[0024] Figure 11 An exemplary IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment is shown;

[0025] Figure 12 An exemplary system-on-chip integrated circuit that can be manufactured using one or more IP cores according to an embodiment is shown;

[0026] Figure 13 An exemplary graphics processor of a system-on-chip integrated circuit that can be manufactured using one or more IP cores is shown;

[0027] Figure 14 Additional exemplary graphics processors of system-on-a-chip integrated circuits that may be fabricated using one or more IP cores are shown;

[0028] Figure 15 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0029] Figures 16A-16D shows a parallel processor component according to an embodiment;

[0030] Figures 17A-17B is a block diagram of a graphics multiprocessor according to an embodiment;

[0031] 18A to 18F An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors.

[0032] Figure 19 shows a graphics processing pipeline according to an embodiment;

[0033] Figure 20 One embodiment of an architecture for implementing embodiments of the present invention is shown;

[0034] Figure 21 A method according to an embodiment of the present invention is shown; and

[0035] Figure 22 Another method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0036] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the present invention.

[0037] Exemplary Graphics Processor Architecture and Data Types

[0038] System Overview

[0039] Figure 1 1 is a block diagram of a processing system 100 according to an embodiment. In various embodiments, system 100 includes one or more processors 102 and one or more graphics processors 108, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0040] Embodiments of system 100 may include or be incorporated into a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 100 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Data processing system 100 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), be coupled to the wearable device, or be integrated into the wearable device. In some embodiments, data processing system 100 is a television or set-top box device having one or more processors 102 and a graphical interface generated by one or more graphics processors 108.

[0041] In some embodiments, one or more processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform operations of the system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, the instruction set 109 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 107 can each process a different instruction set 109, which may include instructions for facilitating emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as a digital signal processor (DSP).

[0042] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among the components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherence techniques. Additionally, a register file 106 is included in the processor 102, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0043] In some embodiments, processor 102 is coupled to a processor bus 110, which is used to transmit communication signals, such as address, data, or control signals, between processor 102 and other components within system 100. In one embodiment, system 100 uses an exemplary 'hub' system architecture, including a memory controller hub 116 and an input / output (I / O) controller hub 130. Memory controller hub 116 facilitates communication between memory devices and other components of system 100, while I / O controller hub (ICH) 130 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 116 is integrated within the processor.

[0044] Memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable properties for use as processing memory. In one embodiment, memory device 120 may operate as system memory for system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute applications or processes. Memory controller hub 116 is also coupled to an optional external graphics processor 112, which may communicate with one or more graphics processors 108 in processor 102 to perform graphics and media operations.

[0045] In some embodiments, the ICH 130 connects peripheral components to the memory devices 120 and the processor 102 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 146, a firmware interface 128, a wireless transceiver 126 (e.g., Wi-Fi, Bluetooth), a data storage device 124 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 142 connect multiple input devices, such as a keyboard and mouse 144 combination. A network controller 134 may also be coupled to the ICH 130. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 110. It should be understood that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, I / O controller hub 130 may be integrated within one or more processors 102 , or memory controller hub 116 and I / O controller hub 130 may be integrated within a discrete external graphics processor, such as external graphics processor 112 .

[0046] Figure 2is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A- 202N, an integrated memory controller 214 , and an integrated graphics processor 208 . Figure 2 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 200 may include additional cores up to and including additional core 202N represented by a dashed box. Processor cores 202A through 202N each include one or more internal cache units 204A through 204N. In some embodiments, each processor core may also have access to one or more shared cache units 206.

[0047] Internal cache units 204A to 204N and shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 206 and 204A to 204N.

[0048] In some embodiments, the processor 200 may further include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 210 provides management functions for various processor components. In some embodiments, the system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0049] In some embodiments, one or more of the processor cores 202A through 202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A through 202N during multithreaded processing. Additionally, the system agent core 210 may include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 202A through 202N and the graphics processor 208.

[0050] In some embodiments, processor 200 also includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 is coupled to a shared cache unit 206 and a system agent core 210, which includes one or more integrated memory controllers 214. In some embodiments, a display controller 211 is coupled to graphics processor 208 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 211 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within graphics processor 208 or system agent core 210.

[0051] In some embodiments, a ring-based interconnect 212 is used to couple the internal components of the processor 200. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 208 is coupled to the ring interconnect 212 via an I / O link 213.

[0052] Exemplary I / O link 213 represents at least one of a variety of I / O interconnects, including package I / O interconnects, that facilitate communication between various processor components and high-performance embedded memory modules 218 (e.g., eDRAM modules). In some embodiments, each of processor cores 202A through 202N and graphics processor 208 utilize embedded memory modules 218 as a shared last-level cache.

[0053] In some embodiments, the processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 200 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0054] Figure 3is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0055] In some embodiments, the graphics processor 300 also includes a display controller 302 for driving display output data to a display device 320. The display controller 302 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0056] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0057] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed functional elements that perform various tasks within components and / or spawned execution threads to 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0058] In some embodiments, the media pipeline 316 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 306. In some embodiments, the media pipeline 316 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 315. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0059] In some embodiments, the 3D / media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and to store output data.

[0060] Graphics processing engine

[0061] Figure 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is Figure 3 One version of the GPE 310 is shown. Figure 4 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 3 4. The 3D pipeline 312 and the media pipeline 316 of the GPE 410 are shown in FIG. 4. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, and in at least one embodiment, separate media and / or graphics processors are coupled to the GPE 410.

[0062] In some embodiments, GPE 410 is coupled to or includes a command streamer 403, which provides a command stream to 3D pipeline 312 and / or media pipeline 316. In some embodiments, command streamer 403 is coupled to a memory, which may be system memory or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 403 receives commands from memory and sends these commands to 3D pipeline 312 and / or media pipeline 316. The commands are instructions obtained from a ring buffer storing commands for 3D pipeline 312 and media pipeline 316. In one embodiment, the ring buffer may also include a batch command buffer that stores multiple batches of commands. Commands for 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 312 and / or image data and memory objects for media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 414 .

[0063] In various embodiments, the 3D pipeline 312 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution units) within the graphics core array 414 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0064] In some embodiments, the graphics core array 414 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations. The general logic can be used with Figure 1 (multiple) processor cores 107 or Figure 2 The general logic within cores 202A to 202N in the FPGA performs processing operations in parallel or in combination.

[0065] Output data generated by threads executing on graphics core array 414 can be output to memory in unified return buffer (URB) 418. URB 418 can store data for multiple threads. In some embodiments, URB 418 can be used to send data between different threads executing on graphics core array 414. In some embodiments, URB 418 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared function logic 420.

[0066] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0067] Graphics core array 414 is coupled to shared function logic 420, which includes a number of resources shared between the graphics cores in the graphics core array. Shared functions within shared function logic 420 are hardware logic units that provide specialized, supplemental functionality to graphics core array 414. In various embodiments, shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 within shared function logic 420. Shared functions are implemented in situations where the demand for a given specialized function is insufficient to include it within graphics core array 414. Instead, a single instance of the specialized function is implemented as a separate entity within shared function logic 420 and shared among the execution resources within graphics core array 414. The exact set of functions shared between and included within graphics core array 414 varies between embodiments.

[0068] Figure 5 is a block diagram of another embodiment of a graphics processor 500 . Figure 5 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0069] In some embodiments, graphics processor 500 includes ring interconnect 502, pipeline front end 504, media engine 537, and graphics cores 580A through 580N. In some embodiments, ring interconnect 502 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0070] In some embodiments, the graphics processor 500 receives batches of commands via a ring interconnect 502. The incoming commands are interpreted by a command streamer 503 in a pipeline front end 504. In some embodiments, the graphics processor 500 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 580A through 580N. For 3D geometry processing commands, the command streamer 503 supplies the commands to a geometry pipeline 536. For at least some media processing commands, the command streamer 503 supplies the commands to a video front end 534, which is coupled to a media engine 537. In some embodiments, the media engine 537 includes a video quality engine (VQE) 530 for video and image post-processing and a multi-format encoding / decoding (MFX) 533 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 536 and the media engine 537 each generate execution threads for thread execution resources provided by at least one graphics core 580A.

[0071] In some embodiments, the graphics processor 500 includes scalable thread execution resource representation module cores 580A to 580N (sometimes referred to as core slices), each of which has multiple sub-cores 550A to 550N and 560A to 560N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 500 can have any number of graphics cores 580A to 580N. In some embodiments, the graphics processor 500 includes a graphics core 580A having at least a first sub-core 550A and a second sub-core 560A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 550A). In some embodiments, the graphics processor 500 includes multiple graphics cores 580A to 580N, each of which includes a group of first sub-cores 550A to 550N and a group of second sub-cores 560A to 560N. Each sub-core in the set of first sub-cores 550A to 550N includes at least a first set of execution units 552A to 552N and a media / texture sampler 554A to 554N. Each sub-core in the set of second sub-cores 560A to 560N includes at least a second set of execution units 562A to 562N and a sampler 564A to 564N. In some embodiments, each sub-core 550A to 550N, 560A to 560N shares a set of shared resources 570A to 570N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0072] Execution Unit

[0073] Figure 6Thread execution logic 600 is shown, comprising an array of processing elements employed in some embodiments of a GPE. Figure 6 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0074] In some embodiments, thread execution logic 600 includes a shader processor 602, a thread dispatcher 604, an instruction cache 606, a scalable execution unit array including a plurality of execution units 608A to 608N, a sampler 610, a data cache 612, and a data port 614. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 608A, 608B, 608C, 608D, through any one of 608N-1 and 608N) based on the computational demands of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 600 includes one or more connections to a memory (e.g., system memory or cache memory) through the instruction cache 606, the data port 614, the sampler 610, and one or more of the execution unit arrays 608A to 608N. In some embodiments, each execution unit (e.g., 608A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A to 608N is scalable to include any number of individual execution units.

[0075] In some embodiments, execution units 608A to 608N are primarily used to execute shader programs. Shader processor 602 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 604. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units 608A to 608N. For example, the geometry pipeline (e.g., Figure 5 536) can dispatch vertex processing, tessellation or geometry processing threads to thread execution logic 600 ( Figure 6 In some embodiments, the thread dispatcher 604 may also process runtime thread generation requests from executing shader programs.

[0076] In some embodiments, execution units 608A through 608N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of execution units 608A through 608N is capable of multi-issue single instruction, multiple data (SIMD), and multi-threaded operation enables an efficient execution environment in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock for pipelines with integer, single-precision floating-point, and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations. When waiting for data from memory or one of the shared functions, dependency logic within execution units 608A through 608N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program that includes a different vertex shader.

[0077] Each execution unit in execution units 608A-608N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes of an instruction. An execution lane is a logical unit that performs data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 608A-608N support integer and floating point data types.

[0078] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compressed data elements (data elements of double word length (DW) size), sixteen separate 16-bit compressed data elements (data elements of word length (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0079] One or more internal instruction caches (e.g., 606) are included in the thread execution logic 600 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 612) are included to cache thread data during thread execution. In some embodiments, a sampler 610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 610 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0080] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 600 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 602 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 602 then executes the pixel or fragment shader program provided by the application programming interface (API). To execute the shader program, the shader processor 602 dispatches the thread to the execution unit (e.g., 608A) via the thread dispatcher 604. In some embodiments, the pixel shader 602 uses the texture sampling logic in the sampler 610 to access texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0081] In some embodiments, the data port 614 provides a memory access mechanism for the thread execution logic 600 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 614 includes or is coupled to one or more cache memories (e.g., data cache 612) to cache data via the data port for memory access.

[0082] Figure 7is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are included only in a subset of instructions. In some embodiments, the instruction format 700 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0083] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 710. A 64-bit compact instruction format 730 may be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit instruction format 730. The native instructions available in the 64-bit instruction format 730 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 710.

[0084] For each format, the instruction opcode 712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, where the color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 714 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., blending). For instructions using the 128-bit instruction format 710, the execution size field 716 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 716 is not available for the 64-bit compact instruction format 730.

[0085] Some execution unit instructions have up to three operands, including two source operands (src0 720, src1 722) and a destination 718. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 724), where the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0086] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0087] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0088] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0089] In some embodiments, instructions are grouped based on the opcode 712 bit field to simplify opcode decoding 740. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares the five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, while the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 744 (e.g., call (call), jump (jmp)) includes instructions using the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 746 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) using the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel across data lanes. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot products.

[0090] Graphics pipeline

[0091] Figure 8 is a block diagram of another embodiment of a graphics processor 800 . Figure 8 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0092] In some embodiments, the graphics processor 800 includes a graphics pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, the graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 800 via a ring interconnect 802. In some embodiments, the ring interconnect 802 couples the graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 802 are interpreted by a command stream converter 803, which supplies instructions to individual components of the graphics pipeline 820 or the media pipeline 830.

[0093] In some embodiments, command stream converter 803 directs the operation of vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 803. In some embodiments, vertex fetcher 805 provides vertex data to vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A and 852B via thread dispatcher 831.

[0094] In some embodiments, execution units 852A-852B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851, which is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0095] In some embodiments, the graphics pipeline 820 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation processor 813 operates under the direction of the hull shader 811 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 820. In some embodiments, the tessellation components (e.g., the hull shader 811, the tessellation processor 813, the domain shader 817) can be bypassed if tessellation is not used.

[0096] In some embodiments, the complete geometric object may be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A-852B, or may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0097] Before rasterization, the clipper 829 processes the vertex data. The clipper 829 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 873 in the render output pipeline 870 dispatches a pixel shader to convert the geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth test component 873 and access the unrasterized vertex data via the outflow unit 823.

[0098] The graphics processor 800 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the graphics processor. In some embodiments, execution units 852A-852B and associated cache(s) 851, texture and media samplers 854, and texture / sampler cache 858 are interconnected via data port 856 to perform memory access and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path.

[0099] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 878 and depth cache 879 are also available in some embodiments. A pixel operation component 877 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 841 or replaced by overlapping display planes by the display controller 843 at display time. In some embodiments, a shared L3 cache 875 can be used for all graphics components, allowing data to be shared without using main system memory.

[0100] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command stream converter 803. In some embodiments, the media pipeline 830 includes a separate command stream converter. In some embodiments, the video front end 834 processes the media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function for generating threads for dispatching to the thread execution logic 850 via the thread dispatcher 831.

[0101] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled to the graphics processor via the ring interconnect 802, or some other interconnect bus or mechanism. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0102] In certain embodiments, graphics pipeline 820 and media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any application programming interface (API). In certain embodiments, the driver software of the graphics processing unit converts the API dispatch dedicated to specific graphics or media library into a command that can be processed by the graphics processing unit. In certain embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group. In certain embodiments, support can also be provided for Microsoft's Direct3D library. In certain embodiments, the combination of these libraries can be supported. Support can also be provided for open source computer vision library (OpenCV). If the mapping from the pipeline of future API to the pipeline of graphics processing unit can be made, the future API with compatible 3D pipeline will also be supported.

[0103] Graphics pipeline programming

[0104] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. Figure 9A Solid-line boxes in show components that are typically included in a graphics command, while dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 9A The exemplary graphics processor command format 900 includes a data field for identifying the target client 902 of the command, a command operation code (opcode) 904, and an associated data field 906 for the command. Some commands also include a sub-opcode 905 and a command size 908.

[0105] In some embodiments, client 902 defines a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once the command is received by the client unit, the client unit reads the opcode 904 and sub-opcode 905 (if any) to determine the operation to be performed. The client unit uses the information in the data field 906 to execute the command. For some commands, it is desired to explicitly define the size of the command using the command size 908. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of the double word length.

[0106] Figure 9B The flowchart in FIG. 9 illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses versions of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these specific commands or command sequences. Furthermore, the commands may be issued as a batch of commands in a command sequence such that the graphics processor processes the command sequence at least partially simultaneously.

[0107] In some embodiments, graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, 3D pipeline 922 and media pipeline 924 are not operating simultaneously. A pipeline flush is performed to allow the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will halt command processing until the active rendering engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0108] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 913 is used. In some embodiments, a pipeline select command 913 is only required once in an execution context before issuing pipeline commands, unless the context is issuing commands for two pipelines. In some embodiments, a pipeline flush command 912 is required immediately before a pipeline switch via a pipeline select command 913.

[0109] In some embodiments, pipeline control commands 914 configure the graphics pipeline for operation and are used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0110] In some embodiments, commands for return buffer status 916 are used to configure a set of return buffers for the corresponding pipeline to write data to. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer status 916 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0111] The remaining commands in the command sequence differ based on the active pipeline for operation.Based on pipeline decision 920 , the command sequence is tailored for either the 3D pipeline 922 starting at 3D pipeline state 930 or the media pipeline 924 starting at media pipeline state 940 .

[0112] The commands used to configure the 3D pipeline state 930 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0113] In some embodiments, the 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 932 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches the shader execution thread to the graphics processor execution unit.

[0114] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution so that the command sequence is flushed through the graphics pipeline. The 3D pipeline performs geometry processing on the 3D primitives. Once the operation is completed, the generated geometric objects are rasterized and the pixel engine shades the generated pixels. These operations may also include additional commands for controlling pixel shading and pixel backend operations.

[0115] In some embodiments, when performing media operations, the graphics processor command sequence 910 follows the media pipeline 924 path. Generally, the specific purpose and manner of programming the media pipeline 924 depends on the media or computational operation to be performed. During the media decoding process, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0116] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands for configuring the media pipeline state 940 is dispatched or placed into the command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0117] In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 942. Once the pipeline state is configured and media object commands 942 are queued, the media pipeline 924 is triggered via an execute 944 command or an equivalent execution event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0118] Graphics software architecture

[0119] Figure 10 An exemplary graphics software architecture for data processing system 1000 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. Graphics application 1010 and operating system 1020 each execute in system memory 1050 of the data processing system.

[0120] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0121] In some embodiments, operating system 1020 is from Microsoft Corporation The operating system 1020 may be a graphics API 1022, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation, or the application may precompile the shader. In some embodiments, during the compilation of the 3D graphics application 1010, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0122] In some embodiments, user-mode graphics driver 1026 includes a back-end shader compiler 1027 that converts shader instructions 1012 into a hardware-specific representation. When using the OpenGL API, shader instructions 1012 in the GLSL high-level language are passed to user-mode graphics driver 1026 for compilation. In some embodiments, user-mode graphics driver 1026 uses operating system kernel-mode functionality 1028 to communicate with kernel-mode graphics driver 1029. In some embodiments, kernel-mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions.

[0123] IP core implementation

[0124] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions representing the various logic within the processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0125] Figure 111 is a block diagram illustrating an IP core development system 1100 that can be used to manufacture integrated circuits to perform operations according to an embodiment. The IP core development system 1100 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SoC integrated circuits). A design facility 1130 can generate a software simulation 1110 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 1115, lower-level designs at the logic or transistor levels can also be created, designed, or synthesized. Consequently, the specific details of the initial design and simulation can vary.

[0126] The RTL design 1115 or an equivalent solution can be further synthesized by the design facility into a hardware model 1120, which can be in hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 1150 or a wireless connection 1160. The manufacturing facility 1165 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0127] Exemplary System-on-Chip Integrated Circuit

[0128] Figures 12 to 14 An exemplary integrated circuit and related graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0129] Figure 121 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., processors), at least one graphics processor 1210, and may also include an image processor 1215 and / or a video processor 1220, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic, including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I 2 S / I 2 The integrated circuit may also include a display device 1245 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 1265 to access SDRAM or SRAM memory devices. Some integrated circuits may also include an embedded security engine 1270.

[0130] Figure 13 is a block diagram illustrating an exemplary graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 1310 may be Figure 12 The graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A to 1315N (e.g., 1315A, 1315B, 1315C, 1315D, all the way to 1315N-1 and 1315N). The graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to perform the operations of the vertex shader program, while the one or more fragment processors 1315A to 1315N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 1315A to 1315N use the primitives and vertex data generated by the vertex processor 1305 to generate a frame buffer for display on the display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0131] In addition, the graphics processor 1310 also includes one or more memory management units (MMUs) 1320A-1320B, one or more caches 1325A-1325B, and (multiple) circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mappings for the graphics processor 1310, including for the vertex processor 1305 and / or one or more fragment processors 1315A-1315N, which can reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B can communicate with other MMUs within the system, including with Figure 12 The graphics processor 1310 may be synchronized with one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 so that each processor 1205 to 1220 may participate in a shared or unified virtual memory system. In accordance with an embodiment, one or more circuit interconnects 1330A to 1330B may enable the graphics processor 1310 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0132] Figure 14 is a block diagram illustrating an additional exemplary graphics processor 1410 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 1410 may be Figure 12 A variant of the graphics processor 1210. The graphics processor 1410 includes Figure 13 One or more MMUs 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B of integrated circuit 1300.

[0133] The graphics processor 1410 includes one or more shader cores 1415A to 1415N (e.g., 1415A, 1415B, 1415C, 1415D, 1415E, 1415F, all the way to 1415N-1 and 1415N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code, to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. In addition, the graphics processor 1410 also includes an inter-core task manager 1405, which acts as a thread dispatcher for dispatching execution threads to the one or more shader cores 1415A to 1415N and a tiling unit 1418 for accelerating tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0134] Exemplary Graphics Microarchitecture

[0135] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0136] In the following description, numerous specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiments.

[0137] System Overview

[0138] Figure 1515 is a block diagram illustrating a computer system 1500 configured to implement one or more aspects of the embodiments described herein. Computing system 1500 includes a processing subsystem 1501 having one or more processors 1502 and a system memory 1504, the one or more processors and the system memory communicating via an interconnect path, which may include a memory hub 1505. Memory hub 1505 may be a separate component within a chipset assembly or integrated within one or more processors 1502. Memory hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. I / O subsystem 1511 includes an I / O hub 1507, which enables computing system 1500 to receive input from one or more input devices 1508. Additionally, I / O hub 1507 enables a display controller (which may be included in one or more processors 1502) to provide output to one or more display devices 1510A. In one embodiment, the one or more display devices 1510A coupled to the I / O hub 1507 may include local display devices, internal display devices, or embedded display devices.

[0139] In one embodiment, the processing subsystem 1501 includes one or more parallel processors 1512, which are coupled to the memory hub 1505 via a bus or other communication link 1513. The communication link 1513 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 1512 form a compute-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 1512 form a graphics processing subsystem that can output pixels to one of one or more display devices 1510A coupled via the I / O hub 1507. The one or more parallel processors 1512 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1510B.

[0140] Within the I / O subsystem 1511, a system storage unit 1514 can be connected to the I / O hub 1507 to provide a storage mechanism for the computing system 1500. An I / O switch 1516 can be used to provide an interface mechanism to enable connection between the I / O hub 1507 and other components that can be integrated into the platform, such as a network adapter 1518 and / or a wireless network adapter 1519, as well as various other devices that can be added via one or more plug-in devices 1520. The network adapter 1518 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 1519 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0141] Computing system 1500 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1507. Figure 15 The communication paths interconnecting the various components can be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or (multiple) any other bus or point-to-point communication interface and / or protocol such as the NV-Link high-speed interconnect or interconnect protocols known in the art.

[0142] In one embodiment, one or more parallel processors 1512 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 1512 incorporate circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 1500 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 1512, memory hub 1505, (multiple) processors 1502, and I / O hub 1507 can be integrated into a system on a chip (SoC) integrated circuit. Alternatively, the components of the computing system 1500 can be integrated into a single package to form a system in package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 1500 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0143] It should be understood that the computing system 1500 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 1502, and the number of parallel processor(s) 1512, can be modified as needed. For example, in some embodiments, the system memory 1504 is connected directly to the processor(s) 1502 rather than through a bridge, while other devices communicate with the system memory 1504 via the memory hub 1505 and the processor(s) 1502. In other alternative topologies, the parallel processor(s) 1512 are connected to the I / O hub 1507 or directly to one of the one or more processors 1502 rather than to the memory hub 1505. In other embodiments, the I / O hub 1507 and the memory hub 1505 can be integrated into a single chip. Some embodiments may include two or more groups of processor(s) 1502 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 1512.

[0144] Some specific components shown herein are optional and may not be included in all implementations of computing system 1500. For example, any number of plug-in cards or peripherals may be supported, or some components may be omitted. In addition, some architectures may use different terminology to describe components related to the computing system 1500. Figure 15 For example, in some architectures, memory hub 1505 may be referred to as a north bridge, while I / O hub 1507 may be referred to as a south bridge.

[0145] Figure 16A The parallel processor 1600 according to an embodiment is shown. The various components of the parallel processor 1600 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 1600 shown is Figure 15 A variation of one or more parallel processors 1116 is shown.

[0146] In one embodiment, parallel processor 1600 includes a parallel processing unit (PPU) 1602. The PPU includes an I / O unit 1604 that enables communication with other devices, including other instances of PPU 1602. I / O unit 1604 can be directly connected to other devices. In one embodiment, I / O unit 1604 connects to other devices via the use of a hub or switch interface, such as memory hub 1505. The connection between memory hub 1505 and I / O unit 1604 forms a communication link 1513. Within PPU 1602, I / O unit 1604 is connected to a host interface 1606 that receives commands related to performing processing operations and a memory crossbar switch 1616 that receives commands related to performing memory operations.

[0147] When host interface 1606 receives command buffers via I / O unit 1604, host interface 1606 can direct work operations for executing those commands to front end 1608. In one embodiment, front end 1608 is coupled to scheduler 1610, which is configured to distribute commands or other work items to processing cluster array 1612. In one embodiment, scheduler 1610 ensures that processing cluster array 1612 is properly configured and in a valid state before assigning tasks to processing clusters within processing cluster array 1612. In one embodiment, scheduler 1610 is implemented via firmware logic executed on a microcontroller. Scheduler 1610 implemented via a microcontroller can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1612. In one embodiment, host software can validate workloads for scheduling on processing array 1612 via one of multiple graphics processing doorbell mechanisms. These workloads may then be automatically distributed across the processing array 1612 by the scheduler 1610 logic within the scheduler microcontroller.

[0148] Processing cluster array 1612 may include up to "N" processing clusters (e.g., cluster 1614A, cluster 1614B, all the way to cluster 1614N). Each cluster 1614A to 1614N of processing cluster array 1612 may execute a large number of concurrent threads. Scheduler 1610 may use various scheduling and / or work distribution algorithms to allocate work to clusters 1614A to 1614N of processing cluster array 1612, which may vary depending on the workload caused by each type of program or calculation. Scheduling may be handled dynamically by scheduler 1610 or may be partially assisted by compiler logic during the process of compiling program logic configured to be executed by processing cluster array 1612. In one embodiment, different clusters 1614A to 1614N of processing cluster array 1612 may be assigned to process different types of programs or to perform different types of calculations.

[0149] Processing cluster array 1612 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 1612 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 1612 can include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0150] In one embodiment, processing cluster array 1612 is configured to perform parallel graphics processing operations. In embodiments where parallel processors 1600 are configured to perform graphics processing operations, processing cluster array 1612 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 1612 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing units 1602 may transfer data from system memory via I / O units 1604 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1622) during processing and then written back to system memory.

[0151] In one embodiment, when parallel processing unit 1602 is used to perform graphics processing, scheduler 1610 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 1614A to 1614N of processing cluster array 1612. In some embodiments, different portions of processing cluster array 1612 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 1614A to 1614N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1614A to 1614N for further processing.

[0152] During operation, processing cluster array 1612 may receive processing tasks to be executed via scheduler 1610, which receives commands defining processing tasks from front end 1608. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and an index of commands (e.g., which program to execute) that define how the data is to be processed. Scheduler 1610 may be configured to obtain an index corresponding to a task or may receive an index from front end 1608. Front end 1608 may be configured to ensure that processing cluster array 1612 is configured to be in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0153] Each of the one or more instances of parallel processing unit 1602 can be coupled to parallel processor memory 1622. Parallel processor memory 1622 can be accessed via memory crossbar switch 1616, which can receive memory requests from processing cluster array 1612 and I / O unit 1604. Memory crossbar switch 1616 can access parallel processor memory 1622 via memory interface 1618. Memory interface 1618 can include multiple partition units (e.g., partition unit 1620A, partition unit 1620B, through partition unit 1620N), each of which can be coupled to a portion (e.g., memory cells) of parallel processor memory 1622. In one implementation, the number of partition units 1620A through 1620N is configured to be equal to the number of memory cells, such that the first partition unit 1620A has a corresponding first memory cell 1624A, the second partition unit 1620B has a corresponding memory cell 1624B, and the Nth partition unit 1620N has a corresponding Nth memory cell 1624N. In other embodiments, the number of partition units 1620A to 1620N may not be equal to the number of memory devices.

[0154] In various embodiments, memory units 1624A through 1624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 1624A through 1624N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 1624A through 1624N may vary and may be selected from a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored on memory units 1624A through 1624N, allowing partition units 1620A through 1620N to write to portions of each render target in parallel, efficiently utilizing the available bandwidth of parallel processor memory 1622. In some embodiments, to support a unified memory design that utilizes system memory along with local cache memory, the local instance of parallel processor memory 1622 may be excluded.

[0155] In one embodiment, any of the clusters 1614A to 1614N of the processing cluster array 1612 can process data to be written to any of the memory units 1624A to 1624N within the parallel processor memory 1622. The memory crossbar 1616 can be configured to pass the output of each cluster 1614A to 1614N to any partition unit 1620A to 1620N or another cluster 1614A to 1614N, which can perform additional processing operations on the output. Each cluster 1614A to 1614N can communicate with a memory interface 1618 via the memory crossbar 1616 to perform read or write operations on various external memory devices. In one embodiment, memory crossbar 1616 may be connected to memory interface 1618 for communicating with I / O unit 1604 and to local instances of parallel processor memory 1622, thereby enabling processing units within different processing clusters 1614A through 1614N to communicate with system memory or other memory that is not local to parallel processing unit 1602. In one embodiment, memory crossbar 1616 may use virtual channels to separate traffic flows between clusters 1614A through 1614N and partition units 1620A through 1620N.

[0156] Although a single instance of parallel processing unit 1602 is shown within parallel processor 1600, any number of instances of parallel processing unit 1602 may also be included. For example, multiple instances of parallel processing unit 1602 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 1602 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 1602 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 1602 or parallel processor 1600 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0157] Figure 16B is a block diagram of a partition unit 1620 according to an embodiment. In one embodiment, the partition unit 1620 is Figure 16A16 . As shown, partition unit 1620 includes an L2 cache 1621, a frame buffer interface 1625, and a ROP 1626 (raster operation unit). L2 cache 1621 is a read / write cache that is configured to execute load and store operations received from memory crossbar 1616 and ROP 1626. Read misses and urgent writeback requests are output by L2 cache 1621 to frame buffer interface 1625 for processing. Updates can also be sent to the frame buffer via frame buffer interface 1625 for processing. In one embodiment, frame buffer interface 1625 interacts with one of the memory units in parallel processor memory, such as memory units 1624A to 1624N of FIG. 16 (e.g., within parallel processor memory 1622).

[0158] In graphics applications, ROP 1626 is a processing unit that performs raster operations (e.g., stenciling, z-testing, color blending, etc.). ROP 1626 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 1626 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 1626 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0159] In some embodiments, ROP 1626 is included within each processing cluster (e.g., clusters 1614A through 1614N of FIG. 16 ) rather than within partition unit 1620. In such embodiments, read and write requests for pixel data are transmitted through memory crossbar 1616 rather than pixel fragment data. The processed graphics data may be displayed on a display device such as a Figure 15 1502 for further processing, or by one of the one or more display devices 1510 of the Figure 16A One of the processing entities within parallel processor 1600 is routed for further processing.

[0160] Figure 16C16 is a block diagram of a processing cluster 1614 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 1614A to 1614N of Figure 16. Processing cluster 1614 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) technology is used to use a public instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters to support the parallel execution of a large number of roughly synchronized threads. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0161] The operation of processing cluster 1614 can be controlled via pipeline manager 1632, which distributes processing tasks to SIMT parallel processors. Pipeline manager 1632 receives instructions from scheduler 1610 of FIG. 16 and manages the execution of those instructions via graphics multiprocessor 1634 and / or texture unit 1636. The illustrated graphics multiprocessor 1634 is an illustrative instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within processing cluster 1614. One or more instances of graphics multiprocessor 1634 can be included within processing cluster 1614. Graphics multiprocessor 1634 can process data, and data crossbar 1640 can be used to distribute processed data to one of multiple possible destinations, including other shading units. Pipeline manager 1632 can facilitate the distribution of processed data by specifying a destination for data to be distributed via data crossbar 1640.

[0162] Each graphics multiprocessor 1634 within a processing cluster 1614 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before the previous instruction has completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0163] Instructions transmitted to processing cluster 1614 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1634. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1634. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 1634. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 1634, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1634.

[0164] In one embodiment, graphics multiprocessor 1634 includes internal cache memory for performing load and store operations. In one embodiment, graphics multiprocessor 1634 may forgo internal cache memory and instead use cache memory (e.g., L1 cache 308) within processing cluster 1614. Each graphics multiprocessor 1634 may also access an L2 cache within a partition unit (e.g., partition units 1620A to 1620N in FIG. 16 ) that is shared across all processing clusters 1614 and may be used to pass data between threads. Graphics multiprocessor 1634 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 1602 may be used as global memory. Embodiments in which processing cluster 1614 includes multiple instances of graphics multiprocessor 1634 may share common instructions and data that may be stored in L1 cache 1708.

[0165] Each processing cluster 1614 may include an MMU 1645 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 1645 may reside within the memory interface 1618 of FIG. 16 . The MMU 1645 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more commonly referred to as tiles) and, optionally, cache line indexes. The MMU 1645 may include a translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1634 or L1 cache or processing cluster 1614. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0166] In graphics and compute applications, processing clusters 1614 can be configured such that each graphics multiprocessor 1634 is coupled to a texture unit 1636 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 1634, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 1634 outputs processed tasks to a data crossbar 1640 to provide the processed tasks to another processing cluster 1614 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1616. A preROP 1642 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1634 and direct the data to ROP units, which can be located using partition units (e.g., partition units 1620A through 1620N of FIG. 16 ) as described herein. The preROP 1642 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0167] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 1634, texture unit 1636, preROP 1642, etc., may be included within processing cluster 1614. Furthermore, while only one processing cluster 1614 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 1614. In one embodiment, each processing cluster 1614 may be configured to operate independently of other processing clusters 1614 using separate and distinct processing units, L1 cache, etc.

[0168] Figure 16D A graphics multiprocessor 1634 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 1634 is coupled to the pipeline manager 1632 of the processing cluster 1614. The graphics multiprocessor 1634 has an execution pipeline that includes, but is not limited to, an instruction cache 1652, an instruction unit 1654, an address mapping unit 1656, a register file 1658, one or more general purpose graphics processing unit (GPGPU) cores 1662, and one or more load / store units 1666. The GPGPU cores 1662 and the load / store units 1666 are coupled to a cache memory 1672 and a shared memory 1670 via a memory and cache interconnect 1668.

[0169] In one embodiment, the instruction cache 1652 receives a stream of instructions to be executed from the pipeline manager 1632. These instructions are cached in the instruction cache 1652 and dispatched for execution by the instruction unit 1654. The instruction unit 1654 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 1662. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 1656 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 1666.

[0170] The register file 1658 provides a set of registers for the functional units of the graphics multiprocessor 1724. The register file 1658 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 1662, load / store unit 1666) connected to the graphics multiprocessor 1724. In one embodiment, the register file 1658 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 1658. In one embodiment, the register file 1658 is divided between the different warps being executed by the graphics multiprocessor 1724.

[0171] The GPGPU cores 1662 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1724. Depending on the embodiment, the architecture of the GPGPU cores 1662 may be similar or different. For example, and in one embodiment, the first portion of the GPGPU core 1662 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 1724 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0172] In one embodiment, the GPGPU core 1662 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1662 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by the shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads can be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0173] Memory and cache interconnect 1668 is an interconnect network that connects each of the functional units of graphics multiprocessor 1724 to register file 1658 and shared memory 1670. In one embodiment, memory and cache interconnect 1668 is a crossbar interconnect that allows load / store unit 1666 to perform load and store operations between shared memory 1670 and register file 1658. Register file 1658 can operate at the same frequency as GPGPU core 1662, so data transfer between GPGPU core 1662 and register file 1658 has very low latency. Shared memory 1670 can be used to facilitate communication between threads executing on functional units within graphics multiprocessor 1634. For example, cache memory 1672 can be used as a data cache to cache texture data communicated between functional units and texture unit 1636. Shared memory 1670 can also be used as a cached managed program. In addition to the automatically cached data stored in cache memory 1672, threads executing on GPGPU core 1662 can also programmatically store data in shared memory.

[0174] 17A to 17B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 1725, 1750 shown are Figure 16C The illustrated graphics multiprocessors 1725, 1750 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0175] Figure 17A A graphics multiprocessor 1725 is shown according to an additional embodiment. The graphics multiprocessor 1725 includes Figure 16DThe graphics multiprocessor 1725 may include multiple additional instances of execution resource units of the graphics multiprocessor 1634. For example, the graphics multiprocessor 1725 may include multiple instances of instruction units 1732A-1732B, register files 1734A-1734B, and texture unit(s) 1744A-1744B. The graphics multiprocessor 1725 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 1736A-1736B, GPGPU cores 1737A-1737B, GPGPU cores 1738A-1738B) and multiple sets of load / store units 1740A-1740B. In one embodiment, the execution resource units have a common instruction cache 1730, texture and / or data cache memory 1742, and shared memory 1746.

[0176] Various components can communicate via an interconnect fabric 1727. In one embodiment, the interconnect fabric 1727 includes one or more crossbar switches to facilitate communication between the various components of the graphics multiprocessor 1725. In one embodiment, the interconnect fabric 1727 is a separate, high-speed network fabric layer upon which each component of the graphics multiprocessor 1725 is stacked. Components of the graphics multiprocessor 1725 communicate with remote components via the interconnect fabric 1727. For example, the GPGPU cores 1736A-1736B, 1737A-1737B, and 1737A-1738B can each communicate with the shared memory 1746 via the interconnect fabric 1727. The interconnect fabric 1727 can arbitrate communications within the graphics multiprocessor 1725 to ensure fair bandwidth distribution between components.

[0177] Figure 17B A graphics multiprocessor 1750 is shown according to an additional embodiment. Figure 16D and Figure 17A As shown, the graphics processor includes multiple sets of execution resources 1756A to 1756D, each of which includes multiple instruction units, register files, GPGPU cores, and load-store units. The execution resources 1756A to 1756D can work with (multiple) texture units 1760A to 1760D to perform texture operations while sharing an instruction cache 1754 and a shared memory 1762. In one embodiment, the execution resources 1756A to 1756D can share multiple instances of the instruction cache 1754 and the shared memory 1762 as well as texture and / or data cache memories 1758A to 1758B. Various components can be connected to the graphics processor via the CPU. Figure 17A The interconnect structure 1727 communicates with a similar interconnect structure 1752.

[0178] Those skilled in the art will understand that Figure 15 、 16A to 16D and 17A to 17B The architecture described in the foregoing is illustrative and does not limit the scope of the embodiments of the present invention. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as parallel processing unit 1602 of FIG. 16 ; and one or more graphics processors or special purpose processing units, without departing from the scope of the embodiments described herein.

[0179] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0180] Technologies for GPU to host processor interconnect

[0181] Figure 18A An exemplary architecture is shown in which multiple GPUs 1810 to 1813 are communicatively coupled to multiple multi-core processors 1805 to 1806 via high-speed links 1840 to 1843 (e.g., a bus, a point-to-point interconnect, etc.). In one embodiment, the high-speed links 1840 to 1843 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0182] Furthermore, in one embodiment, two or more of the GPUs 1810-1813 are interconnected via high-speed links 1844-1845, which may be implemented using the same or different protocols / links as used for high-speed links 1840-1843. Similarly, two or more of the multi-core processors 1805-1806 may be connected via high-speed link 1833, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 18AAll communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0183] In one embodiment, each multi-core processor 1805-1806 is communicatively coupled to processor memory 1801-1802 via memory interconnects 1830-1831, respectively, and each GPU 1810-1813 is communicatively coupled to GPU memory 1820-1823 via GPU memory interconnects 1850-1853, respectively. Memory interconnects 1830-1831 and 1850-1853 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1801-1802 and GPU memory 1820-1823 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memory may be volatile memory while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0184] As described below, although the various processors 1805-1806 and GPUs 1810-1813 may each be physically coupled to a specific memory 1801-1802, 1820-1823, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 1801-1802 may each include 64GB of system memory address space, and the GPU memories 1820-1823 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory space in the described example).

[0185] Figure 18B 1846 according to one embodiment. The graphics acceleration module 1846 may include one or more GPU chips integrated on a line card coupled to the processor 1807 via the high-speed link 1840. Alternatively, the graphics acceleration module 1846 may be integrated on the same package or chip as the processor 1807.

[0186] The illustrated processor 1807 includes a plurality of cores 1860A to 1860D, each of which has a translation lookaside buffer 1861A to 1861D and one or more caches 1862A to 1862D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 1862A to 1862D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1826 may be included in the cache hierarchy and shared by each group of cores 1860A to 1860D. For example, one embodiment of the processor 1807 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 1807 and the graphics accelerator integrated module 1846 are connected to the system memory 1841 , which may include the processor memories 1801 to 1802 .

[0187] Coherence is maintained for data and instructions stored in the various caches 1862A-1862D, 1856, and system memory 1841 via inter-core communication via a coherence bus 1864. For example, each cache may have associated cache coherence logic / circuitry to communicate via the coherence bus 1864 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 1864 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art, and to avoid obscuring the underlying principles of the present invention, they are not described in detail herein.

[0188] In one embodiment, the proxy circuit 1825 communicatively couples the graphics acceleration module 1846 to the coherence bus 1864, thereby allowing the graphics acceleration module 1846 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 1835 provides connectivity to the proxy circuit 1825 via a high-speed link 1840 (e.g., a PCIe bus, NVLink, etc.), and the interface 1837 connects the graphics acceleration module 1846 to the link 1840.

[0189] In one implementation, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1831, 1832, and N of the graphics acceleration module 1846. The graphics processing engines 1831, 1832, and N can each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1831, 1832, and N can include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer engine. In other words, the graphics acceleration module can be a GPU having multiple graphics processing engines 1831, 1832, and N, or the graphics processing engines 1831 to 1832, and N can be separate GPUs integrated on a common package, line card, or chip.

[0190] In one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 1841. The MMU 1839 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1838 stores commands and data for efficient access by graphics processing engines 1831-1832, N. In one embodiment, data stored in cache 1838 and graphics memory 1833-1834, N is kept consistent with core caches 1862A-1862D, 1856, and system memory 1811. As mentioned, this can be accomplished via proxy circuitry 1825, which participates in cache coherence mechanisms on behalf of cache 1838 and memories 1833 to 1834, N (e.g., sending updates to cache 1838 related to modifications / accesses of cache lines on processor caches 1862A to 1862D, 1856 and receiving updates from cache 1838).

[0191] A set of registers 1845 stores context data for threads executed by graphics processing engines 1831 to 1832, 183N, and context management circuitry 1848 manages thread contexts. For example, context management circuitry 1848 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 1848 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer). The context management circuitry can restore register values ​​upon returning to context. In one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0192] In one implementation, the virtual / effective addresses from the graphics processing engine 1831 are translated into real / physical addresses in the system memory 1811 by the MMU 1839. One embodiment of the accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. The graphics accelerator module 1846 can be dedicated to a single application executing on the processor 1807, or can be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented in which the resources of the graphics processing engines 1831 to 1832, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0193] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration modules 1846 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0194] Because the hardware resources of the graphics processing engines 1831-1832, N are explicitly mapped into the actual address space seen by the host processor 1807, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 1836 is the physical separation of the graphics processing engines 1831-1832, N so that they appear on the system as independent units.

[0195] As mentioned, in the illustrated embodiment, one or more graphics memories 1833-1834, M are respectively coupled to each of the graphics processing engines 1831-1832, N. The graphics memories 1833-1834, M store instructions and data being processed by each of the graphics processing engines 1831-1832, N. The graphics memories 1833-1834, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0196] In one embodiment, to reduce data traffic on link 1840, biasing techniques are used to ensure that the data stored in graphics memories 1833-1834, M is the data most frequently used by graphics processing engines 1831-1832, N, and preferably not used (at least not frequently) by cores 1860A-1860D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1831-1832, N) within caches 1862A-1862D, 1856 of the cores and system memory 1811.

[0197] Figure 18C Another embodiment is shown in which an accelerator integrated circuit 1836 is integrated into the processor 1807. In this embodiment, the graphics processing engines 1831 to 1832, 183N communicate directly with the accelerator integrated circuit 1836 via the interface 1837 and the interface 1835 over a high-speed link 1840 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 1836 can perform operations related to Figure 18B The same operations are described, but given their close proximity to the coherency bus 1862 and caches 1862A to 1862D, 1826, it is possible to operate at a higher throughput.

[0198] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0199] In one embodiment of a dedicated process model, graphics processing engines 1831 to 1832, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 1831 to 1832, N, thereby providing virtualization within a VM / partition.

[0200] In a dedicated process programming model, graphics processing engines 1831-1832, N can be shared by multiple VM / application partitions. This shared model requires a hypervisor, which virtualizes graphics processing engines 1831-1832, N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 1831-1832, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 1831-1832, N to provide access to each process or application.

[0201] For the shared programming model, graphics acceleration module 1846 or individual graphics processing engines 1831-1832, N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 1811 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with graphics processing engine 1831-1832, N (i.e., calling system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0202] Figure 18D An exemplary accelerator integrated slice 1890 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 1836. An application effective address space 1882 within system memory 1811 stores process elements 1883. In one embodiment, process elements 1883 are stored in response to GPU calls 1881 from applications 1880 executing on processor 1807. Process elements 1883 contain the processing state of the corresponding application 1880. The work descriptor (WD) 1884 contained in process element 1883 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD 1884 is a pointer to a job request queue in the application address space 1882.

[0203] Graphics acceleration module 1846 and / or individual graphics processing engines 1831 to 1832, N may be shared by all or some processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 1884 to the graphics acceleration module 1846 to start a job in a virtual environment.

[0204] In one implementation, a dedicated process programming model is specific to a particular implementation. In this model, a single process owns either the graphics acceleration module 1846 or a separate graphics processing engine 1831. Because the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1836 to obtain the owning partition, and the operating system initializes the accelerator integrated circuit 1836 to obtain the owning process when the graphics acceleration module 1846 is allocated.

[0205] In operation, a WD fetch unit 1891 in the accelerator integrated slice 1890 fetches the next WD 1884, which includes an indication of work to be performed by one of the graphics processing engines of the graphics acceleration module 1846. As shown, data from WD 1884 can be stored in register 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1846. For example, one embodiment of the MMU 1839 includes a segment / page walk circuit for accessing the segment / page table 1886 within the OS virtual address space 1885. The interrupt management circuitry 1847 can process interrupt events 1892 received from the graphics acceleration module 1846. When executing graphics operations, effective addresses 1893 generated by the graphics processing engines 1831 to 1832, N are converted into real addresses by the MMU 1839.

[0206] In one embodiment, the same set of registers 1845 is replicated for each graphics processing engine 1831 to 1832, N, and / or graphics acceleration module 1846, and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 1890. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0207] Table 1 - Hypervisor Initialization Registers

[0208] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0209] Example registers that may be initialized by the operating system are shown in Table 2.

[0210] Table 2 - Operating System Initialization Registers

[0211] 1 Process and thread identifiers 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (RA) Accelerator Utilizes Record Pointers 4 Virtual Address (RA) storage segment table pointer 5 Authorization Mask 6 Job Descriptor

[0212] In one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831-1832, N. The WD contains all the information needed by the graphics processing engine 1831-1832, N to complete its work, or the WD may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0213] Figure 18E

[00106] Additional details of one embodiment of a sharing model are shown. The embodiment includes a hypervisor real address space 1898 in which a process element list 1899 is stored. The hypervisor real address space 1898 is accessible via a hypervisor 1896 that virtualizes the graphics acceleration module engine of an operating system 1895.

[0214] The shared programming model allows all or some processes from all or some partitions in the system to use the graphics acceleration module 1846. There are two programming models where the graphics acceleration module 1846 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0215] In this model, hypervisor 1896 owns graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. For graphics acceleration module 1846 to support hypervisor 1896 virtualization, it must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 1846 must provide a context save and restore mechanism. 2) Graphics acceleration module 1846 guarantees that application job requests will complete within a specified amount of time, including any translation errors, or graphics acceleration module 1846 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness must be guaranteed for graphics acceleration module 1846 within the process.

[0216] In one embodiment, for a shared model, application 1880 is required to make an operating system 1895 system call using a graphics acceleration module 1846 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 1846 type describes the target acceleration function of the system call. The graphics acceleration module 1846 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 1846 and can take the form of: a graphics acceleration module 1846 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure describing the work to be performed by the graphics acceleration module 1846. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application setting the AMR. If the implementation of the accelerator integrated circuit 1836 and graphics acceleration module 1846 does not support the User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR into the process element 1883, the hypervisor 1896 may optionally apply the current authorization mask override register (AMOR) value. In one embodiment, the CSRP is one of the registers 1845 that contains the effective address of an area in the application address space 1882 for the graphics acceleration module 1846 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be plugged into system memory.

[0217] Upon receiving the system call, the operating system 1895 may verify that the application 1880 is registered and authorized to use the graphics acceleration module 1846. The operating system 1895 then calls the hypervisor 1896 using the information shown in Table 3.

[0218] Table 3 - Parameters of the operating system calling the hypervisor

[0219] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0220] Upon receiving the hypervisor call, the hypervisor 1896 can verify that the operating system 1895 has registered and is authorized to use the graphics acceleration module 1846. The hypervisor 1896 then places the process element 1883 into the process element linked list for the corresponding graphics acceleration module 1846 type. The process element may contain the information shown in Table 4.

[0221] Table 4 - Process element information

[0222]

[0223]

[0224] In one embodiment, the hypervisor initializes multiple accelerator integrated slices 1890 of registers 1845 .

[0225] like Figure 18F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 1801-1802 and GPU memories 1820-1823. In this implementation, operations executed on GPUs 1810-1813 utilize the same virtual / effective memory address space to access processor memories 1801-1802, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801, a second portion is allocated to second processor memory 1802, a third portion is allocated to GPU memory 1820, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1801-1802 and GPU memories 1820-1823, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0226] In one embodiment, bias / coherency management circuitry 1894A-1894E within one or more of MMUs 1839A-1839E ensures cache coherency between the caches of the host processor (e.g., 1805) and GPUs 1810-1813 and performs biasing techniques that indicate physical memory where certain types of data should be stored. Figure 18F Multiple examples of bias / consistency management circuits 1894A to 1894E are shown in FIG, but bias / consistency circuits may also be implemented within an MMU of one or more host processors 1805 and / or within an accelerator integrated circuit 1836.

[0227] One embodiment allows GPU-attached memory 1820 to 1823 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memory 1820 to 1823 as system memory does not incur heavy cache coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows host processor 1805 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 1820 to 1823 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in situations with a large amount of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1810 to 1813. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play an important role in determining the effectiveness of GPU offloading.

[0228] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure consisting of 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1820 to 1823, with or without a bias cache in GPUs 1810 to 1813 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be maintained within the GPU.

[0229] In one implementation, the bias table entry associated with each access to GPU-attached memory 1820-1823 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from GPUs 1810-1813 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1820-1823. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1805 (e.g., over a high-speed link as described above). In one embodiment, requests from processor 1805 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests for GPU bias pages can be forwarded to GPUs 1810-1813. If the GPU is not currently using the page, the GPU can convert the page to the host processor bias.

[0230] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0231] One mechanism for changing bias states employs an API call (e.g., OpenCL) that in turn calls a GPU device driver that in turn sends a message (or queues a command descriptor) to the GPU, thereby directing the GPU to change bias states and, for certain transitions, perform a cache flush operation in the host. The cache flush operation is required for transitions from host processor 1805 bias to GPU bias, but not for the reverse transition.

[0232] In one embodiment, cache coherence is maintained by temporarily rendering GPU offset pages uncacheable to host processor 1805. To access these pages, processor 1805 may request access from GPU 1810, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 1805 and GPU 1810, it is advantageous to ensure that GPU offset pages are required by the GPU but not by host processor 1805, and vice versa.

[0233] Graphics processing pipeline

[0234] Figure 19 16. A graphics processing pipeline 1900 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 1900. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processor 1600 of FIG. 16. In one embodiment, the parallel processor is Figure 1516 ). As described herein, various parallel processing systems can implement the graphics processing pipeline 1900 via one or more instances of a parallel processing unit (e.g., parallel processing unit 1602 of FIG. 16 ). For example, a shader unit (e.g., graphics multiprocessor 1634 of FIG. 17 ) can be configured to perform the functionality of one or more of a vertex processing unit 1904, a tessellation control processing unit 1908, a tessellation evaluation processing unit 1912, a geometry processing unit 1916, and a fragment / pixel processing unit 1924. The functionality of the data assembler 1902, primitive assemblers 1906, 1914, 1918, tessellation unit 1910, rasterizer 1922, and raster operation unit 1926 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 1614 of FIG. 17 ) and corresponding partition units (e.g., partition units 1620A through 1620N of FIG. 16 ). The graphics processing pipeline 1900 may also be implemented using one or more dedicated processing units. In one embodiment, one or more portions of the graphics processing pipeline 1900 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 1900 may access on-chip memory (e.g., parallel processor memory 1622 shown in FIG. 16 ) via a memory interface 1928, which may be an example of the memory interface 1618 of FIG. 16 .

[0235] In one embodiment, data assembler 1902 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 1902 then outputs the vertex data, including vertex attributes, to vertex processing unit 1904. Vertex processing unit 1904 is a programmable execution unit that executes vertex shader programs, thereby lighting and transforming vertex data as specified by the vertex shader programs. Vertex processing unit 1904 reads data stored in cache, local, or system memory for processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0236] A first instance of primitive assembler 1906 receives vertex attributes from vertex processing unit 190. Primitive assembler 1906 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 1908. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0237] The tessellation control processing unit 1908 treats the input vertices as control points of a geometry patch. These control points are transformed from an input representation of the patch (e.g., a basis for the patch) into a representation suitable for surface estimation by the tessellation evaluation processing unit 1912. The tessellation control processing unit 1908 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 1910 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilaterals, which are transmitted to the tessellation evaluation processing unit 1912. The tessellation evaluation processing unit 1912 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0238] A second instance of primitive assembler 1914 receives vertex attributes from tessellation evaluation processing unit 1912, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 1916. Geometry processing unit 1916 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 1914 as specified by the geometry shader programs. In one embodiment, geometry processing unit 1916 is programmed to tessellate a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0239] In some embodiments, the geometry processing unit 1916 may add or remove elements from the geometry stream. The geometry processing unit 1916 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 1918. The primitive assembler 1918 receives the parameters and vertices from the geometry processing unit 1916 and constructs graphics primitives for processing by the viewport scaling, picking, and clipping unit 1920. The geometry processing unit 1916 reads data stored in parallel processor memory or system memory to process the geometry data. The viewport scaling, picking, and clipping unit 1920 performs clipping, picking, and viewport scaling and outputs the processed graphics primitives to the rasterizer 1922.

[0240] The rasterizer 1922 can perform depth sorting and other depth-based optimizations. The rasterizer 1922 also performs scan conversion on new graphics primitives to generate fragments and outputs these fragments and associated coverage data to the fragment segment / pixel processing unit 1924. The fragment / pixel processing unit 1924 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 1924 transforms the fragments or pixels received from the rasterizer 1922 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 1924 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operation unit 1926. The fragment / pixel processing unit 1924 can read data stored in parallel processor memory or system memory for use in processing the fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity based on the sampling rate configured for the processing unit.

[0241] Raster operation unit 1926 is a processing unit that performs raster operations including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 1622 in FIG. 16 , and / or as Figure 15 The raster operation unit 1926 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0242] Method and apparatus for profile-guided graphics processing optimization

[0243] One embodiment of the present invention addresses the limitations of current systems by implementing a profile-guided optimization approach and converting it into a dynamic, runtime optimization approach for GPUs. In one embodiment, a GPU workload is profiled, and then some properties of how the workload executes on the GPU are changed. The impact of the changes is measured, and the optimal configuration of the workload is selected to run the workload forward based on these measurements. This results in significantly improved 3D performance for the application. This method can be repeated at runtime to adapt to dynamically changing workloads.

[0244] Figure 2020. The architecture of one embodiment of the present invention is shown. The first step is to initiate the collection of profile data, which can be stored and maintained in a local database 2005 or in a cloud database 2015 coupled to the system via a network 2010. In one embodiment, a profile manager 2021 initiates the collection of profile data on a workload as it runs on a GPU 2022. As shown, the profile manager 2021 can be included with a user-mode driver 2026. However, different configurations are possible while still conforming to the underlying principles of the present invention (e.g., profile management can be performed at the application layer).

[0245] Profile manager 2021 can collect profile data 2005 once or periodically (e.g., every second, every 15 seconds, every minute, etc.). Alternatively or additionally, profile requester 2036 in application 2035 initiates the collection of profile data 2005 through API extension 2020 within 3D API 2025. In this embodiment, API extension 2020 provides access to profile manager 2021 in user-mode driver 2026. This can occur once when application 2035 is launched. Profile data 2005 can alternatively be measured offline by the designer of GPU 2022 and provided in cloud database 2015 via a cloud service. In one embodiment, in response to profile data 2005, shader compiler 2018 generates shader 2019 that implements appropriate profiling of the workload.

[0246] As an example of system operation, the optimal SIMD dispatch width can be identified for a workload. To make a selection, the profile manager 2021 runs the workload using each of the available dispatch widths (e.g., SIMD8, SIMD16, SIMD32, etc.) and measures the execution time of the workload in each of these configurations. This information is then stored in the profiled data database 2005.

[0247] Once profile data 2005 has been collected from the executed workload or profile data 2005 has been retrieved from the cloud database 2015, the profile manager 2021 then uses the data in the database to determine the optimal hardware and software configuration for GPU 222 to execute the workload during the next execution interval. As mentioned, for example, the shader compiler 2018 can generate shaders 219 using the optimal characteristics for the workload. Additionally, when selecting the optimal SIMD dispatch width, the profile manager 2021 can select the dispatch width that takes the least time to execute. While a specific example is provided here for illustrative purposes, various other GPU profile-guided optimizations can be used to address other problems that may require more complex decision logic that weighs performance, power, latency, and other variables associated with workload execution. By way of example and not limitation, these variables can include frequency balancing in a power-constrained environment, resource cacheability and cache configuration, and the comparison of execution unit thread counts and per-thread registers. For example, the profile manager can select hardware and / or software configuration settings that result in the most efficient execution of a graphics workload that meets a specified power budget.

[0248] In one embodiment, once the optimal configuration is selected, the profile manager 2021 applies the optimal configuration parameters to the GPU 2022. For SIMD dispatch width, this simply involves providing only the shaders 219 corresponding to the optimal configuration to the GPU 2022. To address other issues, this may involve applying new cacheability settings, thread management settings, etc., which are applied to the next (multiple) frames of the workload (which are rendered using these new settings). For example, in the case of SIMD dispatch width, the workload is executed using the shader corresponding to the dispatch width that produced the best performance. In another alternative embodiment, the analysis is done implicitly, meaning that the application does not explicitly request the analysis; instead, the analysis is performed transparently to the application (e.g., performed "under the hood" within the user mode driver 2026).

[0249] exist Figure 21 The method according to one embodiment of the present invention is shown in FIG. The method can be implemented on the above system architecture, but is not limited to any specific system architecture.

[0250] If profile data is provided from a cloud service / database or from a previous program execution via a local profile database (determined at 2101), the profile data is retrieved at 2104. If not, at 2102, the profile manager periodically initiates the collection of profile data for the current workload. Alternatively, the application profile requester can instruct the profile manager to collect this data. At 2103, the profile manager (and / or application) collects profile data on the workload, which is stored in the profile database. At 2105, the profile manager uses the profile data to determine optimal system configuration parameters (e.g., a specific number of SIMD lanes for execution). At 2106, the profile manager applies the optimal system configuration parameters to the GPU hardware and / or software configuration. Finally, at 2107, the workload is executed using the optimal system configuration. In one embodiment, the profile manager or application continues to collect profile data and update the database during execution. Thus, changes in the workload can be detected and the profile can be changed as needed to achieve efficient execution.

[0251] Figure 22 Another method according to an embodiment of the present invention is shown, in which the optimization technique is implemented transparently to the application.Again, this method can be implemented on the above architecture, but is not limited to any particular system architecture.

[0252] At 2201, a profile manager periodically collects profile data related to a workload and stores the profile data in a profile database. At 2202, the profile manager uses the profile data to determine optimal system configuration parameters (e.g., GPU configuration) for processing the workload. At 2203, the profile manager applies the optimal configuration parameters to the GPU hardware and / or software configuration. At 2204, the workload is executed using the optimal system configuration.

[0253] In embodiments, the terms "engine," "manager," "module," or "logic" may be implemented in hardware, firmware, software, or any combination thereof. For example, these terms may refer to, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.

[0254] Embodiments of the present invention may include the steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by dedicated hardware components that contain hard-wired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0255] As described herein, instructions may refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have predetermined functions, or software instructions stored in a memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the accompanying figures may be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices use computer-readable media such as non-transitory computer-readable storage media (e.g., magnetic disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transient computer-readable communication media (e.g., electrical, optical, acoustical, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.) to store and communicate code and data (internally and / or over a network with other electronic devices).

[0256] In addition, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transient machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The coupling of this collection of processors to other components is typically via one or more buses and bridges (also referred to as bus controllers). The storage device and the signal carrying the network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on the collection of one or more processors of the electronic device. Of course, one or more parts of the embodiments of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without some of these specific details. In some instances, well-known structures and functions are not described in detail to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the present invention should be determined based on the appended claims.

Claims

1. A device for graphics processing, comprising: a graphics processor for processing graphics commands in response to execution of the application program; as well as a profile store for storing graphics execution profile data associated with execution of one or more graphics workloads on the graphics processor, wherein the graphics execution profile data indicates a number of single instruction multiple data (SIMD) lanes to be allocated for processing the one or more graphics workloads, and wherein the number of SIMD lanes results in a minimum execution time for execution of the one or more graphics workloads by the graphics processor after the one or more graphics workloads are executed using each of a number of available SIMD lanes of the graphics processor; and A profile manager is configured to read the graphics execution profile data when one of the graphics workloads is detected during execution of the application program, and to configure the graphics processor to execute the one or more workloads during a next execution interval according to the graphics execution profile data.

2. The device according to claim 1, wherein The graphics execution profile data includes both hardware and software configuration settings of the graphics processor.

3. The device according to claim 1, wherein The profile manager is configured to generate the graphics execution profile data by monitoring execution of the workload using different hardware and / or software configuration settings.

4. The device according to claim 3, wherein The profile manager is used to select hardware and / or software configuration settings that result in the most efficient execution of the graphics workload that meets a specified power budget.

5. The apparatus of claim 3, further comprising: An application-level profile requester is configured to instruct the profile manager to generate and subsequently use the graphical execution profile data.

6. The apparatus of claim 5, further comprising: An API extension to an existing 3D application programming interface API is used to establish communication between the application-level profile requester and the profile manager.

7. The apparatus of claim 1 , further comprising: A shader compiler is configured to generate a shader in response to the profile manager implementing the graphics execution profile data, the shader being configured to operate according to a profile specified by the graphics execution profile data.

8. The device according to claim 1, wherein The profile storage includes a local profile database to be stored on a local computer system and / or a cloud profile database to be accessed by the profile manager over a network.

9. A method for graphics processing, comprising: processing graphics commands on a graphics processor in response to execution of the application; as well as storing graphics execution profile data associated with execution of one or more graphics workloads on the graphics processor, wherein the graphics execution profile data indicates a number of single instruction multiple data (SIMD) lanes to be allocated for processing the one or more graphics workloads, and wherein the number of SIMD lanes results in a minimum execution time for execution of the one or more graphics workloads by the graphics processor after the one or more graphics workloads are executed using each of a number of available SIMD lanes of the graphics processor; and reading the graphics execution profile data when one of the graphics workloads is detected during execution of the application; and The graphics processor is configured according to the graphics execution profile data to execute the one or more workloads during a next execution interval.

10. The method according to claim 9, wherein The graphics execution profile data includes both hardware and software configuration settings of the graphics processor.

11. The method according to claim 9, wherein The graphics execution profile data is generated by monitoring execution of the workload using different hardware and / or software configurations.

12. The method according to claim 11, wherein Hardware and / or software configuration settings are selected that result in the most efficient execution of the graphics workload that meets a specified power budget.

13. The method of claim 11, further comprising: The profile manager is instructed to generate and subsequently use the graphics execution profile data, the instructions being executed by an application level profile requester.

14. The method according to claim 13, wherein The communication between the application-level profile requester and the profile manager is achieved through an API extension to the existing 3D application programming interface API.

15. The method of claim 9, further comprising: A shader is generated in response to the profile manager implementing the graphics execution profile data, the shader being configured to operate according to a profile specified by the graphics execution profile data.

16. The method according to claim 9, wherein The storing operation includes storing the graphics execution profile data in a local profile database and / or a cloud profile database, the local profile database to be stored on the local computer system and the cloud profile database to be accessed through a network.

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