Fixed-point to floating-point conversion

Abstract

The present application discloses fixed-point to floating-point conversion. Embodiments of instructions, methods for executing the instructions, and resources for executing the instructions are described in detail. For example, in an embodiment, a processor is described, the processor comprising: decoding circuitry for decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry for executing the decoded instruction to: convert data elements from the least significant packed data element positions of an identified packed data source operand from a fixed-point representation to a floating-point representation, store the floating-point representation into the least significant 32-bit packed data element positions of an identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

Description

Background Art

[0001] There are many different ways to express numbers in a computer processor. For example, integers can be represented as integer values. Fractions and other non-integer values ​​can be represented as fixed-point numbers, which have a number of bits for the integer component and a number of bits for the fractional part (e.g., integer.fraction). Another way to represent fractions is to use floating-point numbers, which include bits for the sign, a string of digits (mantissa, fraction, or significand) - the length of which determines the precision of the number, and an exponent that indicates the location of the decimal places. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The present invention is illustrated by way of example and not by way of limitation in the accompanying figures, in which like reference numerals indicate similar elements, and in which:

[0003] Figure 1 An embodiment illustrating a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand;

[0004] Figure 2 An embodiment of a method for processing a conversion instruction performed by a processor is illustrated;

[0005] Figure 3A-3B illustrates a more detailed description of the execution of an instruction to convert an unsigned word from fixed point to floating point;

[0006] Figure 4 An embodiment illustrating a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand;

[0007] Figure 5 An embodiment of a method for processing a conversion instruction performed by a processor is illustrated;

[0008] Figure 6A-6B illustrates a more detailed description of the execution of an instruction to convert a signed word from fixed point to floating point;

[0009] Figure 7 An embodiment illustrating a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand;

[0010] Figure 8 An embodiment of a method for processing a conversion instruction performed by a processor is illustrated;

[0011] Figure 9A-9B illustrates a more detailed description of the execution of an instruction to convert an unsigned doubleword from fixed point to floating point;

[0012] Fig.10An embodiment illustrating a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand;

[0013] Fig.11 An embodiment of a method for processing a conversion instruction performed by a processor is illustrated;

[0014] Figure 12A-12B illustrates a more detailed description of the execution of an instruction to convert a signed doubleword from fixed point to floating point;

[0015] Fig.13 is an embodiment of pseudo code representing the operation of the described instructions;

[0016] Fig.14 illustrates an embodiment of hardware for processing instructions such as the conversion instructions detailed herein;

[0017] Fig.15A illustrates an exemplary instruction format;

[0018] Fig. 15B Illustration from Fig.15A Which fields of constitute the full opcode field and the basic operation field?

[0019] Fig. 15C Illustration from Fig.15A Which fields of constitute the register index field?

[0020] Fig.16 is a block diagram of a register architecture according to one embodiment of the present invention;

[0021] Fig.17A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0022] Fig. 17B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor in accordance with an embodiment of the present invention;

[0023] Figure 18A-18B A block diagram illustrating a more specific exemplary in-order core architecture, which would be one of multiple logic blocks in a chip (including other cores of the same type and / or different types); Fig.19 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention;

[0024] Figure 20-23 is a block diagram of an exemplary computer architecture; and

[0025] Fig.24 is a block diagram comparing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description.

[0027] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0028] Sometimes, it is beneficial to move from one data type (e.g., fixed point) to another data type (e.g., floating point). Detailed description herein is for converting a single fixed-point value from a packed data operand (e.g., single instruction, multiple data (SIMD) or vector register) to a single-precision floating-point value and storing the value in the packed data operand. Specifically, description is made of instructions for converting 16-bit fixed-point numbers to single-precision floating-point numbers (wherein there is no loss of precision) and for converting 32-bit fixed-point numbers to single-precision floating-point numbers (wherein there may be a loss of precision of up to 8 bits) and embodiments of their execution. Depending on implementation, the instructions detailed herein can use packed data register operands of different sizes (e.g., 128-bit, 256-bit, 512-bit registers, etc.) as the source of instructions and / or at least use memory locations for the source of instructions. These instructions are improvements to the computer itself because they provide support for the conversion of specific data elements that have not been previously executed. Specifically, execution of the fixed-point to floating-point instruction causes data elements at least significant packed data element positions of the identified packed data source operand to be converted from fixed-point representation to floating-point representation, the floating-point representation to be stored in 32-bit least significant packed data element positions of the identified packed data destination operand, and all remaining packed data elements of the identified packed data destination operand to be zeroed.

[0029] Figure 1An embodiment of a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand is illustrated. The format of the instruction includes fields for an opcode ("VCTFUW2SS" is the opcode mnemonic in the illustration), a packed data source operand identifier (shown as "source / MEM"), and a packed data destination operand identifier (shown as "destination").

[0030] The packed data source operand field represents a register location of packed data or a memory location of packed data, where the single unsigned word of packed data (16-bit value) is to be converted from fixed point to a single precision floating point value (32-bit floating point value).

[0031] The packed data destination operand field indicates the register location of the packed data in which the result of the conversion (single-precision floating-point value) is to be stored.

[0032] In the illustrated example, the identified source operand 101 has a plurality of unsigned words. The least significant unsigned word is unsigned word 0, and the most significant unsigned word is unsigned word N. The number of unsigned words depends on the size of the identified source operand 101 (e.g., 128 bits, 256 bits, 512 bits, etc.).

[0033] The execution circuit 111 obtains the least significant unsigned word from the identified source 101 and converts the value of the unsigned word into a single precision floating point value. A more detailed execution flow will be described later.

[0034] The single-precision floating-point value is then stored in the least significant data element position in the identified destination operand 121 , and all other data element positions are set to zero.

[0035] Figure 2 An embodiment of a method performed by a processor for processing a conversion instruction is illustrated.

[0036] At 201, an instruction is fetched. For example, a conversion instruction is fetched. The conversion instruction includes fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier. In some embodiments, the instruction is fetched from an instruction cache. In some embodiments, the opcode also indicates the data element size of the identified source operand and whether the data element is signed.

[0037] At 203, the fetched instruction is decoded. For example, the fetched conversion instruction is decoded by a decoding circuit such as described in detail herein.

[0038] At 205, data values ​​associated with the identified source operands of the decoded instructions are retrieved (as needed) and the decoded instructions are dispatched. For example, when the identified source operands are memory operands, data from the indicated memory locations are retrieved.

[0039] The decoded instruction is executed by execution circuitry (hardware) such as described in detail herein at 207. For a convert instruction, execution will cause the execution circuitry to convert the unsigned word data elements of the least significant packed data element positions of the identified packed data source operand from fixed point representation to floating point representation, store the floating point representation into the 32-bit least significant packed data element positions of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0040] In some embodiments, at 209 , the instruction is committed or retired.

[0041] Figure 3A-3B A more detailed description of the execution of an instruction to convert an unsigned word from fixed point to floating point is illustrated. Typically, this is performed by an execution circuit such as that detailed above. In some embodiments, the circuit executes the method as a state machine.

[0042] The data element from the least significant packed data element position of the identified packed data source operand is zero-extended to 32 bits at 301. For example, 16 zeros are concatenated with the value of the least significant packed data element position of the identified packed data source operand so that the most significant 16 bits are zero and the remaining 16 bits are the value already stored in the identified source operand.

[0043] At 303, it is determined whether the zero-extended data element is 0. In other words, was the previous value 0? When this is true, the floating point value with the sign, significand, and exponent is set to 0 at 305 and stored in the least significant data element position of the destination at 331.

[0044] When this is false, the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand is calculated at 307. For example, ABSVALDE[31:0] is calculated.

[0045] At 309, the sign of the floating point representation of the zero-extended data element is set to zero.

[0046] At 311, the leading 1 position of the absolute value of the zero-extended data element of the least significant packed data element position from the identified packed data source operand is determined. For example, a 5-bit value is generated that can indicate any position in a 32-bit number. The leading 1 position is the position of the most significant bit that is 1.

[0047] When the leading 1 position is empty, at 315, the effective value of the floating point representation is set to zero.

[0048] When the leading 1 position is not empty, at 317, 1 is subtracted from the determined leading 1 position to set the most significant bit position (msbPos). For example, msbPos[4:0]←(leadingBit[4:0]-1'b1.

[0049] At 319, it is determined whether the leading 1 position is greater than the decimal number 23. For example, leadingBit[4:0]>5'd23?

[0050] When the leading 1 position is greater than 23, at 321, the least significant bit position (lsbPos) is calculated. For example, lsbPos←leadingBit[4:0]-5'd23, and at 323, the significand is set to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position. For example, fractional[22:0]←absInteger32Val[msbPos:lsbPos].

[0051] When the leading 1 position is not greater than 23, a number of padding bits are calculated at 325. In some embodiments, this is accomplished by subtracting the leading 1 value from 23 (eg, paddingBits←(5'd23-leadingBit[4:0])).

[0052] At 327, the significand is set to the number of padding bits calculated using the absolute value of the zero-extended data element concatenated from zero to the value of the calculated most significant bit position. For example, fractional[22:0]←{absInteger32Val[msbPos:0],(paddingBits)'b0}.

[0053] At 329, three zeros are concatenated with the leading 1 position value and 127 is added to calculate the exponent (eg, exponent[7:0]←8'd127+{3'b0,leadingBit[4:0]}).

[0054] The sign, exponent, and significand are stored in the least significant data element position of the destination at 331. Additionally, the remaining bits are set to zero.

[0055] Figure 4An embodiment of a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand is illustrated. The format of the instruction includes fields for an opcode ("VCTFSW2SS" is the opcode mnemonic in the illustration), a packed data source operand identifier (shown as "source / MEM"), and a packed data destination operand identifier (shown as "destination").

[0056] The packed data source operand field represents a register location of packed data or a memory location of packed data whose single signed word (16-bit value) is to be converted from fixed point to a single precision floating point value (32-bit floating point value).

[0057] The packed data destination operand field indicates the register location of the packed data in which the result of the conversion (single-precision floating-point value) is to be stored.

[0058] In the illustrated example, the identified source operand 401 has a plurality of signed words. The least significant signed word is signed word 0, and the most significant signed word is signed word N. The number of signed words depends on the size of the identified source operand 401 (e.g., 128 bits, 256 bits, 512 bits, etc.).

[0059] The execution circuit 411 obtains the least significant signed word from the identified source 401 and converts the value of the signed word into a single precision floating point value. A more detailed execution flow will be described later.

[0060] The single-precision floating point value is then stored in the least significant data element position in the identified destination operand 421 , and all other data element positions are set to zero.

[0061] Figure 5 An embodiment of a method performed by a processor for processing a conversion instruction is illustrated.

[0062] At 501, an instruction is fetched. For example, a conversion instruction is fetched. The conversion instruction includes fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier. In some embodiments, the instruction is fetched from an instruction cache. In some embodiments, the opcode also indicates the data element size of the identified source operand and whether the data element is signed.

[0063] At 503, the fetched instruction is decoded. For example, the fetched conversion instruction is decoded by a decoding circuit such as described in detail herein.

[0064] At 505, data values ​​associated with the identified source operands of the decoded instruction are retrieved (as needed) and the decoded instruction is dispatched. For example, when the identified source operand is a memory operand, data from the indicated memory location is retrieved.

[0065] The decoded instruction is executed by execution circuitry (hardware) such as described in detail herein at 507. For a convert instruction, execution will cause the execution circuitry to convert the signed word data elements of the least significant packed data element positions of the identified packed data source operand from fixed point representation to floating point representation, store the floating point representation in the least significant 32-bit packed data element positions of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0066] In some embodiments, at 509 , the instruction is committed or retired.

[0067] Figure 6A-6B A more detailed description of the execution of an instruction to convert a signed word from fixed point to floating point is illustrated. Typically, this is performed by an execution circuit such as that detailed above. In some embodiments, the circuit executes the method as a state machine.

[0068] The data element from the least significant packed data element position of the identified packed data source operand is sign-extended to 32 bits at 601. For example, 16 zeros are concatenated with the value of the least significant packed data element position of the identified packed data source operand so that the most significant 16 bits are zero and the remaining 16 bits are the value already stored in the identified source operand.

[0069] At 603, it is determined whether the sign-extended data element is 0. In other words, was the previous value 0? When this is true, the floating point value with the sign, significand, and exponent is set to 0 at 605 and stored in the least significant data element position of the destination at 631.

[0070] When this is false, the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand is calculated at 607. For example, in some embodiments, ABSVALDE[31:0] is calculated by taking the two's complement of the sign-extended value and adding 1.

[0071] At 609 , the sign of the floating point representation of the sign-extended data element is set to one.

[0072] At 611, the leading 1 position of the absolute value of the sign-extended data element of the least significant packed data element position from the identified packed data source operand is determined. For example, a 5-bit value is generated that can indicate any position in a 32-bit number. The leading 1 position is the position of the most significant bit that is 1.

[0073] When the leading 1 position is empty, at 615, the effective value of the floating point representation is set to zero.

[0074] When the leading 1 position is not empty, at 617, 1 is subtracted from the determined leading 1 position to set the most significant bit position (msbPos). For example, msbPos[4:0]←(leadingBit[4:0]-1'b1.

[0075] At 619, it is determined whether the leading 1 position is greater than the decimal number 23. For example, leadingBit[4:0]>5'd23?

[0076] When the leading 1 position is greater than 23, at 621, the least significant bit position (lsbPos) is calculated. For example, lsbPos←leadingBit[4:0]–5'd23, and at 623, the significand is set to the absolute value of the data element sign-extended using the value from the calculated least significant bit position to the calculated most significant bit position. For example, fractional[22:0]←absInteger32Val[msbPos:lsbPos].

[0077] When the leading 1 position is not greater than 23, a number of padding bits are calculated at 625. In some embodiments, this is accomplished by subtracting the leading 1 value from 23 (eg, paddingBits←(5'd23-leadingBit[4:0])).

[0078] At 627, the significand is set to the number of padding bits calculated using the absolute value of the sign-extended data element concatenated from zero to the value of the calculated most significant bit position. For example, fractional[22:0]←{absInteger32Val[msbPos:0],(paddingBits)'b0}.

[0079] At 629, three zeros are concatenated with the leading 1 position value and 127 is added to calculate the exponent (eg, exponent[7:0]←8'd127+{3'b0,leadingBit[4:0]}).

[0080] The sign, exponent, and significand are stored in the least significant data element position of the destination at 631. Additionally, the remaining bits are set to zero.

[0081] Figure 7 An embodiment of a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand is illustrated. The format of the instruction includes fields for an opcode ("VCTFUD2SS" is the opcode mnemonic in the illustration), a packed data source operand identifier (shown as "source / MEM"), and a packed data destination operand identifier (shown as "destination").

[0082] The packed data source operand field represents a register location of packed data or a memory location of packed data, where the single unsigned doubleword (32-bit value) of packed data is to be converted from fixed point to a single-precision floating point value (32-bit floating point value).

[0083] The packed data destination operand field indicates the packed data register location where the result of the conversion (single-precision floating-point value) is to be stored.

[0084] In the illustrated example, the identified source operand 701 has a plurality of unsigned doublewords. The least significant unsigned doubleword is unsigned doubleword 0, and the most significant unsigned doubleword is unsigned doubleword N. The number of unsigned doublewords depends on the size of the identified source operand 701 (e.g., 128 bits, 256 bits, 512 bits, etc.).

[0085] Execution circuit 711 obtains the least significant unsigned doubleword from the identified source 701 and converts the value of the unsigned doubleword to a single precision floating point value. A more detailed execution flow is described later.

[0086] The single-precision floating-point value is then stored in the least significant data element position in the identified destination operand 721 , and all other data element positions are set to zero.

[0087] Figure 8 An embodiment of a method performed by a processor for processing a conversion instruction is illustrated.

[0088] At 801, an instruction is fetched. For example, a conversion instruction is fetched. The conversion instruction includes fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier. In some embodiments, the instruction is fetched from an instruction cache. In some embodiments, the opcode also indicates the data element size of the identified source operand and whether the data element is signed.

[0089] At 803, the fetched instruction is decoded. For example, the fetched conversion instruction is decoded by a decoding circuit such as described in detail herein.

[0090] At 805, data values ​​associated with the identified source operands of the decoded instruction are retrieved (as needed) and the decoded instruction is dispatched. For example, when the identified source operand is a memory operand, data from the indicated memory location is retrieved.

[0091] The decoded instruction is executed by execution circuitry (hardware) such as described in detail herein at 807. For a convert instruction, execution will cause the execution circuitry to convert the unsigned doubleword data elements of the least significant packed data element positions of the identified packed data source operand from fixed point representation to floating point representation, store the floating point representation in the 32-bit least significant packed data element positions of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0092] In some embodiments, at 809 , the instruction is committed or retired.

[0093] Figure 9A-9B A more detailed description of the execution of an instruction to convert an unsigned doubleword from fixed point to floating point is illustrated. Typically, this is performed by an execution circuit such as that detailed above. In some embodiments, the circuit executes the method as a state machine.

[0094] At 901, it is determined whether the data element of the least significant data element position of the identified source is 0. In other words, was the previous value 0? When this is true, the floating point value with the sign, significand, and exponent is set to 0 at 905 and stored in the least significant data element position of the destination at 929.

[0095] When this is false, the absolute value of the data element from the least significant packed data element position of the identified packed data source operand is calculated at 903. For example, ABSVAEDE[31:0] is calculated.

[0096] At 907, the sign of the floating point representation of the least significant data element is set to zero.

[0097] At 909, the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand is determined. For example, a 5-bit value is generated, which can indicate any position in a 32-bit number. The leading 1 position is the position of the most significant bit that is 1.

[0098] When the leading 1 position is empty, at 913, the effective value of the floating point representation is set to zero.

[0099] When the leading 1 position is not empty, 1 is subtracted from the determined leading 1 position to set the most significant bit position (msbPos) at 915. For example, msbPos[4:0]←(leadingBit[4:0]-1'b1).

[0100] At 917, it is determined whether the leading 1 position is greater than the decimal number 23. For example, leadingBit[4:0]>5'd23?

[0101] When the leading 1 position is greater than 23, at 919, the least significant bit position (lsbPos) is calculated. For example, lsbPos←leadingBit[4:0]−5′d23, and at 921, the significand is set to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position. For example, fractional[22:0]←absInteger32Val[msbPos:lsbPos].

[0102] When the leading 1 position is not greater than 23, a number of padding bits are calculated at 923. In some embodiments, this is accomplished by subtracting the leading 1 value from 23 (eg, paddingBits←(5'd23-leadingBit[4:0])).

[0103] At 925, the significand is set to the calculated number of padding bits concatenated using the absolute value of the zero-extended data element from zero to the calculated value of the most significant bit position. For example, fractional[22:0]←{absInteger32Val[msbPos:0],(paddingBits)'b0}.

[0104] At 927, three zeros are concatenated with the leading 1 position value and 127 is added to calculate the exponent (eg, exponent[7:0]←8'd127+{3'b0,leadingBit[4:0]}).

[0105] The sign, exponent, and significand are stored in the least significant data element position of the destination at 929. Additionally, the remaining bits are set to zero.

[0106] Fig.10 An embodiment of a selected portion of the execution of a fixed-point to floating-point conversion instruction having a source operand (register or memory) and a destination operand is illustrated. The format of the instruction includes fields for an opcode ("VCTFUD2SS" is the opcode mnemonic in the illustration), a packed data source operand identifier (shown as "source / MEM"), and a packed data destination operand identifier (shown as "destination").

[0107] The packed data source operand field represents a register location of packed data or a memory location of packed data, where a single signed doubleword (32-bit value) of packed data is to be converted from fixed point to a single-precision floating point value (32-bit floating point value).

[0108] The packed data destination operand field indicates the packed data register location where the result of the conversion (single-precision floating-point value) is to be stored.

[0109] In the illustrated example, the identified source operand 1001 has a plurality of signed doublewords. The least significant signed doubleword is signed doubleword 0, and the most significant signed doubleword is signed doubleword N. The number of signed doublewords depends on the size of the identified source operand 1001 (e.g., 128 bits, 256 bits, 512 bits, etc.).

[0110] Execution circuit 1011 obtains the least significant signed doubleword from identified source 1001 and converts the value of the signed doubleword into a single precision floating point value. A more detailed execution flow will be described later.

[0111] The single-precision floating-point value is then stored in the least significant data element position in the identified destination operand 1021 , and all other data element positions are set to zero.

[0112] Fig.11 An embodiment of a method performed by a processor for processing a conversion instruction is illustrated.

[0113] At 1101, an instruction is fetched. For example, a conversion instruction is fetched. The conversion instruction includes fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier. In some embodiments, the instruction is fetched from an instruction cache. In some embodiments, the opcode also indicates the data element size of the identified source operand and whether the data element is signed.

[0114] At 1103, the fetched instruction is decoded. For example, the fetched conversion instruction is decoded by a decoding circuit such as described in detail herein.

[0115] At 1105, data values ​​associated with the identified source operands of the decoded instruction are retrieved (as needed) and the decoded instruction is dispatched. For example, when the identified source operand is a memory operand, data from the indicated memory location is retrieved.

[0116] The decoded instruction is executed by execution circuitry (hardware) such as described in detail herein at 1107. For a convert instruction, execution will cause the execution circuitry to convert the signed doubleword data elements of the least significant packed data element positions of the identified packed data source operand from fixed-point representation to floating-point representation, store the floating-point representation in the least significant 32-bit packed data element positions of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0117] In some embodiments, at 1109 , the instruction is committed or retired.

[0118] Figure 12A-12B A more detailed description of the execution of an instruction to convert a signed doubleword from fixed point to floating point is illustrated. Typically, this is performed by an execution circuit such as that detailed above. In some embodiments, the circuit executes the method as a state machine.

[0119] At 1201, it is determined whether the data element of the least significant data element position of the identified source is 0. In other words, was the previous value 0? When this is true, the floating point value with the sign, significand, and exponent is set to 0 at 1205 and stored in the least significant data element position of the destination at 1229.

[0120] When this is false, the absolute value of the data element from the least significant packed data element position of the identified packed data source operand is calculated at 1203. For example, ABSVALDE[31:0] is calculated.

[0121] At 1207, the sign of the floating point representation of the least significant data element is set to one.

[0122] At 1209, the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand is determined. For example, a 5-bit value is generated that can indicate any position in a 32-bit number. The leading 1 position is the position of the most significant bit that is 1.

[0123] When the leading 1 position is empty, at 1213, the effective value of the floating point representation is set to zero.

[0124] When the leading 1 position is not empty, 1 is subtracted from the determined leading 1 position to set the most significant bit position (msbPos) at 1215. For example, msbPos[4:0]←(leadingBit[4:0]-1'b1).

[0125] At 1217, it is determined whether the leading 1 position is greater than the decimal number 23. For example, is leadingBit[4:0]>5'd23?

[0126] When the leading 1 position is greater than 23, at 1219, the least significant bit position (lsbPos) is calculated. For example, lsbPos←leadingBit[4:0]–5'd23, and at 1221, the significand is set to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position. For example, fractional[22:0]←absInteger32Val[msbPos:lsbPos].

[0127] When the leading 1 position is not greater than 23, a number of padding bits are calculated at 1223. In some embodiments, this is accomplished by subtracting the leading 1 value from 23 (eg, paddingBits←(5'd23-leadingBit[4:0])).

[0128] At 1225, the significand is set to the calculated number of padding bits concatenated using the absolute value of the zero-extended data element from zero to the calculated value of the most significant bit position. For example, fractional[22:0]←{absInteger32Val[msbPos:0],(paddingBits)'b0}.

[0129] At 1227, three zeros are concatenated with the leading 1 position value, and 127 is added to calculate the exponent (eg, exponent[7:0]←8'd127+{3'b0,leadingBit[4:0]}).

[0130] At 1229, the sign, exponent, and significand are stored in the least significant data element position of the destination. Additionally, the remaining bits are set to zero.

[0131] Fig.13 is an example of pseudo-code representing the operation of the described instructions.

[0132] Fig.14 An embodiment of hardware for processing instructions such as the conversion instructions detailed herein is illustrated.As shown, storage 1403 stores conversion instructions 1401 to be executed.

[0133] Instruction 1401 is received by decode circuit 1405. For example, decode circuit 1405 receives the instruction from fetch logic / circuitry. The instruction includes fields for an opcode, a source identifier, and a destination identifier. In some embodiments, the source and destination are registers, and in other embodiments, one or more of the source and destination are memory locations.

[0134] More detailed embodiments with at least one instruction format will be described later. Decoding circuitry 1405 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating a plurality of micro-operations to be executed by execution circuitry (such as execution circuitry 1409). Decoding circuitry 1405 also decodes instruction prefixes.

[0135] In some embodiments, the register renaming, register allocation and / or scheduling circuitry 1407 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some embodiments); 2) assigning status bits and flags to decoded instructions; and 3) scheduling decoded instructions out of an instruction pool for execution on execution circuitry (e.g., using a reservation station in some embodiments).

[0136] Registers (register file) and / or memory 1408 store data as operands for instructions to be operated on by execution circuitry 1409. Exemplary register types include packed data registers, general purpose registers, and floating point registers.

[0137] The decoded instruction is executed by the execution circuitry 1409. Execution of the decoded instruction causes the execution circuitry to convert the data element of the least significant packed data element position of the identified packed data source operand from a fixed point representation to a floating point representation, store the floating point representation in the least significant 32-bit packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0138] In some embodiments, retirement / writeback circuitry 1411 architecturally commits the destination register to register or memory 1408 and retires the instruction.

[0139] An embodiment of the format of the above instruction is CONVERTOPCODE DST, SRC / MEM. CONVERTOPCODE is the opcode for the instruction. Exemplary opcode mnemonics have been detailed above. DST is a field identifying the destination operand. SRC is a field for source operand identifiers such as registers and / or memory locations. In some embodiments, the operand fields are encoded using VVVV field 1520, MOD R / M 1540, and / or SIB 1550.

[0140] In an embodiment, the encoding of the instruction includes a scale-index-base (SIB) type memory addressing operand that indirectly identifies a plurality of indexed destination locations in a memory (e.g., field 1550). In one embodiment, a SIB type memory operand may include an encoding that identifies a base address register. The contents of the base address register may represent a base address in a memory, and the address of a particular destination location in the memory is calculated based on the base address in the memory. For example, the base address may be the address of the first location in a block of possible destination locations of an extended vector instruction. In one embodiment, a SIB type memory operand may include an encoding that identifies an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of a corresponding destination location within the block of possible destination locations based on the base address. In one embodiment, a SIB type memory operand may include an encoding that specifies a scale factor that is applied to each index value when calculating the corresponding destination address. For example, if a scale factor value of 4 is encoded in a SIB type memory operand, each index value obtained from an element of the index register may be multiplied by 4 and then added to the base address to calculate the destination address.

[0141] In one embodiment, a SIB-type memory operand in the form of vm32{x,y,z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register including individual elements (each of which is a 32-bit index value) are used to specify an array of memory addresses. The vector index register can be a 128-bit (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, a SIB-type memory operand in the form of vm64{x,y,z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register including individual elements (each of which is a 64-bit index value) are used to specify an array of memory addresses. The vector index register may be a 128-bit (eg, XMM) register (vm64x), a 256-bit (eg, YMM) register (vm64y), or a 512-bit (eg, ZMM) register (vm64z).

[0142] Detailed below are exemplary instruction formats, architectures, and systems that can be used for the instructions detailed above. For example, an exemplary pipeline of support instructions including circuits for executing the methods detailed herein is detailed.

[0143] The instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, position of bits) to specify the operation to be performed (opcode) and the operands on which the operation will be performed, etc. Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format can be defined as having different subsets of the fields of the instruction format (the included fields are usually in the same order, but at least some fields have different bit positions because fewer fields are included), and / or defined as having given fields interpreted in different ways. Thus, each instruction of the ISA is expressed using a given instruction format (and if defined, according to a given one of the instruction templates of the instruction format) and includes fields for specifying operations and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, and the specific instruction format includes an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the ADD instruction appears in the instruction stream so that the operand field has specific content for selecting specific operands.

[0144] Example instruction format

[0145] Embodiments of the (multiple) instructions described herein may be embodied in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. Embodiments of the (multiple) instructions may be executed on such systems, architectures, and pipelines, but are not limited to those systems, architectures, and pipelines described in detail.

[0146] VEX instruction format

[0147] VEX encoding allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The use of the VEX prefix provides a three-operand (or more operand) syntax. For example, the previous two-operand instructions performed operations that overwrote the source operands (such as A=A+B). The use of the VEX prefix enables operands to perform non-destructive operations, such as A=B+C.

[0148] Fig.15A An exemplary instruction format is shown, including a VEX prefix 1502 , a real opcode field 1530 , a Mod R / M byte 1540 , a SIB byte 1550 , a displacement field 1562 , and an IMM8 1572 . Fig. 15B Illustration from Fig.15A Which fields constitute the complete opcode field 1574 and the basic operation field 1541. Fig. 15C Illustration from Fig.15A Which fields of constitute the register index field 1544.

[0149] The VEX prefix (bytes 0-2) 1502 is encoded in three-byte form. The first byte is the format field 1590 (VEX byte 0, bits [7:0]), which contains an explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second-third bytes (VEX bytes 1-2) include multiple bit fields that provide special capabilities. Specifically, the REX field 1505 (VEX byte 1, bits [7-5]) consists of a VEX.R bit field (VEX byte 1, bits [7]-R), a VEX.X bit field (VEX byte 1, bits [6]-X), and a VEX.B bit field (VEX byte 1, bits [5]-B). The other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, whereby Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode map field 1515 (VEX byte 1, bits [4:0]–mmmmm) includes content that encodes the implied leading opcode byte. The W field 1564 (VEX byte 2, bits [7]–W) is represented by the notation VEX.W and provides different functions depending on the instruction. The effects of VEX.vvvv 1520 (VEX byte 2, bits [6:3]-vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand and is valid for instructions with two or more source operands, the first source register operand is specified in inverted (1's complement) form; 2) VEX.vvvv encodes the destination register operand, the destination register operand is specified in 1's complement form for certain vector displacements; or 3) VEX.vvvv does not encode any operand, the field is reserved, and should contain 1111b. If the VEX.L 1568 size field (VEX byte 2, bit [2]-L) = 0, it indicates a 128-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 1525 (VEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field 1541.

[0150] The real opcode field 1530 (byte 3) is also referred to as the opcode byte. Portions of the opcode are specified in this field.

[0151] MOD R / M field 1540 (byte 4) includes MOD field 1542 (bits [7-6]), Reg field 1544 (bits [5-3]), and R / M field 1546 (bits [2-0]). The role of Reg field 1544 may include the following: encoding a destination register operand or a source register operand (rrr in Rrrr); or being treated as an opcode extension and not used to encode any instruction operand. The role of R / M field 1546 may include the following: encoding an instruction operand that references a memory address; or encoding a destination register operand or a source register operand.

[0152] Scale, Index, Base (SIB) - The contents of the scale field 1550 (byte 5) include SS 1552 (bits [7-6]) for memory address generation. The contents of SIB.xxx 1554 (bits [5-3]) and SIB.bbb 1556 (bits [2-0]) have been previously referenced for register indexes Xxxx and Bbbb.

[0153] The displacement field 1562 and the immediate field (IMM8) 1572 contain data.

[0154] Exemplary Register Architecture

[0155] Fig.16 is a block diagram of a register architecture 1600 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 512-bit wide vector registers 1610; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-15. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0156] General purpose registers 1625 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0157] A scalar floating point stack register file (x87 stack) 1645 on which an MMX packed integer flat register file 1650 is overlaid - in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set extension; while MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between MMX and XMM registers.

[0158] Alternative embodiments of the present invention may use wider or narrower registers. In addition, alternative embodiments of the present invention may use more, fewer or different register files and registers.

[0159] Exemplary Core Architectures, Processors, and Computer Architectures

[0160] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more special-purpose cores intended primarily for graphics and / or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip, which may include the described CPU (sometimes referred to as (multiple) application cores or (multiple) application processors), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is then described, followed by an exemplary processor and computer architecture. Circuits (units) including exemplary cores, processors, etc. are described in detail herein.

[0161] Exemplary Core Architecture

[0162] In-order and out-of-order core block diagram

[0163] Fig.17A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to various embodiments of the invention. Fig. 17B is a block diagram illustrating an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention. Figure 17A-17B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optional addition of dashed line boxes illustrates the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0164] exist Fig.17A, the processor pipeline 1700 includes a fetch stage 1702, a length decode stage 1704, a decode stage 1706, an allocation stage 1708, a rename stage 1710, a scheduling (also known as dispatch or issue) stage 1712, a register read / memory read stage 1714, an execute stage 1716, a write back / memory write stage 1718, an exception handling stage 1722, and a commit stage 1724.

[0165] Fig. 17B A processor core 1790 is shown, which includes a front end unit 1730, which is coupled to an execution engine unit 1750, and both the front end unit 1730 and the execution engine unit 1750 are coupled to a memory unit 1770. The core 1790 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 1790 can be a special-purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0166] The front end unit 1730 includes a branch prediction unit 1732, which is coupled to an instruction cache unit 1734, which is coupled to an instruction translation lookaside buffer (TLB) 1736, which is coupled to an instruction fetch unit 1738, which is coupled to a decode unit 1740. The decode unit 1740 (or decoder) can decode the instruction and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from the original instruction, or otherwise reflecting the original instruction, or derived from the original instruction as output. The decode unit 1740 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), etc. In one embodiment, the core 1790 includes a microcode ROM or other medium (e.g., in the decode unit 1740, or otherwise within the front end unit 1730) that stores microcode for certain macroinstructions. Decode unit 1740 is coupled to rename / allocator unit 1752 in execution engine unit 1750 .

[0167] The execution engine unit 1750 includes a rename / allocator unit 1752 coupled to a retirement unit 1754 and a set of one or more scheduler units 1756. The scheduler unit(s) 1756 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler unit(s) 1756 are coupled to physical register file(s) units 1758. Each of the physical register file(s) units 1758 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) units 1758 include vector register units and scalar register units. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) units 1758 are overlapped by the retirement unit 1754 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using reorder buffer(s) and retirement register file(s); using future files(s), history buffer(s), retirement register file(s); using register maps and register pools, etc.). The retirement unit 1754 and the physical register file(s) units 1758 are coupled to the execution cluster(s) 1760. The execution cluster(s) 1760 include a set 1762 of one or more execution units and a set 1764 of one or more memory access units. The execution unit 1762 may perform various operations (e.g., shifts, additions, subtractions, multiplications) and may perform on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler unit(s) 1756, physical register file(s) units 1758, and execution cluster(s) 1760 are shown as potentially multiple, as some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines each with its own scheduler unit, physical register file(s) units, and / or execution cluster—and in the case of separate memory access pipelines, certain embodiments are implemented where only the execution cluster of that pipeline has memory access unit(s) 1764). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the rest may be in-order.

[0168] A set of memory access units 1764 is coupled to a memory unit 1770, which includes a data TLB unit 1772, which is coupled to a data cache unit 1774, which is coupled to a second level (L2) cache unit 1776. In an exemplary embodiment, the memory access unit 1764 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1772 in the memory unit 1770. The instruction cache unit 1734 is also coupled to a second level (L2) cache unit 1776 in the memory unit 1770. The L2 cache unit 1776 is coupled to one or more other levels of cache and ultimately to the main memory.

[0169] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement pipeline 1700 as follows: 1) instruction fetch 1738 executes fetch stage 1702 and length decode stage 1704; 2) decode unit 1740 executes decode stage 1706; 3) rename / allocator unit 1752 executes allocation stage 1708 and rename stage 1710; 4) (multiple) scheduler units 1756 execute schedule stage 1712; 5) (multiple) physical register file units 1758 and memory units 1770 execute register read / memory read stage 1714; execution cluster 1760 executes execute stage 1716; 6) memory unit 1770 and (multiple) physical register file units 1758 execute write back / memory write stage 1718; 7) each unit may be involved in exception handling stage 1722; and 8) retirement unit 1754 and (multiple) physical register file units 1758 execute commit stage 1724.

[0170] Core 1790 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California; the ARM instruction set of ARM Holdings, Inc. of Sunnyvale, California (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 1790 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0171] It should be understood that a core may support multithreading (executing a set of two or more operations or threads in parallel), and that this multithreading may be accomplished in a variety of ways, including time-division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-division fetching and decoding and subsequent operations such as Hyper-Threading (Simultaneous Multithreading).

[0172] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 1734 / 1774 and a shared L2 cache unit 1776, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a first level (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0173] Specific Exemplary In-Order Core Architecture

[0174] Figure 18A-18B A block diagram illustrating a more specific exemplary in-order core architecture, which would be one logic block among several logic blocks in a chip (including other cores of the same type and / or different types). Depending on the application, the logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high bandwidth interconnect network (e.g., a ring network).

[0175] Fig.18A 1 is a block diagram of a single processor core and its connection to an on-die interconnect network 1802 and its local subset 1804 of a second level (L2) cache according to an embodiment of the present invention. In one embodiment, the instruction decoder 1800 supports the x86 instruction set with a packed data instruction set extension. The L1 cache 1806 allows low latency access to cache memory into the scalar and vector units. Although in one embodiment (to simplify the design), the scalar unit 1808 and the vector unit 1810 use separate register sets (scalar registers 1812 and vector registers 1814, respectively), and data transferred between these registers is written to memory and then read back from the first level (L1) cache 1806, alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0176] The local subset 1804 of L2 cache is part of the global L2 cache, which is divided into multiple separate local subsets, one local subset for each processor core. Each processor core has a direct access path to its own local subset 1804 of L2 cache. The data read by the processor core is stored in its L2 cache subset 1804, and can be quickly accessed in parallel with other processor cores accessing its own local L2 cache subset. The data written by the processor core is stored in its own L2 cache subset 1804, and is dumped and cleared from other subsets when necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide for each direction.

[0177] Fig.18B According to an embodiment of the present invention Fig.18A An expanded view of a portion of a processor core in FIG. Fig.18B The L1 data cache 1806A portion of the L1 cache 1804 is included, as well as more details about the vector unit 1810 and vector registers 1814. Specifically, the vector unit 1810 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 1828) that executes one or more of integer, single-precision floating point, and double-precision floating point instructions. The VPU supports blending of register inputs through blending unit 1820, supports numerical conversion through numerical conversion units 1822A-B, and supports copying of memory inputs through copy unit 1824.

[0178] Processor with integrated memory controller and graphics device

[0179] Fig.19 is a block diagram of a processor 1900 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention. Fig.19 The solid line box in the figure illustrates a processor 1900 having a single core 1902A, a system agent 1910, a set 1916 of one or more bus controller units, while the optional addition of the dashed line box illustrates an alternative processor 1900 having multiple cores 1902A-N, a set 1914 of one or more integrated memory controller units in the system agent unit 1910, and dedicated logic 1908.

[0180] Thus, different implementations of processor 1900 may include: 1) a CPU, where the dedicated logic 1908 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 1902A-N are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, combinations of the two); 2) a coprocessor, where cores 1902A-N are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 1902A-N are a large number of general purpose in-order cores. Thus, processor 1900 may be a general purpose processor, a coprocessor, or a special purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, and the like. The processor may be implemented on one or more chips. Processor 1900 may be part of one or more substrates, and / or may be implemented on one or more substrates using any of a variety of process technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0181] The memory hierarchy includes one or more cache levels 1904A-N within the core, a set of one or more shared cache units 1906, and external memory (not shown) coupled to a set of integrated memory controller units 1914. The set of shared cache units 1906 may include one or more intermediate levels of cache, such as a second level (L2), a third level (L3), a fourth level (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 1912 interconnects the integrated graphics logic 1908, the set of shared cache units 1906, and the system agent unit 1910 / (multiple) integrated memory controller units 1914, alternative embodiments may interconnect such units using any number of well-known techniques. In one embodiment, coherency is maintained between the one or more cache units 1906 and the cores 1902A-N.

[0182] In some embodiments, one or more of the cores 1902A-N may be multithreaded. The system agent 1910 includes those components that coordinate and operate the cores 1902A-N. The system agent unit 1910 may include, for example, a power control unit (PCU) and a display unit. The PCU may be, or may include, the logic and components required to regulate the power state of the cores 1902A-N and the integrated graphics logic 1908. The display unit is used to drive one or more externally connected displays.

[0183] The cores 1902A-N may be homogeneous or heterogeneous in terms of the architectural instruction set; that is, two or more of the cores 1902A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0184] Exemplary Computer Architecture

[0185] Figure 20-23 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can contain processors and / or other execution logic as disclosed herein are generally suitable.

[0186] Reference now Fig. 20 , shown is a block diagram of a system 2000 according to one embodiment of the present invention. The system 2000 may include one or more processors 2010, 2015, which are coupled to a controller hub 2020. In one embodiment, the controller hub 2020 includes a graphics memory controller hub (GMCH) 2090 and an input / output hub (IOH) 2050 (which may be on separate chips); the GMCH 2090 includes a memory and a graphics controller, to which a memory 2040 and a coprocessor 2045 are coupled; and the IOH 2050 couples an input / output (I / O) device 2060 to the GMCH 2090. Alternatively, one or both of the memory and the graphics controller are integrated within a processor (as described herein), the memory 2040 and the coprocessor 2045 are directly coupled to the processor 2010, and the controller hub 2020 and the IOH 2050 are in a single chip.

[0187] The optional nature of the additional processor 2015 Fig. 20 Each processor 2010 , 2015 may include one or more of the processing cores described herein, and may be a version of processor 1900 .

[0188] The memory 2040 may be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 2020 communicates with the processor(s) 2010, 2015 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 2095.

[0189] In one embodiment, coprocessor 2045 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 2020 may include an integrated graphics accelerator.

[0190] There may be various differences between the physical resources 2010 and 2015 in terms of a range of quality metrics including architectural, microarchitectural, thermal, and power consumption characteristics.

[0191] In one embodiment, the processor 2010 executes instructions that control general types of data processing operations. Embedded within these instructions may be coprocessor instructions. The processor 2010 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 2045. Therefore, the processor 2010 issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 2045 on a coprocessor bus or other interconnect. The coprocessor(s) 2045 accept and execute the received coprocessor instructions.

[0192] See now Fig.21 , shown is a block diagram of a first more specific exemplary system 2100 according to an embodiment of the present invention. Fig.21 As shown in , the multiprocessor system 2100 is a point-to-point interconnect system and includes a first processor 2170 and a second processor 2180 coupled via a point-to-point interconnect 2150. Each of the processors 2170 and 2180 may be a version of the processor 1900. In one embodiment of the present invention, the processors 2170 and 2180 are processors 2010 and 2015, respectively, and the coprocessor 2138 is the coprocessor 2045. In another embodiment, the processors 2170 and 2180 are the processor 2010 and the coprocessor 2045, respectively.

[0193] Processors 2170 and 2180 are shown as including integrated memory controller (IMC) units 2172 and 2182, respectively. Processor 2170 also includes point-to-point (PP) interfaces 2176 and 2178 as part of its bus controller unit; similarly, second processor 2180 includes PP interfaces 2186 and 2188. Processors 2170, 2180 can exchange information via PP interface 2150 using point-to-point (PP) interface circuits 2178, 2188. Fig.21 As shown in FIG. 2 , IMCs 2172 and 2182 couple the processors to respective memories, namely, memory 2132 and memory 2134 , which may be portions of main memory locally attached to the respective processors.

[0194] The processors 2170, 2180 may each exchange information with the chipset 2190 via respective PP interfaces 2152, 2154 using point-to-point interface circuits 2176, 2194, 2186, 2198. The chipset 2190 may optionally exchange information with the coprocessor 2138 via a high performance interface 2192. In one embodiment, the coprocessor 2138 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0195] A shared cache (not shown) may be included in either processor, or external to both processors but connected to the processors via the PP interconnect, such that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0196] Chipset 2190 may be coupled to first bus 2116 via interface 2196. In one embodiment, first bus 2116 may be a peripheral component interconnect (PCI) bus or a bus such as a PCI Express bus or another I / O interconnect bus, but the scope of the present invention is not limited in this regard.

[0197] like Fig.21 As shown in , various I / O devices 2114 may be coupled to the first bus 2116 along with a bus bridge 2118 that couples the first bus 2116 to a second bus 2120. In one embodiment, one or more additional processors 2115 such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor are coupled to the first bus 2116. In one embodiment, the second bus 2120 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 2120 including, for example, a keyboard and / or mouse 2122, communication devices 2127, and a storage unit 2128 such as a disk drive or other mass storage device which may include instructions / code and data 2130. Additionally, an audio I / O 2124 may be coupled to the second bus 2120. Note that other architectures are possible. For example, instead of Fig.21 Instead of a point-to-point architecture, the system may implement a multi-drop bus or other such architecture.

[0198] Reference now Fig. 22 , shown is a block diagram of a second more specific exemplary system 2200 according to an embodiment of the present invention. Fig.21 and 22Similar elements in the same reference numerals are used, and Fig. 22 Omitted Fig.21 to avoid confusion Fig. 22 other aspects.

[0199] Fig. 22 The illustrated processors 2170, 2180 may include integrated memory and I / O control logic ("CL") 2272 and 2282, respectively. Thus, the CL 2272, 2282 includes an integrated memory controller unit and includes I / O control logic. Fig. 22 The illustration shows that not only the memories 2132, 2134 are coupled to the CL 2272, 2282, but also the I / O devices 2214 are coupled to the control logic 2272, 2282. Legacy I / O devices 2215 are coupled to the chipset 2190.

[0200] Reference now Fig.23 , shown is a block diagram of a SoC 2300 according to an embodiment of the present invention. Fig.19 Similar elements in the same figure are marked with similar reference numerals. In addition, the dashed boxes are optional features on more advanced SoCs. Fig.23 , the interconnect unit(s) 2302 are coupled to: an application processor 2310, which includes a set of one or more cores 1902A-N, cache units 1904A-N, and shared cache unit(s) 1906; a system agent unit 1910; a bus controller unit(s) 1916; an integrated memory controller unit(s) 1914; a set of one or more coprocessors 2320, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 2330; a direct memory access (DMA) unit 2332; and a display unit 2340 for coupling to one or more external displays. In one embodiment, the coprocessor(s) 2320 include a special purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, or an embedded processor, among others.

[0201] The various embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0202] Program code (such as Fig.21The code 2130 illustrated in FIG. 21 is applied to the input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0203] The program code can be implemented with a high-level process-oriented programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented with assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0204] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, which represent various logic in a processor, which when read by a machine causes the machine to fabricate logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into a manufacturing machine that actually manufactures the logic or processor.

[0205] Such machine-readable storage media may include, but are not limited to, a non-transitory, tangible arrangement of an article manufactured or formed by a machine or apparatus, including storage media such as a hard disk; any other type of disk, including a floppy disk, an optical disk, a compact disk-read only memory (CD-ROM), a compact disk-rewritable (CD-RW), and a magneto-optical disk; semiconductor devices, such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase change memory (PCM); a magnetic card or an optical card; or any other type of medium suitable for storing electronic instructions.

[0206] Therefore, embodiments of the present invention also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. These embodiments are also referred to as program products.

[0207] Simulation (including binary conversion, code deformation, etc.)

[0208] In some cases, the instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can convert (e.g., using static binary conversion, dynamic binary conversion including dynamic compilation), deform, simulate or otherwise convert instructions into one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, outside the processor, or partially on the processor and partially outside the processor.

[0209] Fig.24 1 is a block diagram of a software instruction converter that converts binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Fig.24 A program in a high-level language 2402 is shown to be compilable using a first compiler 2404 to generate a first binary code (e.g., x86) 2406 that can be natively executed by a processor 2416 having at least one first instruction set core. In some embodiments, the processor 2416 having at least one first instruction set core represents any processor that performs substantially the same functionality as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of the Intel x86 instruction set core, or 2) an object code version of an application or other software that is targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 2404 represents a compiler that can be operated to generate binary code 2406 (e.g., object code) of a first instruction set that can be executed on a processor 2416 having at least one first instruction set core with or without additional linking processing. Similarly, Fig.24It is shown that a program in high-level language 2402 can be compiled using an alternative instruction set compiler 2408 to generate an alternative instruction set binary code 2410 that can be natively executed by a processor 2414 that does not have at least one first instruction set core (e.g., a processor that has a core that executes the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California, and / or executes the ARM instruction set of ARM Holdings, Inc. of Sunnyvale, California). The instruction converter 2412 is used to convert the first binary code 2406 into code that can be natively executed by the processor 2414 that does not have the first instruction set core. The converted code is unlikely to be the same as the alternative instruction set binary code 2410 because an instruction converter that can do so is difficult to manufacture; however, the converted code will complete the general operation and be composed of instructions from the alternative instruction set. Therefore, the instruction converter 2412 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 2406 through simulation, emulation, or any other process.

[0210] The following paragraphs detail examples of embodiments.

[0211] Example 1. A processor comprising: decoding circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to: convert data elements from least significant packed data element positions of an identified packed data source operand from fixed point representation to floating point representation, store the floating point representation in 32-bit least significant packed data element positions of an identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0212] Example 2. The processor of Example 1, wherein the opcode is used to indicate that the data elements of the identified packed data source are unsigned and is used to indicate the size of the packed data elements of the identified packed data source.

[0213] Example 3. The processor of Example 2, wherein the size of the packed data elements of the identified packed data source is 16 bits, and the execution circuit is further configured to: zero-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty, Subtracting 1 from the determined leading 1 position to set the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data element zero-extended using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0214] Example 4. The processor of Example 2, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the execution circuit is further configured to: calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; and when the leading 1 position is not empty, subtract 1 from the determined leading 1 position to set the highest significant bit positions; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0215] Example 5. The processor of Example 1, wherein the opcode is used to indicate that the data elements of the identified packed data source are signed and is used to indicate the size of the packed data elements of the identified packed data source.

[0216] Example 6. The processor of Example 5, wherein the size of the packed data element of the identified packed data source is 16 bits, and the execution circuit is further configured to: sign-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 1; determine the leading 1 position of the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty , subtracting 1 from the determined leading 1 position to set the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the sign-extended data element using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the concatenation of the absolute value of the sign-extended data element using the value from zero to the calculated most significant bit position; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0217] Example 7. The processor of Example 5, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the execution circuit is further configured to: calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 1; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; set the fractional value of the floating point representation to 0 when the leading 1 position is empty; and subtract 1 from the determined leading 1 position to set the highest leading 1 position to 0 when the leading 1 position is not empty. significant bit positions; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0218] Example 8. A method comprising: decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and executing the decoded instruction to: convert data elements from a least significant packed data element position of an identified packed data source operand from a fixed point representation to a floating point representation, store the floating point representation in a 32-bit least significant packed data element position of an identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0219] Example 9. The method of Example 8, wherein the opcode is used to indicate that the data elements of the identified packed data source are unsigned and is used to indicate the size of the packed data elements of the identified packed data source.

[0220] Example 10. The method of Example 9, wherein the size of the packed data element of the identified packed data source is 16 bits, and the performing step is further used to: zero-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty , subtracting 1 from the determined leading 1 position to set the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data element zero-extended using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0221] Example 11. The method of Example 9, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the performing step is further used to: calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty, subtract 1 from the determined leading 1 position to set the most significant the leading 1 position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, the exponent, and the fraction.

[0222] Example 12. The method of Example 8, wherein the opcode is used to indicate that the data elements of the identified packed data source are signed and to identify the size of the packed data elements of the identified packed data source.

[0223] Example 13. The method of Example 12, wherein the size of the packed data elements of the identified packed data source is 16 bits, and the performing steps are further used to: sign-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 1; determine the leading 1 position of the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty , subtracting 1 from the determined leading 1 position to set the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the sign-extended data element using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the concatenation of the absolute value of the sign-extended data element using the value from zero to the calculated most significant bit position; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0224] Example 14. The method of Example 12, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the performing step is further used to: calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating-point representation to 1; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating-point representation to 0; when the leading 1 position is not empty, subtract 1 from the determined leading 1 position to set the highest significant bit positions; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0225] Example 15. A non-transitory machine-readable medium storing instructions for causing a processor to perform a method comprising: decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and executing the decoded instruction to: convert data elements from a least significant packed data element position of an identified packed data source operand from a fixed-point representation to a floating-point representation, store the floating-point representation in a 32-bit least significant packed data element position of an identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0226] Example 16. The non-transitory machine readable medium of Example 15, wherein the opcode is used to indicate that the data elements of the identified packed data source are unsigned and is used to indicate the size of the packed data elements of the identified packed data source.

[0227] Example 17. A non-transitory machine-readable medium as in Example 16, wherein the size of the packed data elements of the identified packed data source is 16 bits, and the execution steps are further used to: zero-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating-point representation to 0; determine the leading 1 position of the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating-point representation to 0; if the leading 1 position is not empty, When the leading 1 position is empty, subtract 1 from the determined leading 1 position to set the position of the most significant bit; determine when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculate the least significant bit position and set the fraction to the absolute value of the data element extended by zero using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculate a plurality of padding bits and set the fraction to the absolute value of the data element extended by zero using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenate three zeros with the leading 1 position value and add 127 to calculate an exponent; store the sign, exponent, and fraction.

[0228] Example 18. The non-transitory machine-readable medium of Example 16, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the execution steps are further used to: calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty, subtract 1 from the determined leading 1 position to set The method of claim 14, wherein the method comprises: setting the position of the most significant bit; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the position of the least significant bit and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, the exponent, and the fraction.

[0229] Example 19. The non-transitory machine-readable medium of Example 15, wherein the opcode is used to indicate that the data elements of the identified packed data source are signed and is used to indicate the size of the packed data elements of the identified packed data source.

[0230] Example 20. The non-transitory machine-readable medium of Example 19, wherein the size of the packed data elements of the identified packed data source is 16 bits, and the execution steps are further used to: sign-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating-point representation to 1; determine the leading 1 position of the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating-point representation to 0; if the leading 1 position is not empty When the leading 1 position is empty, subtract 1 from the determined leading 1 position to set the position of the most significant bit; determine when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculate the least significant bit position and set the fraction to the absolute value of the sign-extended data element using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculate a plurality of padding bits and set the fraction to the concatenation of the absolute value of the sign-extended data element using the value from zero to the calculated most significant bit position; and concatenate three zeros with the leading 1 position value and add 127 to calculate an exponent; store the sign, exponent, and fraction.

[0231] Example 21. The non-transitory machine-readable medium of Example 19, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the execution steps are further used to: calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 1; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty, subtract 1 from the determined leading 1 position to setting the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data element using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data element using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0232] Example 22. An apparatus comprising: decoding means for decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and executing means for executing the decoded instruction to: convert data elements from least significant packed data element positions of an identified packed data source operand from fixed point representation to floating point representation, store the floating point representation in 32-bit least significant packed data element positions of an identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

[0233] Example 23. The apparatus of Example 22, wherein the opcode is used to indicate that data elements of the identified packed data source are unsigned and is used to indicate a size of the packed data elements of the identified packed data source.

[0234] Example 24. The apparatus of Example 23, wherein the size of the packed data elements of the identified packed data source is 16 bits, and the execution device is further configured to: zero-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty, Subtracting 1 from the determined leading 1 position to set the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data element zero-extended using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0235] Example 25. The apparatus of Example 23, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the execution device is further configured to: calculate the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 0; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; and when the leading 1 position is not empty, subtract 1 from the determined leading 1 position to set the maximum significant bit positions; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0236] Example 26. The apparatus of Example 22, wherein the opcode is used to indicate that the data elements of the identified packed data source are signed and to indicate the size of the packed data elements of the identified packed data source.

[0237] Example 27. The apparatus of Example 26, wherein the size of the packed data elements of the identified packed data source is 16 bits, and the execution device is further configured to: sign-extend the data element from the least significant packed data element position of the identified packed data source operand to 32 bits; calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 1; determine the leading 1 position of the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; when the leading 1 position is empty, set the fractional value of the floating point representation to 0; when the leading 1 position is not empty , subtracting 1 from the determined leading 1 position to set the most significant bit position; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the sign-extended data element using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the concatenation of the absolute value of the sign-extended data element using the value from zero to the calculated most significant bit position; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

[0238] Example 28. The apparatus of Example 26, wherein the size of the packed data elements of the identified packed data source is 32 bits, and the execution device is further configured to: calculate the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand; set the sign of the floating point representation to 1; determine the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand; set the fractional value of the floating point representation to 0 when the leading 1 position is empty; and subtract 1 from the determined leading 1 position to set the highest leading 1 position to 0 when the leading 1 position is not empty. significant bit positions; determining when the leading 1 position is greater than 23; when the leading 1 position is greater than 23, calculating the least significant bit position and setting the fraction to the absolute value of the data elements using the value from the calculated least significant bit position to the calculated most significant bit position; and when the leading 1 position is not greater than 23, calculating a plurality of padding bits and setting the fraction to the absolute value of the data elements using the value from zero to the calculated most significant bit position concatenated with the calculated plurality of padding bits; and concatenating three zeros with the leading 1 position value and adding 127 to calculate an exponent; storing the sign, exponent, and fraction.

Claims

1. A processor, comprising: decoding circuitry for decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; as well as Execution circuitry for executing the decoded instruction to: convert data elements from least significant packed data element positions of an identified packed data source operand from fixed point representation to floating point representation, store the floating point representations in 32-bit least significant packed data element positions of an identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

2. The processor according to claim 1, wherein: The opcode is used to indicate that the data elements of the identified packed data source are unsigned and is used to indicate the size of the packed data elements of the identified packed data source.

3. The processor according to claim 2, wherein: The size of the packed data elements of the identified packed data source is 16 bits, and the execution circuit is further configured to: zero-extends the data element from the least significant packed data element position of the identified packed data source operand to 32 bits, computing the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 0, determining a leading 1 position of the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and setting the score to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position, and When the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the fraction to a number of padding bits calculated by concatenating the absolute value of the zero-extended data element from zero to the value of the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

4. The processor according to claim 2, wherein: The size of the packed data elements of the identified packed data source is 32 bits, and the execution circuit is further configured to: computing the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 0, determining the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and sets the score to the absolute value of the data element using the value from the calculated least significant bit position to the calculated most significant bit position, and When the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the score to a number of padding bits calculated using the absolute value of the data element concatenated with the value from zero to the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

5. The processor according to claim 1, wherein: The opcode is used to indicate that the data elements of the identified packed data source are signed and to indicate the size of the packed data elements of the identified packed data source.

6. The processor according to claim 5, wherein: The size of the packed data elements of the identified packed data source is 16 bits, and the execution circuit is further configured to: sign-extends the data element from the least significant packed data element position of the identified packed data source operand to 32 bits, computes the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 1, determining the leading 1 position of the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and Set the fraction to the absolute value of the data element sign-extended using the values ​​from the calculated least significant bit position to the calculated most significant bit position, and when the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the fraction to the number of padding bits calculated by concatenating the absolute value of the sign-extended data element using values ​​from zero to the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

7. The processor according to claim 5, wherein: The size of the packed data elements of the identified packed data source is 32 bits, and the execution circuit is further configured to: computes the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 1, determining the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and sets the score to the absolute value of the data element using the value from the calculated least significant bit position to the calculated most significant bit position, and When the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the score to a number of padding bits calculated using the absolute value of the data element concatenated with the value from zero to the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

8. A method for instruction processing, comprising: decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; as well as The decoded instruction is executed to convert data elements from the least significant packed data element position of the identified packed data source operand from a fixed point representation to a floating point representation, store the floating point representation in the least significant 32-bit packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

9. The method according to claim 8, characterized in that The opcode is used to indicate that the data elements of the identified packed data source are unsigned and is used to indicate the size of the packed data elements of the identified packed data source.

10. The method according to claim 9, characterized in that The size of the packed data elements of the identified packed data source is 16 bits, and the performing step is further for: zero-extends the data element from the least significant packed data element position of the identified packed data source operand to 32 bits, computing the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 0, determining a leading 1 position of the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and setting the score to the absolute value of the data element zero-extended using the value from the calculated least significant bit position to the calculated most significant bit position, and When the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the fraction to a number of padding bits calculated by concatenating the absolute value of the zero-extended data element from zero to the value of the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

11. The method according to claim 9, characterized in that The size of the packed data elements of the identified packed data source is 32 bits, and the performing step is further used to: computing the absolute value of the zero-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 0, determining the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and sets the score to the absolute value of the data element using the value from the calculated least significant bit position to the calculated most significant bit position, and When the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the score to a number of padding bits calculated using the absolute value of the data element concatenated with the value from zero to the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

12. The method according to claim 8, characterized in that The opcode is used to indicate that the data elements of the identified packed data source are signed and to indicate the size of the packed data elements of the identified packed data source.

13. The method according to claim 12, characterized in that The size of the packed data elements of the identified packed data source is 16 bits, and the performing step is further for: sign-extends the data element from the least significant packed data element position of the identified packed data source operand to 32 bits, computes the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 1, determining the leading 1 position of the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and Set the fraction to the absolute value of the data element sign-extended using the values ​​from the calculated least significant bit position to the calculated most significant bit position, and when the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the fraction to the number of padding bits calculated by concatenating the absolute value of the sign-extended data element using values ​​from zero to the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

14. The method according to claim 12, characterized in that The size of the packed data elements of the identified packed data source is 32 bits, and the performing step is further used to: computes the absolute value of the sign-extended data element from the least significant packed data element position of the identified packed data source operand, sets the sign of the floating point representation to 1, determining the leading 1 position of the absolute value of the data element from the least significant packed data element position of the identified packed data source operand, When the leading 1 position is empty, the fractional value represented by the floating point is set to 0. When the leading 1 position is not empty, subtracting 1 from the determined leading 1 position to set the position of the most significant bit, Determine when the leading 1 position is greater than 23, When the leading 1 position is greater than 23, Calculate the least significant bit position, and sets the score to the absolute value of the data element using the value from the calculated least significant bit position to the calculated most significant bit position, and When the leading 1 position is not greater than 23, Calculate a number of padding bits, and setting the score to a number of padding bits calculated using the absolute value of the data element concatenated with the value from zero to the calculated most significant bit position, and Concatenate three zeros with the leading 1 position value and add 127 to calculate the exponent, The sign, the exponent, and the fraction are stored.

15. A non-transitory machine-readable medium storing instructions for causing a processor to perform a method comprising: decoding an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; as well as The decoded instruction is executed to convert data elements from the least significant packed data element position of the identified packed data source operand from a fixed point representation to a floating point representation, store the floating point representation in the least significant 32-bit packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand.

Images