Semiconductor device

Abstract

A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. The wiring has a main wiring unit extending in an "X" direction in a cross-sectional view and a plurality of sub wiring units extending in a "Y" direction, and is supplied with a power supply potential. The wiring layer has a wiring. The wiring has a main wiring unit extending in an "X" direction in a cross-sectional view and a plurality of sub wiring units extending in a "Y" direction, and is supplied with a reference potential. The sub wiring units and the sub wiring units have end units and end units on a side opposite to the end units, and are alternately arranged between the main wiring units in the "X" direction. A via wiring is coupled to the end units.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2017-199633, filed on October 13, 2017, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device, and to an effective technique applicable to the semiconductor device, said semiconductor device including a power supply circuit for driving circuitry operating at high speeds. Background Technology

[0004] For example, Japanese Unexamined Patent Application Publication No. 2011-165858 discloses a semiconductor device in which a semiconductor chip mounted on a wiring substrate is electrically coupled to the wiring substrate via multiple wires. Japanese Unexamined Patent Application Publication No. 2011-165858 also discloses that parasitic inductance can be reduced by arranging multiple power pads for supplying power between comb-shaped grounding pads for supplying ground voltage in a plan view. Summary of the Invention

[0005] Because semiconductor chips exhibit high performance, techniques are needed to reduce component size, achieve high-speed circuit operation, or reduce power consumption by lowering circuit drive voltages. The inventors have developed techniques to improve the performance of semiconductor devices. As part of this, noise reduction in circuits supplying power voltage to semiconductor chips mounted on wiring substrates has been investigated, and areas for improvement have been identified.

[0006] For example, the spacing between the ends of a semiconductor chip becomes narrower, while the spacing between vias in the wiring substrate on which the semiconductor chip is mounted cannot be narrowed sufficiently. In this case, a portion with a narrow wiring width is inserted into the wiring path used to couple the ends of the semiconductor chip and the vias of the wiring substrate. The resistance is high in the portion with the narrow wiring width.

[0007] Any other purpose and new features will be apparent from the detailed description in this specification and the accompanying drawings.

[0008] The semiconductor device according to an embodiment has a wiring substrate on which a semiconductor chip is mounted. A first wiring layer of the wiring substrate has a first wiring. The first wiring has a first main wiring unit extending along a first direction and a plurality of sub-wiring units extending along a second direction in a plan view, and is provided with a first potential. The first wiring has a second wiring in a cross-sectional view, the second wiring having a second main wiring unit extending along the first direction and a plurality of second sub-wiring units extending along the second direction, and being provided with a second potential. The first and second sub-wiring units have a first end unit and a second end unit on the side opposite to the first end unit, and are arranged alternately along the first direction. Vias are coupled to the first and second end units.

[0009] According to the embodiments, the performance of semiconductor devices can be improved. Attached Figure Description

[0010] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment.

[0011] Figure 2 yes Figure 1 The bottom view of the semiconductor device shown.

[0012] Figure 3 yes Figure 1 The top view of the semiconductor device shown.

[0013] Figure 4 It is along Figure 1 The cross-sectional view taken from line AA.

[0014] Figure 5 It is shown schematically. Figure 4 An illustrative diagram illustrating an example of the circuit configuration of a semiconductor chip.

[0015] Figure 6 yes Figure 1 The diagram shows a plan view of the surface (electrode arrangement surface) of the semiconductor chip.

[0016] Figure 7 It is shown in Figure 3 The diagram shows a plan view of the wiring substrate, excluding the semiconductor chip and the bottom filled with resin.

[0017] Figure 8 It is shown in Figure 7 A plan view of a wiring layer layout example on a wiring substrate, excluding the topmost insulating film.

[0018] Figure 9 It is shown Figure 8 An enlarged plan view of the central part.

[0019] Figure 10 It is shown in Figure 7 A plan view of an example layout of a wiring layer as a second layer on a wiring substrate.

[0020] Figure 11 It is shown Figure 10 wiring layer, and Figure 9 The enlarged planar view of the central part of the overlapping planar surfaces shown.

[0021] Figure 12 yes Figure 11 Enlarged cross-sectional view of line AA.

[0022] Figure 13 yes Figure 11 Enlarged cross-sectional view of the BB line.

[0023] Figure 14 yes Figure 11 Enlarged cross-sectional view of the CC line.

[0024] Figure 15 It is shown Figure 11 The modified enlarged plan view.

[0025] Figure 16 It is only shown for supply Figure 11 The diagram shows the conductor pattern of the power source and an enlarged plan view of the conductor pattern used to supply the reference potential.

[0026] Figure 17 It is shown in Figure 7 The diagram shows a layout example of a wiring layer as the third layer on a wiring substrate.

[0027] Figure 18 Is Figure 17 The wiring layer shown is with Figure 9 Enlarged plan view of the corresponding location.

[0028] Figure 19 It is shown in Figure 9 An enlarged plan view of an example layout of a wiring layer as the fourth layer on a wiring substrate.

[0029] Figure 20 It is shown in Figure 9 An enlarged plan view of an example layout of the wiring layer as the fifth layer on the wiring substrate shown.

[0030] Figure 21 It is shown in Figure 9 An enlarged plan view of an example layout of the wiring layer as the sixth layer on the wiring substrate shown.

[0031] Figure 22 It is based on Figure 4 A modified cross-sectional view of a semiconductor device.

[0032] Figure 23 It is shown in Figure 22 An enlarged plan view of an example layout of a wiring layer as the first layer on a wiring substrate.

[0033] Figure 24 It is shown in Figure 23 An enlarged plan view of an example layout of a wiring layer as the second layer on a wiring substrate. Detailed Implementation

[0034] (Description format / basic terminology / instructions for use in this application)

[0035] In the following preferred embodiments of this application, for convenience, they will be described in multiple parts or preferred embodiments as necessary; however, unless otherwise stated, they are not independent of each other. Whether before or after the description, each part of a single example, i.e., one part, is a detail or overall modification of another part. In principle, the same components are not described repeatedly. Unless explicitly stated as not permissible, theoretically limited in number, or clearly not in the context, the constituent elements in the preferred embodiments are not essential.

[0036] In the preferred embodiments below, even when some material or composition is described as “X formed of A,” any element other than “A” is not excluded unless explicitly specified or clearly not otherwise in the context. For example, it means that the component is “X comprising A as a major component.” For example, when it implies “silicon component,” it is not limited to pure silicon. Needless to say, it can be a component comprising a multi-component alloy comprising a SiGe (silicon / germanium) alloy or other silicon as a major component or any other additive. When it implies “gold plating,” “Cu layer,” or “nickel plating,” it is not limited to its pure material and can also be a component comprising gold, copper, or nickel as a major component, unless explicitly specified otherwise.

[0037] When referencing a specified number of values ​​or elements, quantities greater than or less than the specified number may be used unless explicitly stated not to, theoretically limited in number, or clearly not in the context.

[0038] In the illustrations of the preferred embodiments, the same or similar parts are identified by similar symbols or reference numerals, and therefore will not be described repeatedly.

[0039] In the accompanying illustrations, shading may not be provided even in cross-sections to avoid cumbersome operations or when a clear distinction from the gap is evident. In such cases, background outlines may be omitted even when the hole closure is shown in a plane, as is obvious from the description. Furthermore, shading or dot patterns may be provided to clearly indicate the absence of a gap even without a cross-section, or to clearly indicate the boundaries of an area.

[0040] Semiconductor Devices

[0041] Will use Figures 1 to 4 A schematic configuration of the semiconductor device PKG1 according to a preferred embodiment is described. Figure 1 This is a perspective view showing a semiconductor device according to this embodiment. Figure 2 yes Figure 1 The bottom view of the semiconductor device shown. Figure 3 yes Figure 1 The top view of the semiconductor device shown. Figure 4 It is along Figure 1 The cross-sectional view taken from line AA. For ease of explanation, Figures 1 to 4 A small number of terminals are shown. For ease of explanation, Figure 4 It shows a ratio Figure 2 The example shown has a smaller number of external terminals 30. Although not shown, but in addition to Figures 1 to 4 In addition to the example, the number of terminals (terminal 2PD, connection plate 2LD, external terminal 30) can be modified in various ways.

[0042] like Figure 1 As shown, the semiconductor device PKG1 in this embodiment has a semiconductor chip 10 and a wiring substrate 20. The wiring substrate 20 has an upper surface (surface, main surface, chip mounting surface) 20t on which the semiconductor chip 10 is mounted.

[0043] like Figure 4 As shown, the semiconductor chip 10 has a surface (main surface, upper surface) 10t, a back surface (main surface, lower surface) 10b on the side opposite to the surface 10t, and a side surface 10s located between the surface 10t and the back surface 10b. The semiconductor chip 10 has a rectangular shape, and its planar area in the planar view is smaller than the planar area of ​​the wiring substrate 20, as shown. Figure 3 As shown. In Figure 3 In the example shown, the semiconductor chip 10 is mounted in the central portion of the upper surface 20t of the wiring substrate 20 such that the four side surfaces 10s extend along the four side surfaces 20s of the wiring substrate 20, respectively.

[0044] like Figure 4As shown, multiple electrodes (chip electrodes, electrode pads, and electrode portions) 1PD are arranged on the surface 10t of the semiconductor chip 10. In this embodiment, the electrodes 1PD are arranged in a matrix (array) on the surface 10t of the semiconductor chip 10. Even if the number of electrodes on the semiconductor chip 10 increases, the matrix arrangement of the electrodes 1PD, which serve as external input / output terminals of the semiconductor chip 10, can suppress the increase in planar area. In the planar view, when the electrodes 1PD for power supply are arranged in the central portion of the semiconductor chip 10, the power supply path of the core circuit formed in the central portion of the semiconductor chip 10 can be shortened.

[0045] The surface 10t of the semiconductor chip 10 faces the upper surface 20t of the wiring substrate 20. In this manner, the semiconductor chip 10 is mounted on the wiring substrate 20 such that the surface 10t, which serves as the electrode forming surface of the semiconductor chip 10, faces the upper surface 20t, which serves as the chip mounting surface of the wiring substrate 20. This mounting system is referred to as a face-down mounting system or a flip-chip coupling system.

[0046] In the case of a flip-chip coupling system, coupling is achieved between an electrode 1PD disposed on the surface 10t of the semiconductor chip 10 and a terminal 2PD disposed on the upper surface 20t of the wiring substrate 20 via a bump electrode SB. For example... Figure 4 As shown, the bump electrode SB is coupled to the electrode 1PD, while the electrode 1PD of the semiconductor chip 10 and the terminal 2PD of the wiring substrate 20 are electrically coupled through the bump electrode SB.

[0047] The bump electrode SB is a metallic component formed to protrude above the surface 10t of the semiconductor chip 10. In this embodiment, the bump electrode SB is a so-called solder bump, wherein the solder component is stacked on the electrode 1PD by an under-bump metal film. The under-bump metal film is, for example, a laminated film in which titanium (Ti), copper (Cu), and nickel (Ni) are sequentially stacked with the electrode 1PD from the coupling surface side (in which case a gold (Au) film may be further formed on the nickel film). The solder component used to form the solder bump is formed from a so-called lead-free solder that is substantially free of Pb or a Sn-Pb solder component that includes lead (Pb). Examples of the lead-free solder are tin-only (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), or tin-copper (Sn-Cu). Lead-free solder represents a solder in which the lead content is 0.1 wt% or less. This content is based on the RoHS (Restriction of Hazardous Substances) directive.

[0048] When the semiconductor chip 10 is mounted on the wiring substrate 20, solder bumps are pre-formed on electrodes 1PD and terminals 2PD, and then heat treatment (reflow process) is performed while the solder bumps are in contact with each other. In doing so, the solder bumps bond together to form bump electrodes SB. As a modification of this embodiment, columnar bumps can be used as each bump electrode SB. The columnar bumps are formed by forming a solder film on the tip surface of a conductor pillar made of copper (Cu) or nickel (Ni).

[0049] Although not shown, as a modification of this embodiment, the back surface 10b of the semiconductor chip 10 may be opposite the chip mounting surface (upper surface 20t) of the wiring substrate 20 (referred to as a face-up packaging system). In this case, the electrodes 1PD of the semiconductor chip 10 are arranged on the periphery of the surface 10t. The electrodes 1PD of the semiconductor chip 10 are electrically coupled to the terminals 2PD of the wiring substrate 20 via wiring (not shown). Similar to this embodiment, when the semiconductor chip 10 is mounted on the wiring substrate 20 using a face-down system, the arrangement density of electrodes 1PD per unit area can be increased. Similar to this embodiment, when the electrodes 1PD of the semiconductor chip 10 and the wiring substrate 20 are electrically coupled via bump electrodes SB, the impedance of the transmission path between the electrodes 1PD and the terminals 2PD can be lower than that of a coupling system with such wiring.

[0050] Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip 10 (specifically, the semiconductor element formation region disposed on the element formation surface of the semiconductor substrate serves as the substrate material of the semiconductor chip 10). The electrode 1PD is electrically coupled to the semiconductor element (specifically, between the surface 10t and the semiconductor element formation region not shown) through wiring (not shown) formed on a wiring layer disposed inside the semiconductor chip 10.

[0051] The semiconductor chip 10 (specifically, the substrate material of the semiconductor chip 10) is formed of, for example, silicon (Si). An insulating film covering the substrate material and wiring of the semiconductor chip 10 is formed on the surface 10t. The surface of each electrode 1PD is exposed from the insulating film through an opening formed in the insulating film. In this embodiment, the electrode 1PD is formed of a metal, such as aluminum (Al) or copper (Cu).

[0052] like Figure 4 As shown, the wiring substrate 20 on which the semiconductor chip 10 is mounted has an upper surface 20t on which the semiconductor chip 10 is formed, a lower surface (surface, main surface, mounting surface) 20b on the side opposite to the upper surface 20t, and a plurality of side surfaces 20s arranged between the upper surface 20t and the lower surface 20b (see Figures 1 to 3 ).like Figure 2As shown, the wiring substrate 20 has a rectangular shape in the plan view.

[0053] The wiring substrate 20 has multiple wiring layers for electrically coupling the terminals 2PD on the upper surface 20t, which serves as the chip mounting surface, and the connection pads 2LD on the lower surface 20b, which also serves as the mounting surface. Figure 4 In the example shown, the wiring layer has six wiring layers WL1, WL2, WL3, WL4, WL5, and WL6 sequentially from the top surface 20t side. Each wiring layer is covered by an insulating film 2e. The insulating film 2e covering each wiring layer has multiple openings disposed therein. In each opening, a via wiring (via, interlayer conductive path) 2v is buried. Wiring layers WL1, WL2, and WL3, as well as wiring layers WL4, WL5, and WL6, are electrically coupled to each other through the via wiring.

[0054] The wiring layers of the wiring substrate 20 are formed by stacking wiring layers on the upper surface 2Ca and lower surface 2Cb of the insulating layer (core layer, core component, core insulating film) 2CR using a build-up process. The insulating layer 2CR is formed, for example, from a pre-impregnated material, wherein glass fibers are impregnated with resin. The wiring layer WL3 on the upper surface 2Ca and the wiring layer WL4 on the lower surface 2Cb of the insulating film 2CR are electrically coupled to each other through a plurality of via wirings (interlayer conductive paths) 2TW, which are embedded in a plurality of vias configured to penetrate from one of the upper surface 2Ca and the lower surface 2Cb to the other.

[0055] Figure 4 A wiring substrate 20 with an insulating film 2CR as a core layer is shown as an example of a wiring substrate. However, as... Figure 4 The modification can use a so-called coreless substrate without a core layer. In this case, no via wiring 2TW is formed on the wiring substrate. On this modified wiring substrate, the stacked wiring layers are electrically coupled to each other through via wiring 2v disposed between the wiring layers.

[0056] Terminals (terminal units, pads, semiconductor chip coupling terminals) 2PD electrically coupled to the semiconductor chip 10 are formed on the upper surface 20t of the wiring substrate 20. Terminals 2PD are internal interface terminals for electrically coupling the semiconductor chip 10 and the wiring substrate 20. On the lower surface 20b of the wiring substrate 20, connection pads (terminals, external terminals, electrodes, external electrodes) 2LD are formed as input / output terminals for the semiconductor device PKG1. Connection pads 2LD are external interface terminals for electrically coupling the wiring substrate 20 and external devices (e.g., mounting substrates not shown).

[0057] Terminal 2PD and connector 2LD are electrically coupled to each other through multiple wirings 2w formed on wiring substrate 20, via wirings 2v serving as interlayer conductive paths, and via wirings 2TW for electrically coupling wiring layers WL3 and WL4. Figure 4 In the example, an insulating film 2CR is formed as a core layer between wiring layers WL3 and WL4 of the wiring substrate 20. The thickness and hardness of the core layer are greater than any other insulating film 2e. Therefore, the insulating layer 2CR includes a plurality of vias configured to penetrate from one of the upper surface 2Ca and the lower surface 2Cb of the insulating layer 2CR to the other. In each via, a conductor (metal, such as copper) is buried, thereby forming a via wiring 2TW that serves as an interlayer conductive path. The detailed configuration of each wiring layer included in the wiring substrate 20 will be described later.

[0058] exist Figure 4 In the example, the connection pad 2LD is coupled to external terminals (solder balls, solder components, electrodes, and external electrodes) 30. External terminals 30 are conductive components used to electrically couple multiple terminals (not shown) on the mounting substrate side to the connection pad 2LD when the semiconductor device PKG1 is mounted on the mounting substrate. External terminals 30 are formed, for example, from lead-free solder, such as the bump electrode SB described above.

[0059] like Figure 2 As shown, the external terminals 30 are arranged in a matrix (array). Although not in Figure 2 As shown, but connected to the external terminal 30, the connecting disk 2LD (see...) Figure 4 The external terminals (external terminals 30, connection pads 2LD) are also arranged in a matrix. This semiconductor device is called a planar array semiconductor device. Specifically, in this semiconductor device, external terminals (external terminals 30, connection pads 2LD) are arranged in a matrix on the mounting surface side of the wiring substrate 20. Even if the number of external terminals increases, the planar array semiconductor device is preferred from the perspective of suppressing the increase in the mounting area of ​​the semiconductor device, because one side (lower surface 20b) of the mounting surface of the wiring substrate 20 can be effectively used as the arrangement space for the external terminals. That is, even if the number of external terminals increases due to high functionality and high integration, the semiconductor device can be installed while saving space.

[0060] Figure 1 , Figure 2 and Figure 4 An example of a so-called BGA (Ball Grid Array) type semiconductor package is shown, using solder balls as solder components with a spherical shape (as external terminals 30). However, various modifications can be made to the arrangement and structure of the external terminals. For example, modifications can be made to have the connection pad 2LD exposed. Figure 4The structure shown in the lower surface 20b, or the structure in which a thin solder component is bonded to the exposed connection pad 2LD in the lower surface 20b. A semiconductor package with this modification is called an LGA (Grid Array) type.

[0061] like Figure 4 As shown, an underfill resin (insulating resin) 40 is disposed between the semiconductor chip 10 and the wiring substrate 20. The underfill resin 40 is arranged to fill the gap between the surface 10t of the semiconductor chip 10 and the upper surface 20t of the wiring substrate 20. The underfill resin 40 is formed of an insulating (non-conductive) material (e.g., a resin material) and is arranged to seal the electrically coupled portion (the joint portion of the bump electrode SB) of the semiconductor chip 10 and the wiring substrate 20. In this way, by arranging the underfill resin 40 to seal the coupling portion of the bump electrode SB, the stress occurring at the electrically coupled portion of the semiconductor chip 10 and the wiring substrate 20 can be mitigated.

[0062] <Example of circuit configuration>

[0063] The description will now include Figure 4 An example of circuit configuration in a semiconductor chip is shown. Figure 5 It is schematically shown that includes Figure 4 An illustrative diagram illustrating an example of the circuit configuration of the semiconductor chip shown. Figure 6 yes Figure 1 The diagram shows a plan view of the surface (electrode arrangement surface) of the semiconductor chip. Although Figure 6 It is a plan view, but provides dot and shading patterns to identify multiple electrodes 1PDv, multiple electrodes 1PDg, and multiple electrodes 1PDs. Figure 6 In the diagram, among the electrodes 1PD shown in a circular form, electrodes 1PDs are shown in blank, electrodes 1PDv are shown in a dot pattern, and electrodes 1PDg are shown in a shaded pattern.

[0064] like Figure 5As shown, the semiconductor chip 10 has an input / output circuit 11 and a core circuit 12. The input / output circuit 11 inputs or outputs an electrical signal SIG to or from the outside of the semiconductor chip 10. The core circuit 12 is coupled to the input / output circuit 11 and performs signal data processing (e.g., computational processing). The electrodes 1PD of the semiconductor chip 10 include electrodes 1PDs, 1PDv, and 1PDg. Each electrode 1PDs is a signal terminal coupled to the input / output circuit 11 and transmits an electrical signal. Each electrode 1PDv is a power supply terminal coupled to the core circuit 12 and supplies a power supply potential VD for driving the core circuit 12. Electrodes 1PDv are coupled to each other. Each electrode 1PDg is a reference potential terminal coupled to the core circuit 12 and supplies a reference potential VG to the core circuit 12. Electrodes 1PDg are coupled to each other.

[0065] exist Figure 5 In the example shown, electrodes 1PDv and 1PDg are also electrically coupled to input / output circuit 11. A power supply potential VD is supplied to input / output circuit 11 from electrode 1PDv, while a reference potential VG is supplied to input / output circuit 11 from electrode 1PDg. Input / output circuit 11 can be driven by the potential difference between the power supply potential VD and the reference potential VG. Similar to... Figure 5 In the example shown, when electrodes 1PDv are electrically coupled to each other, if power demand increases instantaneously in, for example, core circuit 12, power supply potential is supplied from multiple paths. Therefore, if the power supply potential can be stably supplied to electrodes 1PDv, voltage drop due to instantaneous increases in power demand can be prevented.

[0066] exist Figure 5 In the modified example shown, when the drive voltages between the input / output circuit 11 and the core circuit 12 are different, a power supply potential different from the power supply potential VD can be supplied to the input / output circuit 11. When there are multiple core circuits 12, and when they operate with different drive voltages, different power supply potentials can be supplied to the core circuits 12. In this case, the electrodes 1PDv can be divided into several groups of electrodes (electrode groups). In this case, if the groups are electrically separated, different power supply potentials can be supplied between the groups. However, note that preferably, there are multiple paths for supplying power supply potentials to suppress voltage drops caused by instantaneous increases in power demand, as described above.

[0067] like Figure 6As shown, electrodes 1PDs, 1PDv, and 1PDg are regularly arranged on the surface 10t of the semiconductor chip 10. Electrodes 1PDv and 1PDg are mainly arranged in the central portion of the surface 10t. Electrodes 1PDs are mainly arranged on the outer peripheral side, that is, on the outer edge and peripheral portion of the central portion of the surface 10t.

[0068] exist Figure 6 In the example shown, electrodes 1PDs are arranged in the outermost periphery and one inner periphery of the electrode 1PD arrangement. This is used to transmit the electrical signal SIG (see [reference]). Figure 5 The wiring path is pulled out to the outer periphery of the wiring substrate 20, as wiring 2ws, such as Figure 10 As shown. Therefore, on the surface 10t of the semiconductor chip 10, the electrodes 1PDs for transmitting the electrical signal SIG are arranged on the outer periphery, thereby reducing the path distance of the signal transmission path.

[0069] Electrodes 1PDv and 1PDg are arranged inside electrode 1PD on surface 10t. In other words, electrodes 1PDs are arranged between electrodes 1PDv, 1PDg, and the outer periphery of surface 10t. Core circuit 12 (see...) Figure 5 The input / output circuit 11 is formed to overlap with the central portion of surface 10t (the portion where electrodes 1PDv and 1PDg are arranged) in the plan view. In the plan view, the aforementioned input / output circuit 11 (see...) Figure 5 Electrodes 1PDv and 1PDg are formed between the central portion and the outer periphery of surface 10t. Electrodes 1PDv and 1PDg are formed to overlap with the core circuit 12, thereby shortening the power supply path for the core circuit 12. This results in reduced power loss or noise when supplying power to the core circuit 12.

[0070] exist Figure 6 In the example shown, in the arrangement of electrodes 1PD on surface 10t, electrodes 1PD and 1PDg are not arranged in the outermost circumference and one inner circumference of the outermost circumference. In the arrangement of electrodes 1PD on surface 10t, electrodes 1PDs are not arranged in the two or more inner circumferences of the outermost circumference (circumferences other than one inner circumference of the outermost circumference and the outermost circumference). However, Figure 6 An ideal configuration is shown, wherein on the surface 10t of the semiconductor chip 10, electrodes 1PDs for signal transmission are arranged on the outer peripheral side, and electrodes 1PDv and 1PDg for supplying driving voltage are arranged in the central portion. Therefore, various modifications can be made to the arrangement of the electrodes 1PDs.

[0071] For example, a portion of electrodes 1PDs can be arranged in two or more inner circumferences of the outermost periphery of the arrangement of electrodes 1PDs on surface 10t. Electrode 1PDv or electrode 1PDg can be arranged in the outermost periphery or one inner periphery of the outermost periphery. For example, for signal transmission, the signal transmission path and the reference path can be formed in parallel with each other. As the reference path, when a transmission path for a reference potential is used, electrode 1PDg for the reference potential is preferably arranged near electrodes 1PDs. In this case, in the arrangement of electrodes 1PDs, a portion of electrode 1PDg is preferably arranged in the outermost periphery or one inner periphery of the outermost periphery.

[0072] like Figure 6 As shown, in the central portion of surface 10t, electrodes 1PDv and 1PDg are arranged as follows. That is, electrodes 1PDv and 1PDg are arranged in a row along the "X" direction. At the intersection with the "X" direction (in... Figure 6 In the orthogonal direction, the rows of electrodes 1PDv and 1PDg are arranged alternately. Electrodes 1PD are arranged in a zigzag pattern.

[0073] The term "Z-shaped arrangement" can be expressed as follows: That is, the electrodes 1PD in the first row along the "Y" direction are arranged between adjacent electrodes 1PD in the second row along the "Y" direction, and the electrodes 1PD in the second row are arranged between adjacent electrodes 1PD in the first row. Similarly, the electrodes 1PD in the third row along the "Y" direction are arranged between adjacent electrodes 1PD in the second row along the "Y" direction, and the electrodes 1PD in the second row are arranged between adjacent electrodes 1PD in the third row. The electrodes 1PD in the first row along the "X" direction are arranged between adjacent electrodes 1PD in the second row along the "X" direction, and the electrodes 1PD in the second row are arranged between adjacent electrodes 1PD in the first row. The electrodes 1PD in the third row along the "X" direction are arranged between adjacent electrodes 1PD in the second row along the "X" direction, and the electrodes 1PD in the second row are arranged between adjacent electrodes 1PD in the third row.

[0074] In order to operate circuit 12 stably, a driving voltage must be stably supplied to the core circuit 12 during its operation. The operating speed (frequency) of the core circuit 12 increases with improvements in semiconductor devices. Figure 5An exemplary core circuit 12 is shown. However, to improve the performance of a semiconductor chip 10, a semiconductor chip 10 may have multiple (many) core circuits 12, each operating at high speed. In this case, sufficient power must be provided at appropriate times to meet the power demands that vary significantly depending on the operation of the core circuits 12. As the requirement for reduced power consumption is met, the drive voltage tends to decrease. This reduces the variation in the voltage to be supplied, and very small noise, negligible in slow operation, may affect the operation of the core circuits 12.

[0075] In particular, when the arrangement density of electrodes 1PD on the surface 10t of semiconductor chip 10 is very high, the spacing between adjacent electrodes 1PD becomes narrower. In this case, the cross-sectional area of ​​the conductive path used to power the electrodes 1PD is smaller near the electrodes 1PD, thus increasing the wiring resistance in the narrower portion of the path. When electrodes 1PDv are coupled to each other through the internal wiring of semiconductor chip 10, multiple power supply paths are strengthened, and the cross-sectional area of ​​the path can be larger in the circuit. However, the internal wiring of semiconductor chip 10 is narrower and thinner than the wiring of wiring substrate 20. Therefore, if wiring substrate 20 (see...) Figure 5 If the wiring resistance in the semiconductor chip 10 is high, noise will be generated before it reaches the semiconductor chip 10. It is difficult to perform noise control using only the internal wiring of the semiconductor chip 10.

[0076] Figure 6 The arrangement pattern of electrodes 1PDv and 1PDg shown is for improving... Figure 4 The wiring layout of the wiring substrate shown achieves stable routing to the core circuit 12 (see...). Figure 5 The layout of the power supply.

[0077] From stable to core circuit 12 (see Figure 5 From the perspective of supplying electrical power, the following points are particularly effective when the wiring substrate 20 is improved.

[0078] In other words, multiple conductive paths coupled to electrodes 1PDv (and 1PDg) of the semiconductor chip 10 are formed on the wiring substrate 20. In other words, on the wiring layers (particularly the uppermost wiring layer) of the wiring substrate 20, charge is forced to move in the horizontal direction (the direction of extension of the wiring layer). As a result, when a momentary increase in power demand occurs at a particular electrode 1PDv, the necessary potential can be supplied to the corresponding electrode 1PDv at the appropriate time through the conductive paths. By forming multiple conductive paths coupled to a single electrode 1PDv, the cross-sectional area of ​​the conductive paths in the circuit can be increased, thereby reducing the wiring resistance.

[0079] The path distance of each conductive path is reduced. In this case, the conductive path is coupled to electrode 1PDv (and electrode 1PDg) of semiconductor chip 10. Figure 5 The power supply potential VD and reference potential VG shown in the figure are from... Figure 4 The wiring layer WL6 side of the wiring substrate 20 shown is supplied. Therefore, in the via wiring 2V and through-hole wiring 2TW used for electrically coupling the wiring layers to each other, the wiring to be used to supply the power supply potential VD or the reference potential VG is arranged on the side of the via wiring 2V. Figure 6 The electrodes 1PDv and 1PDg are shown overlapping. Specifically, numerous wirings are coupled to the semiconductor chip 10 in the region overlapping with it. Figure 4 The wiring layers WL1, WL2, and WL3 are shown. Therefore, the via wiring 2TW for supplying the power supply potential VD or the reference potential VG is preferably arranged in conjunction with... Figure 6 The overlapping position of electrodes 1PDv and 1PDg is shown. Figure 4 In the via 2v between wiring layer WL1 and wiring layer WL shown, the via 2v used to supply power potential VD or reference potential VG is preferably arranged in relation to... Figure 6 The electrodes 1PDv and 1PDg are shown overlapping. Then, the charge can travel along the thickness direction of the wiring substrate 20. Figure 4 The path can be linearly shifted in the "Z" direction. As a result, the path direction of each conductive path can be reduced. If the path direction of a conductive path is shortened, the impedance of the conductive path can be reduced.

[0080] Figure 5 The driving voltage of the core circuit 12 shown is adjusted by the potential difference between the power supply potential VD and the reference potential VG. Therefore, electrodes 1PDv and 1PDg are preferably arranged near each core circuit 12. Thus, a set of electrodes 1PDv and a set of electrodes 1PDg are preferably distributed in a balanced manner (e.g., alternately), rather than locally clustered and arranged.

[0081] exist Figure 6In the example shown, the electrodes 1PD included in the semiconductor chip 10 are arranged as follows. That is, the semiconductor chip 10 has, in a plan view: a set of power potential electrodes, wherein electrodes 1PDv are arranged along the "X" direction; and a set of reference potential electrodes, wherein electrodes 1PDg are arranged along the "X" direction. The set of power potential electrodes and the set of reference potential electrodes comprise multiple rows and are arranged alternately along the "Y" direction in the plan view. In this arrangement, electrodes 1PDv are arranged adjacent to one or more electrodes 1PDg. In other words, the semiconductor chip 10 has multiple pairs of electrodes 1PDv and electrodes 1PDg that are adjacent to each other. In these multiple pairs of electrodes, the spacing between adjacent electrodes 1PDv and electrodes 1PDg is equal. It can be said that in... Figure 6 In the arrangement of electrode 1PD shown, electrode 1PDv and electrode 1PDg are evenly distributed.

[0082] The semiconductor chip 10 and the wiring substrate 20 are coupled according to a flip-chip coupling system. In the case of a flip-chip coupling system... Figure 4 The arrangement of terminals 2PD on the uppermost wiring layer WL1 of the wiring substrate 20 is the same as the arrangement of electrodes 1PD on the semiconductor chip 10. Therefore, in the wiring layer WL1, terminals 2PDv (see...) Figure 5 The terminals 2PDg and 2PDg are preferably distributed evenly (e.g., alternately). In this way, when different types of terminals 2PD are distributed and arranged, the width of the wiring on at least the uppermost wiring layer WL1 needs to be narrower than the conductor pattern of the wiring on another wiring layer.

[0083] Based on the above research results, on the wiring substrate 20, at the power supply potential VD (see... Figure 5 ) or reference potential VG (see Figure 5 In the wiring structure, it is preferable to promote charge movement in the direction along each wiring layer of the wiring substrate 20, and it is also preferable to have short path distances for multiple paths for supplying electrical power through the wiring layers. As described above, the wiring around the terminal 2PD, at least on the uppermost wiring layer WL1, has a narrow wiring width. Therefore, on the wiring substrate 20, the wiring paths for supplying the power supply potential VD or the reference potential VG form a three-dimensional mesh structure. Therefore, it is necessary to suppress the increase in wiring resistance of the wiring layer WL1.

[0084] <Details of Wiring Layout>

[0085] Now, we will use diagrams to describe in detail the following: Figure 4 Wiring layout on each wiring layer in the wiring substrate 20 shown. Figure 7 It is shown in Figure 3The diagram shows a plan view of the wiring substrate, excluding the semiconductor chip and the bottom filled with resin. Figure 8 It is shown in Figure 7 A plan view of a wiring layer layout example on a wiring substrate, excluding the topmost insulating film. Figure 7 and Figure 8 It shows the relationship with Figure 7 The enlarged area showing the overlapping chip mounting areas. Figure 9 It is shown Figure 8 An enlarged plan view of the central part. Figure 9 It shows Figure 8 A further magnified portion of the enlarged view. Figure 10 It is shown in Figure 7 A plan view of an example layout of a wiring layer as a second layer on a wiring substrate. Figure 11 It is shown Figure 10 wiring layer, and Figure 9 The enlarged planar view shows the enlarged central portion of the overlapping planar surfaces. Although Figures 7 to 11 It is a plan view used to identify signal transmission paths, paths for supplying power potential, and paths for supplying reference potential, but they are illustrated with... Figure 6 The same pattern. That is, in Figures 7 to 11 In this diagram, the signal transmission path is blank, the path for supplying power potential is shown as a dotted pattern, and the path for supplying reference potential is shown as a shaded pattern. Figure 9 and Figure 11 In the middle, the position of terminal 2PD of wiring substrate 20 (in other words, with Figure 6 The overlapping positions of the electrodes 1PD of the semiconductor chip 10 are shown by dashed lines. Figure 9 and Figure 11 In the image, the position of the via 2vv directly below the 2wv is shown with a denser dot pattern than the surrounding area. Figure 9 and Figure 11 In the image, the position of the via routing 2vg directly below routing 2wg is shown with a shaded pattern contrasting with its surroundings. Figure 11 In the middle, it is shown by dashed lines. Figure 9 The outlines of wiring 2wv and wiring 2wg are shown.

[0086] Figure 12 yes Figure 11 Enlarged cross-sectional view of line AA. Figure 13 yes Figure 11 Enlarged cross-sectional view of the BB line. Figure 14 yes Figure 11 Enlarged cross-sectional view of the CC line. Figures 12 to 14This illustrates a wiring layer higher than the core insulating film in the wiring substrate and a portion of the surface 10t side of a semiconductor chip. To clearly illustrate the coupling relationship from the wiring layer WL1 to the via wiring, Figures 12 to 14 The vias or through-holes at different locations in the cross-section are shown in dashed lines.

[0087] from Figure 7 and Figure 8 A comparison clearly shows that the uppermost wiring layer WL1 of the wiring substrate 20 is essentially covered by the insulating film 2e1. The insulating film 2e1 is a solder resist film covering the upper surface 20t side of the wiring substrate 20. The insulating film 2e1 has multiple openings disposed therein. The conductor pattern in the lower layer of the insulating film 2e1 is partially exposed through the openings. The portion of the insulating film 2e1 exposed through the openings is the terminal 2PD of the wiring substrate 20.

[0088] Figure 7 The terminal 2PD shown is arranged in relation to Figure 6 The electrodes 1PD of the semiconductor chip 10 are positioned relative to each other. In other words, on the upper surface 20t of the wiring substrate 20, in the region overlapping with the semiconductor chip 10 (see... Figure 1 An opening is formed in the chip mounting region 10r. Furthermore, in other words, on the upper surface 20t of the wiring substrate 20, a terminal 2PD is arranged in the chip mounting region 10r. Therefore, using... Figure 5 and Figure 6 The description of the layout of electrode 1PD can be made using the following: Figure 7 Instead of describing the layout of the terminals 2PDs shown, the wiring substrate 20 includes terminals 2PDs, terminals 2PDv, and terminals 2PDg.

[0089] Terminals 2PDs, 2PDv, and 2PDg are regularly arranged on the upper surface 20t of the wiring substrate 20. Terminals 2PDv and 2PDg are mainly arranged in the central portion of the upper surface 20t. Terminals 2PDs are mainly arranged on the outer periphery of the upper surface 20t, that is, on the outer edge and peripheral portion of the central portion of the upper surface 20t.

[0090] Specifically, terminals 2PDs are arranged in the outermost periphery and one inner periphery of the terminal 2PD arrangement. On the upper surface 20t of the wiring substrate 20, an electrical signal SIG (see...) is transmitted. Figure 5 The terminals 2PDs are arranged on the outer periphery, thereby reducing the path distance of the signal transmission path.

[0091] Terminal 2PDs are set by Figure 10Multiple wirings 2ws on the wiring layer WL2 are electrically coupled to multiple via wirings (vias) 2v disposed on the outer periphery of the wiring substrate 20. On the wiring layer WL2, a conductor plane 2PL is disposed around the wirings 2ws and via wirings 2vs. The wirings 2ws and via wirings 2vs are formed on... Figure 8 The conductor plane 2PL on the wiring layer WL1 shown is covered. Via wiring 2vs is electrically coupled to... Figure 4 The via wiring 2TW is used for signal transmission. The via wiring 2TW is arranged in a location that does not overlap with the semiconductor chip 10 (the area around the wiring substrate 20).

[0092] Terminals 2PDv and 2PDg are arranged inside terminals 2PDs on the upper surface 20t. In other words, terminals 2PDs are arranged between terminals 2PDv, terminal 2PDg, and the outer edge of the upper surface 20t. Figure 1 As shown, the semiconductor chip 10 is installed... Figure 1 In the state shown on the wiring substrate 20, the core circuit 12 (see Figure 5 It overlaps with the portion in which terminals 2PDv and 2PDg are arranged. For example... Figure 4 As shown, the electrodes 1PD of the semiconductor chip 10 and the terminals 2PD of the wiring substrate 20 are coupled to each other via bump electrodes SB. Therefore, terminals 2PDv and 2PDg overlap with the core circuit 12, thereby reducing the path for supplying power to the core circuit 12. This results in reduced power loss or noise when supplying electrical power to the core circuit 12.

[0093] exist Figure 7 In the example shown, in the arrangement of terminals 2PD on the upper surface 20t, terminals 2PDv and 2PDg are not arranged in the outermost circumference and one of the inner circumferences of the outermost circumference. In the arrangement of terminals 2PD on the upper surface 20t, terminals 2PDs are not arranged in two or more of the inner circumferences of the outermost circumference. However, compared with using... Figure 6 The modifications described are similar, for Figure 7 The arrangement of the 2PD terminals shown can be modified in various ways.

[0094] like Figure 7 As shown, terminals 2PDv and 2PDg are arranged in the central portion of the upper surface 20t as follows. That is, terminals 2PDv and 2PDg are arranged in a row along the "X" direction. (The text then abruptly shifts to a description of a location intersecting the "X" direction.) Figure 7 In the orthogonal direction, rows of terminals 2PDv and 2PDg are arranged alternately. Terminals 2PD are arranged in a zigzag pattern. The term "zigzag arrangement" applies to the case where terminals 2PD replace electrodes 1PD. Therefore, the same description will not be repeated.

[0095] Figure 7 Each terminal 2PDv shown is arranged in Figure 8 The diagram shows part of the wiring (conductor pattern, wiring pattern) 2wv on the first layer, wiring layer WL1. Similarly, Figure 7 Each terminal 2PDg shown is arranged in Figure 8 The diagram shows part of the wiring (conductor pattern, wiring pattern) 2wg on the first layer, wiring layer WL1. Each of wiring 2wv and wiring 2wg is arranged in relation to... Figure 1 The semiconductor chip 10 is shown overlapping in the diagram. Wiring 2wv and wiring 2wg extend along the "X" direction and are arranged alternately along the "Y" direction. On wiring layer WL1, conductor plane 2PL is arranged around the area overlapping with the semiconductor chip 10 (see diagram). Figure 1 The area of ​​the conductor plane 2PL is larger than the area of ​​the wiring 2w or the via wiring 2v (see...). Figure 9 For example, supplying a ground potential to the conductor plane 2PL. Figure 4 As shown, in the case of the wiring substrate 20 of the semiconductor device PKG1, the wiring 2ws for signal transmission is arranged on the wiring layer WL2 and overlaps with the conductor plane 2PL provided on the wiring layer WL1. In this way, electromagnetic noise can be shielded when the wiring 2ws for signal transmission is covered by a conductor pattern with a large area supplied with a fixed potential. The wiring (signal wiring) 2ws is pulled out to the outside of the area overlapping with the semiconductor chip 10. Therefore, on the wiring layer WL1, by arranging the conductor plane 2PL in the area that does not overlap with the semiconductor chip 10, the wiring 2ws is substantially covered by the conductor plane 2PL.

[0096] like Figure 8 As shown, on wiring layer WL1, terminals 2PDs, wiring 2wg, and wiring 2wv are arranged in the area overlapping with semiconductor chip 10 (see Figure 10). Figure 4 Terminals 2PDs are arranged around the area where wiring 2wg and wiring 2wv are provided, and through via wiring (via) 2vs for signal transmission (see...). Figure 4 It is electrically coupled to the wiring layer WL2.

[0097] like Figure 9 As shown, the cabling 2wv has a main cabling unit (first main cabling unit) 2wv1 extending along the "X" direction and multiple sub-caching units (first sub-caching units) 2wv2 extending along the "Y" direction intersecting the "X" direction and passing through the main cabling unit 2wv1. Supply to cabling 2wv Figure 5 The power supply potential VD is shown.

[0098] like Figure 9As shown, the cabling 2wg has a main cabling unit (second main cabling unit) 2wg1 extending along the "X" direction and multiple sub-caching units (second sub-caching units) 2wg2 extending along the "Y" direction intersecting the "X" direction and passing through the main cabling unit 2wg1. Supplying cabling 2wg... Figure 5 The reference potential VG is shown.

[0099] Each of the sub-routing units 2wv2 of wiring 2wv and 2wg2 of wiring 2wg has an end unit (first end unit) 2we1 and an end unit (second end unit) 2we2 in the "Y" direction on the side opposite to the end unit 2we1 via the main wiring unit 2wv1 or the main wiring unit 2wg1. The sub-routing units 2wv2 of wiring 2wv and 2wg2 of wiring 2wg are arranged alternately in the "X" direction between the main wiring unit 2wv1 and the main wiring unit 2wg1.

[0100] like Figure 11 As shown, wiring layer WL2 has a conductor pattern (first conductor pattern) 2Pv1, which overlaps with the end units 2we1 of the main wiring unit 2wg1 of wiring 2wg and the sub-wiring unit 2wv2 of wiring 2wv, and extends in the "X" direction. Wiring layer WL2 has a conductor pattern 2Pg1, which overlaps with the end units 2we2 of the main wiring unit 2wv1 of wiring 2wv and the sub-wiring unit 2wg2 of wiring 2wg. Figure 11 In the example shown, wiring layer WL2 has multiple conductor patterns (second conductor patterns) 2Pg1 arranged along the "X" direction. The end units 2we1 of sub-wiring unit 2wv2 are electrically coupled to conductor pattern 2Pv1 via via wiring (first via) 2vv. The end units 2we2 of sub-wiring unit 2wg2 are electrically coupled to conductor pattern 2Pg1 via wiring (second via) 2vg.

[0101] In the semiconductor device PKG1 of this embodiment, the wiring path for supplying the power supply potential VD is configured as described above (see Figure 5 ) and the wiring path used to supply the reference voltage VG (see Figure 5 This enables a stable supply of electrical power to the core circuit 12 (see...). Figure 5 ).

[0102] Figure 9 Each of the wiring 2wv and wiring 2wg shown has a main wiring unit (2wv1 or 2wg1) extending along the "X" direction and a sub-wiring unit (2wv2 or 2wg2) extending along the "Y" direction. Each sub-wiring unit is arranged at both ends of the main wiring unit. The two ends of the sub-wiring unit are coupled to... Figure 11The conductor pattern (2Pv1 or 2Pg1) of the wiring layer WL2 is shown. As a result, when the power demand instantaneously increases, for example, in a portion of wiring 2wv, a power supply potential VD is supplied from the end unit of the sub-wiring unit 2wv2 of wiring 2wv. Similarly, when the power demand instantaneously increases, for example, in a portion of wiring 2wg, a reference potential VG is supplied from the end unit of the sub-wiring unit 2wg2 of wiring 2wg. In this way, according to the wiring structure of the semiconductor device PKG1, multiple conductive paths are formed for supplying potential to each of wiring 2wv and wiring 2wg. Therefore, in wiring 2wv and wiring 2wg, charge is induced to move along the direction of wiring layer WL1. As a result, even when the main wiring unit and sub-wiring unit of wiring 2wv and wiring 2wg have narrow wiring widths, the increase in wiring resistance can be suppressed.

[0103] Sub-routing units 2wv2 of wiring 2wv and 2wg2 of wiring 2wg are arranged alternately in the "X" direction between main wiring units 2wv1 and 2wg1. In this case, the spacing between sub-routing units 2wv2 of wiring 2wv and sub-routing units 2wg2 of wiring 2wg can be reduced. Therefore, when terminal 2PDv is provided in multiple portions of wiring 2wv and when terminal 2PDg is provided in multiple portions of wiring 2wg, terminal 2PDv and terminal 2PDg are evenly (e.g., alternately) distributed.

[0104] exist Figure 7 In the example shown, the terminals 2PD included in the wiring substrate 20 are arranged as follows. That is, the wiring substrate 20 has a set of power potential terminals and a set of reference potential terminals in a plan view. In the set of power potential terminals, terminal 2PDv is arranged along the "X" direction, and in the set of reference potential terminals, terminal 2PDg is arranged along the "X" direction. The set of power potential terminals and the set of reference potential terminals comprise multiple rows and are arranged alternately along the "Y" direction in a plan view. In this arrangement, terminal 2PDv is arranged adjacent to one or more terminals 2PDg. Terminal 2PDg is arranged adjacent to one or more terminals 2PDv. In other words, the wiring substrate 20 has multiple pairs of adjacent terminals 2PDv and terminals 2PDg. In these multiple pairs of terminals, the spacing between adjacent terminals 2PDv and terminals 2PDg is equal. Figure 7 In the arrangement of terminals 2PD shown, terminals 2PDv and 2PDg are evenly distributed.

[0105] Figure 9The sub-routing units 2wv2 and 2wg2 shown can be arranged alternately, thereby reducing the parasitic inductance generated in the sub-routing units 2wv2 of wiring 2wv and 2wg2 of wiring 2wg. As a result, the noise generated in wiring 2wv and wiring 2wg can be reduced.

[0106] like Figure 8 and Figure 9 As shown, the wiring layer WL1 has wiring 2wv and wiring 2wg. In the plan view, wiring 2wv and wiring 2wg extend along the "X" direction (the main wiring unit extends along the "X" direction) and are arranged alternately along the "Y" direction.

[0107] Focusing on 2wg of wiring, the following description can be made. That is to say, as... Figure 9 As shown, the wiring layer WL1 has wiring (second wiring) 2wgA and wiring (third wiring) 2wgB, with a reference potential VG (see...). Figure 5 A wiring unit 2wgA and a wiring unit 2wgB are supplied. Each of wiring units 2wgA and 2wgB has, in the plan view, a main wiring unit 2wg1 extending in the "X" direction and a sub-wiring unit 2wg2 extending in the "Y" direction and intersecting with the main wiring unit 2wg1. Wiring unit 2wvA is arranged along the "Y" direction between wiring units 2wgA and 2wgB. The sub-wiring units 2wv2 of wiring unit 2wvA and 2wg2 of wiring unit 2wgB are arranged alternately along the "X" direction between the main wiring units 2wv1 and 2wg1. Figure 11 As shown, the wiring layer WL2 has a conductor pattern 2PvB, which overlaps with the main wiring unit 2wg1 of wiring 2wgB and the end units 2we2 of the sub-wiring unit 2wv2 of wiring 2wvA. The end units 2we2 of the sub-wiring unit 2wv2 of wiring 2wvA are electrically coupled to the conductor pattern 2PvB through via wiring 2vv, while the end units 2we1 of the sub-wiring unit 2wg2 of wiring 2wvA are electrically coupled to the conductor pattern 2PvA through via wiring 2vg.

[0108] Focusing on 2WV wiring, the following description can be made. For example... Figure 9 As shown, the wiring layer WL1 has wiring (first wiring) 2wvA and wiring (fourth wiring) 2wvB, and the power supply voltage VD (see...). Figure 5A wiring unit 2wvA and a wiring unit 2wvB are supplied. Each of wiring units 2wvA and 2wvB has, in the plan view, a main wiring unit 2wv1 extending in the "X" direction and a sub-wiring unit 2wv2 extending in the "Y" direction and intersecting with the main wiring unit 2wv1. Wiring unit 2wgA is arranged between wiring units 2wvA and 2wvB along the "Y" direction. The sub-wiring units 2wg2 of wiring unit 2wgA and the sub-wiring units 2wv2 of wiring unit 2wvB are arranged alternately in the "X" direction between the main wiring unit 2wg1 and the main wiring unit 2wv1. Figure 9 The main wiring unit 2wv1 of wiring 2wvB is not shown. (e.g., wiring 2wvB's main wiring unit 2wv1). Figure 11 As shown, the wiring layer WL2 has a conductor pattern 2PgB, and the conductor pattern 2PgB is connected to the main wiring unit 2wv1. Figure 11 (Not shown in the diagram) and the end unit 2we1 of the sub-routing unit 2wg2 of routing 2wgA overlap. The end unit 2we1 of the sub-routing unit 2wg2 of routing 2wgA is electrically coupled to the conductor pattern 2PgB through via routing 2vg, while the end unit 2we2 of the sub-routing unit 2wg2 of routing 2wgA is electrically coupled to the conductor pattern 2PgA through via routing 2vg.

[0109] In the case of semiconductor device PKG1, semiconductor chip 10 and wiring substrate 20 are electrically coupled using a flip-chip coupling system. For example... Figure 12 and Figure 13 As shown, the surface 10t of the semiconductor chip 10 is opposite to the upper surface 20t of the wiring substrate 20. The electrodes 1PD of the semiconductor chip 10 (see...) Figure 4 This includes wiring 2wv electrically coupled to wiring substrate 20 (see...) Figure 9 Multiple electrodes 1PDv and wiring 2wg electrically coupled to wiring substrate 20 (see) Figure 9 The semiconductor chip 10 has multiple electrodes 1PDg. The wiring substrate 20 has multiple terminals 2PDv that are opposite to and electrically coupled to the electrodes 1PDv of the semiconductor chip 10, and multiple terminals 2PDg that are opposite to and electrically coupled to the electrodes 1PDg of the semiconductor chip 10. Therefore, by applying a flip-chip coupling system, the conductive path for electrically coupling the semiconductor chip 10 and the wiring substrate 20 can be shortened. This results in a reduction in the impedance of the conductive path.

[0110] In the case of semiconductor device PKG1, the terminal 2PD of wiring substrate 20 is formed on the surface where a junction is formed as shown in the figure. Figure 9 The routing layers 2wv and 2wg shown are on the same layer, WL1. In other words, as... Figure 12 As shown, the wiring substrate 20 has an insulating film 2e1, which covers the wiring layer WL1 and includes a plurality of openings 2eH. Wiring 2wv (see...) Figure 9The insulating film 2e1 has multiple terminals 2PDv exposed through the opening 2eH. Wiring 2wg (see...) Figure 9 The semiconductor chip 10 has multiple terminals 2PDg exposed in the opening 2eH of the insulating film 2e1. The electrodes 1PDv and terminals 2PDv of the semiconductor chip 10 are coupled to each other via bump electrodes SBv. The electrodes 1PDg and terminals 2PDg of the semiconductor chip 10 are coupled to each other via bump electrodes SBg (see...). Figure 14 Therefore, when a portion of wiring 2wv is used as terminal 2PDv, the path for supplying power potential can be shortened. Similarly, when a portion of wiring 2wg is used as terminal 2PDg, the path for supplying reference potential can also be shortened.

[0111] like Figure 9 As shown, a portion of terminal 2PDv forming part of wiring 2wv is included in the end unit of each sub-wiring unit 2wv2. A portion of terminal 2PDg forming part of wiring 2wg is included in the end unit of each sub-wiring unit 2wg2. In other words, terminal 2PDv includes a plurality of terminals 2PDv included in the end units (first end units) 2we1 and 2we2 of sub-wiring units 2wv2. Terminal 2PDg includes a plurality of terminals 2PDg included in the end units 2we1 and 2we2 of sub-wiring units 2wg2. In this way, the end units of sub-wiring units 2wv2 and 2wg2 that intersect with main wiring units 2wv1 and 2wg1 are used as terminals 2PDv and 2PDg, thereby evenly distributing the path for supplying power supply potential and the path for supplying reference potential.

[0112] like Figure 13 As shown, the terminal 2PDv in end unit 2we1 and end unit 2we2 overlaps with the via wiring 2vv. (As...) Figure 14 As shown, the terminals 2PDg of end units 2we1 and 2we2 overlap with the via wiring 2vg. In this way, if terminal 2PDv overlaps with via wiring 2vv, the path for supplying power supply potential in the thickness direction of the wiring substrate 20 can be shortened. Similarly, if terminal 2PDg overlaps with via wiring 2vg, the path for supplying reference potential in the thickness direction of the wiring substrate 20 can also be shortened.

[0113] In the case of semiconductor device PKG1, such as Figure 9As shown, a portion of terminal 2PDv, which forms part of wiring 2wv, is included in main wiring unit 2wv1. A portion of terminal 2PDg, which forms part of wiring 2wg, is included in main wiring unit 2wg1. In other words, terminal 2PDv includes terminal 2PDv in main wiring unit 2wv1. Terminal 2PDg includes terminal 2PDv in main wiring unit 2wg1. Therefore, by providing terminals 2PDv and 2PDg not only in the end units of sub-wiring units 2wv2 and 2wg2, but also in main wiring units 2wv1 and 2wg1, multiple paths for supplying power supply potential and multiple paths for supplying reference potential can be formed.

[0114] like Figure 11 As shown, the main wiring unit 2wv1 of wiring 2wv (see...) Figure 13 The conductor pattern 1Pg1 of wiring layer WL2 overlaps with the main wiring unit 2wg1 of wiring layer 2wg (see...). Figure 14 It overlaps with the conductor pattern 2Pv1 of wiring layer WL2. Therefore, as Figure 13 As shown, in terminal 2PDv, terminal 2PDv in main wiring unit 2wv1 (see...) Figure 11 () Does not overlap with via routing 2VV. For example Figure 14 As shown, in terminal 2PDg, terminal 2PDg in main wiring unit 2wg1 (see...) Figure 11 It does not overlap with the via routing 2vg.

[0115] The wiring layer WL2 has multiple conductor patterns for supplying power and multiple conductor patterns for supplying reference potential. Figure 15 It is shown Figure 11 The modified enlarged plan view. For example... Figure 11 As shown, wiring layer WL2 has a conductor pattern (partial) 2PvA that overlaps with the end unit 2we1 of sub-wiring unit 2wv2 and extends along the "X" direction, and a conductor pattern (partial) 2PvB that overlaps with the end unit 2we2 of sub-wiring unit 2wv2 and extends along the "X" direction. In the plan view, conductor patterns 2PgA (multiple conductor patterns 2PgA) are arranged between conductor patterns 2PvA and conductor patterns 2PvB. The end unit 2we2 of sub-wiring unit 2wv2 is electrically coupled to conductor pattern 2PvB through via wiring 2vv. In other words, conductor patterns 2PvA and conductor patterns 2PvB are electrically coupled to each other through sub-wiring unit 2wv2.

[0116] like Figure 15As shown, in this modified embodiment, conductor pattern 2PvA and conductor pattern 2PvB are separated from each other. In this case, conductor pattern 2PgA between conductor pattern 2PvA and conductor pattern 2PvB is formed to extend along the "X" direction. In this modification, on wiring layer WL2, multiple conductor patterns 2Pv1 and multiple conductor patterns 2Pg1 are separated from each other. Figure 15 In the modification shown, conductor pattern 2PvA and conductor pattern 2PvB are electrically coupled to each other through sub-wiring unit 2wv2, thereby enabling an increase in the number of paths used to supply power potential.

[0117] like Figure 15 As shown, wiring layer WL2 has conductor patterns 2PgA and 2PgB. Conductor pattern 2PgA overlaps with the end unit 2we2 of sub-wiring unit 2wg2 and extends in the "X" direction. Conductor pattern 2PgB overlaps with the end unit 2we1 of sub-wiring unit 2wg2 and extends in the "X" direction. In the plan view, conductor pattern 2PvA is disposed between conductor patterns 2PgA and 2PgB. The end unit 2we1 of sub-wiring unit 2weg2 is electrically coupled to conductor pattern 2PgB through via wiring 2vg, while the end unit 2we2 is electrically coupled to conductor pattern 2PgA through via wiring 2vg. In other words, conductor patterns 2PgA and 2PgB are electrically coupled through sub-wiring unit 2wg2. Figure 15 In the modified case shown, conductor pattern 2PgA and conductor pattern 2PgB are electrically coupled to each other through sub-wiring unit 2wg2, thereby enabling an increase in the number of paths used to supply the reference potential.

[0118] exist Figure 11 In the example, wiring layer WL2 has conductor patterns 2PgA and 2PgB. Conductor pattern 2PgA overlaps with the end unit 2we2 of sub-wiring unit 2wg2 and is arranged in the "X" direction. Conductor pattern 2PgB overlaps with the end unit 2we1 of sub-wiring unit 2wg2 and is arranged in the "X" direction. Figure 11 As shown, when conductor patterns 2Pg1 are arranged separately from each other in the "X" direction, electrical coupling is achieved between conductor patterns 2Pg1 and wiring 2wg provided on wiring layer WL1 (see...). Figure 9 This allows for an increase in the number of paths available for supplying the reference potential.

[0119] Figure 16 It is only shown for supply Figure 11 The diagram shows an enlarged plan view of the conductor pattern of the power source and the conductor pattern used to supply the reference potential. (See diagram for reference.) Figure 16As shown, wiring layer WL2 has conductor pattern 2PgA, which is arranged in the "Y" direction between conductor patterns 2PvA and 2PvB and in a row in the "X" direction. Conductor patterns 2PvA and 2PvB are electrically coupled through connection units 2Pvc disposed between conductor patterns 2PgA. In this way, in Figure 11 and Figure 16 In the example shown, conductor pattern 2PgA is divided into several groups of patterns in the "X" direction of wiring layer WL2. This results in connection units 2Pvc being arranged for adjacent conductor patterns 2PgA. Figure 16 As shown, conductor patterns 2PvA and 2PvB are coupled through multiple connection units 2Pvc. The number of paths used to supply the reference potential can then be further increased.

[0120] Wiring substrate 20 has Figure 17 The wiring layer WL3 is shown. Figure 17 It is shown in Figure 7 The diagram shows a layout example of a wiring layer as the third layer on a wiring substrate. Figure 18 Is Figure 17 The wiring layer shown is with Figure 9 Enlarged plan view of the corresponding location.

[0121] like Figure 4 As shown, wiring layer WL3 is disposed between wiring layer WL2 and lower surface 20b, and is formed adjacent to wiring layer WL2 in a cross-sectional view in the direction intersecting with upper surface 20t. Figure 18 As shown, wiring layer WL3 has conductor pattern 2Pv2, conductor pattern 2Pv2 and conductor pattern 2Pv1 (see... Figure 12 The wiring layer WL3 overlaps with conductor pattern 2Pv1, and is electrically coupled to conductor pattern 2Pv1 through multiple vias (third via) 2vv2, extending in the "X" direction. Conductor pattern 2Pg2 is also present in the wiring layer WL3, which is electrically coupled to conductor pattern 2Pg1 (see [link]). Figure 4 The elements overlap and are electrically coupled to the conductor pattern 2Pg1 through multiple vias (fourth via) 2vg2, extending along the "X" direction. Figure 17 and Figure 18 In the example shown, wiring layer WL3 has conductor pattern 2Pv2 and conductor pattern 2Pg2. Conductor pattern 2Pv2 and conductor pattern 2Pg2 are arranged alternately along the "Y" direction. In this way, conductor pattern 2Pv1 and conductor pattern 2Pv2, which form the path for supplying power potential, overlap with the insulating layer (core layer, core member, core insulating film) 2CR (see Figure 4On a higher wiring layer, conductor patterns 2Pv1 and 2Pv2 are electrically coupled through via wiring 2vv2. As a result, the number of paths used to provide power potential can be increased. Similarly, on a higher wiring layer than the insulating layer (core layer, core member, core insulating layer) 2CR (see... Figure 4 On a higher wiring layer, conductor patterns 2Pg1 and 2Pg2, forming paths for supplying reference potential, overlap each other, thereby electrically coupling conductor patterns 2Pg1 and 2Pg2 through via wiring 2vg2. As a result, the number of paths for supplying reference potential can be increased.

[0122] Multiple vias are routed 2TWv and coupled to a conductor pattern 2Pv2. In other words, as... Figure 4 As shown, the wiring substrate 20 has a wiring layer WL4 disposed between the wiring layer WL3 and the lower surface 20b. The wiring substrate 20 has via wiring 2TW for electrically coupling the wiring layers WL3 and WL4. The via wiring 2TW includes: a plurality of via wiring 2TWv, coupled to a conductor pattern 2Pv2 on the wiring layer WL3; and a plurality of via wiring 2TWg, coupled to a conductor pattern 2Pg2 on the wiring layer WL3.

[0123] Figure 6 The arrangement spacing of electrode 1PD shown is narrowed. Compared to the narrowed arrangement spacing of electrode 1PD, it is difficult to form a narrow arrangement spacing for the via wiring 2TW. Therefore, Figure 6 The electrode 1PD of the semiconductor chip shown has a spacing of less than [missing information]. Figure 17 The arrangement spacing of the via wiring 2TW on the wiring substrate 20 is shown. Specifically, in Figure 17 In the wiring layer WL3 shown, in relation to Figure 4 The spacing between the via wirings 2TW (in other words, via wirings 2TWv and via wirings 2TWg) arranged in the overlapping area of ​​the semiconductor chip 10 shown is greater than [missing information]. Figure 6 The arrangement spacing of the electrodes 1PD of the semiconductor chip 10 shown. Therefore, Figure 18 The width (length in the direction intersecting the "X" direction as the extension direction) of the semiconductor pattern 2Pv2 and conductor pattern 2Pg2 shown is greater than Figure 9 The width of the main wiring unit 2wv1 of the wiring 2wv shown. Figure 18 The widths of conductor patterns 2Pv2 and 2Pg2 shown are greater than the width of the main wiring unit 2wg1 of wiring 2wg.

[0124] Figure 19 It is shown in Figure 9 An enlarged plan view of an example layout of a wiring layer as the fourth layer on a wiring substrate. (See attached image.) Figure 4As shown, wiring layer WL4 is formed between wiring layer WL3 and lower surface 20b, and is adjacent to wiring layer WL3 in the cross-sectional view in the direction intersecting with upper surface 20t. Figure 19 As shown, wiring layer WL4 has conductor pattern 2Pv3, which is the same as conductor pattern 2Pv2 (see...). Figure 18 The wiring layer WL4 overlaps with conductor pattern 2Pg3, which is electrically coupled to conductor pattern 2Pg2 through vias and extends along the "X" direction. Conductor pattern 2Pg3 and conductor pattern 2Pg2 (see...) Figure 18 The elements overlap, are electrically coupled to the conductor pattern 2Pg2 through a via, and extend along the "X" direction. Figure 19 In the example shown, wiring layer WL4 has multiple conductor patterns 2Pv3 and multiple conductor patterns 2Pg3. The conductor patterns 2Pv3 and 2Pg3 are arranged alternately in the "Y" direction. Wiring layers WL4 and WL5 (see [link to example]) are used for electrical coupling. Figure 4 The via routing 2vv3 is coupled to the conductor pattern 2Pv3. Multiple via routing 2vg3 for electrically coupled routing layers WL4 and WL5 are coupled to the conductor pattern 2Pg3.

[0125] Figure 20 It is shown in Figure 9 An enlarged plan view of an example layout of a wiring layer as the fifth layer on a wiring substrate. (See attached image.) Figure 4 As shown, wiring layer WL5 is disposed between wiring layer WL4 and lower surface 20b, and is disposed adjacent to wiring layer WL4 in the cross-sectional view in the direction intersecting with upper surface 20t. Figure 20 As shown, wiring layer WL5 has multiple conductor patterns 2Pv4, conductor patterns 2Pv4 and conductor patterns 2Pv3 (see...) Figure 19 The wiring layer WL5 overlaps and is electrically coupled to conductor pattern 2Pv3 through vias. Conductor pattern 2Pg4 is also present, and conductor pattern 2Pg4 is electrically coupled to conductor pattern 2Pg3 (see...). Figure 19 The vias 2vg3 overlap and are electrically coupled to conductor pattern 2Pg3. In this embodiment, conductor pattern 2Pg4 is a conductor pattern with a large area and is coupled to conductor plane 2PL. Conductor pattern 2Pv4 is a wiring pattern used for electrically coupling vias 2vv3 and 2vv4. The area of ​​conductor pattern 2Pv4 is smaller than the area of ​​conductor pattern 2Pg4. Wiring layers WL5 and WL6 (see...) are used for electrically coupling wiring layers WL5 and WL6. Figure 4 The via routing 2vv4 is coupled to the conductor pattern 2Pv4. Multiple via routing 2vg4 for electrically coupled routing layers WL5 and WL6 are coupled to the conductor pattern 2Pg4.

[0126] Figure 21It is shown in Figure 9 An enlarged plan view of an example layout of a wiring layer as the sixth layer on a wiring substrate. (See attached image.) Figure 4 As shown, wiring layer WL6 is disposed between wiring layer WL5 and lower surface 20b, and is adjacent to wiring layer WL5 in the cross-sectional view in the direction intersecting with upper surface 20t. Figure 21 As shown, wiring layer WL6 has conductor pattern 2Pg5, conductor pattern 2Pv5 and conductor pattern 2Pg4 (see...). Figure 20 The wiring layer WL6 overlaps and is electrically coupled to conductor pattern 2Pg4 through vias. Conductor pattern 2Pg5, conductor pattern 2Pv5 and conductor pattern 2Pg4 (see...) Figure 20 The wiring pattern 2Pv5 overlaps and is electrically coupled to the conductor pattern 2Pg4 via via wiring 2vg4. In this embodiment, the conductor pattern 2Pg5 is a connection pad 2LD, which serves as an external terminal of the wiring substrate 20 for supplying a reference potential. In this embodiment, the area of ​​the conductor pattern 2Pv5 is larger than the area of ​​the conductor pattern 2Pg5. A portion of the conductor pattern 2Pv5 is included in the connection pad 2LD, which serves as an external terminal of the wiring substrate 20 for supplying a power supply potential.

[0127] like Figure 20 and Figure 21 As shown, in this embodiment, a conductor pattern with a large area for transmitting a reference potential to the wiring layer WL5 is provided, and a conductor pattern with a large area for supplying a power supply potential to the wiring layer WL6 is also provided. In this way, by providing large-area conductor patterns for the power supply potential and the reference potential in the wiring substrate 20, the potentials of the paths for supplying the power supply potential and the paths for supplying the reference potential can be stabilized.

[0128] Some modifications to the above embodiments have already been described. Now, any typical modifications other than those to the above embodiments will be described.

[0129] <First Revision>

[0130] As a structural example of a wiring substrate, a wiring substrate 20 having six wiring layers has been described, for example, in Figure 4 In the semiconductor device PKG1 shown, the number of wiring layers is not limited to six and can be modified in various ways. Figure 22 It is based on Figure 4 A modified cross-sectional view of a semiconductor device. Figure 23 It is shown in Figure 22 An enlarged plan view of an example layout of a wiring layer as the first layer on a wiring substrate. Figure 24 It is shown in Figure 23An enlarged plan view of an example layout of a wiring layer as the second layer on a wiring substrate.

[0131] Included Figure 22 Wiring substrate 21 in semiconductor device PKG2 and Figure 4 The difference in the semiconductor device PKG1 shown is that it includes a wiring layer with four layers. In the case of semiconductor device PKG2, the wiring layer WL2 is disposed on the insulating layer 2CR, which serves as the core insulating layer. Therefore, the wiring 2wv and the pattern of wiring 2wv disposed on the wiring layer WL1 need to be formed according to the arrangement of the via wiring 2TW. For example, when the arrangement spacing of the electrode 1PD is smaller than the arrangement spacing of the via wiring 2TW, if the arrangement spacing of the via wiring 2TW is smaller than the arrangement spacing of the electrode 1PD ... Figure 22 The wiring substrate 21 shown is used in conjunction with Figure 9 If the wiring layer WL1 of the wiring substrate 20 shown has the same layout, it may not be possible to properly match the positional relationship between the two end units of the sub-wiring units 2wv2 and 2wg2 and the conductor patterns 2Pw2 and 2Pg2 of the wiring layer WL2. For example... Figure 23 As shown, with Figure 9 Compared to the lengths shown in the example, the lengths of sub-wiring unit 2wv2 and sub-wiring unit 2wg2 in the "Y" direction can be longer.

[0132] exist Figure 23 In the example shown, in wiring 2wv, terminal 2PDv is disposed in the two end units of sub-wiring unit 2wv2 and main wiring unit 2wv1, and also between the end units of main wiring unit 2wv1 and sub-wiring unit 2wv2s. Via wiring 2vv is coupled to the two end units of sub-wiring unit 2wv2, but not to any other components. Similarly, in wiring 2wg, terminal 2PDg is disposed in the two end units of sub-wiring unit 2wg2 and also in main wiring unit 2wg1, and also between the end units of main wiring unit 2wg1 and sub-wiring unit 2wg2. Via wiring 2vg is coupled to the two end units of sub-wiring unit 2wg2, but not to any other components.

[0133] exist Figure 24 In the example shown, to reduce the impedance of the paths used to supply power and reference potentials, via traces 2TWv and 2TWg are arranged in multiple rows in the "Y" direction. Figure 24 (Two lines in the text). Therefore, with Figure 11Compared to the width (length) of conductor pattern 2Pv1 and conductor pattern 2Pg1 shown, conductor pattern 2Pv2, which overlaps with the main wiring unit 2wg1 of wiring 2wg, and conductor pattern 2Pg2, which overlaps with the main wiring unit 2wv1 of wiring 2wv, have a larger width (length) in the "Y" direction. According to this modification, even when conductor patterns 2Pv2 and 2Pg2 have a large width, multiple paths for supplying power supply potential and multiple paths for supplying reference potential can still be provided.

[0134] If the lengths of sub-routing units 2wv2 and 2wg2 are increased, the lengths of the paths used to supply power potential and the paths used to supply reference potential will be increased. Figure 9 The example shown is long. From the viewpoint of shortening the path distance of the conductive path, as... Figure 9 As shown, terminal 2PDv is preferably disposed in the two end units of sub-routing unit 2wv2 and in main wiring unit 2wv1, but preferably not disposed between the end units of main wiring unit 2wv1 and sub-routing unit 2wv2. Terminal 2PDg is preferably disposed in the two end units of sub-routing unit 2wg2 and in main wiring unit 2wg1, but preferably not disposed between the end units of main wiring unit 2wg1 and sub-routing unit 2wg2.

[0135] exist Figure 4 The semiconductor device PKG1 shown is Figure 22 In the case of the semiconductor device PKG2 shown, wiring 2wg and wiring 2wv are arranged on the uppermost wiring layer WL1, and a portion of wiring 2wg and wiring 2wv is configured to form terminals 2PDs for wiring substrates 20 and 21. However, as a modification, a wiring layer on an upper layer (upper surface 20t side) is provided for arranging terminals 2PDs above wiring layer WL1. In this case, wiring 2wg and wiring 2wv are formed on the lower layer of the wiring layer on which terminals 2PDs are formed, and are electrically coupled via vias (not shown). In this modification, some space is provided for arranging terminals 2PDs, thereby increasing the area of ​​the conductor pattern of terminals 2PDs. From the viewpoint of shortening the paths used for supplying power supply potential and reference potential, wiring 2wg and wiring 2wv are preferably arranged on the uppermost layer, as shown. Figure 4 and Figure 22 As shown.

[0136] In addition to the differences mentioned above Figures 22 to 24 The wiring substrate 21 shown can be with Figure 4 The wiring substrate 20 shown is the same. Therefore, it will not be described again.

[0137] <Second Revision>

[0138] For example, in Figure 4 The case of semiconductor chip 10 and wiring substrate 20 being electrically coupled via bump electrodes SB has already been described. The application of the above techniques to wiring devices in which semiconductor chip 10 and wiring substrate 20 are electrically coupled to each other via wiring should not be excluded. However, it should be noted that from the viewpoint of reducing the impedance of the conductive path used for electrically coupling wiring substrate 20 and semiconductor chip 10, it is particularly preferred to apply a flip-chip coupling system as described above. From the viewpoint of shortening the paths used for supplying power supply potential and for supplying reference potential in wiring substrate 20, the application of a flip-chip coupling system is particularly preferred.

[0139] Third revision

[0140] For example, various modifications have been described, and these modifications can be combined together for application.

[0141] The invention has been specifically described based on preferred embodiments. The invention is not limited to the preferred embodiments, but various changes can be made without departing from its scope.

Claims

1. A semiconductor device, characterized by, comprises: a semiconductor chip having a first surface, a first back surface on a side opposite to the first surface, and a plurality of electrodes arranged on the first surface; and a wiring substrate having a first main surface on which the semiconductor chip is mounted, a second main surface on a side opposite to the first main surface, a first wiring layer formed between the first main surface and the second main surface, and a second wiring layer formed between the first wiring layer and the second main surface and adjacent to the first wiring layer in a direction crossing the first main surface in a cross-sectional view, wherein the first wiring layer has: a first wiring having a first main wiring unit extending in a first direction in a plan view and a plurality of first sub-wiring units extending in a second direction crossing the first direction and crossing the first main wiring unit, and being supplied with a first potential, a second wiring having a second main wiring unit extending in the first direction in the plan view and a plurality of second sub-wiring units extending in the second direction and crossing the second main wiring unit, and being supplied with a second potential different from the first potential, wherein the first sub-wiring units of the first wiring and the second sub-wiring units of the second wiring: have first end portion units and second end portion units on a side opposite to the first end portion units, the first end portion units and the second end portion units passing through the first main wiring unit or the second main wiring unit in the second direction, and are alternately arranged between the first main wiring unit and the second main wiring unit in the first direction, wherein the second wiring has: a first conductor pattern overlapping the first end portion units of the first sub-wiring units of the first wiring and the second main wiring unit of the second wiring, and extending in the first direction, and a second conductor pattern overlapping the first main wiring unit of the first wiring and the second end portion units of the second sub-wiring units of the second wiring, wherein the first end portion units of the first sub-wiring units are electrically coupled with the first conductor pattern through a plurality of first vias, and wherein the second end portion units of the second sub-wiring units are electrically coupled with the second conductor pattern through a plurality of second vias.

2. The semiconductor device according to claim 1, wherein: the first surface of the semiconductor chip is opposite to the first main surface of the wiring substrate; the electrodes of the semiconductor chip include: a plurality of first electrodes electrically coupled to the first wiring of the wiring substrate, and a plurality of second electrodes electrically coupled to the second wiring of the wiring substrate, and the wiring substrate has: ​ a plurality of first terminals opposing and electrically coupled to the first electrodes of the semiconductor chips, and a plurality of second terminals opposing and electrically coupled to the second electrodes of the semiconductor chips.

3. The semiconductor device according to claim 2, wherein the wiring substrate has a first insulating film covering the first wiring layer and including a plurality of openings, the first wiring has the first terminals exposed from the first insulating film in the openings included in the first insulating film, the second wiring has the second terminals exposed from the first insulating film in the openings included in the first insulating film, the first electrodes of the semiconductor chips and the first terminals are coupled by first bump electrodes, and the second electrodes of the semiconductor chips and the second terminals are coupled by second bump electrodes.

4. The semiconductor device according to claim 3, wherein the first terminals include a plurality of third terminals formed in the first end units and the second end units of the first sub-wiring units, and the second terminals include a plurality of fourth terminals formed in the first end units and the second end units of the second sub-wiring units.

5. The semiconductor device according to claim 4, wherein the third terminals respectively overlap the first vias, and the fourth terminals respectively overlap the second vias.

6. The semiconductor device according to claim 4, wherein the first terminals include a fifth terminal formed in the first main-wiring unit, and the second terminals include a sixth terminal formed in the second main-wiring unit.

7. The semiconductor device according to claim 6, wherein the fifth terminal does not overlap the first vias, and the sixth terminal does not overlap the second vias.

8. The semiconductor device according to claim 1, wherein the second wiring layer has a third conductor pattern overlapping the second end units of the first sub-wiring units of the first wiring and extending in the first direction, the second conductor pattern is disposed between the first conductor pattern and the third conductor pattern in a plan view, and the second end units of the first sub-wiring units are electrically coupled to the third conductor pattern through the first vias.

9. The semiconductor device according to claim 8, wherein the second wiring layer has the second conductor pattern arranged between the first conductor pattern and the third conductor pattern in the second direction and arranged in a row along the first direction, and the first conductor pattern and the third conductor pattern are electrically coupled to each other through connection units formed between the second conductor pattern.

10. The semiconductor device according to claim 8, wherein the second wiring layer has a fourth conductor pattern overlapping the first end units of the second sub-wiring units of the second wiring, the first conductor pattern is formed between the second conductor pattern and the fourth conductor pattern in a plan view, and the first end portion unit of the second sub-wiring unit is electrically coupled with the fourth conductor pattern through the second via.

11. The semiconductor device according to claim 10, wherein the second wiring layer has the second conductor pattern arranged between the first conductor pattern and the third conductor pattern in the second direction and arranged in a row along the first direction, and the second conductor patterns are electrically coupled with each other through the second wiring of the first wiring layer.

12. The semiconductor device according to claim 1, wherein the wiring substrate has a third wiring layer formed between the second wiring layer and the second main surface and adjacent to the second wiring layer in a cross-sectional view in a direction intersecting the first main surface, the third wiring layer has: a third conductor pattern overlapping the first conductor pattern, electrically coupled with the first conductor pattern through a plurality of third vias, and extending in the first direction, and a fourth conductor pattern overlapping the second conductor pattern, electrically coupled with the second conductor pattern through a plurality of fourth vias, and extending in the first direction.

13. The semiconductor device according to claim 12, wherein the wiring substrate has: a fourth wiring layer formed between the third wiring layer and the second main surface, and a plurality of via wirings for electrically coupling the third wiring layer and the fourth wiring layer, and the via wirings include: a plurality of first via wirings coupled to the third conductor pattern in the third wiring layer; and a plurality of second via wirings coupled to the fourth conductor pattern in the third wiring layer.

14. The semiconductor device according to claim 13, wherein an arrangement pitch of electrodes of the semiconductor chip is smaller than an arrangement pitch of via wirings of the wiring substrate.

15. The semiconductor device according to claim 1, wherein the first wiring layer of the wiring substrate has a plurality of first wirings and a plurality of second wirings, and the first wirings and the second wirings are alternately arranged in the second direction in a plan view.

16. The semiconductor device according to claim 1, wherein the first wiring layer has a third wiring having: a third main wiring unit extending in the first direction in a plan view; and a plurality of third sub-wiring units extending in the second direction and intersecting the third main wiring unit, and the third wiring is supplied with the second potential, the first wiring is arranged between the second wiring and the third wiring in the second direction, the third sub-wiring unit of the third wiring has the first end portion unit passing through the third main wiring unit in the second direction and the second end portion unit on a side opposite to the first end portion unit, the first sub-wiring units and the third sub-wiring units are alternately arranged between the first main-wiring units and the third main-wiring units in the first direction, the second wiring layer has a third conductor pattern that overlaps the third main-wiring units of the third wiring and the second end portion units of the first sub-wiring units of the first wiring, the second end portion units of the first sub-wiring units are electrically coupled with the third conductor pattern through the first via, and the first end portion units of the third sub-wiring units are electrically coupled with the second conductor pattern through the second via.

17. The semiconductor device according to claim 1, wherein the first wiring layer has a fourth wiring that has: a fourth main-wiring unit extending in the first direction in a plan view; and a plurality of fourth sub-wiring units extending in the second direction and crossing the fourth main-wiring unit, the fourth wiring being supplied with the first potential, the second wiring is arranged between the first wiring and the fourth wiring in the second direction, each of the fourth sub-wiring units of the fourth wiring has the first end portion unit and the second end portion unit on the side opposite to the first end portion unit passing through the fourth main-wiring unit in the second direction, the second sub-wiring units and the fourth sub-wiring units are alternately arranged between the second main-wiring units and the fourth main-wiring units in the first direction, the second wiring layer has a fourth conductor pattern that overlaps the fourth main-wiring units of the fourth wiring and the first end portion units of the second sub-wiring units of the second wiring, the first end portion units of the second sub-wiring units are electrically coupled with the fourth conductor pattern through the second via, and the first end portion units of the fourth sub-wiring units are electrically coupled with the first conductor pattern through the first via.

18. The semiconductor device according to claim 1, wherein the semiconductor chip has a circuit that is driven by a potential difference between the first potential and the second potential, and the second potential is a ground potential, and the first potential is a power supply potential different from the ground potential. ​

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