Multi-chip wafer level package and method of forming the same

Abstract

Embodiments of the present invention provide a variety of multi-chip wafer-level packages and methods for forming the same. A multi-chip wafer-level package includes a first level and a second level. The first level includes a first redistribution layer structure and at least one chip located on the first redistribution layer structure. The second level includes a second redistribution layer structure and at least two other chips located on the second redistribution layer structure. The first level is bonded to the second level so that the at least one chip physically contacts the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Description

Technical Field

[0001] The embodiment of the present invention relates to a multi-chip wafer level package and a forming method thereof. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continued improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) In large part, this increase in integration density comes from the continuous reduction in minimum feature size, which enables more components to be integrated into a given area.

[0003] These smaller electronic components also require smaller packages that occupy a smaller area compared to previous packages. Examples of semiconductor package types include quad flat package (QFP), pin grid array (PGA) package, ball grid array (BGA) package, flip chip (FC), three-dimensional integrated circuit (3DIC), wafer level package (WLP), and package on package (PoP) devices. A multi-chip wafer level package has emerged to further reduce the physical size of the package. However, there are many challenges associated with such multi-chip wafer level packages. Summary of the invention

[0004] According to some embodiments of the present invention, a multi-chip wafer-level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip located on the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips located on the second redistribution layer structure. The first tier is bonded to the second tier so that the at least one chip physically contacts the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1A to 1G is a cross-sectional view of a method of forming a multi-chip wafer level package according to some embodiments.

[0006] Figures 2 to 6 is a cross-sectional view of a multi-chip wafer level package according to some embodiments.

[0007] FIG. 7A to FIG. 7Gis a cross-sectional view of a method of forming a multi-chip wafer level package according to an alternative embodiment.

[0008] Figures 8 to 10 is a cross-sectional view of a multi-chip wafer level package according to an alternative embodiment.

[0009] Figures 11 to 14 are cross-sectional views of multi-chip wafer level packages according to yet other alternative embodiments.

[0010] Figure 15 to Figure 16 is a cross-sectional view of a semiconductor chip according to some embodiments.

[0011] Figures 17 to 20 is a cross-sectional view of a semiconductor chip according to an alternative embodiment. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of elements and arrangements are described below for the purpose of conveying the present disclosure in a simplified manner. Of course, these are only examples and are not intended to be limiting. For example, the following description in which the second feature is formed "on" or "on" the first feature may include an embodiment in which the second feature and the first feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature, thereby making the second feature and the first feature may not be in direct contact. In addition, the same reference numbers and / or letters may be used to refer to the same or similar parts in each example of the present disclosure. The repeated use of reference numbers is for the purpose of brevity and clarity, rather than the relationship between the various embodiments and / or configurations discussed by themselves.

[0013] Additionally, spatially relative terms, such as “beneath,” “below,” “lower,” “on,” “over,” “overlying,” “above,” “upper,” etc., may be used herein to facilitate describing the relationship of one element or feature to another (other) element or feature as depicted in a figure. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0014] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate so that the three-dimensional package or the three-dimensional integrated circuit can be tested, a probe and / or a probe card can be used, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in combination with a test method including intermediate verification of known good dies to improve yield and reduce costs.

[0015] Figures 1A to 1G is a cross-sectional view of a method of forming a multi-chip wafer level package according to some embodiments.

[0016] Reference Figure 1A , providing a carrier C on which a first redistribution layer structure RDL1 is formed. In some embodiments, a peeling layer DB is formed between the carrier C and the first redistribution layer structure RDL1. In some embodiments, the carrier C is a non-semiconductor material, such as a glass carrier, a ceramic carrier, and the like. In some embodiments, the peeling layer DB includes an ultraviolet (UV) glue, a light-to-heat conversion (LTHC) glue, and the like, but other types of adhesives may also be used. The peeling layer DB may be decomposed under the heat of light, thereby releasing the carrier C from the structure formed on the carrier C.

[0017] In some embodiments, the first redistribution layer structure RDL1 is referred to as a "back-side redistribution layer structure" throughout the specification. In some embodiments, the first redistribution layer structure RDL1 includes a plurality of redistribution layers 104 embedded by a plurality of polymer layers 102. In some embodiments, each of the redistribution layers 104 comprises copper, nickel, titanium, a combination thereof, or the like, and is formed by photolithography, plating, and a photoresist stripping process. In some embodiments, each of the polymer layers 102 comprises a polymer material (e.g., polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like), and is formed by a suitable manufacturing technique such as spin coating, lamination, and deposition.

[0018] Reference Figure 1B, a plurality of integrated fan-out through-via TIVs are formed on the first redistribution layer structure RDL1. In some embodiments, the integrated fan-out through-via TIVs extend into the uppermost polymer layer 102 and are electrically connected to the uppermost redistribution layer 104. In some embodiments, the integrated fan-out through-via TIVs include copper, nickel, titanium, combinations thereof, or similar materials, and are formed by photolithography, plating, and photoresist stripping processes.

[0019] Reference Figure 1C , the first semiconductor chip 100 and the second semiconductor chip 200 are placed on the first side of the first redistribution layer structure RDL1 and bonded to the first side of the first redistribution layer structure RDL1.

[0020] In some embodiments, the first semiconductor chip 100 includes a substrate 100a, one or more pads 100b, a protective layer 100c, and one or more connectors 100d. The substrate 100a includes (for example but not limited to) an active layer of a doped or undoped bulk silicon or a semiconductor-on-insulator (SOI) substrate. The pad 100b is formed on the substrate 100a, and the protective layer 100c is formed on the pad 100b. In some embodiments, the pad 100b is an aluminum pad, and the protective layer 100c includes a polymer material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or a similar material. The connector 100d is formed through the protective layer 100c and is electrically connected to the underlying pad 100b or the internal connection structure. In some embodiments, the connector 100d is formed as the top portion of the first semiconductor chip 100. The connector 100d protrudes from the rest or lower portion of the first semiconductor chip 100. Throughout this description, the side of the first semiconductor chip 100 having the connector 100d is referred to as the front side. The connector 100d may include Cu, W, Ni, Sn, Ti, Au, an alloy thereof, or a combination thereof, and is formed using a ball drop process or an electroplating process. In some embodiments, the pad 100b constitutes a portion of the connector of the first semiconductor chip 100. In some embodiments, the pad 100b and / or the connector 100d constitute the front side connector of the first semiconductor chip 100.

[0021] In some embodiments, the second semiconductor chip 200 includes a substrate 200a, one or more pads 200b, a protection layer 200c, and one or more connectors 200d. The materials and arrangement of the components of the second semiconductor chip 200 are similar to those of the first semiconductor chip 100, so these details will not be repeated herein.

[0022] In some embodiments, each of the first semiconductor chip 100 and the second semiconductor chip 200 includes an integrated passive device, such as a capacitor, an inductor, or a resistor. In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 are referred to as "first integrated passive device chip and second integrated passive device chip" throughout the specification. In some embodiments, each of the first semiconductor chip 100 and the second semiconductor chip 200 is configured as a capacitor operating at a high frequency of about 1 GHz or greater than 1 GHz. In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 are referred to as "high-frequency capacitors" throughout the specification. In some embodiments, based on process requirements, the first semiconductor chip 100 and the second semiconductor chip 200 are capacitors with different capacitance values, resonance frequencies, and / or different sizes. Specifically, as Fig.15 As shown, the first semiconductor chip 100' further has a deep trench capacitor region CA1 located between the substrate 100a and the pad 100b, and the second semiconductor chip 200' further has a deep trench capacitor region CA2 located between the substrate 200a and the pad 200b. However, the present disclosure is not limited thereto. In alternative embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 are designed to have the same size, function, and / or operating range as required.

[0023] Reference Figure 1D , the first semiconductor chip 100 and the second semiconductor chip 200 are encapsulated by the first encapsulation layer E1. In some embodiments, the first encapsulation layer E1 is formed on the carrier C to encapsulate or surround the sidewalls of the integrated fan-out through-hole TIV and the sidewalls of the first semiconductor chip 100 and the sidewalls of the second semiconductor chip 200. In some embodiments, the first encapsulation layer E1 includes a molding compound, a molding underfill, a resin, etc. (e.g., epoxy). In some embodiments, the first encapsulation layer E1 includes a polymer material (e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or the like), and is formed by performing a molding process and then performing a grinding process until the surface of the integrated fan-out through-hole TIV and the surface of the connector 100d of the first semiconductor chip 100 and the surface of the connector 200d of the second semiconductor chip 200 are exposed.

[0024] Afterwards, a second redistribution layer structure RDL2 is formed on the first encapsulation layer E1. In some embodiments, the second redistribution layer structure RDL2 is referred to as a "front-side redistribution layer structure" throughout the specification. In some embodiments, the second redistribution layer structure RDL2 includes a plurality of redistribution layers 108 embedded by a plurality of polymer layers 106. In some embodiments, each of the redistribution layers 108 comprises copper, nickel, titanium, a combination thereof, or a similar material, and is formed by photolithography, plating, and photoresist stripping processes. In some embodiments, each of the polymer layers 106 comprises a polymer material (e.g., polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or a similar material), and is formed by suitable manufacturing techniques such as spin coating, lamination, and deposition. In some embodiments, the second redistribution layer structure RDL2 also includes a plurality of connection pads 110, which are configured to be connected to other semiconductor chips.

[0025] In some embodiments, the critical dimension of the second redistribution layer structure RDL2 is smaller than that of the first redistribution layer structure RDL1. In alternative embodiments, the critical dimension of the second redistribution layer structure RDL2 may be substantially the same as or larger than that of the first redistribution layer structure RDL1 as desired.

[0026] Reference Figure 1E and Figure 1F , the third semiconductor chip 300 and the fourth semiconductor chip 400 are placed on the second redistribution layer structure RDL2 and bonded to the second redistribution layer structure RDL2.

[0027] like Figure 1EAs shown, a third semiconductor chip 300 and a fourth semiconductor chip 400 are provided. In some embodiments, the third semiconductor chip 300 includes a substrate 300a, one or more pads 300b, a protective layer 300c, one or more connectors 300d, and one or more bumps 300e. The substrate 300a includes (for example but not limited to) an active layer of a doped or undoped bulk silicon or a semiconductor on insulator (SOI) substrate. The pad 300b is formed on the substrate 300a, and the protective layer 300c is formed on the pad 300b. In some embodiments, the pad 300b is an aluminum pad, and the protective layer 300c includes a polymer material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or a similar material. The connector 300d is formed through the protective layer 300c and is electrically connected to the underlying pad 300b or the internal connection structure. In some embodiments, the connector 300d is formed as the top portion of the third semiconductor chip 300. The connector 300d protrudes from the rest or lower part of the third semiconductor chip 300. Throughout this description, the side of the third semiconductor chip 300 with the connector 300d is referred to as the front side. The connector 300d may include a copper column and is formed using an electroplating process. The bump 300e is formed on the connector 300d. In some embodiments, the bump 300e may include a solder bump and is formed using a drop ball process or an electroplating process. In some embodiments, the pad 300b and / or the bump 300e constitute a part of the connector of the third semiconductor chip 300. In some embodiments, the pad 300b, the connector 300d and / or the bump 300e constitute the front side connector of the third semiconductor chip 300.

[0028] In some embodiments, the fourth semiconductor chip 400 includes a substrate 400a, one or more pads 400b, a protective layer 400c, one or more connectors 400d, and one or more bumps 400e. The materials and arrangement of the components of the fourth semiconductor chip 400 are similar to those of the third semiconductor chip 300, so these details will not be repeated herein.

[0029] In some embodiments, each of the third semiconductor chip 300 and the fourth semiconductor chip 400 includes an integrated active device, such as a logic device. The logic device includes an application processor (AP), a system on chip (SoC), etc. In some embodiments, the system on chip (SoC) includes a modem module. Other types of active devices, such as memory devices, metal oxide semiconductor field effect transistors (MOSFET) devices, CMOS devices, and / or bipolar junction transistors (BJT) devices, may be used based on process requirements. In some embodiments, the third semiconductor chip 300 and the fourth semiconductor chip 400 are referred to as "first integrated active device chip and second integrated active device chip" throughout the specification. In some embodiments, the third semiconductor chip 300 and the fourth semiconductor chip 400 are active devices with different functions and / or different sizes. In an alternative embodiment, the third semiconductor chip 300 and the fourth semiconductor chip 400 are designed to have the same size and / or function as needed. In some embodiments, at least one of the third semiconductor chip 300 and the fourth semiconductor chip 400 is electrically connected to six or more integrated passive device chips to form a multi-chip module. This arrangement helps increase the bandwidth of the product and reduce the package size compared to other approaches.

[0030] like Figure 1F As shown, the third semiconductor chip 300 and the fourth semiconductor chip 400 are bonded to the second redistribution layer structure RDL2 and are located above the first semiconductor chip 100 and the second semiconductor chip 200. In some embodiments, the bumps 300e of the third semiconductor chip 300 and the bumps 400e of the fourth semiconductor chip 400 are bonded to the connection pads 110 of the second redistribution layer structure RDL2.

[0031] In some embodiments, the total number of connectors 300d of the third semiconductor chip 300 and the connectors 400d of the fourth semiconductor chip 400 is greater than (e.g., at least two times, at least five times, or at least eight times) the total number of connectors 100d of the first semiconductor chip 100 and the connectors 200d of the second semiconductor chip 200.

[0032] Afterwards, an underfill layer UF is formed to fill the space between the second redistribution layer structure RDL2 and each of the third semiconductor chip 300 and the fourth semiconductor chip 400. In some embodiments, the underfill layer UF is formed to surround the connectors 300d and 400d and the bumps 300e and 400e. In some embodiments, the underfill layer UF includes a molding compound (e.g., epoxy resin) and is formed using dispensing, injecting, and / or spraying techniques.

[0033] Then, the third semiconductor chip 300 and the fourth semiconductor chip 400 are encapsulated with the second encapsulation layer E2. In some embodiments, the second encapsulation layer E2 is formed on the second redistribution layer structure RDL2 to encapsulate or surround the sidewalls and top of the third semiconductor chip 300 and the sidewalls and top of the fourth semiconductor chip 400. In some embodiments, the second encapsulation layer E2 includes a molding compound, a molding bottom filler, a resin (e.g., an epoxy resin), etc. In some embodiments, the second encapsulation layer E2 includes a polymer material (e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or a similar material) and is formed by a molding process. In some embodiments, the first encapsulation layer E1 and the second encapsulation layer E2 include the same material. In an alternative embodiment, the second encapsulation layer E2 includes a material different from that of the first encapsulation layer E1.

[0034] Reference Figure 1G , the carrier C is peeled off from the second side of the first redistribution layer structure RDL1. In some embodiments, the peeling layer DB is decomposed under the heat of light, and then the carrier C is released from the structure formed on the carrier C.

[0035] Afterwards, the bottom polymer layer 102 is patterned to form an opening to expose the connection pad of the first redistribution layer structure RDL1 or the bottom redistribution layer 104. In some embodiments, the opening is formed by a laser drilling process, a dry etching process, or a suitable patterning process. Afterwards, the bump 112 is placed on the second side of the first redistribution layer structure RDL1 and bonded to the connection pad of the first redistribution layer structure RDL1. In some embodiments, the bump 112 may be a solder bump, and / or may include a metal column (e.g., a copper column), a solder cap formed on the metal column, and / or the like. The bump 112 may be formed by a suitable process such as evaporation, electroplating, ball drop, or screen printing. The multi-chip wafer-level package 1 is thereby completed. In some embodiments, the multi-chip wafer-level package 1 is composed of a first level T1 and a second level T2 that are in physical contact with each other. In some embodiments, the first level T1 includes a first redistribution layer structure RDL1 and first and second semiconductor chips 100 and 200 located thereon, and the second level T2 includes a second redistribution layer structure RDL2 and third and fourth semiconductor chips 300 and 400 located thereon.

[0036] In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 are configured to keep the level voltage of the third semiconductor chip 300 and the fourth semiconductor chip 400 relatively stable decoupling capacitors. Specifically, during circuit operation, the power line supplies a transient current with a relatively high intensity, which can cause voltage fluctuations on the power line. This problem has not been observed in the present disclosure. In some embodiments, the decoupling capacitor (e.g., the first semiconductor chip 100 and the second semiconductor chip 200) is arranged close to the active device (e.g., the third semiconductor chip 300 and the fourth semiconductor chip 400) (e.g., correspondingly located below the active element) and acts as a charge reservoir that additionally supplies current to the active device to prevent the power supply voltage from dropping momentarily. In some embodiments, since the decoupling capacitor (e.g., the first semiconductor chip 100 and the second semiconductor chip 200) is provided, the number of TIVs can be reduced, and therefore the TIV pitch can be increased. The pattern pitch of the first redistribution layer structure RDL1 can therefore be increased. Therefore, the process window can be widened and the production cost can be saved.

[0037] Possible modifications and variations may be made to the multi-chip wafer level package. These modifications and variations are provided for illustrative purposes and should not be considered as limiting the present disclosure. Figures 2 to 6 is a cross-sectional view of a multi-chip wafer level package according to some embodiments.

[0038] Figure 2 The multi-chip wafer level package 2 shown in FIG. Figure 1G The multi-chip wafer-level package 1 is similar to the multi-chip wafer-level package 1 shown, and the difference therebetween is that the multi-chip wafer-level package 2 also includes a fifth semiconductor chip 500 and a sixth semiconductor chip 600. In some embodiments, each of the fifth semiconductor chip 500 and the sixth semiconductor chip 600 includes an integrated passive device, such as a capacitor, an inductor, or a resistor. In some embodiments, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are referred to as "third integrated passive device chip and fourth integrated passive device chip" throughout the specification. In some embodiments, each of the fifth semiconductor chip 500 and the sixth semiconductor chip 600 is configured as a capacitor operating at a low frequency of about 1KHz or less than 1KHz. In some embodiments, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are referred to as "low-frequency capacitors" throughout the specification. In some embodiments, based on process requirements, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are capacitors with different capacitance values, resonant frequencies, and / or different sizes. In an alternative embodiment, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are designed to have the same size, function, and / or operating range as needed. In some embodiments, when the first semiconductor chip 100 and the second semiconductor chip 200 are placed on and bonded to the first redistribution layer structure RDL1, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are placed on and bonded to the first redistribution layer structure RDL1 through their bumps 501 and bumps 601.

[0039] Figure 3 The multi-chip wafer level package 3 shown in FIG. Figure 2 The multi-chip wafer level package 2 shown is similar, the difference between them is that Figure 2 The fifth semiconductor chip 500 and the sixth semiconductor chip 600 are bonded to the first redistribution layer structure RDL1. Figure 3The fifth semiconductor chip 500 and the sixth semiconductor chip 600 are shown bonded to the second rewiring layer structure RDL2. In some embodiments, when the third semiconductor chip 300 and the fourth semiconductor chip 400 are placed on the second rewiring layer structure RDL2 and bonded to the second rewiring layer structure RDL2, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are placed on the second rewiring layer structure RDL2 and bonded to the second rewiring layer structure RDL2 through their bumps 501 and 601.

[0040] Figure 4 The multi-chip wafer level package 4 shown in FIG. Figure 1G The multi-chip wafer level package 1 shown is similar, the difference between them is that Figure 1G Each of the first semiconductor chip 100 and the second semiconductor chip 200 is a single-sided semiconductor chip having connectors 100d and 200d on a single side, the connectors 100d and 200d being bonded to the second redistribution layer structure RDL2, and Figure 4 Each of the illustrated first and second semiconductor chips 101 and 201 is a double-sided semiconductor chip having connections on opposite sides, the connections being bonded to the first and second redistribution layer structures RDL1 and RDL2 , respectively.

[0041] In some embodiments, the first semiconductor chip 101 is similar to the first semiconductor chip 100, and the difference therebetween is that the first semiconductor chip 101 further includes one or more pads 100e located in the back side portion of the first semiconductor chip 101 and one or more through silicon vias TSV1 located between the front side pad 100b and the back side pad 100e and electrically connected to the front side pad 100b and the back side pad 100e. In some embodiments, the back side pad 100e is embedded by a polymer material (e.g., polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or a similar material). In some embodiments, a bump is formed at the back side of the first semiconductor chip 101 and the bump is bonded to the pad 100e. In an alternative embodiment, the back side pad 100e is connected to the first redistribution layer structure RDL1, and there is no bump therebetween. In some embodiments, the bottom surface of the first semiconductor chip is not coplanar with the top surface of the first redistribution layer structure RDL1. For example, the bumps are inserted into the top polymer layer of the first redistribution layer structure RDL1. In an alternative embodiment, the bottom surface of the first semiconductor chip is coplanar with the top surface of the first redistribution layer structure RDL1. In some embodiments, the pads 100b and / or the connectors 100d constitute the front side connectors of the first semiconductor chip 100, and the pads 100e and / or the optional bumps constitute the back side connectors of the first semiconductor chip 100.

[0042] In some embodiments, the second semiconductor chip 201 is similar to the second semiconductor chip 200, and the difference therebetween is that the second semiconductor chip 201 further includes one or more pads 200e located in the back side portion of the second semiconductor chip 201 and one or more through silicon vias TSV2 located between and electrically connected to the front side pads 200b and the back side pads 200e. The materials and arrangement of the elements of the second semiconductor chip 201 are similar to those of the first semiconductor chip 101, and therefore these details will not be repeated herein.

[0043] In some embodiments, each of the first semiconductor chip 101 and the second semiconductor chip 201 includes an integrated passive device, such as a capacitor, an inductor, or a resistor. In some embodiments, each of the first semiconductor chip 101 and the second semiconductor chip 201 is configured as a capacitor operating at a high frequency of about 1 GHz or greater than 1 GHz. In some embodiments, the first semiconductor chip 101 and the second semiconductor chip 201 are referred to as "high frequency capacitors" throughout the specification. In some embodiments, based on process requirements, the first semiconductor chip 101 and the second semiconductor chip 201 are capacitors with different capacitance values, resonant frequencies, and / or different sizes. Specifically, as Fig.16 As shown, the first semiconductor chip 101' further has a deep trench capacitor region CA1 located between the substrate 100a and the pad 100b, and the deep trench capacitor region CA1 is separated from the through silicon via TSV1 by a keep out zone (KOZ). Similarly, the second semiconductor chip 201' further has a deep trench capacitor region CA2 located between the substrate 200a and the pad 200b, and the deep trench capacitor region CA2 is separated from the through silicon via TSV2 by a keep out zone (KOZ).

[0044] Figure 5 The multi-chip wafer level package 5 shown in FIG. Figure 2 The multi-chip wafer level package 2 shown is similar, the difference between them is that Figure 2 Each of the first semiconductor chip 100 and the second semiconductor chip 200 is a single-sided semiconductor chip. Figure 5 Each of the illustrated first semiconductor chip 101 and second semiconductor chip 201 is a double-sided semiconductor chip.

[0045] Figure 6 The multi-chip wafer level package 6 shown in FIG. Figure 3 The multi-chip wafer level package 3 shown is similar, the difference between them is that Figure 3 Each of the first semiconductor chip 100 and the second semiconductor chip 200 is a single-sided semiconductor chip. Figure 6Each of the illustrated first semiconductor chip 101 and second semiconductor chip 201 is a double-sided semiconductor chip.

[0046] In the above embodiments, each of the multi-chip wafer level packages is formed using a single carrier, which is for illustrative purposes only and should not be considered as limiting the present disclosure. In alternative embodiments, the multi-chip wafer level package may be formed using two carriers.

[0047] FIG. 7A to FIG. 7G is a cross-sectional view of a method of forming a multi-chip wafer level package according to an alternative embodiment.

[0048] Reference Fig. 7A , providing a first carrier C1 on which a first redistribution layer structure RDL1 is formed. In some embodiments, a first peeling layer DB1 is formed between the first carrier C1 and the first redistribution layer structure RDL1. In some embodiments, the first redistribution layer structure RDL1 includes a plurality of redistribution layers 104 embedded by a plurality of polymer layers 102. In some embodiments, the first redistribution layer structure RDL1 also includes a plurality of connection pads 103 configured to be connected to other semiconductor chips. In some embodiments, a plurality of bumps 105 are formed on the connection pads 103 of the first redistribution layer structure RDL1. The bumps 105 may include solder bumps and are formed using a ball drop process or an electroplating process.

[0049] Then, a chip module CM is provided. In some embodiments, the chip module CM may include FIG. 7B to FIG. 7D The method is formed by the steps shown. Figure 7B As shown, a second carrier C2 on which a second peeling layer DB2 is formed is provided. Afterwards, a plurality of integrated fan-out through-hole TIVs are formed on the second peeling layer DB2. Then, the first semiconductor chip 101 and the second semiconductor chip 201 are placed on the second carrier C2. In some embodiments, the second peeling layer DB2 is formed between the second carrier C2 and the back side of each of the first semiconductor chip 101 and the second semiconductor chip 201. In some embodiments, the first semiconductor chip 101 and the second semiconductor chip 201 are alternately arranged on the second peeling layer DB2. Next, the first semiconductor chip 101 and the second semiconductor chip 201 are encapsulated by the first encapsulation layer E1. Then, a second redistribution layer structure RDL2 is formed on the first encapsulation layer E1.

[0050] In some embodiments, the critical dimension of the second redistribution layer structure RDL2 may be smaller than that of the first redistribution layer structure RDL1. In alternative embodiments, the critical dimension of the second redistribution layer structure RDL2 may be substantially the same as or larger than that of the first redistribution layer structure RDL1 as desired.

[0051] like Figure 7C As shown, the third semiconductor chip 300 and the fourth semiconductor chip 400 are placed on the second redistribution layer structure RDL2 and bonded to the second redistribution layer structure RDL2. In some embodiments, a plurality of third semiconductor chips 300 and a plurality of fourth semiconductor chips 400 are alternately arranged on the second redistribution layer structure RDL2. In some embodiments, the third semiconductor chips 300 correspond to the first semiconductor chips 101, respectively, and the fourth semiconductor chips 400 correspond to the second semiconductor chips 201, respectively.

[0052] Afterwards, an underfill layer UF1 is formed to fill the space between the second redistribution layer structure RDL2 and each of the third semiconductor chip 300 and the fourth semiconductor chip 400 .

[0053] like Fig.7D As shown, the second carrier C2 is peeled off from the back side of the first semiconductor chip 101 and the back side of the second semiconductor chip 201. In some embodiments, bumps may be formed at the back side of the first semiconductor chip 101 and the back side of the second semiconductor chip 201 and the bumps are bonded to the back side pads. Then a singulation process is performed to separate the chip modules CM from each other. In at least one embodiment, the edge of the third semiconductor chip 300 and the edge of the fourth semiconductor chip 400 are substantially aligned with the edge of the second redistribution layer structure RDL2.

[0054] In some embodiments, each of the chip modules CM includes: a second redistribution layer structure RDL2; a first semiconductor chip 101 and a second semiconductor chip 201, located on one side of the second redistribution layer structure RDL2; a first encapsulation layer E1, encapsulating the first semiconductor chip 101 and the second semiconductor chip 201; and a third semiconductor chip 300 and a fourth semiconductor chip 400, located on opposite sides of the second redistribution layer structure RDL2. In some embodiments, each of the chip modules CM includes a first encapsulation layer E1 that encapsulates the sidewalls of the first semiconductor chip 101 and the sidewalls of the second semiconductor chip 201. In some embodiments, each of the chip modules CM includes an integrated fan-out through-via TIV and an underfill glue layer UF1. In some embodiments, the integrated fan-out perforated TIV penetrates the first encapsulation layer E1 and is located on the sides of the first semiconductor chip 101 and the second semiconductor chip 201 and / or between the first semiconductor chip 101 and the second semiconductor chip 201, and the bottom filling glue layer UF1 is formed to fill the space between the second redistribution layer structure RDL2 and each of the third semiconductor chip 300 and the fourth semiconductor chip 400.

[0055] Reference Fig. 7E and Figure 7F, a chip module CM is placed on a first side of the first redistribution layer structure RDL1 and bonded to the first side of the first redistribution layer structure RDL1. In some embodiments, the chip module CM is bonded to the first redistribution layer structure RDL1 so that the back side of the first semiconductor chip 101 and the back side of the second semiconductor chip 201 are physically in contact with the first redistribution layer structure RDL1. In some embodiments, the back side pads of the first semiconductor chip 101 and the back side pads of the second semiconductor chip 201 and the integrated fan-out through-via TIV of the chip module CM are electrically connected to the first redistribution layer structure RDL1 through corresponding bumps 105.

[0056] In some embodiments, when the chip module CM is placed on and bonded to the first redistribution layer structure RDL1, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are placed on and bonded to the first redistribution layer structure RDL1 through their bumps 501 and 601.

[0057] Afterwards, an underfill layer UF2 is formed to fill the space between the first redistribution layer structure RDL1 and each of the chip module CM, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 .

[0058] Reference Figure 7G , the second encapsulation layer E2 is used to encapsulate the chip module CM and the fifth semiconductor chip 500 and the sixth semiconductor chip 600. In some embodiments, the second encapsulation layer E2 is formed on the first redistribution layer structure RDL1 to encapsulate or surround the sidewall and top of the chip module CM and the sidewall and top of the fifth semiconductor chip 500 and the sidewall and top of the sixth semiconductor chip 600. The first encapsulation layer E1 and the second encapsulation layer E2 may include the same or different materials.

[0059] Afterwards, the bump 112 is placed on the second side of the first redistribution layer structure RDL1 opposite to the first side and bonded to the connection pad of the first redistribution layer structure RDL1. The multi-chip wafer-level package 7 is thus completed. In some embodiments, the multi-chip wafer-level package 7 is composed of a first level T1 and a second level T2 that are physically in contact with each other. In some embodiments, the first level T1 includes a first redistribution layer structure RDL1 and a first semiconductor chip 101 and a second semiconductor chip 201 located on the first redistribution layer structure RDL1, and the second level T2 includes a second redistribution layer structure RDL2 and a third semiconductor chip 300 and a fourth semiconductor chip 400 located on the second redistribution layer structure RDL2.

[0060] Possible modifications and variations may be made to the multi-chip wafer level package. These modifications and variations are provided for illustrative purposes and should not be considered as limiting the present disclosure. Figures 8 to 10 is a cross-sectional view of a multi-chip wafer level package according to an alternative embodiment.

[0061] Figure 8 The multi-chip wafer level package 8 shown in FIG. Figure 7G The multi-chip wafer level package 7 shown is similar, the difference between them is that Figure 7G Each of the first semiconductor chip 101 and the second semiconductor chip 201 is a double-sided semiconductor chip. Figure 8 Each of the illustrated first and second semiconductor chips 100 and 200 is a single-sided semiconductor chip.

[0062] Fig. 9 The multi-chip wafer level package 9 shown in FIG. Figure 7G The multi-chip wafer level package 7 shown is similar, the difference between them is that Fig. 9 The multi-chip wafer level package 9 shown is provided without the fifth semiconductor chip 500 and the sixth semiconductor chip 600 .

[0063] Fig.10 The multi-chip wafer level package 10 is shown with Figure 8 The multi-chip wafer level package 8 shown is similar, the difference between them is that Fig.10 The multi-chip wafer level package 10 shown is provided without the fifth semiconductor chip 500 and the sixth semiconductor chip 600 .

[0064] In the above embodiments, each of the multi-chip wafer-level packages has two levels and each level has two chips and a redistribution layer structure, which is for illustrative purposes and should not be considered as limiting the present disclosure. In some embodiments, more than one redistribution layer structure may be included in at least one of the two levels. In some embodiments, at least one of the two levels may be designed to have a single chip or more than two chips as required.

[0065] Figures 11 to 14 are cross-sectional views of multi-chip wafer level packages according to yet other alternative embodiments.

[0066] Fig.11 The multi-chip wafer level package 11 is shown with Figure 3 The multi-chip wafer level package 3 shown is similar, the difference between them is that Fig.11 The first level T1 of the multi-chip wafer level package 11 shown has one semiconductor chip, and Figure 3 The first level T1 of the multi-chip wafer level package 3 shown has two semiconductor chips. Fig.11As shown, a single semiconductor chip (eg, a first semiconductor chip 100 ) is disposed in the first level T1 and is electrically connected to the third semiconductor chip 300 and the fourth semiconductor chip 400 through the second redistribution layer structure RDL2 .

[0067] Fig.12 The multi-chip wafer level package 12 is shown with Figure 3 The multi-chip wafer level package 3 shown is similar, the difference between them is that Fig.12 The first level T1 of the multi-chip wafer level package 12 shown has three semiconductor chips, and Figure 3 The first level T1 of the multi-chip wafer level package 3 shown has two semiconductor chips. Fig.12 As shown, a first semiconductor chip 100 and a second semiconductor chip 200 and an interposer 150 located between the first semiconductor chip 100 and the second semiconductor chip 200 are arranged in the first level T1. In some embodiments, the interposer 150 has a through silicon interposer (TSI) structure for providing electrical connection for the stacked chips. In some embodiments, the interposer 150 includes at least some of silicon vias, passive devices, fuses, redistribution layers, and bumps. In some embodiments, the third semiconductor chip 300 is electrically connected to the fourth semiconductor chip 400 through the interposer 150 located between the first semiconductor chip 100 and the second semiconductor chip 200.

[0068] Fig.13 The multi-chip wafer level package 13 shown is Figure 8 The multi-chip wafer level package 8 shown is similar, the difference between them is that Fig.13 The first level T1 of the multi-chip wafer level package 13 shown has one semiconductor chip, and Figure 8 The first level T1 of the multi-chip wafer level package 8 shown has two semiconductor chips. Fig.13 As shown, a single semiconductor chip (eg, a first semiconductor chip 100 ) is disposed in the first level T1 and is electrically connected to the third semiconductor chip 300 and the fourth semiconductor chip 400 through the second redistribution layer structure RDL2 .

[0069] Fig.14 The multi-chip wafer level package 14 is shown with Figure 8 The multi-chip wafer level package 8 shown is similar, the difference between them is that Fig.14 The first level T1 of the multi-chip wafer level package 14 shown has three semiconductor chips, and Figure 8 The first level T1 of the multi-chip wafer level package 8 shown has two semiconductor chips. Fig.14As shown, a first semiconductor chip 100 and a second semiconductor chip 200 and an interposer 150 between the first semiconductor chip 100 and the second semiconductor chip 200 are disposed in the first level T1. In some embodiments, the third semiconductor chip 300 is electrically connected to the fourth semiconductor chip 400 through the interposer 150 between the first semiconductor chip 100 and the second semiconductor chip 200.

[0070] It should be understood by those skilled in the art that the above-mentioned concept of a single chip or interposer can be applied to other chips besides Figure 3 and Figure 8 Other Figure 1G , Figure 2 , Figures 4 to 6 , Figure 7G ,and Figures 9 to 14 Multi-chip wafer-level packaging in.

[0071] The following reference Figure 1G , Figures 2 to 6 , Figure 7G ,as well as Figures 8 to 14 The structures of various multi-chip wafer-level packages are shown. In some embodiments, the multi-chip wafer-level package 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14 includes a first level T1 and a second level T2 stacked on the first level T1.

[0072] In some embodiments, the first level T1 includes a first redistribution layer structure RDL1 and at least one chip located on the first redistribution layer structure RDL1. In some embodiments, the at least one chip may be a single chip (eg, a first semiconductor chip 100). Fig.11 and Fig.13 In an alternative embodiment, the at least one chip includes two chips (eg, a first semiconductor chip 100 and a second semiconductor chip 200 or a first semiconductor chip 101 and a second semiconductor chip 201), such as Figure 1G , Figures 2 to 6 , Figure 7G and Figures 8 to 10 In some alternative embodiments, the at least one chip includes three chips (eg, a first semiconductor chip 100, a second semiconductor chip 200 and an interposer 150). Fig.12 and Fig.14 As shown. More than three chips may be applied in the first level T1 as required. In some embodiments, the first redistribution layer structure RDL1 extends laterally beyond the at least one chip, such as Figure 1G , Figures 2 to 6 , Figure 7G ,as well as Figures 8 to 14In some embodiments, the at least one chip is encapsulated by the first encapsulation layer E1. In some embodiments, a second encapsulation layer E2 is provided to encapsulate the first encapsulation layer E1, such as Figure 7G and Figures 8 to 10 as well as Figure 13 to Figure 14 shown.

[0073] In some embodiments, the second level T2 includes a second redistribution layer structure RDL2 and at least two other chips located above the second redistribution layer structure RDL2. In some embodiments, the at least two other chips include a third semiconductor chip 300 and a fourth semiconductor chip 400. Figure 1G , Figures 2 to 6 , Figure 7G and Figures 8 to 14 As shown. A single chip or more than two chips may be applied in the second level T2 as required. In some embodiments, the first redistribution layer structure RDL1 extends laterally beyond the second redistribution layer structure RDL2 or extends laterally beyond the at least two other chips, such as Figure 1G , Figures 2 to 6 ,and Figure 11 to Figure 12 In an alternative embodiment, the edge of the second redistribution layer structure RDL2 is substantially aligned with the edge of the first redistribution layer structure RDL1 or the edge of the at least two other chips, such as Figure 7G , Figures 8 to 10 ,and Figure 13 to Figure 14 In some embodiments, the at least two other chips are encapsulated by a second encapsulation layer E2.

[0074] In some embodiments, the first level T1 is bonded to the second level T2 such that the at least one chip in the first level T1 physically contacts the second redistribution layer structure RDL2 in the second level T2. In some embodiments, the connectors of the at least one chip in the first level T1 and the connectors of the at least two other chips in the second level T2 physically contact the second redistribution layer structure RDL2.

[0075] In some embodiments, the total number of connectors of the at least two other chips in the second level T2 is greater than (e.g., at least two times, at least five times, or at least eight times) the total number of connectors of the at least one chip in the first level T1. However, the present disclosure is not limited thereto. In alternative embodiments, the total number of connectors of the at least two other chips in the second level T2 may be substantially equal to or less than the total number of connectors of the at least one chip in the first level T1.

[0076] In some embodiments, at least one chip in the first level T1 includes an integrated passive device chip, and each of the at least two other chips in the second level T2 includes an integrated active device chip. However, the present disclosure is not limited to this. In alternative embodiments, at least one chip among the plurality of chips in the first level T1 includes an integrated active device chip. In some further alternative embodiments, at least one chip among the plurality of chips in the second level T2 includes an integrated passive device chip.

[0077] In some embodiments, the multi-chip wafer level package 2 / 3 / 5 / 6 / 7 / 8 / 11 / 12 / 13 / 14 further includes another chip located on the first redistribution layer structure RDL1 or the second redistribution layer structure RDL2 and located outside the at least one chip. In some embodiments, the another chip includes a fifth semiconductor chip 500 and a sixth semiconductor chip 600, such as Figures 2 to 3 , Figures 5 and 6 , Figure 7G , Figure 8 and Figures 11 to 14 In some embodiments, the other chip is encapsulated by the first encapsulation layer E1, such as Figure 2 and Figure 5 In an alternative embodiment, the other chip is encapsulated by a second encapsulation layer E2, such as Figure 3 , Figure 6 , Figure 7G , Figure 8 and Figures 11 to 14 In some embodiments, the other chip comprises an integrated passive device chip. In an alternative embodiment, the other chip comprises an integrated active device chip.

[0078] In some embodiments, the multi-chip wafer-level package 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 includes a first redistribution layer structure RDL1, a first semiconductor chip 100 / 101, a second semiconductor chip 200 / 201, a second redistribution layer structure RDL2, a third semiconductor chip 300, a fourth semiconductor chip 400, and a plurality of bumps 112. The first semiconductor chip 100 / 101 is located on a first side of the first redistribution layer structure RDL1. The second semiconductor chip 200 / 201 is located on a side of the first semiconductor chip 100 / 101 and on a first side of the first redistribution layer structure RDL1. The second redistribution layer structure RDL2 is located on the first semiconductor chip 100 / 101 and the second semiconductor chip 200 / 201. The third semiconductor chip 300 is located on the second redistribution layer structure RDL2 and is electrically connected to the first semiconductor chip 100 / 101. The fourth semiconductor chip 400 is located on the second redistribution layer structure RDL2 and is electrically connected to the second semiconductor chip 200 / 201 and the third semiconductor chip 300. The bumps 112 are located on a second side of the first redistribution layer structure RDL1 opposite to the first side.

[0079] In some embodiments, at least one of the first semiconductor chip 100 / 101 and the second semiconductor chip 200 / 201 includes an integrated passive device chip. In some embodiments, at least one of the first semiconductor chip and the second semiconductor chip is a single-sided semiconductor chip having a connector on a single side, and the connector is bonded to the second redistribution layer structure RDL2. In an alternative embodiment, at least one of the first semiconductor chip and the second semiconductor chip is a double-sided semiconductor chip having connectors on opposite sides, and the connectors are respectively bonded to the first redistribution layer structure RDL1 and the second redistribution layer structure RDL2. In some embodiments, at least one of the third semiconductor chip 300 and the fourth semiconductor chip 400 includes an integrated active device chip.

[0080] In some embodiments, the third semiconductor chip 300 is electrically connected to the fourth semiconductor chip 400 through the second redistribution layer structure RDL2. In alternative embodiments, the third semiconductor chip 300 is electrically connected to the fourth semiconductor chip 400 through the second redistribution layer structure RDL2 and the interposer 150 located between the first semiconductor chip 100 and the second semiconductor chip 200.

[0081] In some embodiments, a fifth semiconductor chip 500 and a sixth semiconductor chip 600 are further included in some of the multi-chip wafer-level packages. In some embodiments, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are located on the first side of the first redistribution layer structure RDL1 and are located outside the first semiconductor chip 100 and outside the second semiconductor chip 200. In an alternative embodiment, the fifth semiconductor chip 500 and the sixth semiconductor chip 600 are located on the second redistribution layer structure RDL2 and are located outside the third semiconductor chip 300 and outside the fourth semiconductor chip 400.

[0082] The elements or features of each of the above semiconductor chips are only for illustrative purposes and should not be considered as limiting the present disclosure. A person skilled in the art should understand that other elements or features may be included in the semiconductor chip as needed.

[0083] Figures 17 to 20 is a cross-sectional view of a semiconductor chip according to an alternative embodiment.

[0084] Reference Fig.17 , the semiconductor chip 510 includes a substrate 500a, an interconnect structure IS, one or more pads 500b, a protective layer 500c, a post-passivation interconnection structure (PPI), and one or more connectors 500d. The substrate 500a includes (for example but not limited to) an active layer of a doped or undoped bulk silicon or a semiconductor on insulator (SOI) substrate. The interconnect structure IS may be formed on the substrate 500a. The interconnect structure IS includes at least one metal layer embedded by at least one dielectric layer. The pad 500b is formed on the interconnect structure IS, and the protective layer 500c is formed on the pad 500b. In some embodiments, the pad 500b is an aluminum pad, and the protective layer 500c includes a polymer material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or a similar material. Connector 500d is formed through protection layer 500c and electrically connected to underlying pad 500b or interconnect structure IS. In some embodiments, connector 500d may include Cu, W, Ni, Sn, Ti, Au, alloys thereof, or combinations thereof, and may be formed using a ball drop process or an electroplating process.

[0085] Fig.18 The semiconductor chip 511 is shown with Fig.17 The semiconductor chips 510 are similar, the difference between them is that Fig.18The semiconductor chip 511 shown also includes one or more pads 500e located in the back side portion of the semiconductor chip 511 and one or more through silicon vias TSV3 located between the pads 500e and the interconnect structure IS and electrically connected to the pads 500e and the interconnect structure IS. In some embodiments, a bump may be formed on the back side of the semiconductor chip 511 and the bump is bonded to the pad 500e. In some embodiments, the connector 500d constitutes a front side connector of the semiconductor chip 511, and the pad 500e and / or the optional bump constitute a back side connector of the semiconductor chip 511.

[0086] Fig.19 The semiconductor chip 510' is shown with Fig.17 The semiconductor chips 510 are similar to those shown in the figure, and the difference between them lies in the structure of the connector. Fig.19 As shown, each of the connectors 500d' includes, from bottom to top, a copper layer 502, a nickel layer 503, another copper layer 504, and a solder bump 505. Other types of connection structures may be used based on process requirements.

[0087] Fig. 20 The semiconductor chip 511' is shown with Fig.18 The semiconductor chips 511 are similar to those shown in the figure, and the difference between them lies in the structure of the connector. Fig. 20 As shown, each of the connectors 500d' includes, from bottom to top, a copper layer 502, a nickel layer 503, another copper layer 504, and a solder bump 505. Other types of connection structures may be used based on process requirements.

[0088] In some embodiments, at least one of the semiconductor chips in the multi-chip wafer level packages 1 to 14 mentioned above may be replaced by the semiconductor chip 510 / 510' / 511 / 511' based on process requirements. In some embodiments, the back protection interconnect structure PPI of the semiconductor chip 510 / 510' / 511 / 511' may be used as a power line, a redistribution layer (RDL), an inductor, a capacitor, or any passive component and helps to improve process flexibility and improve signal / power integration.

[0089] In summary, in some embodiments of the present disclosure, at least one integrated passive device is arranged close to the active device, and these integrated passive devices and the integrated active device are embedded in the integrated fan-out packaging structure through the encapsulation layer. Through this arrangement, the package size can be significantly reduced, and the decoupling distance between the integrated passive device and the corresponding integrated active device can be greatly shortened. In addition, the pattern pitch of at least one of the redistribution layer structures can be increased. Therefore, the process margin can be widened and the production cost can be saved.

[0090] According to some embodiments of the present disclosure, a multi-chip wafer-level package includes a first level and a second level. The first level includes a first redistribution layer structure and at least one chip located on the first redistribution layer structure. The second level includes a second redistribution layer structure and at least two other chips located on the second redistribution layer structure. The first level is bonded to the second level so that the at least one chip physically contacts the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

[0091] In some embodiments, the first redistribution layer structure extends laterally beyond the second redistribution layer structure.

[0092] In some embodiments, an edge of the second redistribution layer structure is substantially aligned with an edge of the first redistribution layer structure.

[0093] In some embodiments, the at least one chip comprises an integrated passive device chip.

[0094] In some embodiments, each of the at least two other chips comprises an integrated active device chip.

[0095] In some embodiments, the multi-chip wafer level package further includes another chip located on the first redistribution layer structure or the second redistribution layer structure and located outside the at least one chip.

[0096] In some embodiments, the another chip comprises an integrated passive device chip.

[0097] According to an alternative embodiment of the present disclosure, a multi-chip wafer-level package includes: a first semiconductor chip, a second semiconductor chip, a second redistribution layer structure, a third semiconductor chip, a fourth semiconductor chip, and a plurality of bumps. The first semiconductor chip is located on a first side of the first redistribution layer structure. The second semiconductor chip is located at a side of the first semiconductor chip and is located on the first side of the first redistribution layer structure. The second redistribution layer structure is located on the first semiconductor chip and the second semiconductor chip. The third semiconductor chip is located on the second redistribution layer structure and is electrically connected to the first semiconductor chip. The fourth semiconductor chip is located on the second redistribution layer structure and is electrically connected to the second semiconductor chip and the third semiconductor chip. The bump is located on a second side of the first redistribution layer structure opposite to the first side.

[0098] In some embodiments, the total number of the third connectors of the third semiconductor chip and the fourth connectors of the fourth semiconductor chip is greater than the total number of the first connectors of the first semiconductor chip and the second connectors of the second semiconductor chip.

[0099] In some embodiments, the first redistribution layer structure extends laterally beyond the second redistribution layer structure.

[0100] In some embodiments, an edge of the third semiconductor chip and an edge of the fourth semiconductor chip are substantially aligned with an edge of the second redistribution layer structure.

[0101] In some embodiments, at least one of the first semiconductor chip and the second semiconductor chip includes an integrated passive device chip.

[0102] In some embodiments, at least one of the first semiconductor chip and the second semiconductor chip is a single-sided semiconductor chip having connectors on a single side, the connectors being bonded to the second redistribution layer structure.

[0103] In some embodiments, at least one of the first semiconductor chip and the second semiconductor chip is a double-sided semiconductor chip having connectors on opposite sides, the connectors being bonded to the first redistribution layer structure and the second redistribution layer structure, respectively.

[0104] In some embodiments, at least one of the third semiconductor chip and the fourth semiconductor chip includes an integrated active device chip.

[0105] In some embodiments, the third semiconductor chip is electrically connected to the fourth semiconductor chip through an interposer located between the first semiconductor chip and the second semiconductor chip.

[0106] In some embodiments, the multi-chip wafer level package further includes: a first encapsulation layer encapsulating the first semiconductor chip and the second semiconductor chip; and a second encapsulation layer encapsulating the third semiconductor chip and the fourth semiconductor chip.

[0107] In some embodiments, the multi-chip wafer level package further includes a fifth semiconductor chip and a sixth semiconductor chip located on the first side of the first redistribution layer structure and located outside the first semiconductor chip and outside the second semiconductor chip.

[0108] According to another alternative embodiment of the present disclosure, a method for forming a multi-chip wafer-level package includes: providing a carrier having a first redistribution layer structure formed thereon; placing a first integrated passive device chip and a second integrated passive device chip on a first side of the first redistribution layer structure; encapsulating the first integrated passive device chip and the second integrated passive device chip using a first encapsulation layer; forming a second redistribution layer structure on the first encapsulation layer; placing a first integrated active device chip and a second integrated active device chip on the second redistribution layer structure; encapsulating the first integrated active device chip and the second integrated active device chip using a second encapsulation layer; and peeling off the carrier.

[0109] In some embodiments, the method further includes: forming a third integrated passive device chip and a fourth integrated passive device chip on sides of the first integrated active device chip and the second integrated active device chip, and encapsulating the third integrated passive device chip and the fourth integrated passive device chip with the second encapsulation layer.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

[0111] [Explanation of Symbols]

[0112] 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14: Multi-chip wafer level packaging

[0113] 100, 100', 101, 101': first semiconductor chip

[0114] 100a, 200a, 300a, 400a, 500a: Substrate

[0115] 100b, 200b: pad

[0116] 100e, 200e: pad

[0117] 100c, 200c, 300c, 400c, 500c: protective layer

[0118] 100d, 200d, 300d, 400d, 500d, 500d': Connectors

[0119] 102: Polymer layer

[0120] 103, 110: Connection pads

[0121] 104: Rewiring Layer

[0122] 105, 112, 300e, 400e, 501, 601: Bump

[0123] 106: Polymer layer

[0124] 108: Rewiring layer

[0125] 150: Intermediary film

[0126] 200, 200', 201, 201': second semiconductor chip

[0127] 300: The third semiconductor chip

[0128] 300b, 400b, 500b, 500e: pads

[0129] 400: The fourth semiconductor chip

[0130] 500: Fifth Semiconductor Chip

[0131] 510, 510', 511, 511': semiconductor chips

[0132] 502, 504: Copper layer

[0133] 503: Nickel layer

[0134] 505: Solder bump

[0135] 600: Sixth semiconductor chip

[0136] C: Carrier board

[0137] C1: First carrier board

[0138] C2: Second carrier board

[0139] CA1, CA2: Deep trench capacitor area

[0140] CM: Chip Module

[0141] DB: Debonding layer

[0142] DB1: First peeling layer

[0143] DB2: Second peeling layer

[0144] E1: First encapsulation layer

[0145] E2: Second encapsulation layer

[0146] IS: Inner Connected Structure

[0147] PPI: Posterior Protection Inner Link

[0148] RDL1: First redistribution layer structure

[0149] RDL2: Second redistribution layer structure

[0150] T1: First level

[0151] T2: Second level

[0152] TSV1, TSV2, TSV3: Through Silicon Via

[0153] TIV: Integrated Fan-Out Via

[0154] UF, UF1, UF2: bottom fill layer

Claims

1. A multi-chip wafer level package, characterized in that include: A first redistribution layer structure; A chip module is located on the first redistribution layer structure and includes: A first semiconductor chip and a second semiconductor chip are located on the first redistribution layer structure; A third semiconductor chip and a fourth semiconductor chip are located on the first semiconductor chip and the second semiconductor chip; and A second redistribution layer structure physically contacts the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip; and A fifth semiconductor chip and a sixth semiconductor chip are located on the first redistribution layer structure and adjacent to the chip module. wherein each of the first semiconductor chip and the second semiconductor chip comprises an integrated passive device chip, The third semiconductor chip is electrically connected to the fourth semiconductor chip through an interposer located between the first semiconductor chip and the second semiconductor chip. 2 . The multi-chip wafer level package according to claim 1 , wherein the first redistribution layer structure extends laterally beyond the second redistribution layer structure. 3 . The multi-chip wafer level package according to claim 1 , wherein an edge of the second redistribution layer structure is substantially aligned with edges of the first semiconductor chip and the second semiconductor chip. 4 . The multi-chip wafer level package of claim 1 , wherein each of the third semiconductor chip and the fourth semiconductor chip comprises an integrated active device chip. 5 . The multi-chip wafer level package according to claim 1 , wherein the fifth semiconductor chip and the sixth semiconductor chip are located at two sides of the chip module. 6 . The multi-chip wafer level package according to claim 5 , wherein each of the fifth semiconductor chip and the sixth semiconductor chip comprises an integrated passive device chip.

7. A multi-chip wafer level package, characterized in that include: A first redistribution layer structure; Chip module, including: A first semiconductor chip is located on a first side of the first redistribution layer structure; A second semiconductor chip is located at a side of the first semiconductor chip and on the first side of the first redistribution layer structure; A second redistribution layer structure is located on the first semiconductor chip and the second semiconductor chip; a third semiconductor chip located on the second redistribution layer structure and electrically connected to the first semiconductor chip; and a fourth semiconductor chip located on the second redistribution layer structure and electrically connected to the second semiconductor chip and the third semiconductor chip; and a plurality of bumps located on a second side of the first redistribution layer structure opposite to the first side; and A fifth semiconductor chip and a sixth semiconductor chip are located on the first redistribution layer structure and adjacent to the chip module. wherein at least one of the first semiconductor chip and the second semiconductor chip comprises an integrated passive device chip, The third semiconductor chip is electrically connected to the fourth semiconductor chip through an interposer located between the first semiconductor chip and the second semiconductor chip.

8. The multi-chip wafer level package according to claim 7, wherein the total number of the third connectors of the third semiconductor chip and the fourth connectors of the fourth semiconductor chip is greater than the total number of the first connectors of the first semiconductor chip and the second connectors of the second semiconductor chip. 9 . The multi-chip wafer level package according to claim 7 , wherein the first redistribution layer structure extends laterally beyond the second redistribution layer structure. 10 . The multi-chip wafer level package according to claim 7 , wherein edges of the third semiconductor chip and the fourth semiconductor chip are substantially aligned with an edge of the second redistribution layer structure. 11 . The multi-chip wafer level package of claim 7 , wherein at least one of the first semiconductor chip and the second semiconductor chip is a single-sided semiconductor chip having a connector on a single side, the connector being bonded to the second redistribution layer structure.

12. The multi-chip wafer-level package according to claim 7, wherein at least one of the first semiconductor chip and the second semiconductor chip is a double-sided semiconductor chip having connectors on opposite sides, the connectors being respectively bonded to the first redistribution layer structure and the second redistribution layer structure. 13 . The multi-chip wafer level package of claim 7 , wherein at least one of the third semiconductor chip and the fourth semiconductor chip comprises an integrated active device chip.

14. The multi-chip wafer level package according to claim 7, wherein the chip modules have vertical sidewalls.

15. The multi-chip wafer level package according to claim 7, further comprising: a first encapsulation layer, encapsulating the first semiconductor chip and the second semiconductor chip; as well as The second encapsulation layer encapsulates the third semiconductor chip and the fourth semiconductor chip. 16 . The multi-chip wafer level package according to claim 7 , further comprising a fifth semiconductor chip and a sixth semiconductor chip, wherein the fifth semiconductor chip and the sixth semiconductor chip are located at two sides of the chip module.

17. A multi-chip wafer level package, characterized in that include: A first semiconductor chip is located on a first side of the first redistribution layer structure; A second semiconductor chip is located at a side of the first semiconductor chip and on the first side of the first redistribution layer structure; A second redistribution layer structure is located on the first semiconductor chip and the second semiconductor chip; a third semiconductor chip, located on the second redistribution layer structure and electrically connected to the first semiconductor chip; a fourth semiconductor chip, located on the second redistribution layer structure and electrically connected to the second semiconductor chip and the third semiconductor chip; as well as a plurality of bumps located on a second side of the first redistribution layer structure opposite to the first side, The third semiconductor chip is electrically connected to the fourth semiconductor chip through an interposer located between the first semiconductor chip and the second semiconductor chip.

18. A method for forming a multi-chip wafer level package, characterized in that include: Providing a carrier board, on which a first redistribution layer structure is formed; Forming a chip module on a first side of the first redistribution layer structure, wherein forming the chip module comprises: forming a first integrated passive device chip and a second integrated passive device chip on the first side of the first redistribution layer structure; and forming a first integrated active device chip and a second integrated active device chip on the first integrated passive device chip and the second integrated passive device chip respectively; forming at least one semiconductor chip on the first side of the first redistribution layer structure, the at least one semiconductor chip being adjacent to the chip module; and The carrier sheet is peeled off.

19. The method for forming a multi-chip wafer level package according to claim 18, wherein forming the chip module further comprises: A second redistribution layer structure is formed between the first integrated passive device chip and the first integrated active device chip and between the second integrated passive device chip and the second integrated active device chip.

20. The method for forming a multi-chip wafer level package according to claim 18, wherein forming the chip module further comprises: A first encapsulation layer is formed to encapsulate the first integrated passive device chip and the second integrated passive device chip.

21. The method of forming a multi-chip wafer level package according to claim 18, further comprising: Before peeling off the carrier, a second encapsulation layer is formed to encapsulate the chip module and the at least one semiconductor chip.

22. The method for forming a multi-chip wafer level package according to claim 18, wherein forming the chip module further comprises: A bottom filling glue layer is formed to fill the space between the first redistribution layer structure and each of the chip module and the at least one semiconductor chip.

23. The method of forming a multi-chip wafer level package according to claim 18, wherein the at least one semiconductor chip comprises an integrated passive device chip.

24. The method for forming a multi-chip wafer-level package according to claim 18, wherein the first integrated passive device chip and the first integrated active device chip are configured face-to-face and their substrates are far away from each other, and the second integrated passive device chip and the second integrated active device chip are configured face-to-face and their substrates are far away from each other.

25. A method for forming a multi-chip wafer level package, characterized in that include: Providing a first carrier board, on which a first redistribution layer structure is formed; Forming a chip module on a first side of the first redistribution layer structure, wherein forming the chip module comprises: Alternately forming a plurality of first semiconductor chips and a plurality of second semiconductor chips on a second carrier, wherein the plurality of first semiconductor chips are integrated passive device chips; forming a second redistribution layer structure on the plurality of first semiconductor chips and the plurality of second semiconductor chips; forming a plurality of third semiconductor chips and a plurality of fourth semiconductor chips alternately on the second redistribution layer structure; peeling off the second carrier plate; and performing a singulation process to separate the chip module from another chip module; forming a fifth semiconductor chip and a sixth semiconductor chip on the first side of the first redistribution layer structure, the fifth semiconductor chip and the sixth semiconductor chip being adjacent to the chip module; and The first carrier is peeled off.

26. The method for forming a multi-chip wafer level package according to claim 25, wherein forming the chip module further comprises: A first bottom filling glue layer is formed to fill the space between the second redistribution layer structure and each of the plurality of third semiconductor chips and the plurality of fourth semiconductor chips.

27. The method of forming a multi-chip wafer level package according to claim 25, further comprising: A second bottom filling glue layer is formed to fill the space between the first redistribution layer structure and each of the chip module, the fifth semiconductor chip and the sixth semiconductor chip.

28. The method of forming a multi-chip wafer level package according to claim 25, further comprising: After the first carrier is peeled off, a plurality of bumps are formed on a second side of the first redistribution layer structure opposite to the first side.

29. The method of forming a multi-chip wafer level package according to claim 25, wherein a critical dimension of the second redistribution layer structure is smaller than a critical dimension of the first redistribution layer structure.

30. The method for forming a multi-chip wafer level package according to claim 25, wherein forming the chip module further comprises: A first encapsulation layer is formed to encapsulate the plurality of first semiconductor chips and the plurality of second semiconductor chips.

31. The method of forming a multi-chip wafer level package according to claim 25, further comprising: A second encapsulation layer is formed to encapsulate the chip module, the fifth semiconductor chip, and the sixth semiconductor chip.

32. A method for forming a multi-chip wafer level package, characterized in that include: Providing a carrier board, on which a first redistribution layer structure is formed; placing a first semiconductor chip, an interposer, and a second semiconductor chip on a first side of the first redistribution layer structure; forming a first encapsulation layer to encapsulate the first semiconductor chip, the interposer, and the second semiconductor chip; forming a second redistribution layer structure on the first encapsulation layer; placing a third semiconductor chip and a fourth semiconductor chip on the second redistribution layer structure, wherein the third semiconductor chip is electrically connected to the fourth semiconductor chip through the interposer located between the first semiconductor chip and the second semiconductor chip; forming a second encapsulation layer to encapsulate the third semiconductor chip and the fourth semiconductor chip; as well as The carrier sheet is peeled off.

33. The method of forming a multi-chip wafer level package according to claim 32, further comprising: After the carrier is peeled off, a plurality of bumps are formed on a second side of the first redistribution layer structure opposite to the first side.

34. The method of forming a multi-chip wafer level package according to claim 32, further comprising: Before forming the second encapsulation layer, a fifth semiconductor chip and a sixth semiconductor chip are formed on the first side of the first redistribution layer structure and beside the first semiconductor chip and the second semiconductor chip, wherein the second encapsulation layer encapsulates the fifth semiconductor chip and the sixth semiconductor chip.

35. The method of forming a multi-chip wafer level package of claim 32, wherein at least one of the first semiconductor chip and the second semiconductor chip comprises an integrated passive device chip.

36. The method of forming a multi-chip wafer level package according to claim 32, wherein at least one of the third semiconductor chip and the fourth semiconductor chip comprises an integrated active device chip.

37. The method of forming a multi-chip wafer level package according to claim 34, wherein at least one of the fifth semiconductor chip and the sixth semiconductor chip comprises an integrated passive device chip.

38. A multi-chip wafer level package, characterized in that include: An interposer, located on a first side of the first redistribution layer structure and including, from bottom to top, an interposer substrate, an interposer redistribution layer, and an interposer connector; an integrated fan-out via located on the first side of the first redistribution layer structure and on a side of the interposer; A second redistribution layer structure is located on the integrated fan-out type via and the interposer connector of the interposer and is electrically connected to the integrated fan-out type via and the interposer connector of the interposer; at least two semiconductor chips located on the second redistribution layer structure and electrically connected to the second redistribution layer structure; as well as An encapsulation layer encapsulates the at least two semiconductor chips.

39. The multi-chip wafer level package of claim 38, further comprising: At least one other semiconductor chip is located on the first side of the first redistribution layer structure and on a side of the interposer.

40. The multi-chip wafer level package of claim 39, wherein the at least one other semiconductor chip is an integrated passive device chip.

41. The multi-chip wafer level package of claim 38, further comprising: A plurality of bumps are located on a second side of the first redistribution layer structure opposite to the first side.

42. The multi-chip wafer level package of claim 38, wherein the at least two semiconductor chips are integrated active device chips.

43. The multi-chip wafer level package of claim 38, wherein the first redistribution layer structure extends laterally beyond the second redistribution layer structure.

44. The multi-chip wafer level package of claim 38, wherein an edge of the second redistribution layer structure is substantially aligned with an edge of the first redistribution layer structure.

45. The multi-chip wafer level package of claim 38, wherein the interposer further comprises a through substrate via electrically connected to the first redistribution layer structure.

46. ​​The multi-chip wafer level package according to claim 38, further comprising at least one capacitor located on the first redistribution layer structure and located on sides of the at least two semiconductor chips.

47. The multi-chip wafer level package of claim 38, wherein the encapsulation layer is separate from the first redistribution layer structure.

48. The multi-chip wafer level package of claim 38, wherein the encapsulation layer physically contacts the first redistribution layer structure.

49. A multi-chip wafer level package, characterized in that include: an interposer disposed on a first side of the first redistribution layer structure; a second redistribution layer structure located on the interposer and electrically connected to the interposer; at least two semiconductor chips located on the second redistribution layer structure and electrically connected to the second redistribution layer structure; and a bottom filling glue layer configured to fill a space between the second redistribution layer structure and each of the at least two semiconductor chips, wherein the interposer is electrically connected to the at least two semiconductor chips, the interposer and the at least two semiconductor chips are arranged face to face and their substrates are far away from each other, and The first redistribution layer structure extends laterally beyond edges of the at least two semiconductor chips. 50 . The multi-chip wafer level package of claim 49 , further comprising an encapsulation layer, encapsulating the at least two semiconductor chips further comprising wherein the encapsulation layer physically contacts the first redistribution layer structure.

51. The multi-chip wafer level package of claim 49, wherein the first redistribution layer structure extends laterally beyond the second redistribution layer structure.

52. The multi-chip wafer level package of claim 49, further comprising at least two other semiconductor chips located on the first redistribution layer structure and on a side of the interposer.

53. A multi-chip wafer level package, characterized in that include: A first redistribution layer structure; A chip module is located on the first redistribution layer structure and includes: an interposer, located on the first redistribution layer structure; two upper semiconductor chips located on the interposer; and A second redistribution layer structure physically contacts the interposer and the two upper semiconductor chips; and The encapsulation layer is located on the first redistribution layer structure and encapsulates the chip module.

54. The multi-chip wafer level package according to claim 53, wherein the chip module further comprises two lower semiconductor chips, the two lower semiconductor chips are between the first redistribution layer structure and the second redistribution layer structure and are located at a side of the interposer.

55. The multi-chip wafer level package of claim 54, wherein the underlying semiconductor chip is an integrated passive device chip.

56. The multi-chip wafer level package according to claim 53, further comprising two other semiconductor chips located on the first redistribution layer structure and at sides of the chip module.

57. The multi-chip wafer level package of claim 56, wherein the two other semiconductor chips are integrated passive device chips.

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