Method for forming semiconductor device structure

Abstract

A method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer on a dielectric layer, the first mask layer having a trench, the trench having an inner wall and a bottom surface. The method comprises forming a second mask layer in the first trench. The method comprises removing the second mask layer covering the bottom surface to form a second trench in the second mask layer, the second trench exposing the bottom surface and above a first portion of the dielectric layer, the remaining second mask layer covering the inner wall. The method comprises removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method comprises forming a conductive structure in the third trench.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to methods for forming semiconductor device structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing integrated circuits.

[0003] In the history of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased, while geometry size (i.e., the smallest component (or circuit) produced during the manufacturing process) has decreased. This process of device size miniaturization generally has the benefit of increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to shrink, manufacturing processes continue to become more difficult to implement. Therefore, it is a challenge to form reliable semiconductor devices of increasingly smaller sizes. Summary of the invention

[0005] In some embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer above a dielectric layer, wherein the first mask layer has a first trench, and the first trench has an inner wall and a bottom surface; forming a second mask layer in the first trench; removing the second mask layer covering the bottom surface to form a second trench in the second mask layer, wherein the second trench exposes the bottom surface and is above a first portion of the dielectric layer, and the remaining second mask layer covers the inner wall; removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer; and forming a conductive structure in the third trench.

[0006] In some other embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer over a dielectric layer, wherein the first mask layer has a first groove and a second groove, and the first groove has a first inner wall and a first bottom surface; conformally forming a second mask layer over the first inner wall, wherein the second mask layer has a third groove in the first groove and exposes the first bottom surface, the third groove is narrower than the second groove, and the third groove and the second groove are respectively over a first portion and a second portion of the dielectric layer; removing the first portion, the second portion, the first mask layer and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer, wherein the fourth trench is narrower than the fifth trench; and forming a first conductive structure and a second conductive structure in the fourth trench and the fifth trench, respectively.

[0007] In some other embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer over a dielectric layer, wherein the first mask layer has a first groove and a second groove, and the first groove has a first inner wall and a first bottom surface; forming a second mask layer over the top surface and the first inner wall of the first mask layer, wherein the thickness of the second mask layer over the first inner wall increases in a direction away from the dielectric layer, the second mask layer has a third groove in the first groove and exposes the first bottom surface, and the third groove and the second groove are respectively over a first portion and a second portion of the dielectric layer; removing the first portion, the second portion, the first mask layer, and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer, wherein the fourth trench is narrower than the fifth trench; and forming a first conductive structure and a second conductive structure in the fourth trench and the fifth trench, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments of the present invention can be better understood according to the following detailed description and in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various components in the accompanying drawings are not necessarily drawn to scale. In fact, the sizes of various components may be arbitrarily enlarged or reduced to make a clear description.

[0009] Figures 1A-1M Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0010] Figure 2A-2C Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0011] Figures 3A-3H Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0012] Figures 4A-4F Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0013] The reference numerals are described as follows:

[0014] 110Semiconductor substrate

[0015] Area 110A, 110B

[0016] 120 dielectric layer

[0017] 122, 155, S1, S2, S3, S4, 221 top surface

[0018] 130, 150, 220, 310 mask layers

[0019] 140 hard mask layers 151, 152, 153, 154, 182, 212, 222, 224, 226, 228, 312, 314,

[0021] 316, 318, R1, R2, R3, R4 grooves

[0022] 160, 190 lower level

[0023] 170, 200 middle layer

[0024] 180, 210 upper level

[0025] 222a, 224a, 226a, 228a, N1, N2, N3, N4 inner wall

[0026] 229 Sidewall

[0027] 230 Photoresist layer

[0028] 240 Barrier Layer

[0029] 250 Conductive material layer

[0030] B1, B2, B3, B4 bottom surface

[0031] D1, D2 distance

[0032] L1, L2, L3, L4 conductive structure

[0033] M1, M2 patterned mask structure

[0034] T1, T2, T3, T4, T4', T5, T6, T7, T8, T9, T10 thickness

[0035] V1 Direction

[0036] W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12,

[0037] W13, W14 width DETAILED DESCRIPTION

[0038] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the provided subject. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes forming a first component on or above a second component, which means that it includes an embodiment in which the formed first component and the second component are in direct contact, and also includes an embodiment in which an additional component can be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and / or the described appearance structures.

[0039] Furthermore, in order to facilitate the description of the relationship between an element or component and another (plural) element or (plural) component in the drawings, spatially related terms may be used, such as "under...", "below", "lower", "above", "upper" and similar terms. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device in use or operation. The device may also be positioned otherwise (for example, rotated 90 degrees or located in other orientations), and the description of the spatially related terms used may be interpreted accordingly. It should be understood that additional operations may be provided before, during, and after the method of an embodiment of the present invention, and in other embodiments of the method of an embodiment of the present invention, some of the operations described may be replaced or eliminated.

[0040] Figures 1A-1M Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1A As shown, a semiconductor substrate 110 is provided. In some embodiments, the semiconductor substrate 110 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the semiconductor substrate 110 is a silicon wafer.

[0041] The semiconductor substrate 110 may include silicon or other elemental semiconductor materials (e.g., germanium). In some other embodiments, the semiconductor substrate 110 includes a compound semiconductor. The compound semiconductor may include silicon germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, other suitable compound semiconductors, or combinations thereof.

[0042] In some embodiments, the semiconductor substrate 110 includes a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator substrate can be manufactured by using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOS) process, other applicable methods, or a combination thereof.

[0043] In some embodiments, various device elements are formed in and / or above the semiconductor substrate 110. For simplicity and clarity, these device elements are not shown in the drawings. Examples of these device elements include transistors, diodes, other suitable elements, or combinations thereof.

[0044] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel / n-channel field effect transistors (PFETs / NFETs), etc. Various processes (e.g., front-end-of-line (FEOL) semiconductor manufacturing processes) are performed to form various device elements. The front-end-of-line semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination of the foregoing.

[0045] In some embodiments, isolation features (not shown) are formed in the semiconductor substrate 110. The isolation features are used to define active regions and electrically isolate various device elements formed in the active regions in and / or over the semiconductor substrate 110. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0046] In some embodiments, an interconnect structure (not shown) is formed over the semiconductor substrate 110 in the regions 110A and 110B. The regions 110A and 110B may be considered as a narrow line width region and a wide line width region, but the embodiments of the present invention are not limited thereto.

[0047] The interconnect structure includes a plurality of dielectric layers including an interlayer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers. The interconnect structure may also include a plurality of conductive features formed in the interlayer dielectric layer and the intermetal dielectric layer. The conductive features may include conductive lines, vias, and / or conductive contacts. Various processes (e.g., back-end-of-line (BEOL) semiconductor manufacturing processes) are performed to form the interconnect structure.

[0048] Various device elements are interconnected through the interconnection structure above the semiconductor substrate 110 to form an integrated circuit device. The integrated circuit device includes a logic device, a memory device (e.g., static random access memory (SRAMs)), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, an image sensor device, other applicable types of devices, or a combination of the foregoing.

[0049] like Figure 1A As shown, dielectric layer 120 is deposited on semiconductor substrate 110 in regions 110A and 110B. Dielectric layer 120 may serve as an interlayer dielectric layer or an intermetallic dielectric layer of an interconnect structure. Dielectric layer 120 covers device elements formed in and / or on semiconductor substrate 110. Figure 1A The dielectric layer 120 is shown as a single layer, but the present invention is not limited thereto. In some other embodiments, the dielectric layer 120 is a multi-layer structure including a dielectric sub-layer (not shown).

[0050] In some embodiments, the dielectric layer 120 is made of or includes an insulating material, such as silicon oxide, silicon oxynitride, a low-k material, an extreme low-k (ELK) material, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), one or more other suitable materials, or a combination thereof. In some embodiments, the dielectric layer 120 is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin coating process, a spray coating process, one or more other applicable processes, or a combination thereof.

[0051] The low dielectric constant material or the very low dielectric constant material may have a dielectric constant smaller than silicon dioxide. For example, the low dielectric constant material may have a dielectric constant in the range of about 1.5 to about 3.5. The very low dielectric constant material may have a dielectric constant less than about 2.5 or in the range of about 1.5 to about 2.5. As the density of semiconductor devices increases and the size of circuit elements decreases, the resistance capacitance (RC) delay time increasingly dominates the circuit performance. Therefore, using a low dielectric constant material or a very low dielectric constant material as the dielectric layer 120 helps to reduce the RC delay.

[0052] A variety of low-k materials or very low-k materials may be used to form the dielectric layer 120. In some embodiments, the dielectric layer 120 is made of a porous dielectric material, an organic polymer, an organosilicon glass, a SiOF series material, a hydrogen silsesquioxane (HSQ) material, a methyl silsesquioxane (MSQ) series material, a carbon-doped silicon oxide, an amorphous carbon fluoride, polyparaxylene, benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), a silicon oxide polymer (SiOC), a porous organic series material, a spin-on inorganic dielectric, a spin-on organic dielectric material, one or more other suitable materials, or a combination thereof, or includes the foregoing materials.

[0053] A plurality of conductive features (not shown) are formed in the dielectric layer 120 in the regions 110A and 110B. The conductive features may be electrically connected to a gate structure or a power device formed on the semiconductor substrate 110 or a doped region formed in the semiconductor substrate 110. The conductive features in the region 110A may be electrically connected to the gate structure and the doped region, while the conductive features in the region 110B may be electrically connected to the power device.

[0054] The conductive component may include a conductive wire, a via, a conductive contact, or a combination thereof. In some embodiments, the conductive component is made of a conductive material, or includes a conductive material, such as a metal material (e.g., copper, aluminum, tungsten, titanium, cobalt, nickel, gold, platinum, or a combination thereof). Various processes including deposition, etching, planarization, or the like may be used to form the conductive component in the dielectric layer 120.

[0055] According to some embodiments, Figure 1A As shown, a mask layer 130 is deposited over the dielectric layer 120. According to some embodiments, the mask layer 130 is also referred to as an anti-reflective coating (ARC) layer. The mask layer 130 can absorb light, thereby minimizing the amount of reflection during a subsequent photolithography process, thereby improving the resolution of the photolithography process. In some embodiments, the mask layer 130 is made of SiON, SiCN, SiN, HfO, Al2O3, Ta2O5, ZrO, one or more other suitable materials, or a combination of the foregoing, or includes the foregoing materials.

[0056] In some embodiments, the mask layer 130 is a nitrogen-free anti-reflective coating (NFARC) layer. By keeping the interface between the dielectric layer 120 and the mask layer 130 free of nitrogen, little or no nitrogen diffuses into the dielectric layer 120 to prevent contamination. The mask layer 130 is deposited using a spray coating process, a spin coating process, a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0057] like Figure 1AAs shown, a hard mask layer 140 is deposited over the mask layer 130. The hard mask layer 140 is made of or includes titanium nitride (TiN), SiON, one or more other suitable materials, or a combination thereof. In some other embodiments, the hard mask layer 140 is a multi-layer structure, such as an oxide-nitride-oxide (ONO) layer. The hard mask layer 140 is deposited using a physical vapor deposition (PVD) process (e.g., a radio-frequency PVD (RFPVD) process), a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0058] According to some embodiments, Figure 1A As shown, a mask layer 150 is deposited on the hard mask layer 140. According to some embodiments, the mask layer 150 is also called an anti-reflective coating (ARC) layer. The mask layer 150 is made of an anti-reflective material (e.g., SiON, SiCN, SiN, HfO, Al2O3, Ta2O5, ZrO), one or more other suitable materials, or a combination thereof, or includes the aforementioned materials.

[0059] In some embodiments, mask layer 150 and mask layer 130 are made of or include the same material. In some embodiments, dielectric layer 120 and mask layer 150 are made of different materials. In some embodiments, hard mask layer 140 and mask layer 150 are made of different materials.

[0060] In some embodiments, the mask layer 150 is a nitrogen-free anti-reflective coating (NFARC) layer. The mask layer 150 is deposited by using a spray coating process, a spin coating process, a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0061] Then, according to some embodiments, such as Figure 1B As shown, the patterned mask structure M1 is formed on the mask layer 150 . According to some embodiments, the patterned mask structure M1 is a multi-layer mask structure. According to some embodiments, the patterned mask structure M1 includes a lower layer 160 , a middle layer 170 , and an upper layer 180 .

[0062] According to some embodiments, Figure 1BAs shown, the lower layer 160, the middle layer 170 and the upper layer 180 are sequentially deposited on the mask layer 150. In some embodiments, the lower layer 160 is made of or includes a polymer material. In some embodiments, the middle layer 170 is made of or includes a silicon-containing material, such as a silicon-containing polymer material. In some embodiments, the upper layer 180 is made of or includes a photoresist material. In some embodiments, the lower layer 160, the middle layer 170 and the upper layer 180 are deposited by using a physical vapor deposition process, a chemical vapor deposition process, a spin coating process, other applicable processes or a combination thereof.

[0063] According to some embodiments, the upper layer 180 is patterned to form a groove 182 in the upper layer 180. The groove 182 partially exposes the middle layer 170. The upper layer 180 is patterned by a photolithography process. Thereafter, the middle layer 170 is patterned or etched by using the patterned upper layer 180 as an etching mask. Thus, the groove 182 is transferred to the middle layer 170 (not shown).

[0064] The patterned upper layer 180 may be removed during the patterning of the middle layer 170. Similarly, the lower layer 160 is then patterned or etched by using the patterned middle layer 170 as an etch mask. Thus, the trenches 182 are transferred to the lower layer 160 (not shown). The patterned middle layer 170 may be removed during the patterning of the lower layer 160.

[0065] The patterned lower layer 160 is subsequently used as an etching mask to pattern the mask layer 150. According to some embodiments, Figure 1C As shown, the mask layer 150 is patterned or etched by using the patterned lower layer 160 as an etching mask. Therefore, according to some embodiments, grooves 151 and 153 are formed in the mask layer 150. According to some embodiments, the grooves 151 and 153 penetrate the mask layer 150. According to some embodiments, the grooves 151 and 153 partially expose the hard mask layer 140 thereunder. The patterned lower layer 160 may be removed during the patterning of the mask layer 150.

[0066] In some embodiments, the middle layer 170, the lower layer 160, and the mask layer 150 are sequentially patterned by using one or more etching processes. The etching process may be a dry etching process, one or more other applicable processes, or a combination thereof.

[0067] Then, according to some embodiments, such as Figure 1D As shown, the patterned mask structure M2 is formed on the mask layer 150 . According to some embodiments, the patterned mask structure M2 is a multi-layer mask structure. According to some embodiments, the patterned mask structure M2 includes a lower layer 190 , a middle layer 200 , and an upper layer 210 .

[0068] According to some embodiments, Figure 1D As shown, the lower layer 190, the middle layer 200 and the upper layer 210 are sequentially deposited on the mask layer 150. In some embodiments, the lower layer 190 is made of or includes a polymer material. In some embodiments, the middle layer 200 is made of or includes a silicon-containing material, such as a silicon-containing polymer material. In some embodiments, the upper layer 210 is made of or includes a photoresist material. In some embodiments, the lower layer 190, the middle layer 200 and the upper layer 210 are deposited by using a physical vapor deposition process, a chemical vapor deposition process, a spin coating process, other applicable processes or a combination thereof.

[0069] According to some embodiments, the upper layer 210 is patterned to form a trench 212 in the upper layer 210. The trench 212 partially exposes the middle layer 200. The upper layer 210 is patterned by a photolithography process.

[0070] Thereafter, the middle layer 200 is patterned or etched by using the patterned upper layer 210 as an etching mask. Thus, the grooves 212 are transferred to the middle layer 200 (not shown). The patterned upper layer 210 can be removed during the patterning of the middle layer 200. Similarly, the lower layer 190 is then patterned or etched by using the patterned middle layer 200 as an etching mask. Thus, the grooves 212 are transferred to the lower layer 190 (not shown). The patterned middle layer 200 can be removed during the patterning of the lower layer 190.

[0071] The patterned lower layer 190 is subsequently used as an etching mask to pattern the mask layer 150. According to some embodiments, Figure 1E As shown, the mask layer 150 is patterned or etched using the patterned lower layer 190 as an etching mask. Therefore, grooves 152 and 154 are formed in the mask layer 150. The grooves 152 and 154 penetrate the mask layer 150. According to some embodiments, the grooves 152 and 154 partially expose the hard mask layer 140 thereunder. The patterned lower layer 190 may be removed during the patterning of the mask layer 150.

[0072] In some embodiments, the middle layer 200, the lower layer 190, and the mask layer 150 are sequentially patterned by using one or more etching processes. The etching process may be a dry etching process, one or more other applicable processes, or a combination thereof.

[0073] Then, according to some embodiments, such as Figure 1E As shown, trenches 151, 152, 153, and 154 have widths W1, W2, W3, and W4, respectively. According to some embodiments, widths W1, W2, W3, and W4 are substantially equal to each other. According to some embodiments, the term "substantially equal" means "within 10%."

[0074] For example, according to some embodiments, the term "substantially equal" means that the difference between widths W1, W2, W3, and W4 is within 10% of the average width of trenches 151, 152, 153, and 154. According to some embodiments, trenches 151, 152, 153, and 154 have inner walls N1, N2, N3, and N4 and bottom surfaces B1, B2, B3, and B4.

[0075] Then, according to some embodiments, such as Figure 1F As shown, mask layer 220 is deposited over mask layer 150 and in trenches 151, 152, 153, and 154. According to some embodiments, mask layer 220 conformally covers top surface 155, inner walls N1, N2, N3, and N4, and bottom surfaces B1, B2, B3, and B4 of mask layer 150. According to some embodiments, mask layer 220 directly contacts hard mask layer 140 and mask layer 150.

[0076] In some embodiments, a first thickness T1 of the mask layer 220 above the top surface 155 is greater than a second thickness T2 of the mask layer 220 above the inner walls N1, N2, N3, and N4. According to some embodiments, the second thickness T2 is greater than a third thickness T3 of the mask layer 220 above the bottom surfaces B1, B2, B3, and B4.

[0077] According to some embodiments, the mask layer 220 is also called an anti-reflective coating (ARC) layer. The mask layer 220 is made of an anti-reflective material (e.g., SiON, SiCN, SiN, HfO, Al2O3, Ta2O5, ZrO), one or more other suitable materials, or a combination thereof, or includes the aforementioned materials.

[0078] In some embodiments, the mask layer 220 and the mask layer 150 are made of or include the same material. In some embodiments, the mask layer 220 is a nitrogen-free anti-reflective coating (NFARC) layer. The mask layer 220 is deposited using a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0079] According to some embodiments, Figure 1G As shown, the mask layer 220 covering the bottom surfaces B1, B2, B3, and B4 is removed to form trenches 222, 224, 226, and 228 in the mask layer 220. According to some embodiments, the trenches 222, 224, 226, and 228 expose the bottom surfaces B1, B2, B3, and B4, respectively.

[0080] According to some embodiments, the trenches 222 and 224 have widths W5 and W6, respectively. According to some embodiments, the widths W5 and W6 are smaller than the widths W1, W2, W3, and W4. According to some embodiments, after the removal process, the remaining mask layer 220 covers the inner walls N1, N2, N3, and N4 and the top surface 155. According to some embodiments, the removal process includes a dry etching process (e.g., an anisotropic etching process) or a wet etching process. According to some embodiments, the dry etching process includes a plasma etching process.

[0081] According to some embodiments, Figure 1H As shown, the photoresist layer 230 is formed on the mask layer 220 in the region 110A. According to some embodiments, the photoresist layer 230 fills the trenches 151 and 152. According to some embodiments, as Fig. 1I As shown, the mask layer 220 in the region 110B is removed. According to some embodiments, the removal process includes an etching process, such as a dry etching process.

[0082] According to some embodiments, Figure 1J As shown, the photoresist layer 230 is removed. According to some embodiments, the mask layer 220 has a sidewall 229 aligned with the boundary between the region 110A and the region 110B. In some embodiments, the ratio of the thickness T2 of the mask layer 220 above the inner wall N1 to the width W1 of the trench 151 is between about 0.16 and about 0.4. In some embodiments, the ratio of the width W5 of the trench 222 to the width W1 of the trench 151 is between about 0.16 and about 0.66. In some embodiments, the distance D1 between the trench 222 and the trench 224 is less than the distance D2 between the trench 153 and the trench 154.

[0083] According to some embodiments, the mask layers 150 and 220 are used as etching masks for forming conductive lines in subsequent processes. Although the widths W1, W2, W3, and W4 of the trenches 151, 152, 153, and 154 are substantially equal to each other, the mask layer 220 formed on the inner walls N1 and N2 of the trenches 151 and 152 has trenches 222 and 224 narrower than the trenches 151, 152, 153, and 154. Therefore, the formation of the mask layer 220 can narrow the conductive lines formed subsequently by using the mask layer 220 as an etching mask.

[0084] According to some embodiments, Figure 1K As shown, portions of the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 beneath the trenches 222 , 224 , 153 , and 154 are removed to form trenches R1 , R2 , R3 , and R4 in the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 .

[0085] According to some embodiments, trenches R1, R2, R3, and R4 pass through hard mask layer 140 and mask layer 130 and penetrate into dielectric layer 120. According to some embodiments, trenches R1, R2, R3, and R4 have widths W7, W8, W9, and W10, respectively. According to some embodiments, width W7 or W8 is smaller than width W9 or W10.

[0086] According to some embodiments, the removal process includes an etching process using the mask layers 150 and 220 as etching masks. The mask layers 150 and 220 may be consumed during the removal process. In some embodiments, an upper portion of the hard mask layer 140 is consumed during the removal process.

[0087] Since the mask layer 220 covers the hard mask layer 140 in the region 110A during the removal process, the hard mask layer 140 remaining in the region 110A is thicker than the hard mask layer 140 remaining in the region 110B. That is, the thickness T9 of the hard mask layer 140 in the region 110A is greater than the thickness T10 of the hard mask layer 140 in the region 110B. In some embodiments, the hard mask layer 140 remaining in the region 110A is also referred to as a thick portion, and the hard mask layer 140 remaining in the region 110B is also referred to as a thin portion. In some embodiments, the boundary between the thick portion and the thin portion is aligned with the sidewall 229 (e.g., Figure 1J as shown).

[0088] According to some embodiments, Figure 1L As shown, barrier layer 240 is deposited over hard mask layer 140, mask layer 130, and dielectric layer 120. Barrier layer 240 may prevent metal ions of a subsequently deposited conductive material (which will be described in more detail later) from diffusing into dielectric layer 120 during a thermal process or thermal cycle. Barrier layer 240 may also be referred to as a diffusion barrier layer.

[0089] In some embodiments, the barrier layer 240 is made of or includes a refractory metal material such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the barrier layer 240 is deposited using a physical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof. In some embodiments, the barrier layer 240 is conformally deposited.

[0090] According to some embodiments, Figure 1LAs shown, a conductive material layer 250 is formed on the barrier layer 240. According to some embodiments, the trenches R1, R2, R3, and R4 are filled with the conductive material layer 250 and the barrier layer 240. In some embodiments, the conductive material layer 250 is made of a metal material (e.g., copper, aluminum, tungsten, titanium, nickel, gold, platinum, silver, one or more other suitable materials, or a combination thereof), or includes the foregoing materials.

[0091] The conductive material layer 250 may be a single layer or have multiple stacked layers. The conductive material layer 250 is deposited by using an electroplating process, a physical vapor deposition process, a chemical vapor deposition process, an electroless plating process, other applicable processes, or a combination thereof.

[0092] According to some embodiments, Figure 1M As shown, the conductive material layer 250 and the barrier layer 240 outside the trenches R1, R2, R3 and R4, the hard mask layer 140 and the mask layer 130 are removed. According to some embodiments, the conductive material layer 250 and the barrier layer 240 remaining in the trenches R1, R2, R3 and R4 form conductive structures L1, L2, L3 and L4 in the trenches R1, R2, R3 and R4, respectively.

[0093] According to some embodiments, the conductive structures L1, L2, L3, and L4 include conductive lines. According to some embodiments, the conductive structures L1, L2, L3, and L4 have widths (or line widths) W11, W12, W13, and W14, respectively. Since the width W7 or W8 is smaller than the width W9 or W10 (e.g. Figure 1K ), so width W11 or W12 is smaller than width W13 or W14. According to some embodiments, widths W11 and W12 are substantially equal to each other. According to some embodiments, widths W13 and W14 are substantially equal to each other.

[0094] According to some embodiments, conductive structures L1 and L2 are located in region 110A, and conductive structures L3 and L4 are located in region 110B. According to some embodiments, a distance D1 between conductive structures L1 and L2 is smaller than a distance D2 between conductive structures L3 and L4.

[0095] Regions 110A and 110B may be referred to as small pitch regions and large pitch regions, respectively. The pitch of a region is equal to the sum of the width of one of the conductive structures and the spacing between two adjacent conductive structures in the region. According to some embodiments, the pitch of region 110A is equal to the sum of the width W11 (or W12) and the distance D1. According to some embodiments, the pitch of region 110B is equal to the sum of the width W13 (or W14) and the distance D2. Since the width W11 (or W12) is smaller than the width W13 (or W14) and the distance D1 is smaller than the distance D2, the pitch of region 110A is smaller than the pitch of region 110B.

[0096] According to some embodiments, the removal process includes a planarization process. Therefore, according to some embodiments, the top surfaces S1 , S2 , S3 , S4 of the conductive structures L1 , L2 , L3 , and L4 and the top surface 122 of the dielectric layer 120 are coplanar.

[0097] Figure 2A-2C Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 2A-2C An embodiment similar to Figures 1A-1M Embodiments, except Figure 2A-2C The embodiment first removes the mask layer 220 in the area 110B (eg Figure 2B ), and then remove the mask layer 220 covering the bottom surfaces B1 and B2 (as shown in FIG. Figure 2C shown).

[0098] exist Figure 1F After the step of, according to some embodiments, Figure 2A As shown, the photoresist layer 230 is formed on the mask layer 220 in the region 110A. Then, according to some embodiments, as Figure 2B As shown, the mask layer 220 in the region 110B is removed. According to some embodiments, the removal process includes an etching process using the photoresist layer 230 as an etching mask.

[0099] According to some embodiments, Figure 2C As shown, the photoresist layer 230 is removed. According to some embodiments, Figure 2C As shown, the mask layer 220 covering the bottom surfaces B1 and B2 is removed to form grooves 222 and 224 in the mask layer 220. According to some embodiments, the grooves 222 and 224 expose the bottom surfaces B1 and B2, respectively. Then, according to some embodiments, Figure 1K-1M Steps to form conductive structures L1, L2, L3 and L4 (such as Figure 1M shown).

[0100] Figures 3A-3H Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1E After the step of, according to some embodiments, Figure 3A As shown, the mask layer 310 is formed over the top surface 155 of the mask layer 150 and the inner walls N1 , N2 , N3 , and N4 of the trenches 151 , 152 , 153 , and 154 .

[0101] In some embodiments, the thickness T4 of the mask layer 310 above the inner walls N1, N2, N3, and N4 increases along a direction V1 away from the dielectric layer 120. According to some embodiments, the mask layer 310 has grooves 312, 314, 316, and 318 in the grooves 151, 152, 153, and 154, respectively. According to some embodiments, the grooves 312, 314, 316, and 318 expose bottom surfaces B1, B2, B3, and B4 of the grooves 151, 152, 153, and 154, respectively.

[0102] According to some embodiments, the mask layer 310 covering the top surface 155 is thicker than the mask layer 310 covering the inner walls N1, N2, N3, and N4 of the grooves 151, 152, 153, and 154. That is, according to some embodiments, the maximum thickness T5 of the mask layer 310 covering the top surface 155 is greater than the maximum thickness T4' of the mask layer 310 above the inner walls N1, N2, N3, and N4.

[0103] According to some embodiments, the mask layer 310 is also called an anti-bombardment layer. According to some embodiments, the mask layer 310 is used to maintain the height of the mask layer 150 thereunder for a longer time during a subsequent etching process (eg, dry etching process) for forming trenches in the dielectric layer 120.

[0104] According to some embodiments, the mask layer 310 is made of a bombardment resistant material (e.g., titanium nitride or tantalum nitride). According to some embodiments, the mask layer 310 is formed by using a chemical vapor deposition process or an atomic layer deposition process. According to some embodiments, the mask layer 310 is deposited at a first deposition pressure. According to some embodiments, the mask layer 310 is deposited at a first deposition power.

[0105] According to some embodiments, Figure 3B As shown, mask layer 220 is formed over mask layer 310 and hard mask layer 140 exposed through trenches 151, 152, 153, and 154. According to some embodiments, mask layer 220 covers inner walls N1, N2, N3, and N4 and bottom surfaces B1, B2, B3, and B4 of trenches 151, 152, 153, and 154.

[0106] According to some embodiments, the mask layer 220 is also referred to as a chemical etching resistance protection layer. According to some embodiments, the mask layer 220 is used to protect the inner walls N1, N2, N3, and N4 during a subsequent etching process (e.g., a dry etching process) used to form a trench in the dielectric layer 120. According to some embodiments, the mask layer 220 directly contacts the mask layers 150 and 310 and the hard mask layer 140.

[0107] In some embodiments, a first thickness T6 of the mask layer 220 above the top surface 155 is greater than a second thickness T7 of the mask layer 220 above the inner walls N1, N2, N3, and N4. According to some embodiments, the second thickness T7 is greater than a third thickness T8 of the mask layer 220 above the bottom surfaces B1, B2, B3, and B4.

[0108] According to some embodiments, the mask layers 220 and 310 are made of different materials. According to some embodiments, the mask layer 220 is made of a chemical etching resistant material such as a nitride material (e.g., SiON, SiCN, SiN) or a low temperature oxide material (e.g., silicon dioxide) or includes the foregoing materials. The mask layer 220 is deposited by using a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0109] According to some embodiments, the mask layer 220 is deposited at a second deposition pressure. According to some embodiments, the mask layer 220 is deposited at a second deposition power. If the deposition pressure is high and the deposition power is low, the deposition layer tends to be deposited outside the groove. If the deposition pressure is low and the deposition power is high, the deposition layer tends to be deposited in the groove. Therefore, according to some embodiments, the first deposition pressure is greater than the second deposition pressure. According to some embodiments, the first deposition power is less than the second deposition power.

[0110] According to some embodiments, Figure 3C As shown, the mask layer 220 above the bottom surfaces B1, B2, B3, and B4 is removed. According to some embodiments, the removal process forms trenches 222, 224, 226, and 228 in the mask layer 220. According to some embodiments, the trenches 222, 224, 226, and 228 are located in the trenches 312, 314, 316, and 318, respectively. According to some embodiments, the trenches 222, 224, 226, and 228 expose the bottom surfaces B1, B2, B3, and B4, respectively. According to some embodiments, the removal process includes an etching process (e.g., a dry etching process or a wet etching process).

[0111] According to some embodiments, Figure 3D As shown, the photoresist layer 230 is formed on the mask layer 220 in the region 110A. According to some embodiments, the photoresist layer 230 fills the trenches 151 and 152. According to some embodiments, as Figure 3E As shown, the mask layers 220 and 310 in the region 110B are removed. According to some embodiments, the removal process includes an etching process (eg, a dry etching process).

[0112] According to some embodiments, Figure 3FAs shown, the photoresist layer 230 is removed. In some embodiments, the distance D1 between the trenches 222 and 224 is smaller than the distance D2 between the trenches 153 and 154. According to some embodiments, the mask layers 150, 220, and 310 are used as etching masks in subsequent processes for forming conductive lines.

[0113] According to some embodiments, Figure 3G As shown, portions of the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 beneath the trenches 222 , 224 , 153 , and 154 are removed to form trenches R1 , R2 , R3 , and R4 in the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 .

[0114] According to some embodiments, trenches R1, R2, R3, and R4 pass through hard mask layer 140 and mask layer 130 and penetrate into dielectric layer 120. According to some embodiments, trenches R1, R2, R3, and R4 have widths W7, W8, W9, and W10, respectively. According to some embodiments, width W7 or W8 is smaller than width W9 or W10.

[0115] According to some embodiments, the removal process includes an etching process using the mask layers 150, 220, and 310 as etching masks. The mask layers 150, 220, and 310 may be consumed during the removal process. In some embodiments, an upper portion of the hard mask layer 140 is consumed during the removal process.

[0116] According to some embodiments, Figure 3F and 3G As shown, since the mask layer (or anti-bombardment layer) 310 covers the top surface 155 of the mask layer 150, the height of the mask layer 150 is maintained for a longer time during the removal process. Figure 3F and 3G As shown, since the mask layer 220 is made of a chemical etching resistant material, the widths W5 and W6 of the trenches 222 and 224 of the mask layer 220 are maintained for a longer time during the removal process. Figure 3F and 3G As shown, the formation of the mask layers 220 and 310 can improve the yield of the trenches R1 and R2 .

[0117] According to some embodiments, Figure 3G As shown, barrier layer 240 is deposited over hard mask layer 140, mask layer 130, and dielectric layer 120. Barrier layer 240 may prevent metal ions of a subsequently deposited conductive material (which will be described in more detail later) from diffusing into dielectric layer 120 during a thermal process or thermal cycle. Barrier layer 240 may also be referred to as a diffusion barrier layer.

[0118] In some embodiments, the barrier layer 240 is made of or includes a refractory metal material such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the barrier layer 240 is deposited using a physical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof. In some embodiments, the barrier layer 240 is conformally deposited.

[0119] According to some embodiments, Figure 3G As shown, a conductive material layer 250 is formed over the barrier layer 240. According to some embodiments, the trenches R1, R2, R3, and R4 are filled with the conductive material layer 250 and the barrier layer 240.

[0120] According to some embodiments, Figure 3H As shown, the conductive material layer 250 and the barrier layer 240 outside the trenches R1, R2, R3 and R4, the hard mask layer 140 and the mask layer 130 are removed. According to some embodiments, the conductive material layer 250 and the barrier layer 240 remaining in the trenches R1, R2, R3 and R4 form conductive structures L1, L2, L3 and L4 in the trenches R1, R2, R3 and R4, respectively.

[0121] According to some embodiments, the conductive structures L1, L2, L3, and L4 include conductive lines. According to some embodiments, the conductive structures L1, L2, L3, and L4 have widths (or line widths) W11, W12, W13, and W14, respectively. Since the width W7 or W8 is smaller than the width W9 or W10 (e.g. Figure 3G As shown), therefore, width W11 or W12 is smaller than width W13 or W14.

[0122] According to some embodiments, conductive structures L1 and L2 are located in region 110A, and conductive structures L3 and L4 are located in region 110B. According to some embodiments, a distance D1 between conductive structures L1 and L2 is smaller than a distance D2 between conductive structures L3 and L4.

[0123] According to some embodiments, the removal process includes a planarization process. Therefore, according to some embodiments, the top surfaces S1 , S2 , S3 , S4 of the conductive structures L1 , L2 , L3 , and L4 and the top surface 122 of the dielectric layer 120 are coplanar.

[0124] Figures 4A-4F Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1E After the step of, according to some embodiments, Figure 4AAs shown, the mask layer 220 is conformally formed over the top surface 155 of the mask layer 150, the inner walls N1, N2, N3 and N4, and the bottom surfaces B1, B2, B3 and B4 of the trenches 151, 152, 153 and 154. According to some embodiments, the mask layer 220 is made of a chemical etching resistant material such as a nitride material (such as SiON, SiCN or SiN) or a low temperature oxide material (such as silicon dioxide), or includes the foregoing material.

[0125] According to some embodiments, Figure 4B As shown, the mask layer 220 above the bottom surfaces B1, B2, B3, and B4 is removed. According to some embodiments, the mask layer 220 has grooves 222, 224, 226, and 228. According to some embodiments, as Figure 4C As shown, the mask layer 310 is formed on the mask layer 220 .

[0126] According to some embodiments, the mask layer 310 covers the top surface 221 of the mask layer 220 and the inner walls 222a, 224a, 226a, and 228a of the grooves 222, 224, 226, and 228. In some embodiments, the thickness T4 of the mask layer 310 above the inner walls 222a, 224a, 226a, and 228a increases along the direction V1 away from the dielectric layer 120. According to some embodiments, the mask layer 310 is made of a bombardment-resistant material, such as a nitride material (such as titanium nitride or tantalum nitride). According to some embodiments, the mask layers 220 and 310 are made of different materials.

[0127] According to some embodiments, Figure 4D As shown, the mask layers 220 and 310 in the region 110B are removed. According to some embodiments, Figure 4E As shown, portions of the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 beneath the trenches 222 , 224 , 153 , and 154 are removed to form trenches R1 , R2 , R3 , and R4 in the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 .

[0128] According to some embodiments, trenches R1, R2, R3, and R4 pass through hard mask layer 140 and mask layer 130 and penetrate into dielectric layer 120. According to some embodiments, the removal process includes an etching process using mask layers 150, 220, and 310 as etching masks. Mask layers 150, 220, and 310 may be consumed during the removal process. In some embodiments, an upper portion of hard mask layer 140 is consumed during the removal process.

[0129] According to some embodiments, Figure 4D and 4EAs shown, since the mask layer (or anti-bombardment layer) 310 covers the top surface 155 of the mask layer 150, the height of the mask layer 150 is maintained for a longer time during the removal process. Figure 4D and 4E As shown, since the mask layer 220 is made of a chemical etching resistant material, the widths W5 and W6 of the trenches 222 and 224 of the mask layer 220 are maintained for a longer time during the removal process. Figure 4D and 4E As shown, the formation of the mask layers 220 and 310 can improve the yield of the trenches R1 and R2 .

[0130] According to some embodiments, Figure 4E As shown, barrier layer 240 is deposited over hard mask layer 140, mask layer 130, and dielectric layer 120. According to some embodiments, Figure 4E As shown, a conductive material layer 250 is formed over the barrier layer 240 .

[0131] According to some embodiments, Figure 4F As shown, the conductive material layer 250 and the barrier layer 240 outside the trenches R1, R2, R3 and R4, the hard mask layer 140 and the mask layer 130 are removed. According to some embodiments, the conductive material layer 250 and the barrier layer 240 remaining in the trenches R1, R2, R3 and R4 form conductive structures L1, L2, L3 and L4 in the trenches R1, R2, R3 and R4, respectively.

[0132] According to some embodiments, the conductive structures L1, L2, L3, and L4 include conductive lines. According to some embodiments, the conductive structures L1, L2, L3, and L4 have widths (or line widths) W11, W12, W13, and W14, respectively. According to some embodiments, the width W11 or W12 is smaller than the width W13 or W14. According to some embodiments, the distance D1 between the conductive structure L1 and the conductive structure L2 is smaller than the distance D2 between the conductive structure L3 and the conductive structure L4.

[0133] According to some embodiments, the removal process includes a planarization process. Therefore, according to some embodiments, the top surfaces S1 , S2 , S3 , S4 of the conductive structures L1 , L2 , L3 , and L4 and the top surface 122 of the dielectric layer 120 are coplanar.

[0134] According to some embodiments, methods for forming semiconductor device structures are provided. These methods (for forming semiconductor device structures) include: forming a first mask layer over a dielectric layer; conformally forming a second mask layer over an inner wall of a first trench of the first mask layer; and removing the dielectric layer through the first trench to form a second trench in the dielectric layer. Forming the second mask layer over the inner wall can narrow the second trench.

[0135] According to some embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer over a dielectric layer. The first mask layer has a first trench, the first trench having an inner wall and a bottom surface. The method comprises forming a second mask layer in the first trench. The method comprises removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method comprises removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method comprises forming a conductive structure in the third trench.

[0136] In some other embodiments, the step of forming a second mask layer in the first trench includes conformally depositing the second mask layer over the inner wall and the bottom surface.

[0137] In some other embodiments, the second mask layer is more conformally deposited over the top surface of the first mask layer.

[0138] In some other embodiments, a first thickness of the second mask layer over the top surface is greater than a second thickness of the second mask layer over the inner wall, and the second thickness is greater than a third thickness of the second mask layer over the bottom surface.

[0139] In some other embodiments, after forming the conductive structure, the first top surface of the conductive structure is coplanar with the second top surface of the dielectric layer.

[0140] In some other embodiments, the first mask layer and the second mask layer are made of the same material.

[0141] In some other embodiments, the dielectric layer and the first mask layer are made of different materials.

[0142] According to some embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer over a dielectric layer. The first mask layer has a first trench and a second trench, and the first trench has a first inner wall and a first bottom surface. The method comprises conformally forming a second mask layer over the first inner wall. The second mask layer has a third trench in the first trench and exposes the first bottom surface, the third trench is narrower than the second trench, and the third trench and the second trench are respectively over a first portion and a second portion of the dielectric layer. The method comprises removing the first portion, the second portion, the first mask layer, and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer. The fourth trench is narrower than the fifth trench. The method comprises forming a first conductive structure and a second conductive structure in the fourth trench and the fifth trench, respectively.

[0143] In some other embodiments, the above method further includes forming a third mask layer above the dielectric layer before forming the first mask layer, wherein the first mask layer is formed on the third mask layer, and the second groove and the third groove respectively expose a third portion and a fourth portion of the third mask layer; and the step of removing the first portion, the second portion, the first mask layer and the second mask layer further includes removing the third portion and the fourth portion.

[0144] In some other embodiments, the steps of forming the first conductive structure and the second conductive structure include forming a conductive material layer above the third mask layer and the dielectric layer after removing the first part, the second part, the third part, the fourth part, the first mask layer, and the second mask layer, wherein the fourth trench and the fifth trench are filled with the conductive material layer; and removing the conductive material layer outside the fourth trench and the fifth trench and the third mask layer.

[0145] In some other embodiments, the step of removing the conductive material layer outside the fourth trench, the fifth trench and the third mask layer includes performing a planarization process.

[0146] In some other embodiments, the third mask layer and the first mask layer are made of different materials.

[0147] In some other embodiments, wherein the third mask layer has a fifth portion and a sixth portion, the fifth portion is covered by the second mask layer, the sixth portion is covered by the first mask layer and not covered by the second mask layer, and after removing the first portion, the second portion, the first mask layer, and the second mask layer, the sixth portion is thinner than the fifth portion.

[0148] In some other embodiments, the first width of the first trench is substantially equal to the second width of the second trench.

[0149] According to some embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first mask layer over a dielectric layer. The first mask layer has a first trench and a second trench, and the first trench has a first inner wall and a first bottom surface. The method comprises forming a second mask layer over the top surface and the first inner wall of the first mask layer. The thickness of the second mask layer over the first inner wall increases in a direction away from the dielectric layer, the second mask layer has a third trench in the first trench and exposes the first bottom surface, and the third trench and the second trench are respectively over a first portion and a second portion of the dielectric layer. The method comprises removing the first portion, the second portion, the first mask layer, and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer, the fourth trench being narrower than the fifth trench. The method comprises forming a first conductive structure and a second conductive structure in the fourth trench and the fifth trench, respectively.

[0150] In some other embodiments, the second mask layer covering the top surface is thicker than the second mask layer covering the first inner wall.

[0151] In some other embodiments, the above method further includes forming a third mask layer over the second mask layer and covering the first inner wall after forming a second mask layer over the top surface of the first mask layer and over the first inner wall and before removing the first portion, the second portion, the first mask layer and the second mask layer, and the step of removing the first portion, the second portion, the first mask layer and the second mask layer further includes removing the third mask layer.

[0152] In some other embodiments, the second mask layer and the third mask layer are made of different materials.

[0153] In some other embodiments, the above method further includes forming a third mask layer above the top surface and the first inner wall before forming the second mask layer above the top surface and the first inner wall of the first mask layer, the second mask layer is formed above the third mask layer, and the steps of removing the first portion, the second portion, the first mask layer and the second mask layer further include removing the third mask layer.

[0154] In some other embodiments, the second mask layer and the third mask layer are made of different materials.

[0155] The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present invention. Various changes, substitutions or modifications may be made to the present invention without departing from the spirit and scope of the invention of the present invention.

Claims

1. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench, and the first trench has an inner wall and a bottom surface; forming an anti-bombardment layer on a top surface of the first mask layer, and forming the anti-bombardment layer on the inner wall; forming a second mask layer in the first trench, wherein the second mask layer and the anti-bombardment layer are formed of different materials; removing the second mask layer covering the bottom surface to form a second trench in the second mask layer, wherein the second trench exposes the bottom surface and is above a first portion of the dielectric layer, and the remaining second mask layer covers the inner wall; removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer; and A conductive structure is formed in the third trench.

2. The method for forming a semiconductor device structure as described in claim 1, wherein the second mask layer is further formed on the anti-bombardment layer, the first thickness of the second mask layer on the anti-bombardment layer is greater than the second thickness of the second mask layer on the inner wall, and the second thickness is greater than the third thickness of the second mask layer on the bottom surface. 3 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein after forming the conductive structure, a first top surface of the conductive structure is coplanar with a second top surface of the dielectric layer. 4 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the first mask layer and the second mask layer are formed of the same material. 5 . The method for forming a semiconductor device structure as claimed in claim 4 , wherein the dielectric layer and the first mask layer are formed of different materials. 6 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the second mask layer covers the anti-bombardment layer. 7 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the anti-bombardment layer near the dielectric layer is thinner than the anti-bombardment layer near the top surface of the first mask layer.

8. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench and a second trench, and the first trench has a first inner wall and a first bottom surface; Forming a second mask layer on the first inner wall, wherein the second mask layer has a third groove in the first groove and exposes the first bottom surface, the third groove is narrower than the second groove, and the third groove and the second groove are respectively on a first portion and a second portion of the dielectric layer; removing the first portion, the second portion, the first mask layer, and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer, wherein the fourth trench is narrower than the fifth trench; forming a first conductive structure and a second conductive structure in the fourth trench and the fifth trench respectively; as well as Before forming the first mask layer, forming a third mask layer on the dielectric layer, The first mask layer is formed on the third mask layer, the second groove and the third groove expose a third portion and a fourth portion of the third mask layer respectively, and Wherein removing the first portion, the second portion, the first mask layer and the second mask layer further includes: removing the third portion and the fourth portion.

9. The method for forming a semiconductor device structure as claimed in claim 8, wherein the step of forming the first conductive structure and the second conductive structure comprises: After removing the first portion, the second portion, the third portion, the fourth portion, the first mask layer, and the second mask layer, forming a conductive material layer on the third mask layer and the dielectric layer, wherein the conductive material layer fills the fourth trench and the fifth trench; and The conductive material layer outside the fourth trench, the fifth trench and the third mask layer is removed. 10 . The method for forming a semiconductor device structure as claimed in claim 9 , wherein the step of removing the conductive material layer outside the fourth trench, the fifth trench and the third mask layer comprises performing a planarization process. 11 . The method for forming a semiconductor device structure as claimed in claim 8 , wherein the third mask layer and the first mask layer are formed of different materials.

12. A method for forming a semiconductor device structure as described in claim 8, wherein the third mask layer has a fifth portion and a sixth portion, the fifth portion is covered by the second mask layer, the sixth portion is covered by the first mask layer and not covered by the second mask layer, and after removing the first portion, the second portion, the first mask layer and the second mask layer, the sixth portion is thinner than the fifth portion. 13 . The method for forming a semiconductor device structure as claimed in claim 8 , wherein a first width of the first trench is equal to a second width of the second trench.

14. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench and a second trench, and the first trench has a first inner wall and a first bottom surface; Forming a second mask layer on a top surface of the first mask layer and the first inner wall, wherein the thickness of the second mask layer on the first inner wall increases in a direction away from the dielectric layer, the second mask layer has a third groove in the first groove and exposes the first bottom surface, and the third groove and the second groove are respectively on a first portion and a second portion of the dielectric layer; removing the first portion, the second portion, the first mask layer, and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer, the fourth trench being narrower than the fifth trench; as well as A first conductive structure and a second conductive structure are formed in the fourth trench and the fifth trench respectively. 15 . The method for forming a semiconductor device structure as claimed in claim 14 , wherein the second mask layer covering the top surface is thicker than the second mask layer covering the first inner wall.

16. The method for forming a semiconductor device structure according to claim 14, further comprising: After forming the second mask layer on the top surface of the first mask layer and the first inner wall, and before removing the first portion, the second portion, the first mask layer and the second mask layer, forming a third mask layer on the second mask layer and covering the first inner wall, and The step of removing the first portion, the second portion, the first mask layer and the second mask layer further includes removing the third mask layer. 17 . The method for forming a semiconductor device structure as claimed in claim 16 , wherein the second mask layer and the third mask layer are formed of different materials.

18. The method for forming a semiconductor device structure as claimed in claim 14, further comprising forming a third mask layer on the top surface and the first inner wall before forming the second mask layer on the top surface and the first inner wall of the first mask layer, the second mask layer being formed on the third mask layer, and The step of removing the first portion, the second portion, the first mask layer and the second mask layer further includes removing the third mask layer. 19 . The method for forming a semiconductor device structure as claimed in claim 18 , wherein the second mask layer and the third mask layer are formed of different materials.

20. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench, and the first trench has an inner wall and a bottom surface; forming a second mask layer on a first top surface, the inner wall and the bottom surface of the first mask layer; removing the second mask layer covering the bottom surface to form a second trench in the second mask layer, wherein the second trench exposes the bottom surface and is on a first portion of the dielectric layer; forming an anti-bombardment layer on a second top surface of the second mask layer, wherein the second mask layer and the anti-bombardment layer are formed of different materials; removing the first portion, the first mask layer, the second mask layer and the anti-bombardment layer to form a third trench in the dielectric layer; as well as A conductive structure is formed in the third trench. 21 . The method for forming a semiconductor device structure as claimed in claim 20 , wherein the anti-bombardment layer covers a side wall of the second mask layer. 22 . The method for forming a semiconductor device structure as claimed in claim 21 , wherein the anti-bombardment layer covers an upper portion of the sidewall and exposes a lower portion of the sidewall. 23 . The method for forming a semiconductor device structure as claimed in claim 21 , wherein the anti-bombardment layer and the first mask layer are formed of different materials. 24 . The method for forming a semiconductor device structure as claimed in claim 21 , wherein the anti-bombardment layer on the second top surface of the second mask layer is thicker than the anti-bombardment layer on the sidewall of the second mask layer. 25 . The method for forming a semiconductor device structure as claimed in claim 20 , wherein the anti-bombardment layer has a fourth trench, the fourth trench exposes the bottom surface and is on the first portion of the dielectric layer.

26. The method for forming a semiconductor device structure as claimed in claim 25, wherein the step of removing the first portion of the dielectric layer comprises: The first portion is removed through the second trench of the second mask layer and the fourth trench of the anti-bombardment layer.

27. The method for forming a semiconductor device structure as described in claim 20, wherein the second mask layer on the first top surface of the first mask layer is thicker than the second mask layer on the inner wall, and the second mask layer on the inner wall is thicker than the second mask layer on the bottom surface. 28 . The method for forming a semiconductor device structure as claimed in claim 20 , wherein the first mask layer and the second mask layer are formed of the same material. 29 . The method for forming a semiconductor device structure as claimed in claim 28 , wherein the dielectric layer and the first mask layer are formed of different materials.

30. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench and a second trench, and the first trench has a first inner wall and a first bottom surface; Forming a second mask layer on the first inner wall, wherein the second mask layer has a third groove in the first groove and exposes the first bottom surface, the third groove is narrower than the second groove, and the third groove and the second groove are respectively on a first portion and a second portion of the dielectric layer; forming an anti-bombardment layer on a first top surface of the first mask layer and a second top surface of the second mask layer, wherein the second mask layer and the anti-bombardment layer are formed of different materials; removing the first portion, the second portion, the first mask layer, the second mask layer, and the anti-bombardment layer to form a fourth trench and a fifth trench in the dielectric layer, wherein the fourth trench is narrower than the fifth trench; as well as A first conductive structure and a second conductive structure are formed in the fourth trench and the fifth trench respectively.

31. The method for forming a semiconductor device structure according to claim 30, further comprising: Before forming the first mask layer, forming a third mask layer on the dielectric layer, wherein the first mask layer is formed on the third mask layer, the second groove and the third groove respectively expose a third portion and a fourth portion of the third mask layer, and The removing of the first portion, the second portion, the first mask layer, the second mask layer and the anti-bombardment layer further comprises: The third portion and the fourth portion are removed.

32. The method for forming a semiconductor device structure according to claim 31, wherein the step of forming the first conductive structure and the second conductive structure comprises: After removing the first portion, the second portion, the third portion, the fourth portion, the first mask layer, the second mask layer and the anti-bombardment layer, forming a conductive material layer on the third mask layer and the dielectric layer, wherein the conductive material layer fills the fourth trench and the fifth trench; as well as The third mask layer and the conductive material layer outside the fourth trench and the fifth trench are removed. 33 . The method for forming a semiconductor device structure as claimed in claim 31 , wherein the third mask layer and the first mask layer are formed of different materials.

34. A method for forming a semiconductor device structure as described in claim 31, wherein the third mask layer has a fifth portion and a sixth portion, the fifth portion is covered by the second mask layer, the sixth portion is covered by the first mask layer and is not covered by the second mask layer, and after removing the first portion, the second portion, the first mask layer, the second mask layer and the anti-bombardment layer, the sixth portion is thinner than the fifth portion.

35. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench and a second trench, and the first trench has an inner wall and a bottom surface; A second mask layer is formed on a first portion of a top surface of the first mask layer and the inner wall, wherein the second mask layer exposes a second portion of the top surface, the first portion and the second portion are adjacent to the first groove and the second groove respectively, the second mask layer has a third groove in the first groove and exposes the bottom surface, and the third groove and the second groove are respectively on a third portion and a fourth portion of the dielectric layer; removing the third portion, the fourth portion, the first mask layer, and the second mask layer to form a fourth trench and a fifth trench in the dielectric layer; as well as A first conductive structure and a second conductive structure are formed in the fourth trench and the fifth trench respectively. 36 . The method for forming a semiconductor device structure as claimed in claim 35 , wherein a thickness of the second mask layer on the inner wall increases in a direction away from the dielectric layer. 37 . The method for forming a semiconductor device structure as claimed in claim 36 , wherein the second mask layer covering the first portion of the top surface is thicker than the second mask layer covering the inner wall.

38. The method for forming a semiconductor device structure according to claim 35, further comprising: Before forming the second mask layer on the first portion of the top surface and the inner wall of the first mask layer, a third mask layer is formed on the top surface and the inner wall, and the second mask layer is formed on the third mask layer, and Removing the third portion, the fourth portion, the first mask layer, and the second mask layer further includes removing the third mask layer. 39 . The method for forming a semiconductor device structure as claimed in claim 38 , wherein the second mask layer and the third mask layer are formed of different materials.

40. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface; forming an anti-bombardment layer on a first top surface of the first mask layer; Forming a second mask layer on the first inner wall of the first trench, wherein the second mask layer has a second trench, the second trench exposes the bottom surface and is located on a first portion of the dielectric layer, and the second mask layer and the anti-bombardment layer are formed of different materials; removing the first portion, the first mask layer, the anti-bombardment layer and the second mask layer to form a third trench in the dielectric layer; as well as A conductive structure is formed in the third trench. 41 . The method for forming a semiconductor device structure as claimed in claim 40 , wherein after forming the anti-bombardment layer on the first top surface of the first mask layer, the second mask layer is formed on the first inner wall. 42 . The method for forming a semiconductor device structure as claimed in claim 41 , wherein the second mask layer is further formed on a second top surface of the anti-bombardment layer. 43 . The method for forming a semiconductor device structure as claimed in claim 41 , wherein the anti-bombardment layer is further formed on the first inner wall of the first trench. 44 . The method for forming a semiconductor device structure as claimed in claim 43 , wherein a thickness of the anti-bombardment layer on the first inner wall decreases toward the dielectric layer. 45 . The method for forming a semiconductor device structure as claimed in claim 43 , wherein the second mask layer covers the anti-bombardment layer on the first inner wall. 46 . The method for forming a semiconductor device structure as claimed in claim 40 , wherein the second mask layer is formed on the first inner wall before the anti-bombardment layer is formed on the first top surface of the first mask layer. 47 . The method for forming a semiconductor device structure as claimed in claim 46 , wherein the anti-bombardment layer covers a second top surface of the second mask layer. 48 . The method for forming a semiconductor device structure as claimed in claim 47 , wherein the anti-bombardment layer further covers a second inner wall of the second trench of the second mask layer. 49 . The method for forming a semiconductor device structure as claimed in claim 48 , wherein a thickness of the anti-bombardment layer on the second inner wall decreases toward the dielectric layer.

50. A method for forming a semiconductor device structure, comprising: Forming a first mask layer on a dielectric layer, wherein the first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface; forming an anti-bombardment layer on a top surface of the first mask layer and the first inner wall of the first groove, wherein the anti-bombardment layer on the top surface is thicker than the anti-bombardment layer on the first inner wall; forming a second mask layer on the anti-bombardment layer on the first inner wall; removing the dielectric layer partially through the first trench to form a second trench in the dielectric layer; as well as A conductive structure is formed in the second trench. 51 . The method for forming a semiconductor device structure as claimed in claim 50 , wherein the first mask layer, the anti-bombardment layer and the second mask layer are consumed during the partial removal of the dielectric layer through the first trench.

52. A method for forming a semiconductor device structure as described in claim 50, wherein the first mask layer further has a third trench, the third trench has a second inner wall, the anti-bombardment layer and the second mask layer expose the second inner wall, partially removing the dielectric layer through the first trench further includes partially removing the dielectric layer through the third trench to form a fourth trench in the dielectric layer, and forming the conductive structure in the second trench further includes forming the conductive structure in the fourth trench.

53. The method for forming a semiconductor device structure as claimed in claim 52, wherein the second trench is narrower than the fourth trench.

54. The method for forming a semiconductor device structure as claimed in claim 50, wherein the second mask layer and the anti-bombardment layer are formed of different materials.

55. A method for forming a semiconductor device structure, comprising: forming a first mask layer on a dielectric layer; Forming a second mask layer on the first mask layer, wherein the second mask layer has a first groove, and the first groove has a first inner wall and a bottom surface; Forming a third mask layer on the first inner wall, wherein the third mask layer has a second groove, and the second groove is on a first portion of the first mask layer and a second portion of the dielectric layer; removing the first portion of the first mask layer, the second portion of the dielectric layer, the second mask layer, and the third mask layer to form a third trench in the dielectric layer; as well as A conductive structure is formed in the third trench.

56. The method for forming a semiconductor device structure as claimed in claim 55, wherein the step of forming the conductive structure in the third trench comprises: forming a conductive material layer on the first mask layer and in the third trench; as well as The first mask layer and the conductive material layer outside the third trench are removed.

57. The method for forming a semiconductor device structure as claimed in claim 55, wherein the third mask layer is further formed on a third portion of a top surface of the second mask layer.

58. A method for forming a semiconductor device structure as described in claim 55, wherein after removing the first portion of the first mask layer, the second portion of the dielectric layer, the second mask layer and the third mask layer, the remaining first mask layer initially under the third mask layer is thicker than the remaining first mask layer initially exposed by the third mask layer.

59. The method for forming a semiconductor device structure as claimed in claim 55, wherein the first mask layer and the second mask layer are formed of different materials.

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