RF Switching System

Abstract

A radio frequency switch system, comprising: a plurality of radio frequency switch circuits, each of the plurality of radio frequency switch circuits comprising a switch branch coupled between a first branch terminal and a second branch terminal, and configured to allow a radio frequency signal to pass through the switch branch in an on state, and to prevent the radio frequency signal from passing through the switch branch in an off state in response to a control signal applied to a branch control terminal of the switch branch. Also included is a switch controller, the switch controller being configured to apply the control signal to the branch control terminal of the switch branch of each of the plurality of radio frequency switch circuits, wherein the control signal has a first voltage level, the first voltage level placing the switch branch in the on state; and a second voltage level, the second voltage level placing the switch branch in the off state, without digital signal decoding of the control signal.

Description

[0001] Related Applications

[0002] This application claims the benefit of provisional patent application serial number 62 / 582,704, filed on November 7, 2017, the disclosure of which is hereby incorporated by reference in its entirety.

[0003] This application is related to: U.S. Patent Application Serial No. 16 / 161,444, filed on October 16, 2018, and entitled RADIO FREQUENCY SWITCHBRANCH CIRCUITRY, which claims the benefit of Provisional Patent Application Serial No. 62 / 582,714, filed on November 7, 2017; U.S. Patent Application Serial No. 16 / 161,543, filed on October 16, 2018, and entitled RECONFIGURABLE PATCH ANTENNA AND PHASED ARRAY, which claims the benefit of Provisional Patent Application Serial No. 62 / 583,195, filed on November 8, 2017; and U.S. Patent Application Serial No. 16 / 161,543, filed on October 16, 2018, and entitled RADIO FREQUENCY SWITCH CIRCUITRY's U.S. patent application serial number 16 / 161,454, which claims the benefit of provisional patent application serial number 62 / 582,704 filed on November 7, 2017, the disclosure of which is hereby incorporated by reference in its entirety. Field of the Invention

[0004] The present disclosure relates to radio frequency switching systems for wireless communications, and in particular to radio frequency systems in which radio frequency switching circuits with minimal real estate are required. Background Art

[0005] Radio frequency switching circuits are widely used in many applications, such as front-end modules and antenna tuning networks. As the capacity of cellular wireless networks increases due to consumer demand, new frequency bands are introduced along with new wireless standards. The fifth generation (5G) wireless network has new standards for wireless operation in the millimeter wavelength band including 28 GHz, 38 GHz and 66 GHz radio frequencies. Radio frequency switching circuits having switch branches coupled between signal ports must provide high isolation between signal ports through high impedance when the switch branches are in the off state and through low impedance when the switch branches are in the on state. The new 5G wireless radio presents a new challenge, namely, providing a high on-state / off-state impedance ratio while maintaining maximum isolation in the off state and maintaining minimum insertion loss in the on state. Therefore, a new radio frequency switching circuit is needed, which provides a high off-state / on-state impedance ratio for the switch branches while maintaining maximum isolation from the switch branches in the off state and maintaining minimum insertion loss in the switch branches in the on state. Summary of the invention

[0006] A radio frequency switch system includes: a plurality of radio frequency switch circuits, each of the plurality of radio frequency switch circuits includes a switch branch coupled between a first branch terminal and a second branch terminal, and is configured to allow radio frequency signals to pass through the switch branch in an on state, and to prevent radio frequency signals from passing through the switch branch in an off state in response to a control signal applied to a branch control terminal of the switch branch. Also included is a switch controller, the switch controller being configured to apply a control signal to a branch control terminal of a switch branch of each of the plurality of radio frequency switch circuits, wherein the control signal has a first voltage level, the first voltage level places the switch branch in an on state, and a second voltage level, the second voltage level places the switch branch in an off state, without digital signal decoding of the control signal.

[0007] Those skilled in the art will understand the scope of the present disclosure and recognize other aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

[0009] Figure 1A is a schematic diagram of a prior art switch branch 10 including a resistor network.

[0010] Figure 1B It is configured to switch the RF signal Figure 1A A simplified schematic diagram of a prior art switch branch.

[0011] Figure 1C is a simplified schematic diagram of a prior art switch branch, which illustrates the on-state resistance of the prior art switch branch when in the on-state.

[0012] Figure 1D is a simplified schematic diagram of a prior art switch branch, which illustrates the off-state capacitance of the prior art switch branch when in the off state.

[0013] Figure 2A is a graph of normalized on-state resistance of a switch branch in the prior art versus millimeter wave frequency.

[0014] Figure 2B 4 is a graph of normalized off-state capacitance of a switch branch in the prior art versus millimeter wave frequency.

[0015] Figure 2C This is a graph of the quality factor of the product of the on-state resistance and the off-state capacitance of the switch branch in the prior art versus the millimeter wave frequency.

[0016] Figure 3A is a schematic diagram of an on-state simulation circuit of a prior art switch branch represented as an on-state resistance between a first port terminal and a second port terminal.

[0017] Figure 3B is a schematic diagram of an off-state simulation circuit of a prior art switch branch represented as an off-state capacitance between a first port terminal and a second port terminal.

[0018] Figure 3C is based on Figure 3A The on-state simulation circuit and Figure 3B A simulation of the off-state analog circuit is performed to plot graphs of power gain, insertion loss, and isolation.

[0019] Figure 4 is a schematic diagram of one embodiment of a radio frequency switching circuit that provides a high off-state / on-state impedance ratio for a switch branch in accordance with the present disclosure.

[0020] Figure 5A is a graph of the insertion loss of an RF switching circuit with and without an isolation inductor.

[0021] Figure 5B is a graph of the isolation provided by placing an isolation inductor in parallel with the switching branch and the isolation provided by the switching branch alone.

[0022] Figure 5C yes Figure 4 A graph of the real and imaginary parts of the on-state impedance of an RF switching circuit.

[0023] Figure 5D yes Figure 4 A graph of the real and imaginary parts of the off-state impedance of an RF switching circuit.

[0024] Figure 6 is a schematic diagram of another embodiment of a radio frequency switching circuit including a first series capacitor and a second series capacitor for resonating with a first port inductor and a second port inductor.

[0025] Figure 7 is a graph of the real and imaginary parts of the on-state impedance with a first series capacitor and a second series capacitor added to the radio frequency switching circuit.

[0026] Figure 8 yes Figure 6 3D structure diagram of the RF switch circuit.

[0027] Fig. 9 is a schematic diagram of an exemplary embodiment of a radio frequency switch circuit that adds a first ESD shunt branch and a second ESD shunt branch configured to shunt electrostatic discharge (ESD) energy away from ESD sensitive components.

[0028] Fig.10 is a schematic diagram of an exemplary embodiment of a radio frequency switching circuit in which the switch branches are micro-electromechanical system (MEMS) switch devices.

[0029] Fig.11A 500×500μm for RF switch circuit 2 version of the floor plan of the integrated circuit die layout.

[0030] Fig. 11B 752×500μm for RF switch circuit 2 version of the floor plan of the integrated circuit die layout.

[0031] Fig. 11C It is 752×752μm for RF switch circuit 2 version of the floor plan of the integrated circuit die layout.

[0032] Fig.12 is a schematic diagram of another exemplary embodiment of a radio frequency circuit having a configuration that can be considered as a two-terminal switch die.

[0033] Fig.13 is an exemplary embodiment of a configuration of a radio frequency switch circuit having a configuration that can be considered as a four-terminal switch die.

[0034] Fig.14is an exemplary embodiment of a configuration of a radio frequency switch circuit having a configuration that can be considered as a three-terminal switch die.

[0035] Fig.15 is a schematic diagram of a single-pole double-throw (SPDT) switch die that integrates multiple switching circuits.

[0036] Fig.16 is a schematic diagram of an exemplary RF switch system including a patch phased array having a group including four antennas coupled via 4×SPDT switch dies.

[0037] Fig.17 is a schematic diagram of another exemplary RF switching system including a patch phased array having individual antennas coupled to a power amplifier via a SPDT switch die.

[0038] Fig.18 is a schematic diagram of another exemplary RF switch system illustrating the general reconfigurability of an RF system having multiple switches through a single control output according to the present disclosure. DETAILED DESCRIPTION

[0039] The embodiments set forth below represent the necessary information that enables those skilled in the art to practice the embodiments, and illustrate the best mode for practicing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize the application of these concepts not specifically proposed herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0040] It will be understood that although the terms first, second, etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0041] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, the element may be directly on or directly extending to the other element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly" to another element, there are no intervening elements. Similarly, it will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending to the other element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly on" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0042] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0043] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It will be further understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein clearly indicate the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or combinations thereof.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by a person of ordinary skill in the art to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meanings in the context of this specification and the related art, and should not be interpreted in an idealized or overly formal sense, unless clearly defined in this document. For example, in the present disclosure, digital signal decoding is defined as parsing digital signals into addresses and commands using digital processing through digital logic gates. Examples of digital signals requiring digital signal decoding are preambles, addresses, and commands delivered via a general purpose input / output (GPIO) bus.

[0045] Figure 1A is a schematic diagram of a prior art switch branch 10 including a resistor network. In particular, the prior art switch branch 10 is composed of stacked layers of field effect transistors M1 to MN coupled in series. The source-drain resistor network is composed of source-drain resistors RSD, each of which is coupled from the source to the drain across each of the field effect transistors M1 to MN. The gate resistor network is composed of gate resistors RG, which are coupled between the gates of adjacent field effect transistors of the field effect transistors M1 to MN. The body resistor network is composed of body resistors RB, which are coupled to the body terminals of the field effect transistors M1 to MN.

[0046] The gate terminal G1 is coupled to the gate resistor network through a common gate resistor RGC, and the body terminal B1 is coupled to the body resistor network through a common body resistor RBC, each of the gate terminal G1 and the body terminal B1 receives a bias voltage to control an on-state, the on-state is used to pass a radio frequency signal between the first port terminal P1 and the second port terminal P2; and an off-state, the off-state prevents the radio frequency signal from passing between the first port terminal P1 and the second port terminal P2. Table 1 below lists some typical bias values ​​(in volts) for the gate bias VG and the body bias VB applied to the gate terminal G1 and the body terminal B1, respectively. In the on-state, the source, drain and body bias are set to 0 volts, and the gate is biased to 2.5 volts. In the off-state, the source and drain are biased to 0 volts, but the body and gate are both set to -2.5 volts, such as strong off. The body is sometimes referred to as the "body".

[0047] Table 1

[0048]

[0049] Figure 1B1 is a schematic diagram of a simplified prior art switch branch 10, which is configured to switch a radio frequency signal between a first port terminal P1 and a second port terminal P2. The prior art switch branch 10 is composed of a stack of field effect transistors M1 to MN coupled in series in a drain-source relationship between the first port terminal P1 and the second port terminal P2, where N is a finite integer count. The prior art switch branch 10 has an on state, where the field effect transistors M1 to MN have a conducting channel that allows the radio frequency signal to pass between the first port terminal P1 and the second port terminal P2. Figure 1C As shown, a simplified prior art switch branch 10 has an on-state resistance R 接通 , which is a total resistance equal to the sum of the drain-source resistance of each of the field effect transistors M1 to MN in the on state. It should be understood that the on-state parasitic capacitance and the on-state parasitic inductance are associated with the prior art switch branch 10. However, the on-state parasitic capacitance and the on-state parasitic inductance are relatively small and are not present in the prior art switch branch 10. Figure 1C Shown in.

[0050] Figure 1D 1 is a simplified schematic diagram of the prior art switch branch 10, which shows the off-state capacitance C of the prior art switch branch 10 when the prior art switch branch 10 is in the off state. 关断 It will be appreciated that other off-state parasitic capacitances and off-state parasitic inductances are associated with the prior art switch branch 10. However, these other off-state parasitic capacitances and off-state parasitic inductances are relatively small and are not present in the prior art switch branch 10. Figure 1D In the off state, the channels of the field effect transistors M1 to MN are non-conductive and prevent the radio frequency signal from being transmitted between the first port terminal P1 and the second port terminal P2. However, when the switch branch 10 of the prior art is in the off state, each of the field effect transistors M1 to MN contributes to the off state capacitance C 关断 As the frequency of the RF signal applied to the prior art switch branch 10 increases to the millimeter wavelength frequency, the off-state capacitive reactance Z of the prior art switch branch 10 关断 =1 / (jωC 关断 ) is reduced to a certain value, wherein the first port terminal P1 is not effectively isolated from the second port terminal P2. Therefore, even when the prior art switch branch 10 is in the off state, the RF signal is undesirably transmitted between the first port terminal P1 and the second port terminal P2. The prior art attempts to solve this problem of lack of effective isolation of RF signals in the millimeter wavelength region are unsuccessful.

[0051] Figure 2A and Figure 2B Together with Figure 2CTogether they show the extent of the problem of the lack of effective isolation of the previously mentioned prior art switch branch 10 when the switching of RF signals is in the millimeter wavelength region. In particular, Figure 2A is the normalized on-state resistance R of the prior art switch branch 10 接通 Graph for millimeter wave frequencies. Figure 2B is the normalized off-state capacitance C of the switch branch 10 of the prior art 关断 Graph for millimeter wave frequencies. In this example, the prior art switch branch 10 was constructed using a 110 nm silicon-on-insulator fabrication process. Measured data for this 110 nm version of the prior art switch branch 10 produced an average on-state resistance R of 0.45 ohm-mm between 40 GHz and 50 GHz. 接通 and an average off-state capacitance C of 400 femtofarads (fF) / mm 关断 Therefore, for an insertion loss limit of 0.5 dB, the prior art switch branch 10 should have an on-state resistance R of no greater than 4.5 ohms. 接通 Therefore, the gate width of the switch branch 10 in the prior art should be (0.45ohm-mm) / (4.5ohm), that is, 0.1mm. Correspondingly, the off-state capacitor C 关断 It is (400fF / mm)·(0.1mm), which is 40fF. Figure 2C is a graph of the figure of merit (FOM) for the product of the on-state resistance and the off-state capacitance of the prior art switch branch 10 versus millimeter wave frequency. It should be understood that this example of the prior art switch branch 10 is applicable to a single stack switch branch. However, the measured data of the single stack switch branch can be scaled to apply to any finite number of stacked layers. For example, a four-stack switch branch with a 0.4mm device size will also result in an on-state resistance of 4.5Ω and an off-state capacitance of 40fF.

[0052] Figure 3A The on-state resistance R of the prior art switch branch 10 is represented as 4.5Ω between the first port terminal P1 and the second port terminal P2. 接通 A 50Ω source impedance ZS is coupled between a first port terminal P1 at a first node N1 and a ground terminal, and a 50Ω load impedance ZL is coupled between a second port terminal P2 at a second node N2 and a ground terminal. Figure 3B The off-state capacitance C of the prior art switch branch 10 is represented as 40 fF between the first port terminal P1 and the second port terminal P2. 关断A 50Ω source impedance ZS is coupled between the first port terminal P1 at the third node N3 and the ground terminal, and a 50Ω load impedance ZL is coupled between the second port terminal P2 at the fourth node N4 and the ground terminal. Figure 2A The analog circuit is used to determine the scattering parameters S21 and S11 associated with the first node N1 and the second node N2. Figure 2B The analog circuit is used to determine the scattering parameter S43 associated with the third node N3 and the fourth node N4.

[0053] Figure 3C is a graph of power gain shown as a dotted line, insertion loss shown as a dashed line, and isolation shown as a solid line, all based on Figure 3A The on-state simulation circuit and Figure 3B A simulation of the off-state analog circuit is plotted. At marker MK1 where the simulated frequency of the RF signal is 38.5 GHz, the isolation is unacceptable by 3 dB. The main reason for this low isolation value despite the narrow gate width of 0.1 mm is due to the off-state capacitance C of 40 fF at 38.5 GHz. 关断 There is a relatively very low capacitive reactance of -j103Ω. In addition, at a simulated frequency of 38.5GHz, the off-state / on-state impedance ratio is close to 17. For certain applications such as antenna tuning, an off-state / on-state impedance ratio of 17 is generally unrealistically low to meet fifth generation (5G) performance specifications. Therefore, there is a need for RF switching circuits with a practical off-state / on-state impedance ratio to meet the requirements of new wireless standards such as the 5G standard.

[0054] Figure 4 is a schematic diagram of one embodiment of a radio frequency switch circuit 12 that provides a high off-state / on-state impedance ratio for a switch branch 14 while maintaining maximum isolation from the switch branch 14 in the off-state and maintaining minimum insertion loss in the switch branch 14 in the on-state in accordance with the present disclosure. The switch branch 14 has a first branch terminal T1 coupled to a first port terminal P1 and a second branch terminal T2 coupled to a second port terminal P2. A transmitter 15 has a transmit terminal TX1 coupled to the first port terminal P1, wherein the transmitter 15 is configured to transmit a first radio frequency signal having a first frequency different from a second frequency. In at least some embodiments, the first frequency and the second frequency are within a frequency range extending from 26 GHz to 66 GHz.

[0055] Furthermore, in this exemplary embodiment, the switch branch 14 is still composed of stacked layers of field effect transistors M1 to MN coupled in series in a drain-source manner between the first branch terminal T1 and the second branch terminal T2, where N is a finite integer count. It should be understood that the switch branch 14 can be based on silicon-on-insulator technology and high electron mobility technology.

[0056] The switch branch 14 has both an on state and an off state to control the transfer of the radio frequency signal between the first port terminal P1 and the second port terminal P2 in response to the gate bias voltage VG applied to the gate terminal G1 and the body bias voltage VB applied to the body terminal B1. In this exemplary embodiment, each of the field effect transistors M1 to MN has a gate coupled to the gate terminal G1. In this exemplary embodiment, whenever the gate bias voltage is a positive voltage (e.g., +2.5V) applied to the gate terminal G1 and the body bias voltage VB is a zero voltage applied to the body terminal B1, the channels of the field effect transistors M1 to MN become conductive, thereby placing the switch branch 14 in the on state. When the gate bias voltage is a negative voltage (e.g., -2.5V) applied to the gate terminal G1 and the body bias voltage is a negative voltage (e.g., -2.5V) applied to the body terminal B1, the channels of the field effect transistors M1 to MN become non-conductive, thereby placing the switch branch 14 in the off state.

[0057] The RF switch circuit 12 also includes an isolation inductor 16, which is coupled between the first branch terminal T1 and the second branch terminal T2, so that the isolation inductor 16 is connected in parallel with the switch branch 14. The isolation inductor 16 has a given inductance, which provides resonance together with the total off-state capacitance of the switch branch 14 in the off state at a given frequency, and the given frequency is between the first frequency and the second frequency. The first port inductor 18 shown as coupled between the first port terminal P1 and the first branch terminal T1 represents the inductance associated with the first bonding element of the first port terminal P1 between the first port terminal P1 and the switch branch 14. The first bonding element is typically a bonding wire or a solder bump. The second port inductor 20 shown as coupled between the second port terminal P2 and the second branch terminal T2 represents the inductance associated with the second bonding element of the second port terminal P2 between the second port terminal P2 and the switch branch 14. Similar to the first bonding element, the second bonding element is typically a bonding wire or a solder bump.

[0058] Figure 5Ais a graph of the insertion loss of the RF switch circuit 12 with and without the isolation inductor 16. The insertion loss without the isolation inductor 16 is shown by the dashed line, and the insertion loss with the isolation inductor 16 coupled in parallel with the switch branch is shown by the solid line. It should be noted that no substantial increase in insertion loss occurs due to the addition of the isolation inductor. In particular, the insertion loss of the isolation inductor 16 and the switch branch 14 coupled in parallel between the first port terminal P1 and the second port terminal P2 does not exceed 5% of 0.5 dB.

[0059] Figure 5B 1 is a graph of the isolation provided by the isolation inductor 16 provided in parallel with the switch branch 14 and the isolation provided by the switch branch 14 alone. The isolation provided by the switch branch 14 alone in the absence of the isolation inductor 16 is shown as a dotted line, and the isolation provided by the isolation inductor 16 coupled in parallel with the switch branch 14 is shown as a solid line. The isolation between the first port terminal P1 and the second port terminal P2 provided by the switch branch 14 alone at a signal frequency of 27.5 GHz at the mark MK1 does not exceed 5 dB, and at the mark MK2, at a signal frequency of 40 GHz, the isolation is reduced to 2.5 dB. In most switch applications, such a low degree of isolation between the first port terminal P1 and the second port terminal P2 would be unacceptable. In contrast, when the switch branch 14 is in the off state, the isolation inductor 16 provides at least 10 dB of isolation between the first port terminal P1 and the second port terminal P2 in the frequency range between 27.5 GHz and 40 GHz over a signal bandwidth of 12 GHz. Furthermore, when the switch branch 14 is in the off state, the isolation inductor 16 provides at least 20 dB of isolation between the first port terminal P1 and the second port terminal P2 over a signal bandwidth of 4 GHz in a frequency range between 27.5 GHz and 40 GHz. It should also be noted that when the switch branch 14 is in the off state, the isolation inductor 16 provides at least 30 dB of isolation between the first port terminal P1 and the second port terminal P2 over a signal bandwidth of 1.5 GHz in a frequency range between 27.5 GHz and 40 GHz. In fact, for a signal frequency of 33.8 GHz, the isolation between the first port terminal P1 and the second port terminal P2 is as high as 50 dB.

[0060] Figure 5C yes Figure 4 The on-state impedance Z of the RF switch circuit 12 接通 Graph of the real and imaginary parts of . Figure 5D yes Figure 4 The off-state impedance Z of the RF switch circuit 12 关断 The real and imaginary parts of Figure 5C and Figure 5D As determined in the graph of FIG. 1 , the minimum off-state / on-state impedance ratio (|Zoff| / |Zon|) is 35, which exceeds by a factor of two the maximum off-state / on-state impedance ratio (|Zoff| / |Zon|) of 17 for the prior art switch branch 10 of FIG. 1 . In particular, for signal frequencies between 26 GHz and 40 GHz, the ratio of the off-state impedance between the first port terminal P1 and the second port terminal P2 to the on-state impedance between the first port terminal P1 and the second port terminal P2 is at least 35.

[0061] Figure 6 is a schematic diagram of another embodiment of the RF switch circuit 12, which includes a first series capacitor 22 and a second series capacitor 24 for resonating with the first port inductor 18 and the second port inductor 20. The first series capacitor 22 is coupled in series with the first port inductor 18 and the first branch terminal T1. The second series capacitor 24 is coupled in series with the second port inductor 20 and the second branch terminal T2. The first series capacitor 22 and the second series capacitor 24 are each simulated with a capacitance of 1.48 pF. Therefore, the on-state impedance Z 接通 The reactance part is Figure 7 The shown figure can be centered at zero. Figure 7 is the on-state impedance Z when the first series capacitor 22 and the second series capacitor 24 are added to the RF switch circuit 12 接通 The first series capacitor 22 and the second series capacitor 24 resonate with the first port inductor 18 and the second port inductor 20, respectively, to increase the off-state / on-state impedance ratio to more than Figure 4 In particular, for signal frequencies between 26 GHz and 40 GHz, the ratio of the off-state impedance between the first port terminal P1 and the second port terminal P2 to the on-state impedance between the first port terminal P1 and the second port terminal P2 is at least 45. Furthermore, in an exemplary embodiment, at a signal frequency of about 33.8 GHz, the off-state / on-state impedance ratio is about 46.

[0062] Figure 8 It is integrated in the integrated circuit die 26 Figure 63D block diagram of the RF switch circuit 12. In this exemplary embodiment, the isolation inductor 16 is shown as a single loop inductor made of metal traces, which can be in the third metal layer of the integrated circuit die 26. In this 3D block diagram, the first port inductor 18, the second port inductor 20, the first series capacitor 22 and the second series capacitor 24 are all symbolically shown in dashed lines. In this exemplary embodiment, the first port inductor 18 is a first solder bump 28 that couples the first branch terminal T1 to the first port terminal P1, and the second port inductor 20 is a second solder bump 30 that couples the second branch terminal T2 to the second port terminal P2.

[0063] The first series capacitor 22 and the second series capacitor 24 may present an electrostatic discharge (ESD) vulnerability that may cause irreparable damage to the RF switch circuit 12 during an ESD event. Fig. 9 As shown, another exemplary embodiment of the RF switch circuit 12 adds a first ESD shunt branch 32 and a second ESD shunt branch 34 configured to shunt ESD energy from the first series capacitor 22 and the second series capacitor 24. The first ESD shunt branch 32 is composed of a second stack of transistors Q1 to QN, where N is a finite integer count. The second ESD shunt branch 34 is composed of a third stack of transistors Q1' to QN'. In operation, the first stack of transistors Q1 to QN of the first ESD shunt branch 32 and the second stack of transistors Q1' to QN' of the second ESD shunt branch 34 are in their off state and do not burden the switch branch 14 because virtually all of the current of the radio frequency (RF) signal is passed by the first series capacitor 22 and the second series capacitor 24. However, during an ESD event, the first ESD shunt branch 32 and the second ESD shunt branch 34 provide sufficient leakage current paths for the ESD current to bypass the ESD-sensitive first series capacitor 22 and the second series capacitor 24.

[0064] Fig.10is a schematic diagram of an exemplary embodiment of an RF switch circuit 12, wherein the switch branch 14 is a micro-electromechanical system MEMS switch device 36 having a parasitic source-drain capacitance that resonates with the isolation inductor 16 when the MEMS switch device 36 is in the off state to improve isolation. The MEMS switch device 36 has an anchor point 38 having an attached cantilever 40. An actuator plate 42 positioned opposite the cantilever 40 is coupled to the gate control terminal GT1. During operation, an on-state control signal applied to the gate control terminal GT1 excites the actuator plate 42. In response to the actuator plate being excited, the cantilever 40 is electrostatically pulled toward the actuator plate 42, which causes the closure of the electrical contact 44. Once the electrical contact 44 is closed, an RF signal path between the first port terminal P1 and the second port terminal P2 is formed. In contrast, when the off-state control signal de-energizes the actuator plate 42, the cantilever 40 pops away from the actuator plate 42 and the electrical contact 44 opens. At a given frequency of the RF signal transmitted by the transmitter 15, the isolation inductor 16 resonates with the parasitic capacitance of the MEMS switch device 36 between the first branch terminal T1 and the second branch terminal T2 to improve the isolation between the first port terminal P1 and the second port terminal P2.

[0065] Fig.11A 500×500μm of RF switch circuit 12 2 version of the floor plan of the integrated circuit die layout. Fig. 11B RF switch circuit 12 is 752×500μm 2 version of the floor plan of the integrated circuit die layout. Fig. 11C It is 752×752μm of RF switch circuit 12 2 1 and 2. The plan view of the integrated circuit die layout of each version. Each version of the integrated circuit die layout includes an ESD diode and a low-pass filter for filtering the control signal. The ESD diode and the low-pass filter are coupled between the control voltage input terminal VCTRL and the ground voltage terminal VGND. The control voltage input terminal VCTRL receives a control signal, and the control signal causes the switch branch 14 to switch between the off state and the on state, and vice versa.

[0066] Fig.12is a schematic diagram of another exemplary embodiment of the RF switch circuit 12. This particular embodiment receives a control signal coupled to an RF signal that switches between a first port terminal P1 and a second port terminal P2 in response to the control signal. The RF front end 46 includes a switch controller 48 that outputs the control signal through a switch control terminal SWC1. The RF front end 46 also includes a positive voltage generator 50 and a negative voltage generator 52, both of which are in communication with the switch controller 48. The RF front end 46 is typically in communication with a baseband processor (not shown) that sends commands to the switch controller 48 to select the appropriate on state or off state for the switch branch 14.

[0067] exist Fig.12 In the exemplary embodiment of , the positive voltage generator 50 generates a positive voltage level that is selected by the switch controller 48 and provided through the switch control terminal SWC1 to switch the switch branch 14 to the on state. In contrast, the negative voltage generator 52 generates a negative voltage level that is selected by the switch controller 48 and provided through the switch control terminal SWC1 to switch the switch branch 14 to the off state. A biaser 54 coupled between the transmit terminal TX1 of the transmitter 15, the switch control terminal SWC1, and the first port terminal P1 combines the RF signal with the control signal. The biaser 54 couples the control signal with the RF signal to provide a composite signal to the first port terminal P1.

[0068] The control signal decoupling circuit 56 has a control signal input terminal CSI1 coupled to the first port terminal P1 to receive the composite signal; and a control signal output terminal CSO1, wherein the control signal decoupling circuit 56 is configured to decouple the control signal from the RF signal. In addition, a DC blocking capacitor CBLK1 is coupled between the control signal input terminal CSI1 and the first branch terminal T1 to prevent the control signal from entering the switch branch 14 through the first branch terminal T1.

[0069] In this particular embodiment, the control signal decoupling circuit 56 includes a control signal conditioning circuit 58, which is configured to filter the RF signal from the control signal. The control signal conditioning circuit 58 is coupled between the control voltage input terminal VCTRL and the ground voltage terminal VGND. In this exemplary embodiment, the first low-pass filter is composed of the following items: a first filter resistor RFIL1, which is coupled between the control voltage input terminal VCTRL and the control signal output terminal CSO1; and a first filter capacitor CF1, which is coupled between the control voltage input terminal VCTRL and the ground voltage terminal VGND. The second low-pass filter is composed of the following items: a second filter resistor RFIL2, which is coupled between the first filter resistor RFIL1 and the control signal output terminal CSO1; and a second filter capacitor CF2, which is coupled between the ground voltage terminal VGND and a node shared by the first filter resistor RFIL1 and the second filter resistor RFIL2.

[0070] The electrostatic discharge (ESD) shunt diode 60 coupled between the control voltage input terminal VCTRL and the ground voltage terminal VGND is configured to shunt the energy of an ESD event away from the switch branch 14. Fig.12 In the exemplary configuration of , the ESD shunt diodes 60 are arranged in two anti-parallel branches, each of which includes three of the ESD shunt diodes coupled in series.

[0071] Also included in the control signal decoupling circuit 56 is a first RF attenuation branch 62 coupled between the control voltage input terminal VCTRL and the control signal input terminal CSI1 to present an impedance to the RF signal within the first path including the control signal conditioning circuit 58. The first RF attenuation branch 62 may include a first attenuation resistor RA1 and / or a first attenuation inductor LA1 coupled between the control voltage input terminal VCTRL and the control signal input terminal CSI1. In addition, a first attenuation capacitor CA1 may be coupled in parallel with the first attenuation inductor LA1 to provide a notch filter to further attenuate the RF signal without significantly attenuating the control signal.

[0072] Also included in the control signal decoupling circuit 56 is a second RF attenuation branch 64 coupled between the ground voltage terminal VGND and the second branch terminal T2 to present an impedance to the RF signal within the second path including the control signal conditioning circuit 58. The second RF attenuation branch 64 may include a second attenuation resistor RA2 and / or a second attenuation inductor LA2 coupled between the ground voltage terminal VGND and the second branch terminal T2. In addition, a second attenuation capacitor CA2 may be coupled in parallel with the second attenuation inductor LA2 to provide a notch filter to further attenuate the RF signal so as to prevent the RF signal from being applied to the control signal output terminal CSO1. In an exemplary embodiment, the first attenuation inductor LA1 and the second attenuation inductor LA2 each have an inductance value of 2.84nH to provide an impedance of 500Ω to an RF signal having a frequency of 28GHz. In some embodiments, the first RF attenuation branch 62 and the second RF attenuation branch 64 each provide an impedance to the RF signal that is at least an order of magnitude higher than the impedance to the RF signal due to either the first port inductor 18 or the second port inductor 20 .

[0073] Bias circuit 66 is coupled between control signal output terminal CSO1 and gate terminal G1, and (in this exemplary embodiment) body terminal B1. In this particular embodiment, bias circuit 66 biases both the body and gate of the stacked layers of field effect transistors M1 to MN that make up switch branch 14. In response to a control signal provided by switch controller 48, gate bias voltage VG is applied to gate terminal G1, and body bias voltage VB is applied to body terminal B1.

[0074] Additionally, this embodiment may further include an isolation inductor 16 having a given inductance that provides resonance with the total off-state capacitance of the switch branch 14 at the center frequency of an RF signal within a frequency range extending from 26 GHz to 66 GHz.

[0075] Fig.12 An exemplary embodiment of the RF switch circuit 12 is integrated into a silicon-on-insulator (SOI) die. In this configuration, the RF switch circuit 12 can be considered a two-terminal switch die because, apart from a possible ground terminal, only the first port terminal P1 and the second port terminal P2 are external to the die.

[0076] Fig.13is an exemplary embodiment of a configuration of the RF switch circuit 12 having a configuration that can be considered as a four-terminal switch die. In this particular embodiment, the control voltage input terminal VCTRL is coupled to the switch control terminal SWC1, thereby eliminating the need for the first RF attenuation branch 62 and the second RF attenuation branch 64 of the control signal decoupling circuit 56. However, this reduction is relative to Fig.12 The exemplary embodiment of the present invention is provided at the expense of increased pin count. The control signal conditioning circuit 58 maintains filtering of the control signal to reduce possible RF noise that is inadvertently coupled to the control signal. In addition, the ESD shunt diode 60 coupled between the control voltage input terminal VCTRL and the ground voltage terminal VGND remains configured to shunt the energy of the ESD event away from the switch branch 14. Further, this embodiment may also include an isolation inductor 16 having a given inductance that provides resonance with the total off-state capacitance of the switch branch at the center frequency of the RF signal within a frequency range extending from 26 GHz to 66 GHz. Fig.13 An exemplary embodiment of the RF switch circuit 12 is also integrated into the SOI die. An advantage of any embodiment of the RF switch circuit 12 disclosed herein is that there is no need to integrate the digital signal decoding circuit into the die containing the RF switch circuit 12. Therefore, any die containing the RF switch circuit 12 is at least an order of magnitude smaller in area than a conventional RF switch circuit, which includes the digital signal decoding circuit required to parse the preamble, address, and command to operate the RF switch to switch between its open and closed states. It should also be noted that the switch controller 48 and the positive voltage generator 50 and the negative voltage generator 52 are not integrated with the RF switch circuit 12. Therefore, the switch controller 48 and the positive voltage generator 50 and the negative voltage generator 52 are outside the RF switch circuit 12 and do not occupy the substrate surface on the SOI die on which the RF switch circuit 12 is integrated.

[0077] Fig.14 is an exemplary embodiment of a configuration of the RF switch circuit 12 having a configuration that can be considered as a three-terminal switch die. In this exemplary embodiment, the second port terminal P2 and the ground voltage terminal VGND are coupled together to protect the control voltage input terminal VCTRL, the ground voltage terminal VGND, and the first port terminal P1 and the second port terminal P2. In this particular exemplary embodiment, the RF attenuation branch 64 is used to couple the second port terminal P2 with the ground voltage terminal VGND.

[0078] Fig.15is a schematic diagram of a single-pole double-throw (SPDT) switch die 68 integrating a plurality of RF switch circuits 12. The SPDT switch die 68 is shown as a transmit / receive (TX / RX) switch for a power amplifier PA1, an antenna ANT1, and a low noise amplifier LNA1 in a typical application. A first RF switch circuit 12-1 of the plurality of RF switch circuits 12 is in a first series branch, the first series branch being coupled between a power output terminal PO1 and a first node N1 where the antenna ANT1 is coupled. A second RF switch circuit 12-2 of the plurality of RF switch circuits 12 is in a first shunt branch, the first shunt branch being coupled between a second node N2 and a fixed voltage terminal such as a ground terminal GND. A third RF switch circuit 12-3 of the plurality of RF switch circuits 12 is in a second series branch, the second series branch being coupled between the first node N1 and an RX input terminal RIN1 of LNA1. The fourth RF switch circuit 12 - 4 of the plurality of RF switch circuits 12 is in a second shunt branch coupled between the third node N3 and a fixed voltage terminal such as a ground terminal GND.

[0079] In this exemplary embodiment, the control signal conditioning circuit 58 is common to each RF switch circuit 12-1 to 12-4 in the plurality of RF switch circuits 12. In this particular embodiment, the signal conditioning circuit is configured to receive the transmit control signal V provided by the switch controller 48. TX and receives a receiving control signal V provided by the switch controller RX . Emission control signal V TX and receives the control signal V RX The first voltage level and the second voltage level respectively place the switch branch 14 of each RF switch circuit 12-1 to 12-4 of the plurality of RF switch circuits 12 in an on state and an off state without transmitting the control signal V TX Or receive control signal V RX In this exemplary embodiment, the first voltage level is generated by the positive voltage generator 50, and the second voltage level is generated by the negative voltage generator 52. As in the previous embodiment, the control signal conditioning circuit 58 provides control signal filtering and ESD protection.

[0080] In operation, in a transmit mode for routing a transmit signal from power amplifier PA1 to antenna ANT1, switch controller 48 controls the transmit control signal V TX Outputs a positive voltage level and receives a control signal V RXOutputs a negative voltage level. Therefore, the switch branch 14 of the first RF switch circuit 12-1 and the switch branch 14 of the fourth RF switch circuit 12-4 are switched to their on states, while the switch branch 14 of the second RF switch circuit 12-2 and the switch branch 14 of the third RF switch circuit 12-3 are switched to their off states. In the reception mode of routing the received signal from the antenna ANT1 to the low noise amplifier LNA1, the switch controller 48 receives the control signal V RX Outputs a positive voltage level and transmits a control signal V TX Output negative voltage level. Therefore, the switch branch 14 of the first RF switch circuit 12-1 and the switch branch 14 of the fourth RF switch circuit 12-4 are switched to their off state, while the switch branch 14 of the second RF switch circuit 12-2 and the switch branch 14 of the third RF switch circuit 12-3 are switched to their on state. The typical positive voltage level of the on state is +2.5V, and the typical negative voltage level of the off state is -2.5V.

[0081] No need to control the transmission signal V TX and receives the control signal V RX Performing signal decoding provides the SPDT switch die 68 with the advantage of requiring at least an order of magnitude less real estate than a switch die of similar functionality that includes, for example, circuitry for GPIO decoding. Thus, the RF switch circuit 12 and switch dies such as the SPDT switch die formed from the RF switch circuit 12 become possible for use in RF switch systems where circuit real estate is critical.

[0082] In this regard, Fig.16 is a schematic diagram of an exemplary RF switch system 70, which includes a patch phased array 72 having groups of four antennas ANT1, ANT2, ANT3, and ANT4. Within each group, each of the antennas ANT1 to ANT4 is selectively coupled between a corresponding power amplifier PA1, PA2, PA3, and PA4 and a corresponding low noise amplifier LNA1, LNA2, LNA3, and LNA4 through a multi-way switch die 74. The multi-way switch die 74 integrates four SPDT switches, each of which has Fig.15 The switching topology of the SPDT switch die 68.

[0083] When the RF switch system 70 is in the transmit mode, the switch controller 48 controls the transmit control signal V TX Outputs the positive voltage level generated by the positive voltage generator 50, and receives the control signal V RXThe negative voltage level generated by the negative voltage generator 52 is output. Therefore, the multiplexer die 74 responds by coupling the outputs of the power amplifiers PA1-PA4 to the corresponding antennas in each group of antennas ANT1-ANT4, while decoupling the inputs of the low noise amplifiers LNA1-LNA4 from the corresponding antennas in each group of antennas ANT1-ANT4. In contrast, in the receive mode, the switch controller 48 responds to the transmit control signal V TX The negative voltage level generated by the negative voltage generator 52 is output, and the .... RX outputs the positive voltage level generated by the positive voltage generator 50. Therefore, the multiplexer die 74 responds by decoupling the outputs of the power amplifiers PA1-PA4 from the corresponding antennas in each group of antennas ANT1-ANT4 while coupling the inputs of the low noise amplifiers LNA1-LNA4 to the corresponding antennas in each group of antennas ANT1-ANT4.

[0084] The switch controller 48 is typically in communication with a baseband processor (not shown) that sends commands to the switch controller 48 to select a transmit mode or a receive mode for the RF switch system 70 depending on the desired operation under a given communication band and communication protocol. For example, the sequence of operations of the RF switch system 70 may depend on the generation of wireless technology, such as 2G, 3G, 4G, and 5G, and the specific operating bands, such as Ku and K bands.

[0085] It should also be understood that although the exemplary RF switch system 70 is shown as being configured for synchronous operation, wherein all antennas ANT1-ANT4 of each group are in a transmit mode or a receive mode, the RF switch system 70 may also be configured for asynchronous operation. For example, in asynchronous operation, a selected antenna of the antennas ANT1-ANT4 may be in a transmit mode in a first frequency band, while the other antennas of the antennas ANT1-ANT4 may be in a receive mode in a second frequency band at the same time. The first frequency band may be a high frequency band, and the second frequency band may be a low frequency band, or vice versa. In addition, with Fig.16 An advantage of the RF switch system 70 associated with the patch antenna example is that half-wavelength and quarter-wavelength spacing of the antennas ANT1-ANT4 can be achieved because there is no need to integrate signal decoding circuitry into the multi-way switch die 74. Furthermore, the switch controller 48, the positive voltage generator 50, and the negative voltage generator 52 are external to the patch phased array 72.

[0086] Fig.17is a schematic diagram of another exemplary RF switch system 76, which includes a patch phased array 78 having two groups of four antennas ANT1, ANT2, ANT3 and ANT4. In each group, each of the antennas ANT1 to ANT4 is selectively coupled between a corresponding power amplifier such as PA1 and a corresponding low noise amplifier such as LNA1 through a single switch die 80. The single switch die 80 integrates a SPDT switch having Fig.15 6. Switching topology of the SPDT switch die 68. In this particular exemplary RF switch system 76, one of the single-way switch dies 80 is dedicated to one of each grouped antenna ANT1 to ANT4.

[0087] When the RF switch system 76 is in the transmit mode, the switch controller 48 controls the transmit control signal V TX Outputs the positive voltage level generated by the positive voltage generator 50, and receives the control signal V RX The negative voltage level generated by the negative voltage generator 52 is output. Therefore, Fig.17 As shown at the beginning of FIG. 1 , the single-way switch die 80 responds by coupling the output of the corresponding power amplifier such as PA1 to the corresponding antenna such as ANT1 while decoupling the input of the low noise amplifier such as LNA1 from the corresponding antenna such as ANT1. In contrast, in the receive mode, the switch controller 48 responds to the transmit control signal V TX The negative voltage level generated by the negative voltage generator 52 is output, and the .... RX The positive voltage level generated by the positive voltage generator 50 is output. Therefore, the single switch die 80 responds by decoupling the output of the power amplifier such as PA1 from the corresponding one of the antennas such as ANT1 while coupling the input of the low noise amplifier such as LNA1 to the corresponding one of the antennas such as ANT1.

[0088] Fig.18 is a schematic diagram of another exemplary RF switch system 82, which illustrates the general reconfigurability of an RF system having multiple switches through a single control output. The exemplary RF switch system 82 includes a patch phased array 84 having sixteen antennas ANT1 to A16, each of which is selectively coupled to one of a plurality of load impedances 86 through one of a plurality of RF switch circuits 12. The load impedance 86 can be inductive, capacitive, resistive, and combinations thereof.

[0089] In operation, the positive voltage generator 50 and the negative voltage generator 52 generate the voltage levels required to switch each of the plurality of switch branches 14 between the off state and the on state, and vice versa. The switch controller 48 outputs the positive voltage level generated by the positive voltage generator 50 through the switch control terminal SWC1 to synchronously turn each of the plurality of switch branches 14 to the on state, which in turn couples each of the antennas ANT1 to ANT16 to a corresponding one of the plurality of load impedances 86. In order to decouple the corresponding one of the plurality of load impedances 86, the switch controller 48 outputs the negative voltage generated by the negative voltage generator 52 through the switch control terminal SWC1 to synchronously turn each of the plurality of switch branches 14 to the off state.

[0090] This particular example uses a single control signal output terminal CTRL to provide impedance tuning for the patch phased array 84 through the switch control output terminal SWC1 of the switch controller 48. However, it should be understood that the exemplary RF switch system 82 is only one example of using a single switch control output terminal to control multiple RF switch circuits 12 to achieve reconfigurability of the RF system. Fig.18 At least one advantage of the illustrated embodiment is that efficient use of real estate is achieved by employing only one of the switch controllers 48, one of the positive voltage generators 50, and one of the negative voltage generators 52 to control multiple RF switch circuits 12. At least one other advantage is that no signal decoding is required for the single control signal output terminal CTRL, which has the advantage of requiring at least an order of magnitude less real estate than a similarly functional RF switch circuit that includes, for example, circuitry for GPIO decoding. Such a huge savings in real estate allows for higher frequency patch phased arrays to be implemented by allowing the antennas of the patch phased array to be appropriately spaced apart from each other.

[0091] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A radio frequency switch system, comprising: a plurality of RF switch circuits, each of the plurality of RF switch circuits comprising a switch branch coupled between a first branch terminal and a second branch terminal, an isolation inductor coupled between the first branch terminal and the second branch terminal in parallel with the switch branch, wherein the isolation inductor has a given inductance that provides resonance with a total off-state capacitance of the switch branch at a center frequency of an RF signal in a frequency range extending from 26 GHz to 66 GHz to allow the RF signal to pass through the switch branch in an on-state and prevent the RF signal from passing through the switch branch in an off-state in response to a control signal applied to a branch control terminal of the switch branch; a switch controller configured to apply the control signal to the branch control terminal of the switch branch of each of the plurality of RF switch circuits, wherein the control signal has a first voltage level that places the switch branch in the on state; and a second voltage level, the second voltage level placing the switch branch in the off state without digital signal decoding of the control signal; as well as A plurality of patch antennas and a plurality of load impedances, wherein each of the plurality of RF switching circuits is coupled to a corresponding one of the plurality of patch antennas, so that when a switch branch of a corresponding one of the plurality of RF switching circuits is in the on state, a corresponding one of the plurality of load impedances selectively loads the corresponding one of the plurality of patch antennas. 2 . The RF switch system of claim 1 , wherein each of the plurality of RF switch circuits is integrated onto a separate die. 3 . The RF switch system of claim 1 , wherein the plurality of RF switch circuits are integrated onto a single die.

4. The RF switch system of claim 1 , wherein the switch controller has a single control signal output terminal, the single control signal output terminal is coupled to the branch control terminal of each of the plurality of RF switch circuits, the control signal is transmitted through the branch control terminal to switch the switch branch of each of the plurality of RF switch circuits between the on state and the off state.

5. The RF switch system according to claim 1, wherein the switch controller has a plurality of control signal output terminals, each of the plurality of control signal output terminals is coupled to a branch control terminal of a switch branch of a corresponding RF switch circuit in the plurality of RF switch circuits, wherein the switch controller is configured to transmit the control signal to the switch branch of the corresponding RF switch circuit in the plurality of RF switch circuits so that the switch branch of the corresponding RF switch circuit in the plurality of RF switch circuits switches between the on state and the off state.

6. The RF switching system of claim 1, wherein the switch branch of each of the plurality of RF switching circuits comprises a stacked layer of N transistors coupled in series between the first branch terminal and the second branch terminal, wherein N is a finite integer count. 7 . The RF switch system of claim 6 , further comprising a first resistor network configured to bias gates of the stacked layers of the N transistors.

8. The radio frequency switch system of claim 7, further comprising a second resistor network configured to bias a body of the stack of N transistors.

9. The RF switching system of claim 1, wherein the switch branch of each of the plurality of RF switching circuits comprises a micro-electromechanical system switch device.

10. The RF switch system of claim 1, wherein each of the plurality of RF switch circuits further comprises: a first port terminal and a second port terminal, wherein the switch branch is further configured to pass the RF signal between the first branch terminal and the second branch terminal in the on state, and prevent the RF signal from passing between the first branch terminal and the second branch terminal in the off state, in response to the control signal coupled to the RF signal and received at the first port terminal; as well as a control signal decoupling circuit having a control signal input terminal coupled to the first port terminal to receive the control signal coupled to the radio frequency signal; and a control signal output terminal coupled to the branch control terminal, wherein the control signal decoupling circuit is configured to decouple the control signal from the RF signal and provide the control signal to the branch control terminal.

11. The RF switch system as claimed in claim 10, further comprising a DC blocking capacitor, wherein the DC blocking capacitor is coupled between the control signal input terminal and the first branch terminal to prevent the control signal from entering the switch branch from the first branch terminal.

12. The RF switch system of claim 10, wherein the control signal decoupling circuit of each of the plurality of RF switch circuits comprises a control signal conditioning circuit configured to filter the RF signal from the control signal.

13. The RF switch system of claim 12, further comprising a first RF attenuation branch coupled between a control voltage input terminal and the control signal input terminal to present an impedance to the RF signal within a first path including the control signal conditioning circuit.

14. The RF switch system of claim 13, further comprising a ground voltage terminal and a second RF attenuation branch, wherein the second RF attenuation branch is coupled between the ground voltage terminal and the second port terminal to present an impedance to the RF signal within a second path including the control signal conditioning circuit.

15. The RF switch system of claim 14, wherein the first RF attenuation branch comprises a first resistor coupled between the control voltage input terminal and the first port terminal, and the second RF attenuation branch comprises a second resistor coupled between the ground voltage terminal and the second port terminal.

16. The RF switch system of claim 14, wherein the first RF attenuation branch comprises a first inductor coupled between the control voltage input terminal and the first port terminal, and the second RF attenuation branch comprises a second inductor coupled between the ground voltage terminal and the second port terminal. 17 . The radio frequency switch system of claim 16 , further comprising a first capacitor coupled in parallel with the first inductor and a second capacitor coupled in parallel with the second inductor. 18 . The RF switch system of claim 14 , wherein the control signal conditioning circuit comprises a low pass filter configured to filter out the RF signal from the control signal.

19. The RF switch system of claim 14, wherein the control signal conditioning circuit comprises an electrostatic discharge (ESD) shunt diode coupled between the control voltage input terminal and the ground voltage terminal, wherein the ESD shunt diode is configured to shunt energy of an ESD event away from the switch branch.

20. The RF switch system of claim 1, wherein the plurality of RF switch circuits are integrated into a single-pole double-throw switch die.

21. The RF switch system of claim 1, wherein the plurality of RF switch circuits are integrated onto a switch die comprising two series switch branches and two shunt switch branches.

22. The radio frequency switching system of claim 1, wherein the switch controller is configured to synchronously control switching of the plurality of radio frequency switching circuits by transmitting the control signal via a single output control terminal.

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