Method for manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a transistor having a source region and a drain region. The source / drain regions are formed with: a first via; a first metal layer extending along a first direction over the first via; a second via overlapping the first via on the first metal layer; and a second metal layer extending along a second direction different from the first direction over the second via; and the drain / source regions are formed with: a third via; a third metal layer located on the third via; a fourth via overlapping the third via on the third metal layer; and a controlled device at the same height level on the third metal layer as the second metal layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device. More specifically, embodiments of the present invention relate to a semiconductor device having a vertical wiring structure and a method for manufacturing the semiconductor device, wherein the semiconductor device is designed by a strategy provided by the vertical wiring structure of the device. Background Art

[0002] As the demand for high-density integrated circuits for miniaturized devices (e.g., portable devices) or for more powerful computing capabilities increases, high aspect ratio devices have been developed. Although the substrate surface area occupied by high aspect ratio devices is reduced compared to low aspect ratio thin film devices, the components of the control circuits of high aspect ratio devices are still dispersed over the surface of the substrate. For devices controlled by multiple control devices (e.g., controlling multiple voltage levels at the source of a transistor to achieve precise control of the drain of the device), the multiple control devices will occupy a large amount of surface area in the substrate. Therefore, there is a need for a multifunctional device that can effectively reduce the substrate surface area occupied by the device and the control devices that control the device while enhancing controllability. Summary of the invention

[0003] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, characterized in that the method includes: forming a transistor on a substrate, the transistor having a source region and a drain region; in the source region: forming a first through hole above the source region; forming a first metal layer on the first through hole, the first metal layer extending along a first direction; forming a second through hole above the first metal layer, the second through hole overlapping the first through hole; and forming a second metal layer on the second through hole, the second metal layer extending along a second direction different from the first direction, and in the drain region: forming a third through hole above the drain region, the third through hole being at the same height level as the first through hole; forming a third metal layer on the third through hole; forming a fourth through hole above the third metal layer, the fourth through hole overlapping the third through hole; and forming a controlled device on the fourth through hole, the controlled device being at the same height level as the second metal layer and controlled by the transistor.

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, characterized in that the method comprises: forming a transistor on a substrate, the transistor having a source region and a drain region; in the source region: forming a first through hole surrounded by a first protective layer in a first interlayer dielectric layer on the source region; forming a first metal layer on the first through hole, the first metal layer extending along a first direction; forming a second through hole surrounded by a second protective layer in a second interlayer dielectric layer on the first metal layer, the second through hole overlapping the first through hole; and forming a second metal layer on the second through hole, the second metal layer The metal layer extends along a second direction different from the first direction, and in the drain region: a third through hole surrounded by a third protective layer is formed in the first interlayer dielectric layer above the drain region, and the third through hole is at the same height level as the first through hole; a third metal layer is formed on the third through hole; a fourth through hole surrounded by a fourth protective layer is formed in the second interlayer dielectric layer above the third metal layer, and the fourth through hole overlaps with the third through hole; and a controlled device is formed on the fourth through hole, the controlled device is at the same height level as the second metal layer and is controlled by the transistor.

[0005] One embodiment of the present invention discloses a semiconductor device, characterized in that it includes: a transistor located on a substrate, the transistor having a source region and a drain region; a first through hole located above the source / drain region; a first metal layer located on the first through hole, the first metal layer extending along a first direction; a second through hole located on the first metal layer, the second through hole overlapping the first through hole; and a second metal layer located on the second through hole, the second metal layer extending along a second direction different from the first direction; a third through hole located above the drain / source region, the third through hole being at the same height level as the first through hole; a third metal layer located on the third through hole; a fourth through hole located on the third metal layer, the fourth through hole overlapping the third through hole; and a controlled device located on the fourth through hole, the device being at the same height level as the second metal layer and controlled by the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A cross-sectional view of a semiconductor device cut along the x-direction or the source-drain direction according to an embodiment of the present invention is shown.

[0008] Figure 2(a) shows Figure 1 2( a ) and 2( b ) are top plan views of a semiconductor device, and FIGS. 2( b ) and 2 ( c ) illustrate alternative embodiments of FIG. 2( a ).

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 8(a) or 8(b), FIG. 9(a) or 9(b), and FIG. 10(a) or 10(b) show a method of forming a substrate according to an embodiment of the present invention. Figure 1 Sequential manufacturing operations for a portion of a semiconductor device are shown.

[0010] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 ,and Fig.17 The method according to the embodiment of the present invention is shown Figure 1 The remaining sequential manufacturing operations of the semiconductor device are shown.

[0011] Fig.18 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0012] Fig.19 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0013] Fig. 20 The method according to the embodiment of the present invention is shown Figure 1 A method for a semiconductor device is shown.

[0014] Fig.21 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown.

[0015] Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 ,and Fig.29 The method according to the embodiment of the present invention is shown Fig.21 Sequential manufacturing operations for a portion of a semiconductor device are shown.

[0016] Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 ,and Fig.35 The method according to the embodiment of the present invention is shown Fig.21 The remaining sequential manufacturing operations of the semiconductor device are shown.

[0017] Fig.36 The method according to the embodiment of the present invention is shown Fig.21 A method for a semiconductor device is shown.

[0018] Description of Figure Numbers

[0019] 100: Semiconductor substrate / substrate

[0020] 110: Buffer layer

[0021] 120: First well layer / well layer

[0022] 130: Isolation insulation layer / shallow trench isolation layer

[0023] 140: Source region / source part / drain region / drain part / diffusion region / left diffusion region / right diffusion region

[0024] 140': Groove

[0025] 150: Second semiconductor layer

[0026] 160: Gate dielectric layer

[0027] 170: Gate electrode layer

[0028] 180: Sidewall spacer

[0029] 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k, 190l, 190m, 190n, 190o: through hole

[0030] 190a', 190b', 190c', 190d', 190e', 190f', 190g', 190h', 190i', 190j', 190k', 190l': protective layer

[0031] 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g, 210h: metal layer

[0032] 220: Controlled device

[0033] 300a, 300b, 300d, 300f, 300h, 300j, 300l: first interlayer dielectric layer / interlayer dielectric layer

[0034] 300c, 300e, 300g, 300i, 300k: Second interlayer dielectric layer / interlayer dielectric layer

[0035] 400a, 410a, 410e: Control device / device

[0036] 400b, 400c, 410b, 410c, 410d, 410f, 410g, 410h: Control device

[0037] C: Imaginary circle

[0038] S2001, S2002, S2003, S2004, S2005, S2006, S2007, S2008, S2009, S2010, S2011, S2012, S3601, S3602, S3603, S3604, S3605, S3606, S3607, S3608, S3609, S3610, S3611, S3612: Operation

[0039] x, y, z: direction DETAILED DESCRIPTION

[0040] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and structures are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the size of each element is not limited to the disclosed range or value, but may depend on the process conditions and / or required properties of the device. In addition, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For the sake of simplicity and clarity, various features can be arbitrarily drawn in different proportions.

[0041] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or feature shown in the figure and another element or features. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figure. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "being made of" may mean "including" or "consisting of". In the present invention, unless otherwise specified, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A and B and C), and does not mean one element from A, one element from B and one element from C.

[0042] Figure 1 A semiconductor device cut along the x-direction or the source-drain direction according to an embodiment of the present invention is shown. In some embodiments, the semiconductor device includes a transistor portion. In some embodiments, the transistor portion includes a planar transistor (field effect transistor (FET)). In some embodiments, the transistor portion includes a surrounding gate transistor or a fin field effect transistor (FinFET). In current technology nodes, fin field effect transistors with high-k dielectric and metal gate (HKMG) formed on a Si substrate are standard. The next generation of fin field effect transistors may be Ge field effect transistors, SiGe field effect transistors, and gate-all-around (GAA) field effect transistors. For demonstration purposes, in Figure 1 1 and 2. A planar transistor is shown in FIG. 1. The transistor is partially formed on a substrate 100. In some embodiments, the substrate 100 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 100 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 100 is made of crystalline silicon.

[0043] exist Figure 1 In the embodiment of the present invention, the semiconductor device includes a buffer layer 110. In some embodiments, the buffer layer 110 is a SiGe layer or an oxide layer, such as silicon oxide, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide, etc. In some embodiments, the buffer layer 110 has the function of adjusting the stress and strain of the layer formed thereon. In some embodiments, the buffer layer 110 prevents leakage current from being transmitted from the layer formed on the buffer layer 110 to other devices formed on the substrate 100. Typically, a SiGe buffer layer is used for a SiGe field effect transistor or a Ge field effect transistor. For a Si field effect transistor, a buffer layer is not used, and in some embodiments, the buffer layer 110 is removed from the Si field effect transistor.

[0044] exist Figure 1In the embodiment, the semiconductor device further comprises a first well layer 120, a portion of which is used as a charge carrier transport channel in the transistor portion. In some embodiments, the first well layer 120 is appropriately doped. The first well layer 120 comprises a diffusion region 140 as a source region / drain region (hereinafter, for demonstration purposes, the left diffusion region 140 is designated as the source region of the transistor portion, and the right diffusion region 140 is designated as the drain region of the transistor portion. A person of ordinary skill in the art should understand that, as another option, the left diffusion region 140 and the right diffusion region 140 may be the drain region and the source region of the transistor, respectively). The diffusion region 140 is formed by doping the first well layer 120 by an ion implantation method. The transistor portion further comprises an isolation insulating layer 130, which is also referred to as a shallow trench isolation (STI) layer. The isolation insulating layer 130 is made of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric (such as carbon-doped oxide), an ultra-low dielectric constant dielectric (such as porous carbon-doped silicon dioxide), a polymer (such as polyimide), and combinations thereof.

[0045] In some embodiments, the transistor portion further includes a second semiconductor layer 150 disposed on the source / drain region 140 , the second semiconductor layer 150 serving as a source / drain structure.

[0046] Between the source / drain regions 140, the transistor portion includes a gate stack formed by a gate dielectric layer 160 and a gate electrode layer 170, wherein the gate dielectric layer 160 is located on the channel region between the source / drain regions 140 of the first well layer 120. In some embodiments, the gate electrode layer 170 is a single-layer or multi-layer structure. In some embodiments, the gate electrode layer 170 is polysilicon. In addition, in some embodiments, the gate electrode layer 170 is doped polysilicon that is uniformly or non-uniformly doped. In some alternative embodiments, the gate electrode layer 170 includes a metal (e.g., Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi), other conductive materials having a work function compatible with the substrate material, or a combination thereof. In the present embodiment, the gate electrode layer 170 has a thickness in the range of about 20 nm to about 100 nm.

[0047] In some embodiments, the gate dielectric layer 160 comprises silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant dielectric. The high dielectric constant dielectric comprises a metal oxide. Examples of metal oxides used as high dielectric constant dielectrics include oxides of the following metals: Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In the present embodiment, the gate dielectric layer 160 is a high dielectric constant dielectric layer having a thickness in the range of about 1 nm to about 5 nm. In some embodiments, the gate dielectric layer 160 further comprises an interfacial layer (not shown) to reduce damage between the gate dielectric layer 160 and the channel of the first well layer 120. In some embodiments, the interfacial layer comprises chemically formed silicon oxide.

[0048] The gate stack is surrounded by sidewall spacers 180, which separate the gate stack from the source / drain regions 140. The sidewall spacers 180 include one or more of SiN, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material.

[0049] The transistor portion is covered by first interlayer dielectric (ILD) layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l, in each of which a through hole is formed and a through hole 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k, and 190l is formed by filling the through hole with a conductive material. In some embodiments, the first interlayer dielectric layers 300a and 300b are one layer instead of two layers. The two interlayer dielectric layers 300a and 300b facilitate the formation of devices on the interlayer dielectric layers (for example, a control device 400a is formed in the first interlayer dielectric layer 300a, and a through hole can be formed in the interlayer dielectric layer 300b at the same time). In some embodiments, the vias are formed of a conductive material including one or more of Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi2, Ni-Si, Co-Si, WN, TiAlN, TaCN, TaC, TaSiN, metal alloys (e.g., Ti-Al alloys, Al-Cu alloys), other suitable materials, and / or combinations thereof. In some embodiments, the conductive material is deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or physical vapor deposition (PVD) followed by an optional reflow process, or other suitable film formation processes.

[0050] Materials for the first interlayer dielectric layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l include inorganic compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC, or organic materials such as polymers.

[0051] The transistor portion is also covered by a second interlayer dielectric layer 300c, 300e, 300g, 300i and 300k, in which trenches are formed by patterning the second interlayer dielectric layers 300c, 300e, 300g, 300i and 300k, respectively, and metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g and 210h are formed by filling the trenches with a conductive material. In some embodiments, the metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h are formed of a conductive material including one or more of the following: Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi2, Ni-Si, Co-Si, WN, TiAlN, TaCN, TaC, TaSiN, a metal alloy (e.g., a Ti-Al alloy, an Al-Cu alloy), other suitable materials, and / or combinations thereof. In some embodiments, the conductive material is deposited using a process such as chemical vapor deposition, atomic layer deposition, electroplating, or physical vapor deposition followed by an optional reflow process, or other suitable film formation process. In some embodiments, metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g, 210h, 210i, 210j, 210k, and 210l are patterned in the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k before filling the through holes to form the through holes 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k, and 190l. 0d, 210e, 210f, 210g and 210h of the grooves so that the metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g and 210h and the through holes 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k and 190l are formed simultaneously.

[0052] In some embodiments, the material for the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k includes: an inorganic compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC; or an organic material, such as a polymer. In some embodiments, the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k are formed of the same material as the first interlayer dielectric layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l. In some embodiments, the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k are formed of a different material from the first interlayer dielectric layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l.

[0053] exist Figure 1 In the embodiment of the present invention, a controlled device 220 is formed at the same height level as the metal layer 210c. In some embodiments, the controlled device 220 is a semiconductor component, such as a light emitting diode, an organic light emitting diode, a memory, and a processor. In some embodiments, the controlled device 220 is a memory cell, such as a magnetic random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, and / or a resistance change random access memory (RRAM) cell.

[0054] exist Figure 1 In the embodiment, all through holes 190a, 190b, 190c, 190d, 190e and 190f on the source region 140 overlap and align with each other in the z direction, thereby forming a vertical wiring structure together with the pad structure formed by the metal layers 200a, 200b, 200c, 210a, 210b and 210c. In some embodiments, all through holes 190a, 190b, 190c, 190d, 190e and 190f on the source region 140 completely overlap with each other (i.e., the maximum in-plane areas of each through hole in the xy plane overlap with each other, and there is no non-overlapping portion in the in-plane area of ​​any of the through holes). In some embodiments, the geometric center of each through hole and each pad is located within an imaginary circle C (FIG. 2(a)) having a diameter of less than about 1.0 nm in the xy plane. In other embodiments, the diameter of circle C is less than about 0.5 nm. In some embodiments, the sizes or areas of the overlapping vias (eg, 190a and 190b) are not the same.

[0055] exist Figure 1In the embodiment, the number of through holes is six (6), but the number of through holes is not limited to 6. The number of through holes in the vertical wiring structure can be two, three, four or five, or more than six, and up to twenty.

[0056] exist Figure 1 In the embodiment, the controlled device 220 is formed at the same height level as the metal layer 210c. In some embodiments, the controlled device 220 operates by receiving different voltages applied by the drain region 140 of the transistor portion. The different voltages supplied from the drain region 140 are due to different voltages applied to the source region 140 by different control devices connected to the metal layers 200a, 200b, 200c, 210a, 210b and / or 210c.

[0057] Figure 2(a) shows Figure 1 2( a ) shows a top plan view of the semiconductor device. In some embodiments, the metal layer 200 c and the metal layer 210 c are formed to extend in different directions. That is, in the embodiment shown in FIG. 2( a ), the metal layer 200 c extends in the −x direction, and the metal layer 210 c extends in the −y direction.

[0058] In FIG. 2( a), one end portion of the metal layer 200c contacts a via 190f that overlaps with a source region 140 of a transistor portion. An opposite end portion of the metal layer 200c contacts a via 190n ( FIG. 2( a)) that is connected to another metal layer or electrically connected to a device 400a (e.g., a capacitor, a resistor, a transistor, a processor, a logic circuit, a driver circuit, and a combination thereof). In some embodiments, the device 400a includes a control device that controls a voltage applied to the source region 140, and in this way, the operation of the controlled device 220 can be controlled by the control device connected to the via 190n that contacts the metal layer 200c.

[0059] In FIG. 2( a), one end portion of the metal layer 210c contacts a through-hole 190f that overlaps with the source region 140 of the transistor portion. In some embodiments, the opposite end portion of the metal layer 210c contacts a through-hole 190m that is connected to another metal layer or electrically connected to a device 410a (e.g., a capacitor, a transistor, a processor, a logic circuit, a driver circuit, and a combination thereof). In some embodiments, the device 410a includes a control device that controls the voltage applied to the source region 140, and in this way, the operation of the controlled device 220 of the semiconductor device can be controlled by the control device connected to the through-hole 190m that contacts the metal layer 210c. Therefore, the controlled device 220 can be controlled by the control device connected to the through-hole 190n and / or 190m. In some embodiments, the control device contacts the metal layer (e.g., 200c and 210c) directly and not through any through-hole (not shown in FIG. 2( a)).

[0060] In some embodiments, the operation of the controlled device 220 depends on the combination of voltages (signals) applied by the control device (not shown in FIG. 2( a)) to the source region 140 of the transistor portion through the metal layers 200 c and 210 c. The higher the number of control devices, the higher the number of combinations of signals applied to the source region 140, the higher the number of possible ways in which the controlled device 220 can perform operations, and the more functions the controlled device 220 has.

[0061] FIG. 2( b) shows a top plan view of an alternative embodiment of FIG. 2( a). In FIG. 2( b), in some embodiments, metal layer 200 c and metal layer 210 c are formed to extend in different directions. That is, in the embodiment shown in FIG. 2( b), metal layer 200 c extends in the -x direction, and metal layer 210 c extends in the -y direction and then in the -x direction. That is, metal layer 210 c is a bent metal layer rather than a straight metal layer. Metal layer 210 c is formed to meet a specific circuit design of a semiconductor device (e.g., designed for a small control device connected to metal layer 200 c and / or 210 c).

[0062] In FIG. 2( b), one end portion of the metal layer 200c contacts a via 190f that overlaps with the source region 140 of the transistor portion. The opposite end portion of the metal layer 200c contacts a via 190n that is connected to another metal layer or electrically connected to a device 400a (e.g., a capacitor, a resistor, a transistor, a processor, a logic circuit, a driver circuit, and a combination thereof). In some embodiments, the device 400a includes a control device that controls the voltage applied to the source region 140, and in this way, the operation of the controlled device 220 can be controlled by the control device connected to the via 190n that contacts the metal layer 200c. In some embodiments, the control device 400a contacts the metal layer 200c directly rather than through any vias.

[0063] In FIG. 2( b ), one end portion of the metal layer 210 c contacts a via 190 f that overlaps with a source region 140 of a transistor portion. In some embodiments, an opposite end portion of the metal layer 210 c contacts a via 190 m that is connected to another metal layer or electrically connected to a device 410 a (e.g., a capacitor, a transistor, a processor, a logic circuit, a driver circuit, and combinations thereof). In some embodiments, the device 410 a includes a control device that controls a voltage applied to the source region 140, and in this way, the operation of the controlled device 220 can be controlled by the control device connected to the via 190 m that contacts the metal layer 210 c. In some embodiments, the control device 410 a contacts the metal layer 210 c directly, rather than through any vias.

[0064] In some embodiments, the operation of the controlled device 220 depends on the combination of voltages (signals) applied by the control devices (e.g., 400a and 410a) to the source region 140 of the transistor portion through the metal layers 200c and 210c, respectively. The higher the number of control devices, the higher the number of combinations of signals applied to the source region 140, the higher the number of possible ways in which the controlled device 220 can perform operations, and the more functions the controlled device 220 has.

[0065] FIG. 2( c ) shows a top plan view of an alternative embodiment of FIG. 2( a ). In FIG. 2( c ), metal layer 210 h extends in the same direction as metal layer 210 c. In some embodiments, metal layer 210 h extends in different directions (e.g., perpendicular directions, i.e., the x direction and the −y direction) from metal layer 210 c. Metal layer 210 h contacts through hole 190 o, and a control device (not shown in FIG. 2( c )) is connected to through hole 190 o at the drain side to control controlled device 220. That is, the voltage generated by the drain region is changed by the voltage applied by the control device through through hole 190 o and metal layer 210 h to achieve the desired performance of controlled device 220.

[0066] In FIG2(c), one end portion of the metal layer 200c contacts a via 190f that overlaps with the source region 140 of the transistor portion. The opposite end portion of the metal layer 200c contacts a via 190n (FIG2(c)) that is connected to another metal layer or electrically connected to a device 400a (e.g., a capacitor, a resistor, a transistor, a processor, a logic circuit, a driver circuit, and a combination thereof). In some embodiments, the device 400a includes a control device that controls the voltage applied to the source region 140, and in this way, the operation of the controlled device 220 can be controlled by the control device connected to the via 190n that contacts the metal layer 200c.

[0067] In FIG. 2( c ), one end portion of the metal layer 210 c contacts a via 190 f that overlaps with a source region 140 of a transistor portion. In some embodiments, an opposite end portion of the metal layer 210 c contacts a via 190 m that is connected to another metal layer or electrically connected to a device 410 a (e.g., a capacitor, a transistor, a processor, a logic circuit, a driver circuit, and combinations thereof). In some embodiments, the device 410 a includes a control device that controls a voltage applied to the source region 140, and in this way, the operation of the controlled device 220 can be controlled by the control device connected to the via 190 m that contacts the metal layer 210 c. In some embodiments, the control device 410 a contacts the metal layer 210 c directly, rather than through any vias.

[0068] The embodiment shown in FIG. 2( c ) further includes a metal layer 210 h. One end portion of the metal layer 210 h contacts a through hole 190 l overlapping the drain region 140 of the transistor portion. In some embodiments, the opposite end portion of the metal layer 210 h contacts a through hole 190 o connected to another metal layer or electrically connected to a device 410 e (e.g., a capacitor, a transistor, a processor, a logic circuit, a driver circuit, and a combination thereof). In some embodiments, the device 410 e includes a control device that controls the voltage applied to the drain region 140, and in this way, the operation of the controlled device 220 can be controlled by the control device connected to the through hole 190 o contacting the metal layer 210 h. In some embodiments, the control device 410 e contacts the metal layer 210 h directly rather than through any through hole.

[0069] In some embodiments, the operation of the controlled device 220 depends on the combination of voltages (signals) applied by the control devices (e.g., 400a, 410a, and 410e) to the source region 140 and the drain region 140 of the transistor portion through the metal layers 200c, 210c, and 210h, respectively. The higher the number of control devices, the higher the number of combinations of signals applied to the source region 140 and the drain region 140, the higher the number of possible ways in which the controlled device 220 can perform operations and the more functions the controlled device 220 has.

[0070] In some embodiments, the through holes 190f, 190m, 190n, 190l, and 190o have a rectangular in-plane cross-sectional shape. In some embodiments, the through holes 190f, 190m, 190n, 190l, and 190o have the following in-plane cross-sectional shapes: circular, elliptical, triangular, square, square with rounded corners, pentagonal, hexagonal, etc. In some embodiments, the overlapping through holes in the source region side, for example, have the same in-plane cross-sectional shape, while the overlapping through holes in the drain region side, for example, have the same in-plane cross-sectional shape. In some embodiments, the through hole in the source region side has a different in-plane cross-sectional shape from the through hole in the drain region side. In some embodiments, the through hole in the source region side has the same in-plane cross-sectional shape as the through hole in the drain region side.

[0071] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 8(a) or 8(b), FIG. 9(a) or 9(b), and FIG. 10(a) or 10(b) show a method of forming a substrate according to an embodiment of the present invention. Figure 1 1 and 2. The sequential manufacturing operations of a portion of the semiconductor device shown in FIG. 1 are shown in FIG. 1. It should be understood that in the sequential manufacturing process, Figure 3 to Figure 10(b)One or more additional operations are provided before, during, and after the stages shown, and some of the operations described below may be replaced or eliminated as additional embodiments of the method. The order of the operations / processes may be interchangeable. Figure 3 In the process, the buffer layer 110 is formed on the substrate 100 by a deposition method such as chemical vapor deposition, including low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD); atomic layer deposition; physical vapor deposition, such as pulsed laser deposition (PLD); sputtering; evaporation deposition; or other suitable processes, such as wet thermal oxidation. In some embodiments, the buffer layer 110 is a SiGe layer.

[0072] exist Figure 4 In the process, a first well layer 120 is formed on the substrate 100 by a deposition method such as chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; physical vapor deposition, such as pulsed laser deposition; sputtering; evaporation deposition; or other suitable processes. In some embodiments, the first well layer 120 is formed to reduce the thickness of stress / strain. In some embodiments, for example (but not limited to), the first well layer 120 is formed to have a thickness of about 2 nm to about 20 nm. In some embodiments, the first well layer 120 includes a germanium layer or a silicon layer. In addition, the first well layer 120 is doped with an n-type dopant to increase the charge carrier concentration, and in some embodiments, the n-type dopant includes phosphorus. The doping operation can be performed by in-situ doping during the deposition of the first well layer 120 and / or by ion implantation. In this way, the first well layer 120 can be a phosphorus-doped germanium layer or a phosphorus-doped silicon layer. In some embodiments, the buffer layer 110 is not formed, and the substrate 100 is locally doped with a suitable dopant to form the well layer 120.

[0073] exist Figure 5 In the process, a shallow trench isolation layer (also referred to as an isolation insulating layer 130) is formed by an etching process, a long film process (such as chemical vapor deposition, flowable chemical vapor deposition (FCVD)) or a spin-on-glass process, and a planarization process (such as chemical mechanical polishing), but any acceptable process may be used. In other embodiments, the shallow trench isolation layer 130 is formed before forming the well layer 120 and / or the buffer layer 110, and the well layer 120 and / or the buffer layer 110 are formed on the surface of the semiconductor substrate 100 where the shallow trench isolation layer is not formed.

[0074] exist Figure 6 and Figure 7 In the embodiment of the present invention, a gate stack is formed on the first well layer 120, and the gate stack includes a gate dielectric layer 160 and a gate electrode layer 170. The gate dielectric layer 160 is formed using a suitable process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, thermal oxidation, ultraviolet ozone oxidation, or a combination thereof. The gate electrode layer 170 can be formed by using chemical vapor deposition (including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition), physical vapor deposition, atomic layer deposition, or other suitable processes. The formed gate electrode layer 170 and gate dielectric layer 160 are patterned by photolithography and etching methods. In some embodiments, a gate replacement technique is used.

[0075] FIG8(b) shows an operation of forming a diffusion region at the source region 140 and the drain region 140 in the first well layer 120. The diffusion region is formed by performing ion implantation using the gate electrode layer 170 as a mask to dope the first well layer 120. In some embodiments, the dopant concentration is in the range of about 5×10 17 cm -3 About 5×10 18 cm -3 in the range of.

[0076] 9( b ) shows the operation of forming sidewall spacers 180 around the gate stack. The sidewall spacers 180 may be formed by atomic layer deposition or chemical vapor deposition or any other suitable method and anisotropic etching.

[0077] In FIG. 10( b), in some embodiments, a second semiconductor layer 150 is epitaxially grown on the source region 140 and the drain region 140 in the first well layer 120 by an epitaxial growth method including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes, such as vapor-phase epitaxy (VPE), chemical vapor deposition, molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE). The second semiconductor layer 150 is formed to a thickness that applies stress / strain in the structure. In some embodiments, for example (but not limited to), the second semiconductor layer 150 is formed to have a thickness of about 2 nm to about 20 nm. In some embodiments, the second semiconductor layer 150 includes a SiGe layer, a SiP layer, a SiC layer, and / or a SiCP layer. In addition, the second semiconductor layer 150 is doped with an n-type dopant to increase the charge carrier concentration, and in some embodiments, the n-type dopant includes phosphorus. The doping operation can be performed by in-situ deposition or ion implantation. In this way, the second semiconductor layer 150 can be a phosphorus-doped silicon layer. The phosphorus-doped Si layer can reduce, for example, the through hole 190a ( Figure 1 ) and the contact resistance at the interface between the second semiconductor layer 150.

[0078] In some embodiments, instead of forming the source region 140 and the drain region 140 by ion implantation (FIG. 8(b)) and forming the second semiconductor layer 150 on the source region 140 and the drain region 140 (FIG. 10(b)) as shown in FIG8(b), FIG9(b), and FIG10(b), in FIG9(a), the region to be the source region and the drain region in the first well layer 120 (FIG. 8(a)) is grooved by one or more photolithography and etching operations to form a recess 140', and in FIG10(a), the second semiconductor layer 150 is epitaxially formed in and on the recess 140'. In some embodiments, the recess 140' is formed after forming the sidewall spacer 180 (FIG. 9(a)). In one embodiment, the second semiconductor layer 150 is selectively formed in and on the recess 140'.

[0079] Fig.11The operation of forming a dielectric structure on the transistor portion and the substrate 100 is shown. The operation of forming the dielectric structure is performed by using a deposition technique such as a chemical vapor deposition technique or a physical vapor deposition technique. In some embodiments, the operation of forming the dielectric structure includes forming interlayer dielectric layers 300a and 300b stacked on top of each other. In some embodiments, the interlayer dielectric layers 300a and 300b are formed of silicon oxide, SiOC, SiON, and / or SiOCN. In some embodiments, the interlayer dielectric layers 300a and 300b are formed by the same material deposited continuously. In some embodiments, the interlayer dielectric layers 300a and 300b are formed of different materials. Depending on the material used to form the interlayer dielectric layers 300a and 300b, the etching rates of the interlayer dielectric layers 300a and 300b are the same for the interlayer dielectric layers 300a and 300b formed of the same material, and the etching rates of the interlayer dielectric layers 300a and 300b are different for the interlayer dielectric layers 300a and 300b formed of different materials. For different etching rates, the interlayer dielectric layer 300a can act as an etching stop layer when the interlayer dielectric layer 300b is etched to form a structure such as a through hole for a through hole on the interlayer dielectric layer 300a. In this case, the interlayer dielectric layer 300a completely covers the transistor portion (not shown in the figure).

[0080] Fig.12The operation of forming a through hole in the interlayer dielectric layer 300b is shown. In some embodiments, the operation of forming the through hole includes removing a portion of the interlayer dielectric layer 300b using an etching technique such as dry etching, photolithography and etching methods, directional etching methods, and cyclotron resonance plasma etching. The through holes 190a and 190g are formed by filling the through holes using methods such as: chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; non-conformal physical vapor deposition (non-conformal PVD), such as pulsed laser deposition; sputtering; evaporative deposition; cathode arc deposition; electron beam physical vapor deposition; or other suitable processes. In some embodiments, the through holes 190a and 190g are through holes that completely penetrate the interlayer dielectric layer 300b. In some embodiments, each of the vias 190a and 190g has a vertical portion that penetrates the interlayer dielectric layer 300b and another vertical portion that does not penetrate the interlayer dielectric layer 300b, and in this way, the via 190a or 190g partially penetrates the interlayer dielectric layer 300b. The via 190a or 190g of such a structure has the function of adjusting the resistance along the vertical axis of the via 190a or 190g to meet a specific device design, thereby enabling the device to implement specific functions for various purposes. In some embodiments, such a partially penetrating via structure has the function of balancing the resistance of the vias 190a and 190g to achieve the same resistance value of the device. In some embodiments, such a partially penetrating via structure has different resistances at the source portion 140 and the drain portion 140 to implement a specific transistor portion for a specific purpose.

[0081] Fig.13 The operation of forming an interlayer dielectric layer 300c and forming metal layers 200a and 210d in the interlayer dielectric layer 300c is shown. In some embodiments, the operation of forming the interlayer dielectric layer 300c is performed using a deposition technique such as a chemical vapor deposition technique or a physical vapor deposition technique. In some embodiments, the interlayer dielectric layer 300c is formed of silicon nitride, silicon carbide, or silicon oxide. In some embodiments, the interlayer dielectric layer 300c is formed of the same material as the interlayer dielectric layer 300b. In some embodiments, the interlayer dielectric layer 300c is formed of a material different from the interlayer dielectric layer 300b. Depending on the material used to form the interlayer dielectric layers 300c and 300b, the etching rates of the interlayer dielectric layers 300c and 300b are the same for the interlayer dielectric layers 300c and 300b formed of the same material, and the etching rates of the interlayer dielectric layers 300c and 300b are different for the interlayer dielectric layers 300c and 300b formed of different materials.

[0082] The formed interlayer dielectric layer 300c is patterned to form grooves to be filled with metal to form metal layers 200a and 210d. In some embodiments, the patterning technique is a lithography and etching method such as deep ultraviolet (DUV) lithography and plasma etching or cyclotron plasma etching method using a mask. The metal layers 200a and 210d are formed by filling the grooves using methods such as: chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; non-conformal physical vapor deposition, such as pulsed laser deposition; sputtering; evaporation deposition; cathode arc deposition; electron beam physical vapor deposition; or other suitable processes. In some embodiments, the metal layers 200a and 210d are formed of a material selected from the above-mentioned materials used to form the through holes 190a and 190g. In some embodiments, the metal layers 200a and 210d are formed of the same material as the through holes 190a and 190g. In some embodiments, the metal layers 200a and 210d are formed of a different material than the through holes 190a and 190g. In some embodiments, the metal layers 200a and 210d and the through holes 190a and 190g are formed in the same processing chamber by the same process. In some embodiments, the metal layers 200a and 210d and the through holes 190a and 190g are formed by different processes implemented in the same chamber or implemented in different chambers through a wafer translation mechanism. In some embodiments, a dual damascene method is applied.

[0083] exist Fig.14 , Fig.15 and Fig.16 In the above, the formation of interlayer dielectric layers 300d, 300e, 300f, 300g, 300h, 300i, 300j, 300k and 300l, the formation of through holes 190b, 190c, 190d, 190e, 190f, 190h, 190i, 190j, 190k, 190l, and the formation of metal layers 200b, 200c, 210a, 210b, 210c, 210e, 210f, 210g and 210h are all performed using the above method. Fig.11 , Fig.12 and Fig.13 In some embodiments, Fig.14 , Fig.15 and Fig.16 The operations in are performed with any combination of methods and materials, including the same method, different methods, using the same method for some layers and using different methods for some layers, the same materials, and different materials.

[0084] exist Fig.17In the embodiment of the present invention, a controlled device 220 is formed at the same height level as the metal layer 210c. In some embodiments, the controlled device 220 is a semiconductor component, such as a light emitting diode, an organic light emitting diode, a memory, and a processor. In some embodiments, the controlled device 220 operates by receiving different voltages applied by the drain region 140 of the transistor portion.

[0085] Fig.18 FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Fig.18 In the embodiment, control devices 400a, 400b, and 400c are formed and connected to metal layers 200a, 200b, and 200c, respectively, to apply different controls to the voltage applied to the source region. In some embodiments, each of the control devices 400a, 400b, and 400c applies the same voltage to the source region 140. In some embodiments, each of the control devices 400a, 400b, and 400c applies different or the same voltage to the source region. Fig.18 Hidden from view, control devices 410a, 410b and 410c (outlined by dashed lines) are connected to metal layers 210a, 210b and 210c, respectively, to apply different controls to the voltages applied to the source regions. The combined voltage formed by the applied voltages controls the source region 140 and the transistor portion. Fig.18 In the illustrated embodiment, the drain region 140 does not have any control device connected to the metal layers 210d, 210e, 210f, 210g, and 210h. In this way, the controllability of the controlled device 220 can be further enhanced while reducing the surface area of ​​the substrate 100 through the vertical structure.

[0086] Fig.19 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown. Fig.19 The semiconductor device shown is similar to Fig.18 The embodiment shown is different in that the end portions of the metal layers 210d, 210e, 210f, 210g and 210h opposite to the stacked through-holes are respectively connected to the control devices 410d, 410e, 410f, 410g and 410h to receive the same or different voltages from the control devices 410d, 410e, 410f, 410g and 410h. In this way, the controllability of the controlled device 220 can be further enhanced while reducing the surface area of ​​the substrate 100 through the vertical structure. The control device shown by the dotted line is located at the end portion of the metal layer away from the through-hole, and the dotted line is used to indicate the overlapping position of the control device along the y-axis.

[0087] Fig. 20 The method according to the embodiment of the present invention is shown Figure 1Flow chart of a method for forming a semiconductor device as shown. The method includes: operation S2001: providing a substrate; operation S2002: forming a thin film transistor having a source region and a drain region on the substrate. After operation S2002, two sets of operations S2003 to S2007 and S2008 to S2012 are performed on the source region and the drain region. The two sets of operations can be performed on the source region and the drain region at the same time or in the order of completing their corresponding sequences on the source region and then completing their corresponding sequences on the drain region. That is, the method includes performing the following operations at S2003 (i.e., on the source region): S2004: forming a first through hole on the source region; S2005: forming a first metal layer extending along a first direction on the first through hole; S2006: forming a second through hole on the first metal layer that completely overlaps the first through hole; and S2007: forming a second metal layer extending along a second direction different from the first direction on the second through hole. The method also includes performing the following operations at S2008 (i.e., on the drain region): S2009: forming a third through hole on the drain region at the same height level as the first through hole; S2010: forming a third metal layer on the third through hole; S2011: forming a fourth through hole on the third metal layer that completely overlaps the third through hole; and S2012: forming a controlled device on the fourth through hole, and the device is at the same height level as the second metal layer and is controlled by a thin film transistor.

[0088] Fig.21 A semiconductor device having a vertical wiring structure according to an embodiment of the present invention is shown. In some embodiments, the semiconductor device includes a transistor portion. In some embodiments, the transistor portion includes a planar transistor. In some embodiments, the transistor portion includes a gate-all-around transistor or a fin field effect transistor. For demonstration purposes, Fig.21 100 is a planar transistor (field effect transistor) as an example. The transistor is partially formed on a substrate 100. In some embodiments, the substrate 100 includes a single crystal semiconductor layer at least on a surface portion thereof. In some embodiments, the substrate 100 includes a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 100 is made of crystalline silicon.

[0089] exist Fig.21In the embodiment, the semiconductor device includes a buffer layer 110. In some embodiments, the buffer layer 110 is a SiGe layer or an oxide layer, such as silicon oxide, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide, etc. In some embodiments, the buffer layer 110 has a function of adjusting the stress and strain of the layer formed thereon. In some embodiments, the buffer layer 110 prevents leakage current from being transmitted from the layer formed on the buffer layer 110 to other devices formed on the substrate 100.

[0090] exist Fig.21 In the semiconductor device, the first well layer 120 is further provided, and a portion of the first well layer 120 is used as a charge carrier transport channel in the transistor portion. In some embodiments, the first well layer 120 is formed of a semiconductive material such as crystalline silicon and germanium. The first well layer 120 is disposed on a buffer layer 110 on a substrate 100. The first well layer 120 includes a diffusion region 140 as a source region and a drain region (hereinafter, for demonstration purposes, the left diffusion region 140 is designated as the source region of the transistor portion, and the right diffusion region 140 is designated as the drain region of the transistor portion; and a person skilled in the art should understand that the left diffusion region 140 and the right diffusion region 140 can be the drain region and the source region of the transistor, respectively). The diffusion region 140 is formed by doping the first well layer 120 using an ion implantation method. The transistor portion further includes an isolation insulating layer 130, which is also referred to as a shallow trench isolation layer. The isolation insulating layer 130 is made of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, low dielectric constant dielectrics (such as carbon-doped oxide), ultra-low dielectric constant dielectrics (such as porous carbon-doped silicon dioxide), polymers (such as polyimide), and combinations of these materials.

[0091] The transistor portion further includes a second semiconductor layer 150 disposed on the source region 140 and the drain region 140 .

[0092] Between the source region 140 and the drain region 140, the transistor portion includes a gate stack formed by a gate dielectric layer 160 and a gate electrode layer 170, wherein the gate dielectric layer 160 is located on the channel region between the source region 140 and the drain region 140 of the first well layer 120. In some embodiments, the gate electrode layer 170 is a single-layer or multi-layer structure. In some embodiments, the gate electrode layer 170 is polysilicon. In addition, in some embodiments, the gate electrode layer 170 is doped polysilicon that is uniformly or non-uniformly doped. In some alternative embodiments, the gate electrode layer 170 includes a metal (e.g., Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi), other conductive materials whose work function is compatible with the substrate material, or a combination of these materials. In the present embodiment, the gate electrode layer 170 has a thickness in the range of about 20 nm to about 100 nm.

[0093] In some embodiments, the gate dielectric layer 160 comprises silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant dielectric. The high dielectric constant dielectric comprises a metal oxide. Examples of metal oxides used as high dielectric constant dielectrics include the following oxides: Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In the present embodiment, the gate dielectric layer 160 is a high dielectric constant dielectric layer having a thickness in the range of about 1 nm to about 5 nm. In some embodiments, the gate dielectric layer 160 further comprises an interface layer (not shown) to reduce damage between the gate dielectric layer 160 and the channel of the first well layer 120. In some embodiments, the interface layer comprises chemically formed silicon oxide.

[0094] The gate stack is surrounded by sidewall spacers 180, which separate the gate stack from the source and drain regions 140. The sidewall spacers 180 include one or more of SiN, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material.

[0095] The transistor portion is covered by a first interlayer dielectric layer 300a, 300b, 300d, 300f, 300h, 300j and 300l, in each of which a through hole is formed, and through holes 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k and 190l are formed which are surrounded by protective layers 190a', 190b', 190c', 190d', 190e', 190f, 190g, 190h, 190i, 190j, 190k and 190l', and the through holes are formed by filling the through holes coated with the protective layer with a conductive material. In some embodiments, the protection layers 190a', 190b', 190c', 190d', 190e', 190f', 190g', 190h', 190i', 190j', 190k', and 190l' are formed of materials such as titanium nitride or tantalum nitride. The protection layers serve as barrier layers to prevent materials from diffusing into the vias surrounded by the protection layers to contaminate the vias and affect the pre-designed resistance of the vias, and to prevent conductive materials from diffusing into the interlayer dielectric layer to form a leakage current path. In some embodiments, the protective layers 190a', 190b', 190c', 190d', 190e', 190f', 190g', 190h', 190i', 190j', 190k', and 190l' are formed by electroplating methods such as chemical vapor deposition, metal organic chemical vapor deposition (MOCVD), and conformal physical vapor deposition methods. In some embodiments, the through holes are formed of a conductive material including one or more of the following: Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi2, Ni-Si, Co-Si, WN, TiAlN, TaCN, TaC, TaSiN, metal alloys (such as Ti-Al alloy, Al-Cu alloy), other suitable materials, and / or combinations thereof. In some embodiments, the conductive material is deposited using chemical vapor deposition, atomic layer deposition, electroplating, or physical vapor deposition followed by an optional reflow process, or other suitable film formation processes.

[0096] Materials for the first interlayer dielectric layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l include inorganic compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC, or organic materials such as polymers.

[0097] The transistor portion is also covered by second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k, and trenches are formed therein by patterning the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k, respectively. Metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h are formed by filling the trenches with a conductive material. In some embodiments, the metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h are formed of a conductive material including one or more of the following: Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi2, Ni-Si, Co-Si, WN, TiAlN, TaCN, TaC, TaSiN, a metal alloy (e.g., a Ti-Al alloy, an Al-Cu alloy), other suitable materials, and / or combinations thereof. In some embodiments, the conductive material is deposited using a process such as chemical vapor deposition, atomic layer deposition, electroplating, or physical vapor deposition followed by an optional reflow process, or other suitable film formation process. In some embodiments, metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g, 210h, 210i, 210j, 210k, and 210l are patterned in the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k before filling the through holes to form the through holes 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k, and 190l. 0d, 210e, 210f, 210g and 210h of the grooves so that the metal layers 200a, 200b, 200c, 210a, 210b, 210c, 210d, 210e, 210f, 210g and 210h and the through holes 190a, 190b, 190c, 190d, 190e, 190f, 190g, 190h, 190i, 190j, 190k and 190l are formed simultaneously.

[0098] In some embodiments, the material for the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k includes: an inorganic compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC; or an organic material, such as a polymer. In some embodiments, the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k are formed of the same material as the first interlayer dielectric layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l. In some embodiments, the second interlayer dielectric layers 300c, 300e, 300g, 300i, and 300k are formed of a different material from the first interlayer dielectric layers 300a, 300b, 300d, 300f, 300h, 300j, and 300l.

[0099] exist Fig.21 In the embodiment of the present invention, a controlled device 220 is formed at the same height level as the metal layer 210c. In some embodiments, the controlled device 220 is a semiconductor component, such as a light emitting diode, an organic light emitting diode, a memory, and a processor. In some embodiments, the controlled device 220 is a memory cell, such as a magnetic random access memory cell, a phase change random access memory cell, and / or a resistive random access memory cell.

[0100] exist Fig.21 In some embodiments, all through holes 190a, 190b, 190c, 190d, 190e, and 190f on the source region 140 overlap with each other, thereby forming a vertical wiring structure together with the trenches occupied by the metal layers 200a, 200b, 200c, 210a, 210b, and 210c. In some embodiments, all through holes 190a, 190b, 190c, 190d, 190e, and 190f on the source region 140 completely overlap with each other (i.e., the maximum in-plane areas of each through hole in the xy plane overlap with each other, and there is no non-overlapping portion in the in-plane area of ​​any of the through holes).

[0101] Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 ,and Fig.29 The method according to the embodiment of the present invention is shown Fig.21 The sequential manufacturing operations of a portion of the semiconductor device are shown. Fig. 22In the embodiment, the buffer layer 110 is formed on the substrate 100 by a deposition method such as chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; physical vapor deposition, such as pulsed laser deposition; sputtering; evaporation deposition; or other suitable processes, such as wet thermal oxidation. In some embodiments, the buffer layer 110 is a SiGe layer.

[0102] exist Fig.23 In the process, a first well layer 120 is formed on the substrate 100 by a deposition method such as chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; physical vapor deposition, such as pulsed laser deposition; sputtering; evaporation deposition; or other suitable processes. In some embodiments, the first well layer 120 is formed to a thickness that reduces stress / strain. In some embodiments, for example (but not limited to), the first well layer 120 is formed to have a thickness of about 2 nm to about 20 nm. In some embodiments, the first well layer 120 includes a germanium layer or a silicon layer. In addition, the first well layer 120 is doped with an n-type dopant to increase the charge carrier concentration, and in some embodiments, the n-type dopant includes phosphorus. The doping operation can be performed by in-situ doping during the deposition of the first well layer 120 and / or by ion implantation. In this way, the first well layer 120 can be a phosphorus-doped germanium layer or a phosphorus-doped silicon layer. In some embodiments, the buffer layer 110 is not formed, and the substrate 100 is locally doped with a suitable dopant to form the well layer 120.

[0103] exist Fig.24 In the process, a shallow trench isolation layer (which is also referred to as an isolation insulating layer 130) is formed by an etching process, a film formation process (such as chemical vapor deposition, reflowable chemical vapor deposition) or a spin-on-glass process, and a planarization process (such as chemical mechanical polishing), but any acceptable process may be used.

[0104] exist Fig.25 and Fig.26 In the embodiment of the present invention, a gate stack is formed on the first well layer 120, and the gate stack includes a gate dielectric layer 160 and a gate electrode layer 170. The gate dielectric layer 160 is formed using a suitable process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, thermal oxidation, ultraviolet ozone oxidation, or a combination thereof. The gate electrode layer 170 can be formed by using chemical vapor deposition (including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition), physical vapor deposition, atomic layer deposition, or other suitable processes. The formed gate electrode layer 170 and gate dielectric layer 160 are patterned by photolithography and etching methods. In some embodiments, a gate replacement technique is used.

[0105] Fig. 27The operation of forming a diffusion region at the source region 140 and the drain region 140 in the first well layer 120 is shown. The diffusion region is formed by performing ion implantation using the gate electrode layer 170 as a mask to dope the first well layer 120. In some embodiments, the dopant concentration is in the range of about 5×10 17 cm -3 About 5×10 18 cm -3 in the range of.

[0106] Fig.28 The operation of forming sidewall spacers 180 around the gate stack is shown. The sidewall spacers 180 may be formed by atomic layer deposition or chemical vapor deposition or any other suitable method and anisotropic etching.

[0107] exist Fig.29 In some embodiments, the second semiconductor layer 150 is formed on the source region 140 and the drain region 140 in the first well layer 120 by a deposition method such as chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; physical vapor deposition, such as pulsed laser deposition; sputtering; evaporative deposition; or other suitable processes. The second semiconductor layer 150 is formed to a thickness that applies stress / strain in the structure. In some embodiments, for example (but not limited to), the second semiconductor layer 150 is formed to have a thickness of about 2nm to about 20nm. In some embodiments, the second semiconductor layer 150 includes a SiGe layer, a SiP layer, a SiC layer, and / or a SiCP layer. In addition, the second semiconductor layer 150 is doped with an n-type dopant to increase the charge carrier concentration, and in some embodiments, the n-type dopant includes phosphorus. The doping operation can be performed by in-situ deposition or ion implantation. In this way, the second semiconductor layer 150 can be a phosphorus-doped silicon layer. The phosphorus-doped Si layer can reduce, for example, the through hole 190a ( Fig.21 ) and the contact resistance at the interface between the second semiconductor layer 150.

[0108] Fig.30The operation of forming a dielectric structure on the transistor portion and the substrate 100 is shown. The operation of forming the dielectric structure is performed using a deposition technique such as a chemical vapor deposition technique or a physical vapor deposition technique. In some examples, the operation of forming the dielectric structure includes forming interlayer dielectric layers 300a and 300b stacked on top of each other. In some embodiments, the interlayer dielectric layers 300a and 300b are formed of silicon nitride, silicon carbide, or silicon oxide. In some embodiments, the interlayer dielectric layers 300a and 300b are formed of the same material. In some embodiments, the interlayer dielectric layers 300a and 300b are formed of different materials. Depending on the material used to form the interlayer dielectric layers 300a and 300b, the etching rates of the interlayer dielectric layers 300a and 300b are the same for the interlayer dielectric layers 300a and 300b formed of the same material, and the etching rates of the interlayer dielectric layers 300a and 300b are different for the interlayer dielectric layers 300a and 300b formed of different materials.

[0109] Fig.31 , Fig.32 and Fig.33 The operation of forming a through hole, protective layers 190a' and 190g', and through holes 190a and 190g in the interlayer dielectric layer 300b is shown. Fig.31 In some embodiments, the operation of forming the through hole includes removing a portion of the interlayer dielectric layer 300b using an etching technique such as dry etching, photolithography and etching, directional etching, and cyclotron resonance plasma etching.

[0110] exist Fig.32 In the embodiment, protective layers 190a', 190b', 190c', 190d', 190e', 190f', 190g', 190h', 190i', 190j', 190k' and 190l' are formed on the inner surfaces of the through holes by an electroplating method such as chemical vapor deposition, metal organic chemical vapor deposition and conformal physical vapor deposition. The protective layers 190a', 190b', 190c', 190d', 190e', 190f', 190g', 190h', 190i', 190j', 190k' and 190l' are formed of a material such as titanium nitride or tantalum nitride.

[0111] exist Fig.33In the embodiment, the through holes 190a and 190g are formed by filling the through holes using methods such as: chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; non-conformal physical vapor deposition, such as pulsed laser deposition; sputtering; evaporative deposition; cathode arc deposition; electron beam physical vapor deposition; or other suitable processes. In some embodiments, the through holes 190a and 190g are through holes that completely penetrate the interlayer dielectric layer 300b. In some embodiments, each of the through holes 190a and 190g has a vertical portion that penetrates the interlayer dielectric layer 300b and another vertical portion that does not penetrate the interlayer dielectric layer 300b, and in this way, the through hole 190a or 190g partially penetrates the interlayer dielectric layer 300b. The through hole 190a or 190g of such a structure has the function of adjusting the resistance along the vertical axis of the through hole 190a or 190g to meet a specific device design, so that the device implements a specific function for various purposes. In some embodiments, such a partial through-type via structure has the function of balancing the resistance of vias 190a and 190g to achieve the same resistance value of the device. In some embodiments, such a partial through-type via structure has different resistances at source portion 140 and drain portion 140 to achieve a specific transistor portion for a specific purpose.

[0112] Fig.34 The operation of forming an interlayer dielectric layer 300c and forming metal layers 200a and 210d in the interlayer dielectric layer 300c is shown. The operation of forming the interlayer dielectric layer 300c is performed using a deposition technique such as a chemical vapor deposition technique or a physical vapor deposition technique. In some embodiments, the interlayer dielectric layer 300c is formed of silicon nitride, silicon carbide, or silicon oxide. In some embodiments, the interlayer dielectric layer 300c is formed of the same material as the interlayer dielectric layer 300b. In some embodiments, the interlayer dielectric layer 300c is formed of a material different from the interlayer dielectric layer 300b. Depending on the material used to form the interlayer dielectric layers 300c and 300b, the etching rates of the interlayer dielectric layers 300c and 300b are the same for the interlayer dielectric layers 300c and 300b formed of the same material, and the etching rates of the interlayer dielectric layers 300c and 300b are different for the interlayer dielectric layers 300c and 300b formed of different materials.

[0113] The formed interlayer dielectric layer 300c is patterned to form grooves to be filled with metal to form metal layers 200a and 210d. In some embodiments, the patterning technique is a lithography and etching method such as deep ultraviolet lithography and plasma etching or cyclotron plasma etching method using a mask. The operation of forming the groove includes removing a portion of the interlayer dielectric layer 300c using etching techniques such as dry etching techniques, lithography and etching methods, directional etching methods, and cyclotron resonance plasma etching. The metal layers 200a and 210d are formed by filling the grooves using methods such as: chemical vapor deposition, including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition; atomic layer deposition; non-conformal physical vapor deposition, such as pulsed laser deposition; sputtering; evaporation deposition; cathode arc deposition; electron beam physical vapor deposition; or other suitable processes. In some embodiments, the metal layers 200a and 210d are formed of a material selected from the above-mentioned materials used to form the through holes 190a and 190g. In some embodiments, the metal layers 200a and 210d are formed of the same material as the through holes 190a and 190g. In some embodiments, the metal layers 200a and 210d are formed of a different material than the through holes 190a and 190g. In some embodiments, the metal layers 200a and 210d and the through holes 190a and 190g are formed in the same processing chamber by the same process. In some embodiments, the metal layers 200a and 210d and the through holes 190a and 190g are formed by different processes implemented in the same chamber or implemented in different chambers through a wafer translation mechanism. In some embodiments, a dual damascene method is applied.

[0114] exist Fig.35 In the above, the formation of additional interlayer dielectric layers 300d, 300e, 300f, 300g, 300h, 300i, 300j, 300k and 300l, the formation of additional vias 190b, 190c, 190d, 190e, 190f, 190h, 190i, 190j, 190k, 190l, and the formation of additional metal layers 200b, 200c, 210a, 210b, 210c, 210e, 210f, 210g and 210h are all formed using the above method. Fig.30 , Fig.31 , Fig.32 , Fig.33 ,and Fig.34 In some embodiments, Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 ,and Fig.35The operations in are performed with any combination of methods and materials, including the same method, different methods, using the same method for some layers and using different methods for some layers, the same materials, and different materials.

[0115] exist Fig.35 In the embodiment of the present invention, a controlled device 220 is formed at the same height level as the metal layer 210c. In some embodiments, the controlled device 220 is a semiconductor component, such as a light emitting diode, an organic light emitting diode, a memory, and a processor. In some embodiments, the controlled device 220 operates by receiving different voltages applied by the drain region 140 of the transistor portion.

[0116] Fig.36 The method according to the embodiment of the present invention is shown Fig.21 Flow chart of a method for a semiconductor device shown in FIG. The method includes: operation S3601: providing a substrate; S3602: forming a thin film transistor having a source region and a drain region on the substrate. After operation S3602, two sets of operations S3603 to S3607 and S3608 to S3612 are performed on the source region and the drain region. The two sets of operations may be performed on the source region and the drain region at the same time or the two sets of operations may be performed on the source region and the drain region in the order of completing the corresponding sequence on the source region and then completing the corresponding sequence on the drain region. That is, the method includes performing the following operations on the source region (S3603): S3604: forming a first protective coating and a first through hole on the source region; S3605: forming a first metal layer extending along a first direction on the first through hole; S3606: forming a second protective coating and a second through hole completely overlapping the first through hole on the first metal layer; and S3607: forming a second metal layer extending along a second direction different from the first direction on the second through hole. The method also includes performing the following operations on the drain region (S3608): S3609: forming a third protective coating and a third through hole at the same height level as the first through hole on the drain region; S3610: forming a third metal layer on the third through hole; S3611: forming a fourth protective coating and a fourth through hole completely overlapping the third through hole on the third metal layer; and S3612: forming a controlled device on the fourth through hole, and the device is at the same height level as the second metal layer and is controlled by a thin film transistor.

[0117] As semiconductor integrated circuit technology evolves, the rapid growth of the market and the increase in functional density have pushed integrated circuit technology from two-dimensional (2D) thin film technology to three-dimensional (3D) device structures. While more and more functional components are packaged to perform highly complex control of device components within the integrated circuit, the two-dimensional aspect of the three-dimensional device structure still causes the problem of substrate area being occupied. For example, when multiple voltage levels of the source of a transistor are controlled to achieve precise control of the drain of the device, multiple control devices will occupy a large surface area in the substrate. An embodiment of the present invention provides a device structure that solves the above-mentioned problems of the three-dimensional device structure and pushes integrated circuit technology to a new level. Specifically, an embodiment of the present invention provides a semiconductor device with a vertical wiring structure and a method for making the device. The semiconductor device enhances controllability while effectively reducing the substrate surface area occupied by the device and the control device that controls the device. In addition, the device enhances the control complexity of the device, thereby pushing integrated circuit technology and functions to a new high-density level and high-multifunctionality level.

[0118] The present application discloses an exemplary method for manufacturing a semiconductor device. The method includes forming a transistor having a source region and a drain region on a substrate. On the source region, a first through hole is formed above the source region. A first metal layer extending along a first direction is formed on the first through hole. A second through hole overlapping the first through hole is formed on the first metal layer. A second metal layer extending along a second direction different from the first direction is formed on the second through hole. On the drain region, a third through hole is formed at the same height level as the first through hole and above the drain region. A third metal layer is formed on the third through hole. A fourth through hole is formed on the third metal layer. The fourth through hole overlaps the third through hole. A controlled device is formed on the fourth through hole, and the controlled device is at the same height level as the second metal layer and is controlled by the transistor. In one or more of the above or following embodiments, in a plan view, the first through hole and the second through hole have the same area. In one or more of the above or following embodiments, the first metal layer is connected to a control device that controls a voltage applied to the first metal layer. In one or more of the above or following embodiments, the second metal layer is connected to a control device that controls a voltage applied to the second metal layer. In one or more of the above or following embodiments, the controlled device includes one of an organic light emitting diode device, a memory, and a transistor. In one or more of the above or following embodiments, between the first metal layer and the second through hole, the method includes alternately forming a plurality of through holes and a plurality of metal layers, and in a plan view, all of the plurality of through holes have the same shape (or area), and all of the plurality of metal layers have the same shape (or area).

[0119] The present application also discloses an exemplary method for manufacturing a semiconductor device. The method includes forming a transistor having a source region and a drain region on a substrate. A first through hole surrounded by a first protective layer is formed in a first interlayer dielectric layer on the source region. A first metal layer extending along a first direction is formed on the first through hole. A second through hole overlapping with the first through hole and surrounded by a second protective layer is formed in a second interlayer dielectric layer above the first metal layer. A second metal layer extending along a second direction different from the first direction is formed on the second through hole. On the drain region, a third through hole at the same height level as the first through hole and surrounded by a third protective layer is formed in the first interlayer dielectric layer above the drain region. A third metal layer is formed on the third through hole. A fourth through hole overlapping with the third through hole and surrounded by a fourth protective layer is formed in the second interlayer dielectric layer above the third metal layer. A controlled device is formed on the fourth through hole, the controlled device being at the same height level as the second metal layer and being controlled by the transistor. In one or more of the above or following embodiments, in a plan view, the first through hole and the second through hole have the same area. In one or more of the above or following embodiments, the first protective layer and the second protective layer are formed of titanium nitride or tantalum nitride. In one or more of the above or following embodiments, the first metal layer is connected to a control device applied to control the voltage of the first metal layer. In one or more of the above or following embodiments, the second metal layer is connected to a control device that controls the voltage applied to the second metal layer. In one or more of the above or following embodiments, the controlled device includes one of an organic light emitting diode device, a memory, and a transistor. In one or more of the above or following embodiments, the method further includes: between the first metal layer and the second through hole, a plurality of through holes and a plurality of metal layers are alternately formed, and in a plan view, all of the plurality of through holes have the same shape (or area), and all of the plurality of metal layers have the same shape (or area).

[0120] The present application discloses an embodiment of a semiconductor device. The semiconductor device includes a transistor having a source region and a drain region. The transistor is formed on the substrate. A first through hole is arranged above the source region, and a first metal layer extends along a first direction on the first through hole. A second through hole overlaps with the first through hole on the first metal layer, and the second metal layer extends along a second direction different from the first direction on the second through hole. A third through hole is at the same height level as the first through hole above the drain region. A third metal layer is arranged on the third through hole. A fourth through hole overlaps with the third through hole and is located on the third metal layer, and a controlled device is arranged on the fourth through hole. The device is at the same height level as the second metal layer and is controlled by the transistor. In one or more of the above or following embodiments, in a plan view, the first through hole and the second through hole have the same area. In one or more of the above or following embodiments, the first metal layer is connected to a control device that controls a voltage applied to the first metal layer. In one or more of the above or following embodiments, the second metal layer is connected to a control device that controls a voltage applied to the second metal layer. In one or more of the above or following embodiments, the controlled device includes one of an organic light emitting diode device, a memory, and a transistor.

[0121] The above content summarizes the features of several embodiments or examples so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications to this article without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a transistor on a substrate, the transistor having a source region and a drain region; In the source region: forming a first through hole on the source region; forming a first metal layer on the first through hole, wherein the first metal layer extends along a first direction; forming a second through hole on the first metal layer, the second through hole overlapping the first through hole; and forming a second metal layer on the second through hole, the second metal layer extending along a second direction different from the first direction, and In the drain region: forming a third through hole on the drain region, wherein the third through hole is at the same height level as the first through hole; forming a third metal layer on the third through hole; forming a fourth through hole on the third metal layer, the fourth through hole overlapping the third through hole; and A controlled device is formed on the fourth through hole, the controlled device being at the same height level as the second metal layer and being controlled by the transistor.

2. The method according to claim 1, characterized in that In a plan view, the first through hole and the second through hole have the same area.

3. The method according to claim 1, characterized in that The first metal layer is connected to a control device that controls a voltage applied to the first metal layer.

4. The method according to claim 1, characterized in that The second metal layer is connected to a control device that controls a voltage applied to the second metal layer.

5. The method according to claim 1, characterized in that The controlled device includes one of an organic light emitting diode device, a memory, and a transistor.

6. The method according to claim 1, characterized in that Further including: A plurality of through holes and a plurality of metal layers are alternately formed between the first metal layer and the second through hole.

7. The method according to claim 6, characterized in that In a plan view, all of the plurality of through holes have the same shape (or area), and all of the plurality of metal layers have the same shape (or area).

8. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a transistor on the substrate, the transistor having a source region and a drain region; On the source region: forming a first through hole surrounded by a first protection layer in a first interlayer dielectric (ILD) layer on the source region; forming a first metal layer on the first through hole, wherein the first metal layer extends along a first direction; forming a second through hole surrounded by a second protection layer in a second interlayer dielectric layer over the first metal layer, the second through hole overlapping the first through hole; and forming a second metal layer on the second through hole, the second metal layer extending along a second direction different from the first direction, and On the drain region: forming a third through hole surrounded by a third protection layer in the first interlayer dielectric layer above the drain region, the third through hole being at the same height level as the first through hole; forming a third metal layer on the third through hole; forming a fourth through hole surrounded by a fourth protection layer in the second interlayer dielectric layer over the third metal layer, the fourth through hole overlapping the third through hole; and A controlled device is formed on the fourth through hole, the controlled device being at the same height level as the second metal layer and being controlled by the transistor.

9. The method according to claim 8, characterized in that In a plan view, the first through hole and the second through hole have the same area.

10. The method according to claim 8, characterized in that The first protection layer and the second protection layer are formed of titanium nitride or tantalum nitride.

11. The method according to claim 8, characterized in that The first metal layer is connected to a control device that controls a voltage applied to the first metal layer.

12. The method according to claim 8, characterized in that The second metal layer is connected to a control device that controls a voltage applied to the second metal layer.

13. The method according to claim 8, characterized in that The controlled device includes one of an organic light emitting diode device, a memory, and a transistor.

14. The method according to claim 8, characterized in that Further including: A plurality of through holes and a plurality of metal layers are alternately formed between the first metal layer and the second through hole.

15. The method according to claim 14, characterized in that In a plan view, all of the plurality of through holes have the same shape, and all of the plurality of metal layers have the same shape.

16. A semiconductor device, characterized in that: include: A transistor, located on the substrate, wherein the transistor has a source region and a drain region; A first through hole, located on the source region / drain region; A first metal layer, located on the first through hole, and the first metal layer extends along a first direction; a second through hole, located on the first metal layer, the second through hole overlapping the first through hole; as well as A second metal layer, located on the second through hole, the second metal layer extending along a second direction different from the first direction; A third through hole, located above the drain region / source region, the third through hole being at the same height level as the first through hole; A third metal layer, located on the third through hole; a fourth through hole, located on the third metal layer, the fourth through hole overlapping the third through hole; and A controlled device is located on the fourth through hole, wherein the controlled device is at the same height level as the second metal layer and is controlled by the transistor.

17. The semiconductor device according to claim 16, wherein: In a plan view, the first through hole and the second through hole have the same area.

18. The semiconductor device according to claim 16, wherein: The first metal layer is connected to a control device that controls a voltage applied to the first metal layer.

19. The semiconductor device according to claim 16, wherein: The second metal layer is connected to a control device that controls a voltage applied to the second metal layer.

20. The semiconductor device according to claim 16, wherein: The controlled device includes one of an organic light emitting diode device, a memory, and a transistor.

21. A method for manufacturing a semiconductor device, characterized in that: The method comprises: (i) forming a transistor on a substrate, wherein the transistor has a gate electrode, a source region, and a drain region; (ii) forming an interlayer dielectric layer; (iii) forming a source-side via hole in the interlayer dielectric layer and above the source region, and forming a drain-side via hole in the interlayer dielectric layer and above the drain region; (iv) forming a source-side metal layer in contact with the source-side through hole and a drain-side metal layer in contact with the drain-side through hole; (v) repeating steps (ii) to (iv) at least four times; and (vi) forming a controlled device on one of the topmost source-side through hole and the topmost drain-side through hole formed through step (v), Wherein, between step (i) and step (ii), the method further comprises: A semiconductor layer is formed, the semiconductor layer being in contact with the sidewall spacer formed on the side of the gate electrode, the source region, and the drain region, wherein a second semiconductor material of the semiconductor layer is different from the first semiconductor material of the substrate.

22. The method according to claim 21, characterized in that: The controlled device is formed on the drain-side through hole of the topmost layer, and At least one of the source-side metal layers is coupled to a logic device.

23. The method according to claim 22, characterized in that The drain side metal layer is not coupled to a logic device.

24. The method according to claim 21, characterized in that The controlled device is a memory unit.

25. The method according to claim 24, characterized in that The memory cell is one of a phase change memory cell and a resistive change memory cell.

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