Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device, comprising: forming a fin-type pattern protruding from a substrate and extending in a first direction; forming a field insulating layer on the substrate to cover a limited portion of the fin-type pattern such that the field insulating layer exposes another limited portion of the fin-type pattern; forming a gate structure on the field insulating layer and the fin-type pattern, the gate structure extending in a second direction different from the first direction; forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, the first region is adjacent to the gate structure and extends in the second direction; forming gate spacers on the first barrier layer and on sidewalls of the gate structure.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2017 - 0152979, filed on November 16, 2017, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the same. Background art

[0004] Recently, semiconductor devices have become smaller and have higher performance. Therefore, even small structural differences in transistors included in a semiconductor device can cause a significant impact on the performance of the semiconductor device. Previously, transistors included polysilicon gate electrodes. To meet performance requirements, such polysilicon gate electrodes can be replaced with metal gate electrodes. To fabricate a metal gate, a “post - gate process” or an “alternate - gate process” can be used. Summary of the invention

[0005] Aspects of the present disclosure provide a semiconductor device having improved performance and yield and a method of manufacturing such a semiconductor device by forming a barrier layer.

[0006] This aspect and other aspects, embodiments, and advantages of the present disclosure will become apparent to those of ordinary skill in the art upon review of the following detailed description and claims.

[0007] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: forming a fin - type pattern protruding from a substrate and extending in a first direction; forming a field insulating layer on the substrate to cover a limited portion of the fin - type pattern such that the field insulating layer exposes another limited portion of the fin - type pattern; forming a gate structure on the field insulating layer and the fin - type pattern, the gate structure extending in a second direction different from the first direction; forming a first barrier layer in a first region of the field insulating layer, the first region being exposed by the gate structure, the first region being adjacent to the gate structure and extending in the second direction, the first barrier layer including nitrogen; and forming a gate spacer on the first barrier layer and on sidewalls of the gate structure.

[0008] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: forming a fin-type pattern protruding from a substrate and extending in a first direction; forming a field insulating layer on the substrate to cover a limited portion of the fin-type pattern such that the field insulating layer exposes another limited portion of the fin-type pattern; forming a gate structure on the field insulating layer and the fin-type pattern, the gate structure extending in a second direction different from the first direction; and forming gate spacers on sidewalls of the field insulating layer and the gate structure. The field insulating layer may include a first region overlapping with the gate spacers, and the first region of the field insulating layer may include a nitrogen element.

[0009] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: forming a fin-type pattern protruding from a substrate and extending in a first direction; forming a field insulating layer on the substrate to cover a limited portion of the fin-type pattern such that the field insulating layer exposes another limited portion of the fin-type pattern; forming a dummy gate structure on the field insulating layer and the fin-type pattern, the dummy gate structure extending in a second direction different from the first direction; performing a nitridation process on an upper surface of the field insulating layer, an upper surface of the fin-type pattern, sidewalls of the fin-type pattern, an upper surface of the dummy gate structure, and sidewalls of the dummy gate structure to form a blocking layer including a nitrogen element; forming gate spacers on sidewalls of the blocking layer and the dummy gate structure; forming a semiconductor pattern on the fin-type pattern; and removing the dummy gate structure.

[0010] According to some example embodiments of the inventive concept, a semiconductor device may include: a fin-type pattern protruding from a substrate and extending in a first direction; a field insulating layer on the substrate covering at least a portion of the fin-type pattern; a gate structure on the field insulating layer and the fin-type pattern, the gate structure extending in a second direction different from the first direction; and gate spacers on sidewalls of the gate structure. The field insulating layer may include a first region overlapping with the gate spacers, and an upper portion of the field insulating layer in the first region of the field insulating layer includes a nitrogen element. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become clearer by describing example embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0012] Figure 1 is a perspective view of a semiconductor device according to some example embodiments of the present disclosure;

[0013] Figure 2 is along Figure 1 taken along line A-A' of;

[0014] Figure 3 is along Figure 1 taken along line B-B' of; and

[0015] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23 are diagrams for explaining processing steps of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Although the accompanying drawings related to semiconductor devices according to some example embodiments of the present disclosure illustratively show fin field-effect transistors (FinFETs) including a channel region having a fin pattern, this is merely illustrative. It should be understood that semiconductor devices according to some example embodiments of the present disclosure may include tunneling FETs, transistors including nanowires, transistors including nanosheets, or three-dimensional (3D) transistors. Additionally, semiconductor devices according to some example embodiments of the present disclosure may include bipolar junction transistors, laterally diffused metal oxide semiconductor (LDMOS), etc.

[0017] Although semiconductor devices according to some example embodiments of the present disclosure are described as using multi-channel transistors having a fin pattern, it should be understood that planar transistors may also be employed.

[0018] Hereinafter, a semiconductor device according to some example embodiments of the present disclosure will be described with reference to Figures 1 to 3 .

[0019] Figure 1 is a perspective view of a semiconductor device according to some example embodiments of the present disclosure. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 . Figure 3 is a cross-sectional view taken along line B-B' of Figure 1 . For ease of illustration, the interlayer insulating layer 170 is not shown in Figure 1 .

[0020] Reference is made to Figures 1 to 3, a semiconductor device according to some example embodiments of the present disclosure may include a substrate 100, a first fin pattern 111, a second fin pattern 112, a field insulating layer 120, a first gate structure 130, a gate spacer 140, a barrier layer 150, a first semiconductor pattern feature 161, and a second semiconductor pattern feature 162.

[0021] The substrate 100 may be, for example, a bulk silicon substrate or an SOI (silicon-on-insulator) substrate. In some example embodiments, the substrate 100 may be a silicon substrate or may be a substrate made of other materials, such as silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe) compounds, indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), and gallium antimonide (GaSb). In some example embodiments, the substrate 100 may be formed by growing an epitaxial layer on a base substrate.

[0022] The first fin pattern 111 and the second fin pattern 112 may protrude from the substrate 100 and extend along a first direction D1. The first fin pattern 111 and the second fin pattern 112 may be spaced apart from each other along a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be perpendicular to each other.

[0023] In the following drawings, the sidewalls of each of the first fin pattern 111 and the second fin pattern 112 are shown as vertical. However, it should be understood that this is merely illustrative. For example, the sidewalls of each of the first fin pattern 111 and the second fin pattern 112 may be inclined. Additionally, for example, the first fin pattern 111 and the second fin pattern 112 may be tapered in shape.

[0024] The first fin pattern 111 and the second fin pattern 112 may be formed by using an epitaxial layer formed on a base substrate. The epitaxial layer may include an elemental semiconductor material such as silicon or germanium. In some example embodiments, the epitaxial layer may include a compound semiconductor, for example, a group-IV-IV compound semiconductor or a group-III-V compound semiconductor. Specifically, as an example of a group-IV-IV compound semiconductor, the epitaxial layer may include a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or such a compound doped with a group-IV element. As an example of a group-III-V compound semiconductor, the epitaxial layer may include a binary compound, a ternary compound, or a quaternary compound composed of at least one of group-III elements aluminum (Al), gallium (Ga), and indium (In) and at least one of group-V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0025] In a semiconductor device according to some example embodiments of the present disclosure, the first fin pattern 111 and the second fin pattern 112 are described as including silicon.

[0026] A field insulating layer 120 may be formed on a substrate 100. The field insulating layer 120 may cover at least a portion of each of the first fin pattern 111 and the second fin pattern 112. When the field insulating layer 120 covers a portion of each of the first fin pattern 111 and the second fin pattern 112, each of the first fin pattern 111 and the second fin pattern 112 may protrude above the field insulating layer 120 formed on the substrate 100.

[0027] The field insulating layer 120 may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0028] The first gate structure 130 may be disposed to intersect each of the first fin pattern 111 and the second fin pattern 112. For example, the first gate structure 130 may extend in a second direction D2 over the field insulating layer 120, the first fin pattern 111, and the second fin pattern 112.

[0029] The first gate structure 130 may include a first gate insulating layer 131 and a first gate electrode 133.

[0030] The first gate electrode 133 may include a metal material. Although the first gate electrode 133 is shown as a single layer in the drawings, this is merely illustrative. For example, the first gate electrode 133 may include two or more metal layers. When the first gate electrode 133 includes two or more metal layers, one of the two or more metal layers may control the work function.

[0031] The first gate insulating layer 131 may be disposed between the gate spacer 140 and the first gate electrode 133, between the first fin pattern 111 and the first gate electrode 133, and between the second fin pattern 112 and the first gate electrode 133. The first gate insulating layer 131 may also be disposed between the field insulating layer 120 and the first gate electrode 133.

[0032] The first gate insulating layer 131 may include a high-k material having a dielectric constant higher than that of a silicon oxide layer. For example, the first gate insulating layer 131 may include, but is not limited to, at least one of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0033] The gate spacers 140 may be disposed on two sidewalls of the first gate structure 130 extending along the second direction D2. Although the gate spacers 140 are shown as a single layer, this is merely illustrative. It should be understood that the gate spacers 140 may have a multi-layer structure.

[0034] The gate spacers 140 may include at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbide nitride (SiOCN), and combinations thereof.

[0035] The first semiconductor pattern feature 161 may be disposed on the first fin pattern 111 on at least one side of the first gate structure 130. The second semiconductor pattern feature 162 may be disposed on the second fin pattern 112 on at least one side of the first gate structure 130. The outer peripheral surfaces of the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 may have various shapes. For example, the outer peripheral surfaces of the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 may have various shapes such as a rhombus, a circle, and a rectangle. In the following drawings, as an example, the semiconductor pattern feature has a pentagonal shape.

[0036] When the semiconductor device according to some example embodiments of the present disclosure is a PMOS transistor, the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 may include a compressive stress material. For example, the lattice constant of the compressive stress material may be greater than the lattice constant of Si, for example, SiGe. The compressive stress material may improve the carrier mobility in the channel region by applying compressive stress to the first fin pattern 111 and the second fin pattern 112.

[0037] In some example embodiments, when the semiconductor device according to some example embodiments of the present disclosure is an NMOS transistor, the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 may be the same material as the first fin pattern 111 and the second fin pattern 112, or may be a tensile stress material. For example, if the first fin pattern 111 and the second fin pattern 112 include silicon (Si), the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 may be silicon or a material having a lattice constant smaller than the lattice constant of silicon (e.g., SiC).

[0038] The blocking layer 150 may be disposed between the field insulating layer 120 and the interlayer insulating layer 170 (to be described later). Additionally, the blocking layer 150 may be disposed in a region (i.e., the first region R1) of the field insulating layer 120 that overlaps with the gate spacer 140 (``overlaps in the vertical direction''). Additionally, the blocking layer 150 may be disposed on a portion of the first fin pattern 111 that overlaps with the gate spacer 140. Additionally, the blocking layer 150 may be disposed on a portion of the second fin pattern 112 that overlaps with the gate spacer 140.

[0039] The blocking layer 150 may be at least partially disposed (``formed'') in the field insulating layer 120 as the upper surface of the field insulating layer 120. However, the technical concept of the present disclosure is not limited thereto. For example, at least a portion of the blocking layer 150 may protrude from the upper surface of the field insulating layer 120.

[0040] The blocking layer 150 may be disposed in each of the first fin pattern 111 and the second fin pattern 112 as a part of the upper surface of the first fin pattern 111 and a part of the upper surface of the second fin pattern 112. This part of the upper surface of the first fin pattern 111 and this part of the upper surface of the second fin pattern 112 may be the part of the first fin pattern 111 that overlaps with the gate spacer 140 and the part of the second fin pattern 112 that overlaps with the gate spacer 140, respectively.

[0041] However, the technical concept of the present disclosure is not limited thereto. For example, it should be understood that at least a portion of the third blocking layer 150c may protrude from the upper surfaces of the first fin pattern 111 and the second fin pattern 112.

[0042] The blocking layer 150 may include a first blocking layer 150a and a third blocking layer 150c.

[0043] The first blocking layer 150a may be the portion of the blocking layer 150 disposed in the first region R1 of the field insulating layer 120. The first blocking layer 150a may be disposed on the upper portion of the field insulating layer 120. The upper portion of the field insulating layer 120 may be the portion of the field insulating layer 120 that includes the upper surface 120U of the field insulating layer 120. The third blocking layer 150c may be the portion of the blocking layer 150 disposed in the portions of the first fin pattern 111 and the second fin pattern 112 that overlap with the gate spacer 140. The third blocking layer 150c may be disposed on the upper portions of the first fin pattern 111 and the second fin pattern 112. The upper portions of the first fin pattern 111 and the second fin pattern 112 may be the portions including the upper surface of the first fin pattern 111 and the portion including the upper surface of the second fin pattern 112, respectively.

[0044] The blocking layer 150 may include a nitrogen element.

[0045] Specifically, in a first region R1 of the field insulating layer 120, the upper portion of the field insulating layer 120 may include nitrogen. That is, since the first barrier layer 150a is disposed on the upper portion of the field insulating layer 120 in the first region R1 of the field insulating layer 120, the upper portion of the field insulating layer 120 may include nitrogen. For example, in the first region R1 of the field insulating layer 120, the concentration of nitrogen may decrease from the upper surface 120U of the field insulating layer 120 to the lower surface 120L of the field insulating layer 120.

[0046] In addition, in a region where the first fin pattern 111 overlaps with the gate spacer 140 and in a region where the second fin pattern 112 overlaps with the gate spacer 140, the upper portions of the first fin pattern 111 and the second fin pattern 112 may respectively include nitrogen. In addition, in a region where the first fin pattern 111 overlaps with the gate spacer 140 and in a region where the second fin pattern 112 overlaps with the gate spacer 140, the third barrier layer 150c is disposed in each of the upper portions of the first fin pattern 111 and the second fin pattern 112, and thus the upper portions of the first fin pattern 111 and the second fin pattern 112 may include nitrogen. For example, in a region where the first fin pattern 111 overlaps with the gate spacer 140 and in a region where the second fin pattern 112 overlaps with the gate spacer 140, the concentration of nitrogen decreases from the upper surface to the lower surface of each of the first fin pattern 111 and the second fin pattern 112.

[0047] The following will refer to Figure 13 and Figure 15 and so on to describe in detail the concentration of nitrogen.

[0048] The "nitrogen element" mentioned herein may include elemental (atomic) nitrogen, diatomic nitrogen, nitrogen-containing compounds (e.g., nitrides, nitrogen oxides, etc.), certain combinations thereof, and the like.

[0049] The interlayer insulating layer 170 may cover the first semiconductor pattern feature 161, the second semiconductor pattern feature 162, and the first gate structure 130 on the barrier layer 150.

[0050] The interlayer insulating layer 170 may include at least one of a low-k dielectric material, an oxide film, a nitride film, and a nitrogen oxide film. The low-k dielectric material may be made of, for example, a material such as flowable oxide (FOX), tonen silicon nitride (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high density plasma (HDP), plasma enhanced oxide (PEOX), flowable CVD (FCVD), or a combination thereof.

[0051] Hereinafter, a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure will be described with reference to Figures 4 to 18 For clarity of explanation, redundant descriptions will be omitted.

[0052] Figures 4 to 18 is a diagram for illustrating processing steps of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0053] With reference to Figure 4 , a first fin pattern 111 and a second fin pattern 112 may be formed.

[0054] The first fin pattern 111 and the second fin pattern 112 may protrude from the substrate 100 and extend in a first direction D1. For example, the first fin pattern 111 and the second fin pattern 112 may be formed by forming a mask pattern on the substrate 100 and then performing an etching process. Grooves may be formed around each of the first fin pattern 111 and the second fin pattern 112.

[0055] The first fin pattern 111 may include an upper surface 111U that is higher than the upper surface 100U of the substrate 100. The first fin pattern 111 may include sidewalls 111S that connect the upper surface 111U of the first fin pattern 111 to the upper surface 100U of the substrate 100. The second fin pattern 112 may include an upper surface 112U that is higher than the upper surface 100U of the substrate 100. The second fin pattern 112 may include sidewalls 112S that connect the upper surface 112U of the second fin pattern 112 to the upper surface 100U of the substrate 100.

[0056] With reference to Figure 5 , a field insulating layer 120 may be formed on the substrate 100.

[0057] The field isolation layer 120 may include an upper surface 120U and a lower surface 120L that face each other. The lower surface 120L of the field isolation layer 120 may be in contact with the upper surface of the substrate 100. The field isolation layer 120 may cover at least a portion of each of the first fin pattern 111 and the second fin pattern 112. As Figure 5 shown, for example, the field isolation layer 120 may cover a limited portion of each of the first fin pattern 111 and the second fin pattern 112, such that the field isolation layer 120 exposes another limited portion of each of the first fin pattern 111 and the second fin pattern 112.

[0058] When the field isolation layer 120 covers a portion of each of the first fin pattern 111 and the second fin pattern 112, the upper surface of each of the first fin pattern 111 and the second fin pattern 112 may be higher than the upper surface 120U of the field isolation layer 120. A portion of the sidewall 111S of the first fin pattern 111 and a portion of the sidewall 112S of the second fin pattern 112 may be surrounded by the field isolation layer 120. That is, the lower portion of each of the first fin pattern 111 and the second fin pattern 112 may be surrounded by the field isolation layer 120, while the upper portion of each of the first fin pattern 111 and the second fin pattern 112 may protrude from the field isolation layer 120.

[0059] The field isolation layer 120 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0060] In some exemplary embodiments of the present disclosure, the first fin pattern 111 and the second fin pattern 112 may be doped with impurities to adjust the threshold voltage. If the transistor formed by using the first fin pattern 111 and the second fin pattern 112 is an NMOS transistor, the impurity may be p-type, such as boron (B). If the transistor formed by using the first fin pattern 111 and the second fin pattern 112 is a PMOS transistor, the impurity may be n-type, such as phosphorus (P) or arsenic (As).

[0061] Referring Figure 6 to, a second gate structure 180 may be formed on the field isolation layer 120, the first fin pattern 111, and the second fin pattern 112. The second gate structure 180 may be disposed such that it intersects each of the first fin pattern 111 and the second fin pattern 112. For example, the second gate structure 180 may extend in the second direction D2.

[0062] The second gate structure 180 may include a second gate insulating layer 181, a second gate electrode 183, and a first hard mask 185 that are sequentially stacked on each other. The second gate structure 180 may be a stack of the second gate insulating layer 181, the second gate electrode 183, and the first hard mask 185 that extends in the second direction D2.

[0063] The first hard mask 185 can be used as an etching mask to form the second gate structure 180. In some example embodiments, the second gate structure 180 can be formed based on the following method: a gate structure layer is formed on the field insulating layer 120 and the first fin pattern 111 and the second fin pattern 112, and the gate structure layer is further patterned to form the second gate structure 180.

[0064] The second gate insulating layer 181 is shown as being formed not only on the outer peripheries of each of the first fin pattern 111 and the second fin pattern 112, but also on the upper surface 120U of the field insulating layer 120. However, it should be understood that this is merely illustrative. For example, the second gate insulating layer 181 can be formed only on the sidewalls 111S and the upper surface 111U of the first fin pattern 111 protruding above the field insulating layer 120 and the sidewalls 112S and the upper surface 112U of the second fin pattern 112.

[0065] The second gate insulating layer 181 is shown as not being formed at the outer peripheries of each of the first fin pattern 111 and the second fin pattern 112 that do not overlap with the second gate structure 180. However, it should be understood that this is merely illustrative. For example, the second gate insulating layer 181 can also be formed at the entire outer peripheries of each of the first fin pattern 111 and the second fin pattern 112 protruding above the field insulating layer 120.

[0066] The second gate insulating layer 181 can include, for example, silicon oxide.

[0067] In some example embodiments of the present disclosure, the second gate structure 180 can further include an interfacial insulating layer. The interfacial insulating layer can be formed between the second gate insulating layer 181 and the field insulating layer 120, between the second gate insulating layer 181 and the first fin pattern 111, and between the second gate insulating layer 181 and the second fin pattern 112. The interfacial insulating layer can include a low-k material layer with a dielectric constant (k) of 9 or less. For example, a silicon oxide film with a k value of about 4 or a silicon oxynitride film with a k value of about 4 to 8 (depending on the content of oxygen atoms and nitrogen atoms).

[0068] The second gate electrode 183 may be disposed on the second gate insulating layer 181. The second gate electrode 183 may completely cover each of the first fin pattern 111 and the second fin pattern 112 that overlaps with the second gate structure 180 and protrudes above the field insulating layer 120. That is, the height from the upper surface 120U of the field insulating layer 120 to the upper surface 111U of the first fin pattern 111 and the height from the upper surface 120U of the field insulating layer 120 to the upper surface 112U of the second fin pattern 112 may be less than the height from the upper surface 120U of the field insulating layer 120 to the upper surface of the second gate electrode 183.

[0069] In some exemplary embodiments of the present disclosure, the second gate electrode 183 may include polysilicon. Each of the second gate electrode 183 and the second gate insulating layer 181 may have a high etch selectivity with respect to each other. The second gate electrode 183 may be etched to form an alternative gate metal gate (e.g., Figure 1 the first gate structure 130). In doing so, the second gate electrode 183 is removed, but the second gate insulating layer 181 may be retained.

[0070] The first hard mask 185 may be formed on the second gate electrode 183. The first hard mask 185 may include, but is not limited to, silicon nitride (SiN).

[0071] Reference Figure 7 、 Figure 8 and Figure 9 ,a barrier layer 150 may be formed. Figure 8 is a cross-sectional view taken along line C-C’ of Figure 7 . Figure 9 is a cross-sectional view taken along line D-D’ of Figure 7 .

[0072] The barrier layer 150 may be formed on the field insulating layer 120 exposed by the second gate structure 180. Additionally, the barrier layer 150 may be formed on the upper surface 111U and sidewalls 111S of the first fin pattern 111 and the upper surface 112U and sidewalls 112S of the second fin pattern 112 that protrude from the field insulating layer 120 and are exposed by the second gate structure 180. Additionally, the barrier layer 150 may be formed on the two sidewalls 180S1 and 180S2 and the upper surface of the second gate structure 180.

[0073] The barrier layer 150 may include a first barrier layer 150a, a second barrier layer 150b, a third barrier layer 150c, and a fourth barrier layer 150d.

[0074] The first blocking layer 150a may be formed in a first region R1 of the field insulating layer 120. The first region R1 of the field insulating layer 120 may be a portion of the field insulating layer 120 that is exposed by the second gate structure 180, adjacent to the second gate structure 180, and elongated (extends along the second direction D2) in the second direction D2. In the first region R1 of the field insulating layer 120, the gate spacer 140 may be formed in a subsequent process (e.g., after forming the first blocking layer 150a) (see Figure 10 ). That is, in the first region R1 of the field insulating layer 120, the gate spacer may overlap the field insulating layer 120 ("overlap in the vertical direction"). The first region R1 may include nitrogen element.

[0075] At least as Figure 7 shown, the first blocking layer 150a may be formed in the upper portion of the field insulating layer 120 (e.g., including the upper surface of the field insulating layer 120). However, the technical concept of the present disclosure is not limited thereto. For example, at least a portion of the first blocking layer 150a may protrude from the upper surface 120U of the field insulating layer 120.

[0076] The first blocking layer 150a may include nitrogen element (e.g., a nitrogen-containing compound). The first blocking layer 150a may include, for example, silicon oxynitride. Due to the first blocking layer 150a, in the first region R1 of the field insulating layer 120, the upper portion of the field insulating layer 120 may include nitrogen element.

[0077] The second gate structure 180 may include a first sidewall 180S1 and a second sidewall 180S2 that face each other. The second blocking layer 150b may be formed on the upper surface of the second gate structure 180, the first sidewall 180S1 of the second gate structure 180, and the second sidewall 180S2 of the second gate structure 180.

[0078] For example, the second blocking layer 150b may be formed in the second gate insulating layer 181, formed in the second gate electrode 183, and formed in the first hard mask 185. In this case, a portion of the second gate insulating layer 181 adjacent to the first sidewall 180S1 and the second sidewall 180S2 of the second gate structure 180 may include a portion of the second blocking layer 150b. In addition, a portion of the second gate electrode 183 adjacent to the first sidewall 180S1 and the second sidewall 180S2 of the second gate structure 180 may include a portion of the second blocking layer 150b. In addition, a portion of the first hard mask 185 adjacent to the first sidewall 180S1 and the second sidewall 180S2 of the second gate structure 180 and a portion of the upper surface of the first hard mask may include the remaining portion of the second blocking layer 150b.

[0079] However, the technical concept of the present disclosure is not limited thereto. For example, at least a portion of the second barrier layer 150b may cover the second gate structure 180 and may protrude above the upper surface of the second gate structure 180, the first sidewall 180S1, and the second sidewall 180S2.

[0080] The second barrier layer 150b may include a nitrogen element. The second barrier layer 150b may include, for example, silicon oxynitride. In another example, the second barrier layer 150b may include silicon nitride. Due to the second barrier layer 150b, the first sidewall 180S1 and the second sidewall 180S2 of the second gate structure 180 may include a nitrogen element.

[0081] The third barrier layer 150c may be formed on the upper surface 111U of the first fin pattern 111 and the upper surface 112U of the second fin pattern 112. In some exemplary embodiments, the third barrier layer 150c may be formed on the upper surface 111U of the first fin pattern 111 and the upper surface 112U of the second fin pattern 112 that do not overlap with the second gate structure 180. For example, the third barrier layer 150c may be formed in a region where the gate spacer 140 (see Figure 10 ) will be formed on the first fin pattern 111 and the second fin pattern 112 in a subsequent process. In other words, the third barrier layer 150c may include a portion formed in a region where the first fin pattern 111 overlaps with the gate spacer, and a portion formed in a region where the second fin pattern 112 overlaps with the gate spacer.

[0082] The third barrier layer 150c may be formed, for example, in the upper portion of the first fin pattern 111 and the upper portion of the second fin pattern 112. However, the technical concept of the present disclosure is not limited thereto. For example, it should be understood that at least a portion of the third barrier layer 150c may protrude from the upper surface 111U of the first fin pattern 111 and the upper surface 112U of the second fin pattern 112.

[0083] The third barrier layer 150c may include a nitrogen element. The third barrier layer 150c may include, for example, silicon oxynitride or silicon nitride. Due to the third barrier layer 150c, the upper portion of the first fin pattern 111 in a region where the first fin pattern 111 overlaps with the gate spacer and the upper portion of the second fin pattern 112 in a region where the second fin pattern 112 overlaps with the gate spacer may include a nitrogen element.

[0084] The fourth blocking layer 150d may be formed on sidewalls 111S of the first fin-type pattern 111 protruding from the field insulating layer 120 and sidewalls 112S of the second fin-type pattern 112. In some example embodiments, the fourth blocking layer 150d may be formed on sidewalls 111S of the first fin-type pattern 111 and sidewalls 112S of the second fin-type pattern 112 that do not overlap with the second gate structure 180.

[0085] The fourth blocking layer 150d may be formed on, for example, sidewalls 111S of the first fin-type pattern 111 and sidewalls 112S of the second fin-type pattern 112. The fourth blocking layer 150d may connect the third blocking layer 150c to the first blocking layer 150a.

[0086] The fourth blocking layer 150d may be formed in, for example, sidewalls 111S of the first fin-type pattern 111 and also formed in sidewalls 112S of the second fin-type pattern 112. However, the technical concept of the present disclosure is not limited thereto. For example, it should be understood that at least a portion of the fourth blocking layer 150d may protrude from sidewalls 111S of the first fin-type pattern 111 and sidewalls 112S of the second fin-type pattern 112.

[0087] The fourth blocking layer 150d may include a nitrogen element. The fourth blocking layer 150d may include, for example, silicon oxynitride or silicon nitride.

[0088] In some example embodiments, the blocking layer 150 may be formed by a nitridation process (NP). For example, as Figures 7 to 9 shown, the blocking layer 150 may be formed based on performing a nitridation process on the following parts: the upper surface of the field insulating layer 120, upper surfaces 111U and 112U of the first fin-type pattern 111 and the second fin-type pattern 112, sidewalls 111S and 112S of the first fin-type pattern 111 and the second fin-type pattern 112, the upper surface of the second gate structure 180, and the sidewalls of the second gate structure 180. In some example embodiments, the blocking layer 150 may be formed by depositing a nitride film containing a nitrogen element through a deposition process. In some example embodiments, the first blocking layer 150a, the second blocking layer 150b, the third blocking layer 150c, and the fourth blocking layer 150d may be formed simultaneously.

[0089] Reference Figure 10 may be made to form gate spacers 140 on two sidewalls of the second gate structure 180, respectively.

[0090] The gate spacers 140 may be formed on the sidewalls of the second gate structure 180. The gate spacers 140 may be formed on a first region R1 of the field insulating layer 120, and the gate spacers 140 may overlap with the first region R1 of the field insulating layer 120. The gate spacers 140 may be formed on the first blocking layer 150a and the second blocking layer 150b. AsFigure 10 As shown, the second blocking layer 150b may be between the gate spacer 140 and the sidewalls of the second gate structure 180.

[0091] Each of the first semiconductor pattern features 161 and the second semiconductor pattern features 162 may be formed on the first fin pattern 111 and the second fin pattern 112, respectively. Each of the first semiconductor pattern features 161 and the second semiconductor pattern features 162 may be formed on at least one side of the second gate structure 180. Each of the first semiconductor pattern features 161 and the second semiconductor pattern features 162 may be a source / drain of a transistor, for example, a raised source / drain.

[0092] Each of the first semiconductor pattern features 161 and the second semiconductor pattern features 162 may have various shapes, such as a rhombus, a circle, and a rectangle. Although Figure 10 the semiconductor pattern features shown in have a pentagonal shape, this is merely illustrative.

[0093] In some example embodiments, each of the first semiconductor pattern features 161 and the second semiconductor pattern features 162 may be formed by removing portions of the first fin pattern 111 and the second fin pattern 112 that protrude from the blocking layer 150 and then using epitaxial growth.

[0094] Referring Figure 11 to, an interlayer insulating layer 170 covering the first semiconductor pattern features 161, the second semiconductor pattern features 162, and the second gate structure 180 may be formed on the blocking layer 150.

[0095] In some example embodiments, the interlayer insulating layer 170 may be planarized until the upper surface of the second blocking layer 150b is exposed.

[0096] In some example embodiments, the interlayer insulating layer 170 may be planarized until the upper surface of the second gate electrode 183 is exposed. In this case, the portion of the second blocking layer 150b on the first hard mask 185 and the first hard mask 185 may be removed together.

[0097] Figure 12 is a cross-sectional view taken along line E-E’ of Figure 11 . Figure 13 is an example graph illustrating the concentration of nitrogen element in the second gate structure 180 of Figure 12 . In the graph shown in Figure 13 , the x-axis may represent the distance between the first sidewall 180S1 and the second sidewall 180S2 of the second gate structure 180 in AU, and the y-axis may represent the concentration of nitrogen element in the second gate structure 180 in AU.

[0098] Reference Figure 12 and Figure 13 Figure 13

[0099] In addition, after the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 are formed, the third barrier layer 150c may remain in the portions where the first fin pattern 111 and the second fin pattern 112 overlap with the gate spacer 140. For example, the first fin pattern 111 and the second fin pattern 112 may each include a region overlapping with the gate spacer 140, and the upper portions of each of the first fin pattern 111 and the second fin pattern 112 include a nitrogen element in the region overlapping with the gate spacer 140.

[0100] The concentration of the nitrogen element in the second gate structure 180 may decrease and then increase from the first sidewall 180S1 of the second gate structure 180 to the second sidewall 180S2 of the second gate structure 180.

[0101] That is, the concentration of the nitrogen element in the second gate structure 180 may decrease from the first point Pa to the second point Pb. In addition, the concentration of the nitrogen element in the second gate structure 180 may increase from the second point Pb to the third point Pc. The first point Pa may be, for example, the position where the first sidewall 180S1 of the second gate structure 180 is located. The second point Pb may be, for example, the center point between the first sidewall 180S1 and the second sidewall 180S2 of the second gate structure 180. The third point Pc may be, for example, the position where the second sidewall 180S2 of the second gate structure 180 is located.

[0102] Due to the second barrier layer 150b, the concentration of the nitrogen element in the portion of the second gate structure 180 adjacent to the first point Pa may be greater than the concentration of the nitrogen element in the portion of the second gate structure 180 adjacent to the second point Pb. Due to the second barrier layer 150b, the concentration of the nitrogen element in the portion of the second gate structure 180 adjacent to the third point Pc may be greater than the concentration of the nitrogen element in the portion of the second gate structure 180 adjacent to the second point Pb.

[0103] Figure 14 is a cross-sectional view taken along the line F-F’ Figure 11 is an exemplary graph showing the concentration of the nitrogen element in the first region R1 of the field insulating layer 120 Figure 15 is to illustrate Figure 14 In Figure 15In the graph shown, the x-axis may represent the depth from the upper surface of the first barrier layer 150a in the field insulating layer 120 in AU, and the y-axis may represent the concentration of nitrogen element in the first region R1 of the field insulating layer 120 in AU.

[0104] In the first region R1 of the field insulating layer 120, the concentration of nitrogen element at the upper part of the field insulating layer 120 may be greater than that at the lower part of the field insulating layer 120. The lower part of the field insulating layer 120 may be, for example, the part including the lower surface 120L of the field insulating layer 120. The concentration of nitrogen element in the first region R1 of the field insulating layer 120 may decrease from the upper surface 120U to the lower surface 120L of the field insulating layer 120. In other words, the concentration of nitrogen element in the first region R1 may be inversely proportional to the distance from the upper surface 120U and directly proportional to the distance from the lower surface 120L.

[0105] That is to say, the concentration of nitrogen element in the first region R1 of the field insulating layer 120 may decrease from the fourth point Pd to the fifth point Pe.

[0106] The fourth point Pd may be, for example, the point where the upper surface of the first barrier layer 150a is located. In some exemplary embodiments, when the first barrier layer 150a is formed in the field insulating layer 120, the fourth point Pd may be the point where the upper surface 120U of the field insulating layer 120 is located. The fifth point Pe may be a point adjacent to the lower surface 120L of the field insulating layer.

[0107] Although there is a certain concentration of nitrogen element at the fifth point Pe in the graph of Figure 15 , this is merely illustrative. For example, at the fifth point Pe adjacent to the lower surface 120L of the field insulating layer 120, the concentration of nitrogen element may be substantially 0 AU.

[0108] Figure 17 is a cross-sectional view taken along the line G-G’ of Figure 16 . Figure 18 is a cross-sectional view taken along the line H-H’ of Figure 16 .

[0109] Referring to Figure 16 , Figure 17 and Figure 18 , the second gate insulating layer 181 and the second gate electrode 183 may be removed so that the gate trench 130T can be formed. The sidewalls of the gate trench 130T may be defined by the gate spacers 140. The gate trench 130T may expose the upper surfaces of the first fin pattern 111, the second fin pattern 112, and the upper surface 120U of the field insulating layer 120.

[0110] In some example embodiments, the second gate insulating layer 181 and the second gate electrode 183 (and thus the second gate structure 180) may be removed to form a replacement gate electrode (e.g., Figure 1 the first gate structure 130). For example, the second gate insulating layer 181 and the second gate electrode 183 may be removed by a wet etching process. In some example embodiments, the removed second gate structure 180 may be referred to as a "dummy gate structure".

[0111] By performing a process of etching the second gate insulating layer 181 and the second gate electrode 183, the second gate insulating layer 181 and the second gate electrode 183 may be removed, leaving the gate spacer 140. In the process of etching the second gate insulating layer 181 and the second gate electrode 183, an etchant may be used to remove the second gate insulating layer 181 and the second gate electrode 183.

[0112] Due to the second barrier layer 150b, the etchant may not penetrate into the gate spacer 140. By means of the second barrier layer 150b, thinning of the thickness of the gate spacer 140 due to the etchant in the process of etching the second gate insulating layer 181 and the second gate electrode 183 may be prevented. Therefore, an increase in the width of the first gate structure 130 to be formed in the gate trench 130T in a subsequent process in the first direction D1 may be prevented. This may lead to an improvement in the performance and yield of the semiconductor device.

[0113] By means of the first barrier layer 150a and the third barrier layer 150c, the etchant may be prevented from penetrating into the first semiconductor pattern feature 161 and the second semiconductor pattern feature 162 through the field insulating layer 120, the first fin pattern 111, and the second fin pattern 112. In other words, by means of the first barrier layer 150a and the third barrier layer 150c, a short circuit caused by the etchant may be prevented.

[0114] In a subsequent process, the first gate structure 130 may be formed in the gate trench 130T (see Figure 1 ).

[0115] Hereinafter, with reference to Figure 4 、 Figure 5 、 Figure 19 and Figure 20 a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure will be described. For clarity of illustration, redundant descriptions will be omitted.

[0116] Figures 19 to 20 is a perspective view for illustrating processing steps of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure. Figure 19 is a view in which reference Figure 4 and Figure 5View after the described process of manufacturing a semiconductor device.

[0117] Reference Figure 19 , a third gate structure layer 190P and a mask pattern 197 may be formed on the field insulating layer 120, the first fin pattern 111, and the second fin pattern 112.

[0118] The third gate structure layer 190P may include a preliminary third gate insulating layer 191P, a preliminary third gate electrode 193P, and a preliminary second hard mask 195P sequentially stacked on the field insulating layer 120, the first fin pattern 111, and the second fin pattern 112.

[0119] In some example embodiments, the third gate structure layer 190P may further include an interface insulating layer. The interface insulating layer may be formed between the preliminary third gate insulating layer 191P and the field insulating layer 120, between the preliminary third gate insulating layer 191P and the first fin pattern 111, and between the preliminary third gate insulating layer 191P and the second fin pattern 112. The interface insulating layer may include a low-k material layer with a dielectric constant (k) of 9 or less. For example, a silicon oxide film with a k value of about 4 or a silicon oxynitride film with a k value of about 4 to 8 (depending on the content of oxygen atoms and nitrogen atoms).

[0120] The preliminary third gate insulating layer 191P may be formed on the field insulating layer 120 so as to cover the first fin pattern 111 and the second fin pattern 112 protruding from the field insulating layer 120. The preliminary third gate insulating layer 191P may include, for example, a high-k dielectric material with a dielectric constant higher than that of silicon. The preliminary third gate insulating layer 191P may include, but is not limited to: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalum oxide (PbScTaO), or a combination thereof.

[0121] The preliminary third gate electrode 193P may be formed on the preliminary third gate insulating layer 191P. The preliminary third gate electrode 193P may include a metal material. Although the preliminary third gate electrode 193P is shown as a single layer in the drawings, this is merely illustrative. For example, the preliminary third gate electrode 193P may include two or more metal layers. When the preliminary third gate electrode 193P includes two or more metal layers, one of the two or more metal layers may control the work function.

[0122] A second hard mask 195P may be formed on the third preliminary gate electrode 193P. The second hard mask 195P may include, but is not limited to, silicon nitride.

[0123] A mask pattern 197 may be formed on the third gate structure layer 190P.

[0124] Reference Figure 20 , a third gate structure 190 may be formed. The third gate structure 190 may be formed by patterning the third gate structure layer 190P by using the mask pattern 197 as an etching mask.

[0125] The third gate structure 190 may include a third gate insulating layer 191, a third gate electrode 193, and a second hard mask 195 stacked on each other in sequence.

[0126] A nitridation process NP may be performed on the third gate structure 190, and the first fin pattern 111, the second fin pattern 112, and the field insulating layer 120 exposed by the third gate structure 190 to form a blocking layer 150. Figure 7 to form a blocking layer 150.

[0127] In Figures 7 to 15 each of the figures, the second gate structure 180 may correspond to the third gate structure 190. In other words, the method of manufacturing a semiconductor device described above with reference to Figures 7 to 15 may be similarly applied to a gate-first process of first forming a gate structure (i.e., the third gate structure 190). For example, a first blocking layer 150a may be formed on a first region R1 of the field insulating layer 120 overlapping with a gate spacer 140 (see Figure 10 ) to be formed on any sidewall of the third gate structure 190. In addition, a second blocking layer 150b may be formed on any sidewall of the third gate structure 190. In addition, a third blocking layer 150c may be formed on a portion of the first fin pattern 111 overlapping with the gate spacer 140 (see Figure 10 ) and a portion of the second fin pattern 112 overlapping with the gate spacer 140.

[0128] Hereinafter, a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference to Figures 21 to 23 . For clarity of explanation, redundant descriptions will be omitted.

[0129] Figures 21 to 22 is a perspective view for explaining processing steps of a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 23 is a cross-sectional view taken along line I-I’ of Figure 22 . Figure 22The cross-sectional view taken along line J-J’ can correspond to Figure 9 the cross-sectional view of

[0130] Referring to Figure 21 , the third fin-type pattern 113 and the fourth fin-type pattern 114 can protrude from the substrate 100 and extend along the first direction D1. The third fin-type pattern 113 and the fourth fin-type pattern 114 can be spaced apart from each other along the second direction D2.

[0131] The third fin-type pattern 113 can include a first portion 113_1 and a second portion 113_2, and the fourth fin-type pattern 114 can include a first portion 114_1 and a second portion 114_2.

[0132] The first portion 113_1 of the third fin-type pattern 113 can be formed between the second portions 113_2 of the third fin-type pattern 113. The first portion 113_1 of the third fin-type pattern 113 can be connected to the second portion 113_2 of the third fin-type pattern 113. The first portion 113_1 of the third fin-type pattern 113 can overlap with the fourth gate structure 200 (see Figure 22 ). The first portion 113_1 of the third fin-type pattern 113 can correspond to the channel region of the transistor.

[0133] The second portion 113_2 of the third fin-type pattern 113 can have a first thickness THK1 with respect to the upper surface of the substrate 100. The first portion 113_1 of the third fin-type pattern 113 can have a second thickness THK2 with respect to the upper surface of the substrate 100. The first thickness THK1 can be greater than the second thickness THK2.

[0134] The first portion 114_1 of the fourth fin-type pattern 114 can correspond to the first portion 113_1 of the third fin-type pattern 113, and the second portion 114_2 of the fourth fin-type pattern 114 can correspond to the second portion 113_2 of the third fin-type pattern 113.

[0135] Referring to Figure 22 and Figure 23 , the fourth gate structure 200 can be formed on the field insulating layer 120, the third fin-type pattern 113, and the fourth fin-type pattern 114. For example, the fourth gate structure 200 can be formed such that it overlaps with the first portion 113_1 of the third fin-type pattern 113 and the first portion 114_1 of the fourth fin-type pattern 114.

[0136] The fourth gate structure 200 can include a fourth gate insulating layer 201, a fourth gate electrode 203, and a third hard mask 205.

[0137] The fourth gate insulating layer 201 may be formed on the upper surface of the field insulating layer 120. The fourth gate insulating layer 201 may be formed to cover the first portion 113_1 of the third fin pattern 113 and the first portion 114_1 of the fourth fin pattern 114. The fourth gate insulating layer 201 may be formed on the sidewalls of the second portion 113_2 of the third fin pattern 113 and the second portion 114_2 of the fourth fin pattern 114.

[0138] The fourth gate electrode 203 may be formed on the fourth gate insulating layer 201. The fourth gate electrode 203 may cover the first portion 113_1 of the third fin pattern 113 and the first portion 114_1 of the fourth fin pattern 114.

[0139] The third hard mask 205 may be formed on the fourth gate electrode 203.

[0140] A nitridation process NP may be performed on the portion of the field insulating layer 120 exposed by the fourth gate structure 200, the second portion 113_2 of the third fin pattern 113, the second portion 114_2 of the fourth fin pattern 114, the upper surface of the fourth gate structure 200, and the sidewalls 200S1 and 200S2 of the fourth gate structure 200.

[0141] The first barrier layer 150a may be formed in the first region R1 of the field insulating layer 120. That is, even if the shape of the channel region is different from Figure 1 the shape of, the first region R1 of the field insulating layer 120 may include the first barrier layer 150a. The second barrier layer 150b may be formed on the upper surface of the fourth gate structure 200 and on the two sidewalls 200S1 and 200S2 of the fourth gate structure 200. The third barrier layer 150c may be formed on the upper surface of the second portion 113_2 of the third fin pattern 113 and on the upper surface of the second portion 114_2 of the fourth fin pattern 114. That is, even if the shape of the channel region is different from Figure 1 the shape of, the portion where the fin pattern overlaps with the gate spacer may include the third barrier layer 150c. The fourth barrier layer 150d may be formed on the sidewalls of the second portion 113_2 of the third fin pattern 113 and on the sidewalls of the second portion 114_2 of the fourth fin pattern 114.

[0142] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept defined by the appended claims. Therefore, it is intended that these embodiments be considered illustrative in all respects and not restrictive, and that the scope of the inventive concept be indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A method of manufacturing a semiconductor device, the method comprises: forming a fin pattern protruding from a substrate and extending in a first direction; forming a field insulating layer on the substrate to cover a limited portion of the fin pattern, such that the field insulating layer exposes another limited portion of the fin pattern; forming a gate structure on the field insulating layer and the fin pattern, the gate structure extending in a second direction different from the first direction; after forming the gate structure, forming a first barrier layer in a first region of the field insulating layer exposed by the gate structure, the first region adjacent to the gate structure and extending in the second direction, the first barrier layer including nitrogen element; and after forming the first barrier layer, forming a gate spacer on the first barrier layer and on sidewalls of the gate structure, such that the first barrier layer is formed after forming the gate structure and before forming the gate spacer.

2. The method according to claim 1, further comprises: forming a second barrier layer on sidewalls of the gate structure, the second barrier layer including nitrogen element, wherein the gate spacer is formed on the second barrier layer, such that the second barrier layer is between the gate spacer and sidewalls of the gate structure.

3. The method according to claim 2, wherein, the first barrier layer and the second barrier layer are formed simultaneously.

4. The method according to claim 2, wherein, the first barrier layer includes silicon oxynitride, and the second barrier layer includes silicon nitride.

5. The method according to claim 1, further comprises: forming a third barrier layer on an upper surface and sidewalls of the fin pattern exposed by the gate structure, the third barrier layer being formed before forming the gate spacer, the third barrier layer including nitrogen element.

6. The method according to claim 5, wherein, the third barrier layer includes silicon nitride.

7. The method according to claim 1, wherein, at least a part of the first barrier layer is formed in an upper portion of the field insulating layer, the upper portion of the field insulating layer including an upper surface of the field insulating layer.

8. The method according to claim 7, wherein, a concentration of nitrogen element in the first region of the field insulating layer decreases from the upper surface of the field insulating layer to a lower surface of the field insulating layer.

9. A method of manufacturing a semiconductor device, the method comprises: forming a fin pattern protruding from a substrate and extending in a first direction; forming a field insulating layer on the substrate to cover a limited portion of the fin pattern, such that the field insulating layer exposes another limited portion of the fin pattern; forming a gate structure on the field insulating layer and the fin pattern, the gate structure extending in a second direction different from the first direction; after forming the gate structure, making a first region of the field insulating layer include nitrogen element; and after making the first region of the field insulating layer include nitrogen element, forming a gate spacer on the first region of the field insulating layer and on sidewalls of the gate structure, such that: After forming the gate structure and before forming the gate spacer on the first region, the first region includes a nitrogen element, and the first region overlaps with the gate spacer.

10. The method according to claim 9, wherein, the concentration of the nitrogen element in the first region of the field insulating layer decreases from the upper surface to the lower surface of the field insulating layer.

11. The method according to claim 9, wherein, the sidewall of the gate structure includes a first sidewall and a second sidewall, the first sidewall and the second sidewall are opposite to each other, and the concentration of the nitrogen element in the portion of the gate structure adjacent to the center point between the first sidewall and the second sidewall is less than both of the following: the concentration of the nitrogen element in the portion of the gate structure adjacent to the first sidewall; and the concentration of the nitrogen element in the portion of the gate structure adjacent to the second sidewall.

12. The method according to claim 9, wherein, the concentration of the nitrogen element in the first region of the field insulating layer is higher at the upper part of the field insulating layer than at the lower part of the field insulating layer.

13. The method according to claim 9, wherein, the fin pattern includes a region overlapping with the gate spacer, and the upper part of the fin pattern in the region overlapping with the gate spacer includes a nitrogen element.

14. The method according to claim 9, further comprises: performing a nitridation process on the fin pattern, the field insulating layer, and the gate structure before forming the gate spacer.

15. The method according to claim 9, further comprises: forming a semiconductor pattern on the fin pattern after forming the gate spacer; and removing the gate structure.

16. The method according to claim 9, wherein, forming the gate structure includes: forming a gate structure layer on the field insulating layer and the fin pattern; and patterning the gate structure layer to form the gate structure.

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