System and method for tag-less buffer implementation

Abstract

The present disclosure provides a data management method for a computer system, the computer system comprising at least one processor and at least a first cache, a second cache, a victim buffer and a memory allocated to the at least one processor, the method comprising: selecting a victim cache line to be evicted from the first cache; finding a victim buffer position corresponding to the victim cache line from the victim buffer; copying data of the victim cache line to a data field of the victim buffer position; copying a back pointer associated with the victim cache line to a back pointer field of the victim buffer position; and reclaiming the victim space of the first cache using the victim buffer. The present disclosure also provides a multi-processor system and a computer-readable storage medium.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] U.S. Provisional Application No. 62 / 588,712, filed with the U.S. Patent and Trademark Office on November 20, 2017, is incorporated herein by reference in its entirety. Technical Field

[0003] At least some example embodiments of the inventive concepts relate generally to methods and systems for accessing data in a computer memory device, and more particularly, to mechanisms and techniques for implementing a tag-less buffer. Background Art

[0004] Today's processors are often equipped with caches that can store copies of data and copies of instructions stored in some high-capacity memory. A popular example of such high-capacity memory today is dynamic random access memory (DRAM). In this article, the term "memory" will be used to collectively refer to all existing and future memory implementations. Cache memory, or simply "cache", is usually built with a much smaller and faster memory than other memory implementations, and can then only keep a copy of a small portion of the data stored in the main memory or auxiliary storage device at any given time. Today, caches are often implemented using SRAM, and large caches can be implemented using DRAM. The caches described herein can be implemented using any existing and future memory technology.

[0005] Typically, the memory system of a computer system includes a series of caches, where larger and slower caches (here referred to as higher-level caches) are closer to the main memory and smaller and faster caches (here referred to as lower-level caches) are closer to the processor. This configuration is often referred to as a cache hierarchy, a memory hierarchy, or a memory system. Each level in the cache hierarchy is called a cache level. FIG. 1 is a block diagram showing a portion of a computer system. In the example shown in FIG. 1 , the computer system is a multiprocessor system, where each CPU 101 is assigned its own first-level dedicated cache 102 (L1 cache). A more detailed example of a CPU 101 and an L1 cache 102 is described below with reference to FIG. 2 . A dedicated cache is a cache in which the space for a data unit can only respond to the activity of a CPU local to the cache (or a CPU located in the same node as the cache, where the cache is dedicated to the node). In this example, a second-level cache 103 is shared by all CPUs 101 and can contain data and instructions accessed by all CPUs 101. Cache 103 is a global cache because the space for data units can be made responsive to the activity of any CPU 101. In addition, cache 103 is a shared cache because each data unit can only exist in one shared copy (whereas each private cache can have its own replica). Memory 105 also stores instructions and data accessed by all CPUs 101. Physical addresses (or PAs for short) are typically used to access (main) memory 105, while addresses generated by CPU 101 are typically virtual addresses. For example, a computer system with multiple CPUs and multiple private caches, such as the system shown in Figure 1, requires an effective mechanism to find a requested data unit in one of the caches, and to keep multiple copies of data stored in different nodes consistent.

[0006] In addition to the main memory and cache memory, such a computer system typically includes one or more auxiliary storage devices. These auxiliary storage devices may include one or more of a hard disk drive, an optical drive, a flash drive, etc., collectively represented here by disk 104. Disk or auxiliary storage 104 can store several orders of magnitude more data than memory 105, but cannot be directly accessed using physical addresses. If CPU 101 wants to access data stored on disk 104, a virtual memory system (not shown in FIG. 1 ) moves a large block of data (commonly referred to as a page) from disk 104 to memory 105, and creates a translation from a virtual address corresponding to the page to a physical address. A special type of translation cache (not shown in FIG. 1 ) (commonly referred to as a "translation look-aside buffer" or TLB for short) caches the translation mapping from a virtual page to a physical page. The virtual memory system can be viewed as a cache system that stores a portion of the data located on disk 104 in memory 105.

[0007] FIG2 is a block diagram for explaining an example cache hierarchy of a computer system. FIG2 shows a more detailed view of the cache organization from FIG1 , with the CPU 101 shown as containing multiple cache-like structures, such as an instruction TLB (ITLB, 201) and a data TLB (DTLDB, 205), and a CPU core 202. The level 1 cache 102 is shown as including an instruction cache 200 and a data cache 206 interposed between the CPU 101 and the level 2 (and possibly higher level) cache 207. FIG2 also shows a high capacity memory 208 connected to the cache hierarchy. However, the computer system in FIG2 is shown as a uniprocessor (i.e., single processor) system.

[0008] When CPU 101 requests data that is present in the cache (referred to as a cache hit), the request can be serviced much faster than an access to data that is not present in the cache (referred to as a cache miss). Typically, an application running on CPU 101 that experiences fewer cache misses will execute faster and consume less energy than the same application that experiences more cache misses (assuming the two versions of the application have similar properties). Therefore, considerable effort has been invested in techniques for avoiding cache misses, and implementations have been designed that can make cache hits and cache misses efficient in terms of access latency and the energy consumed by these memory transactions.

[0009] In order to understand how to develop solutions to this cache hit / miss problem, some understanding of cache organization and terminology will be useful. Typically, data is installed into the cache in fixed blocks that are larger than the word size of the processor, called cache lines. Common cache line sizes today are, for example, 32, 64, and 128 bytes, but as will be appreciated by those skilled in the art, there are larger and smaller cache line sizes for various cache implementations. For some cache implementations, the cache line size may also be variable.

[0010] A common way to organize data placement in memory 208 is in a way that each data word is statically mapped to reside in a specific cache line. Each cache typically has an index function that identifies the portion of the cache where each cache line can reside, which is called a group. A group can contain space for holding one or more cache lines at the same time. The number of cache lines that a group can hold is called its associativity. Typically, the associativity of all groups in a cache is the same. Such caches are typically called set associative caches. Associativity can also vary between groups. Each space in a group that can hold a cache line is called a way.

[0011] In order to determine the identity of each cache line stored in each group, the cache lines in the cache each have some identifier associated with them. A common example of such an identifier is an address tag. When looking up a particular cache line in a cache, its address can be used to determine the group of cache in which it may reside. The address tag of the cache line of the corresponding group is compared with the tag portion of the address used to identify the cache line (see, for example, the tags and ATAGs depicted in Figure 3 and described below) to determine whether the desired cache line resides in the cache, and if so, in which way it resides, that is, in which space in the group that can hold the cache line. Typically, the size of such ADDR address tags is quite large and can be in the range of 30-40 bits, which is 6-10% of the size of a typical cache line.

[0012] Typically, each cache has a built-in strategy to determine which cache lines to keep in a set and which cache lines to evict (also called replaced) to make room for new cache lines to be introduced into the set, which is called a replacement policy. The cache lines that are replaced are called victim cache lines or replaced cache lines. Popular replacement policies used in conjunction with cache memories include (but are not limited to) least recently used (LRU), pseudo-LRU, and random replacement policies.

[0013] An inclusive cache hierarchy requires that a copy of a data block (e.g., a cache line) present in one cache level, such as the L1 cache, also be present in higher cache levels (here, higher refers to cache levels with a number higher than 1), such as in the L2 and L3 caches. An exclusive cache hierarchy only has one copy of a data block (e.g., a cache line) present in the entire cache hierarchy, while a non-inclusive hierarchy may have a mix of the two strategies. In both exclusive and non-inclusive cache hierarchies, a cache line is typically installed in the next higher cache level upon eviction from a given cache level.

[0014] With this background of caches and cache lines in mind, the discussion now continues to illustrate a conventional technique for identifying a specific cache location within a cache hierarchy similar to that shown in FIGS. 1 and 2 . FIG. 3 is a block diagram for explaining a conventional implementation of a two-level cache hierarchy including a set associative cache and a set associative data translation lookaside buffer (TLB). FIG. 3 shows an example of the organization of a computer system node including a CPU 301, a DTLB 303, an L1 cache 307, and an L2 cache 311. CPU 301 generates a memory request including a virtual address 302 (VADDR), which is used to perform an associative lookup in DTLB 303. In this example, virtual address 302 is divided into three parts: P_OFFSET (page offset, e.g., consisting of low-order bits), a tag, and an index. The index portion of virtual address 302 is used to identify a group within DTLB 303 where an address translation can be stored.

[0015] The DTLB 303 used in this example is shown to have a bidirectional associative organization, which shows two entries of the identified group. Each entry consists of an address tag (ATAG) 304 and a physical page frame (PPF) 305. The tag portion of the virtual address 302 is compared with the ATAG 304 of each entry of the identified group. Logic 318 determines whether there is a match for any entry, and if so, controls MUX 306 to select the corresponding PPF 305. The physical address PADDR 316 is composed by concatenating the PPF 305 selected by MUX 306 with the P_OFFSET portion of the virtual address 302. Alternatively, if none of the entries of the identified group matches the tag portion of the virtual address 302, a TLB fill operation is performed and the required translation entries are introduced into the DTLB 303.

[0016] PADDR 316 is used to perform a lookup in L1 cache 307. More specifically, the index portion of PADDR 316 is used to identify a group that can store a cache line containing the requested data. (It should be noted that the L1 index may contain different bits than the DTLB index). The depicted L1 cache 307 has a bidirectional associative organization with two entries in the identified group. Each entry consists of an address tag (ATAG) 308 and data 309 of the corresponding cache line. The tag portion of PADDR 316 is compared with the ATAG of each entry of the identified group. Logic 319 determines whether there is a match for any entry and controls MUX 310 to select the corresponding data. If none of the entries match (indicated by L1 miss 317), a lookup is required in L2 cache 311. Although the division of PADDR 316 into index and tag portions for L2 cache lookups may be different from the divisions made for L1 cache lookups, the remaining steps for L2 cache lookups are generally similar to the steps performed for lookups in L1 caches. If a miss in the L2 cache is determined, a new lookup in a higher level cache or access to memory may be required. It may be noted that if the index portion of PADDR 316 used by the L1 cache consists entirely of P_OFFSET bits, accesses to the L1 cache 307 may begin before the PPF information from MUX 306 is available. This is often referred to as a virtually indexed physically tagged (VIPT) cache.

[0017] Those skilled in the art will appreciate that multiple "nodes", each having a memory hierarchy similar to the memory hierarchy shown in FIG3, can be connected together to form a consistent multiprocessor system. Another example of a multiprocessor is shown in FIG1, where each CPU has its own private L1 cache. This further complicates the task of locating where the requested data resides, as it is no longer sufficient to always search for the data in the next higher cache level. A mechanism is needed to search the caches of other nodes and to keep multiple copies of datums stored in different nodes consistent.

[0018] As additional background information, FIG4 is a block diagram illustrating an example implementation of a tag-less cache. Such a cache relies on location information LI (sometimes referred to as a cache line pointer CP) corresponding to a requested cache line of a matching cache table entry CTE (sometimes referred to as a region location) to indicate in which cache the requested cache line resides and at which location within that cache. This will cause the computer system to perform a direct cache lookup in the appropriate cache. The example implementation of a tag-less cache shown in FIG4 includes a two-level cache hierarchy and a two-level cache location buffer (CLB) hierarchy, wherein the first level is accessed virtually and the second level is accessed physically.

[0019] For example, in the system shown in FIG. 4 (which may be a node in a multiprocessor system), location information may distinguish between an L1 cache and an L2 cache. It may also distinguish between other caches (not shown in the figure) present in the rest of the multiprocessor system. FIG. 4 shows a sparsely tagged node that may be connected to other nodes in a multiprocessor system having a set associative cache and a CPU (which may include one or more traditional caches, described here as L0) in a two-level cache hierarchy, where a CPU 401 generates an address (ADDR) 402. FIG. 4 also shows a set associative CLB in a two-level CLB (sometimes also referred to as a metadata cache-MD cache) hierarchy, where a first-level CLB CLB1 410 and a second-level CLB CLB2 420 are indexed by ADDR. As used in the present disclosure, the term "CLB1" may refer to a first-level CLB, and the term "CLB2" may refer to a second-level CLB. Each entry in CLB1 410 includes at least an address tag (AT) 411 and a cache location table (CLT) 412. It may store additional information, such as region information (RI) 413. CLT 412 stores location information (LI) of cache lines of corresponding regions (also referred to as micropages). FIG. 4 shows four LIs per region as an example. Empirical studies by the inventors have shown that 8 to 16 LIs per region (i.e., 8 to 16 data units (cache lines) per region) are cost-effective and efficient. The location information encodes the location of the corresponding cache line that can be found in a multiprocessor system. For example, the location information may include an identification of a cache in which the data unit can be found. The location information may also include a location in which the data unit can be found within the cache. Alternatively, the location information may include an identification of a node in which the data unit can be found, or some symbols that provide information about its location, such as the symbol "MEM" indicating that the data unit can be found in memory. In at least some cases, the symbol "unknown" may indicate that the location of the corresponding data unit is not recorded in the CLT corresponding to the region.

[0020] MUX 416 selects the CLT having AT 411 that matches the tag portion of ADDR 402, and MUX 415 selects the LI 414 corresponding to the requested cache line based on the L-OFFSET portion of ADDR 402. If the cache tag stored in the selected LI corresponds to L2 cache 440, an address 417 for accessing the requested data unit in L2 cache 440 is formed using the index portion of address 402 and a portion of location information 414. In the example of a set associative L2 cache 440, this portion contains information corresponding to the associated way in which the requested data unit is stored. If the cache tag stored in the selected LI corresponds to L1 cache 430, an address 418 for accessing the requested data unit in L1 cache 430 is formed in a similar manner.

[0021] For a cache hierarchy consisting of set-associative caches with the same associativity, the number of bits in each LI depends on the number of ways and the number of caches of the cache hierarchy covered by the CLB. One LI value may be reserved for invalid mode ("MEM"). In this embodiment, the number of LI bits is equal to the base 2 logarithm of the number of ways plus the base 2 logarithm of the number of cache levels covered by the CLB plus 1 (i.e., log2(way)+log2(level)+1). If the number of ways of different cache levels varies, or if caches other than set-associative caches are used, those skilled in the art will appreciate that other LI representations are possible. Typically, the size of the LI is much smaller than the size of a typical address tag. A 2-level cache hierarchy with 16-way associative caches at each level may be encoded using 6 LI bits.

[0022] In the example shown in FIG. 4 , each entry in L1 cache 430 and L2 cache 440 has a back pointer (BP) (432 and 442, respectively) associated with its cache line (DATA) (431 and 441, respectively). In this example, the BP pointers point to their respective associated CTEs in CLB2 420. Each CTE in CLB2 420 contains an address tag (AT) 421, a CLT 422, and a CLB1 pointer (CIP) 423. If a CLB2 entry has a corresponding CLT residing on CLB1 410, its CIP will point to the entry. In this case, CLB1 410 will contain the latest information for the region. In this case, the CLE in CLB1 is referred to as an active CLB entry, while the CLB entry for the region in CLB2 420 contains a passive entry. If CLB1 410 contains an active entry for a region, CLB2 420 will be required to contain a passive entry for the region.

[0023] When a matching CTE is not found in CLB1 410, the corresponding CTE may be looked up in CLB2 420 and copied to CLB1, and the old entry in CLB1 may be copied to CLB2 420, which is referred to as overflow and fill or simply represented as overflow / fill (overflow and fill in FIG. 4 ). For example, overflow is also performed when a conventional inclusive cache evicts a data unit to the next level to make room for a new data unit, which may be introduced (filled) from the next cache level. Similar overflow / fill activities will be performed between different CLB levels, where CLB entries are moved between CLB levels as the CLB levels form an inclusive hierarchy. The directory DIR may be located at the root of the CLB hierarchy and use the highest level CLB for overflow / fill.

[0024] Access to the requested data unit may be initiated in parallel with the overflow / fill activity.

[0025] The contents of the CLBs of the multi-level CLB implementation can be consistent with the locations of the data units of the multi-level cache system they manage. Data units moved in the cache hierarchy (including but not limited to movements caused by requests for data units from the CPU, eviction of data units, prefetch activities, and consistency activities) result in updates to their corresponding location information in one or more CLBs. For example, in Figure 4, eviction of data unit 441 from cache 440 may include the following steps: following its associated BP 442 pointer to find its corresponding CTE (which is in CLB2 420 in this example) and updating its corresponding location information to point to the new location of the data unit (e.g., storing the MEM symbol). And, if the CIP pointer of the CLE corresponding to CLB2 is valid, follow the CIP to find its corresponding CTE in CLB1 410 and update its location information associated with the cache line. If there is a valid CIP pointer, the entry in CLB2 will not be updated. For example, the CLT can be updated so that only the active CLT is updated.

[0026] As can be understood from the foregoing description, the use of the above-mentioned sparsely tagged cache system (i.e., a cache system in which data units stored in the cache do not have address tags associated therewith) will result in many different types of transactions that will occur when the CPU 401 requests various cache lines located in different storage devices. The node depicted in Figure 4 can be a subsystem (or node) of a larger multiprocessor system composed of multiple such cache nodes. Keeping the data in the caches of multiple nodes consistent requires a cache consistency protocol, such as implementing snooping or directory-based consistency. The consistency protocol sends consistency requests to the nodes depicted in Figure 4 (external requests). These requests are usually first directed to CLB2 420, which can determine that the cache system does not have the requested cache line (CLB2 misses or CLB2 hits an entry with an inactive CIP and the location information of the requested cache line maintains a numerical memory mode). If so, no further action is required regarding the data caches L1 and L2 (called consistency filtering), but the corresponding LI in the active CLT still needs to be updated to track the new location associated with the data unit. Otherwise, the CLB2 lookup can provide the requested location information (CLB2 hits and the location information of the requested cache line maintains the location where the cache line is stored), or it can determine that CLB1 410 stores the associated location information (CLB2 hits and a valid CIP). In the latter case, a lookup is required in CLB1 410 to determine the location of the requested cache line or the cache line does not reside in the cache subsystem. (The corresponding location information in CLB1 contains the memory mode). Depending on the nature of the consistency request, such as an invalidation request, a read request, or an exclusive read request, the consistency protocol will perform some operations on the requested data unit and may change its state. It may also be necessary to update the corresponding LI in the active CLT to track the new location associated with the data unit.

[0027] Although the node shown in Figure 4 consists of two cache levels, those skilled in the art will appreciate that other numbers of levels may be used to assemble the node, and that the node may contain more than one CPU. In addition, the number of cache levels in a node and the number of CLB levels do not need to be the same.

[0028] 5 is a block diagram showing a portion of a computer system including two CPUs connected to a two-level cache hierarchy and a two-level cache location buffer (CLB) hierarchy. For example, the computer system in FIG. 5 includes two CPU nodes (580 and 590), each having a CLB (CLB1A 503 and CLB1B 513) and a dedicated cache L1 cache (504 and 514) in their own first-level cache hierarchy. The system also includes a globally shared L2 cache 523 (sometimes referred to as a last-level cache (LLC)) that is shared between the two CPUs 501, 511.

[0029] The lookup in CLB1 (513 or 503) selects a single LI based on the address generated by their respective CPU (501, 511), for example using techniques similar to CLB1 410. As indicated by the three arrows starting from the two CLT entries in CLB1A 503 and CLB1B 513 shown, the selected LI may identify that the location is in the corresponding L1 cache (504 and 514, respectively), in the L2 cache 523, or in another node (represented by 570 and 571, respectively). In this example, CLB1A 503 identifies that its access data is 505 in the shared L2 cache 523, while CLB1A 503 identifies that its access data is 505 in its L1 514 (shown by the solid arrows).

[0030] FIG. 6 is a block diagram showing a portion of a computer system including a tagged cache hierarchy with a single monolithic last level cache. Referring to FIG. 6 , FIG. 6 shows a general description of a tagged multiprocessor memory system. The example includes N nodes ranging from node 1 601 to node N 699. Each node has an X-level CLB and a Y-level dedicated cache (i.e., a cache dedicated to the node). The nodes are connected to each other through an on-chip network (NoC) 650 circuit. The NoC 650 also connects the node to a directory (DIR) 660, a global last level cache (LLC) 670, and a memory 680. The DIR 660 is organized similarly to the CLB, and the DIR 660 has entries consisting of at least an address tag (AT) 661 and a cache location table (CLT) 662. The entry may also contain additional information, such as region information (RI) 663, which will be described in more detail below. The highest level CLBs in a node (CLB-X 630, CLB-X 693) overflow / fill to / from the DIR. The DIR also plays a central role in the coherence protocol that keeps the contents of the caches and CLBs consistent and coherent.

[0031] The CLB and DIR can be viewed as forming an inclusive "cache hierarchy" that caches metadata with information about the contents of the data cache hierarchy. The data hierarchy containing L-1 to LY and LLC can be viewed as a separate cache hierarchy to which the inclusive attribute is not applied. For example, it can be non-inclusive, inclusive, or exclusive.

[0032] In the example shown in FIG. 6 , each node has a CPU (CPU-1 600, CPU-1 696), which may contain zero, one or more traditional tag-based caches, which are depicted as LO-D and LO-1. A memory request that cannot be satisfied by any traditional LO cache will generate a lookup in the node's CLB-1 (e.g., 610) to search for the corresponding CLB entry CLT, and a scheme similar to CLB-1 410 in FIG. 4 may be used. If a corresponding entry is found in CLB-1, the location information (LI) corresponding to the requested data unit may be located in its CLT field (612). The LI identifies the location where the requested data unit can be found. The LI in the CLB 610 residing in node 1 601 can identify any of the node's own caches (L-1 620 to LY 640), LLC (670), memory 680, or other nodes (node ​​2 690 to node N 699) as the location of the data unit it is tracking. The LI may also identify the location of the data unit in the identified cache. The LI may also indicate whether the data unit resides in any of the conventional caches L0-D or L0-I of the CPU 600 connected to the node.

[0033] If a cache location (or memory) is identified as where the data can be found, the request can be satisfied by directly reading the cache without consulting the directory (DIR) 660. If a node is identified as where the requested data can be found, the request is sent to the CLB-X of that node and satisfied similarly to the external request discussed in FIG. 4. However, there is still no need to consult the directory in order to find the data. This is different from most traditional directory-based consistency schemes, in which the directory is consulted and updated for accesses external to the node.

[0034] 6 shows one CPU in each node, those skilled in the art will recognize that a node may contain any number (including zero) of CPUs, GPUs, accelerators, or other devices that can access memory, such as I / O devices. In addition, the configuration and size of CLBs and caches may vary greatly between nodes.

[0035] There can be a strict hierarchical search level by level in an inclusive CLB / DIR hierarchy. If the location information is not found at level CLB-i, a search is performed at the next level CLB-(i+1). If the location information is not found in the highest level (CLB-X) of the node, a search is performed in the DIR. If the location information is found in the CLB level or DIR, a read request can be sent to the data location identified by the corresponding location information of the level, and a new CLE entry corresponding to the requested area is created in CLB-1. The CLB / DIR hierarchy can be inclusive. This means that if there is an available CLB entry at level CLB-L, an entry must be installed at level CLB-(L+1). The CLB entry closest to the CPU is in an active state. There can be forced inclusion between cache level K (and lower caches, i.e., higher caches in Figure 6) and a certain CLB level C (and all higher CLB levels, i.e., lower positions in Figure 6). For example, in order for data to be available in any cache L-1 620 to LY 640, there must be a corresponding entry in CLB-X 630. If the entry in CLB-X 630 is evicted, all data of the corresponding region should be evicted from caches L-1 620 to LY 640. This is called forced eviction. In addition, all CLB entries under the same node to CLB-1 610 need to be evicted.

[0036] It should be noted that there is no inclusion requirement between cache levels within a node (e.g., cache L-1 620 to LY 640) or between LLC 670 and caches in a node (e.g., cache L-1 620 to LY 640). For example, valid data corresponding to a particular address may be present in L1 cache 620, but not in cache LY 640 or LLC cache 670. This enables cache bypass optimizations, where, for example, streaming data only needs to be installed in L1 cache 620 (actually, only in L0 if it is present), and not in other levels. However, corresponding CLB entries (typically 50 times smaller than the corresponding data area) need to be installed in all levels.

[0037] The directory (DIR) 660 contains CLB-like information: address tags (AT) 661, cache location table (CLT) 662, and region information (RI) 663. Although these fields have the same names as the fields of the CLB (e.g., CLB-X 630), the contents of these fields may be different from the corresponding CLB fields. The RI field 663 of the DIR 660 may contain N so-called presence bits (PB) that indicate which nodes are tracking the region, where N corresponds to the number of nodes in the system. If bit K in the PB is set, it means that there is a corresponding entry in CLB-X of node K. This further means that there may be cached data in any of the cache levels L-1 to LY of node K, and there may also be a corresponding entry in CLB-1 in node K, which will enable the CPU in node K to access any cache line of the corresponding region. Although an N-bit implementation involving PB information is described, those skilled in the art will recognize that many scalable techniques for directory implementation (including but not limited to coarse-grained, limited pointers, and linked lists) can be used to achieve similar functionality.

[0038] The PB bit can be used to classify regions. If one of the PB bits of the corresponding entry in the directory 660 is set, the region is classified as a dedicated region (PR). Empirical studies have shown that on average about 80% of all accessed regions are PR regions of widely selected research benchmarks. Regional classification PR means that the data of the region can only exist in one node whose corresponding PB bit is set, and it is also guaranteed that no other node can access the data from the region at this point in time. Node 1 601, whose PB bit is the only set bit in the DIR, can be notified that the corresponding region is a dedicated region (PR), and the regional classification can be recorded in its corresponding region information (RI) in its CLB (e.g., in CLB-1 610 to CLB-X 630). PR regions can be accessed efficiently in many ways. For example, global consistency is not required to add write permissions for a node to a data unit present in the node, while the node currently only has read permissions for the data unit (to upgrade the data unit from state S to state E), because only one node may have cached a copy of the data of the data unit, and no other node can access any data unit of the region. In addition, the movement of data units of the PR region can be efficiently implemented because data can be moved up and down the entire cache hierarchy (e.g., performing an eviction from LX to LLC or moving data from LLC to L-1) without notifying any structure outside the node. The movement also needs to be recorded in the CLB (610 to 630) local to the node. This means that the CLT information of the PR region stored in the CLB (610 to 630) of the node can be different from (e.g., it is updated) the CLT information of the region stored in the DIR 660.

[0039] When the second node (e.g., 690) accesses the PR region (empirical studies have shown that this is a relatively rare event), it will miss in all of its CLBs 691 to 693 and will send a request to DIR 660 to obtain the appropriate location information LI required to access the data and allow its own CLB entries to be created in CLBs 691 to 693. Since this request is for the PR region, DIR 660 may not have the latest information and it needs to obtain the latest location information from Node 1 601, ensure that the CLB of Node 1 601 no longer marks the region as PR, update its own CLT information for the region, set the PB bit corresponding to Node 2 690 and send the information of the appropriate CLB for the region to Node 2 690. Node 2 690 can now create its own local CLB entry managed with the region. Before sending the latest location information to DIR 660, it may be necessary that Node 1 601 must complete all of its ongoing direct data memory requests for the region.

[0040] If another node (e.g., node N 699) accesses the region, it will also miss in all of its CLBs and will also send a request to DIR 660, which now has the latest information about the region and can reply to node N 699 with the appropriate information and will also set the PB bit for the region for the requesting node (i.e., node N 699).

[0041] A region with more than one PB bit set is classified as a shared region (SR). This means that multiple nodes have CLBs that are tracking the location information of the region. It also means that nodes with corresponding PB bits set can store data units of the region in any of their caches (e.g., 620 to 640). If the region is classified as SR, requests from the CPU (e.g., 600) to access data units that cannot be satisfied locally within the node (e.g., by caches L-1 620 to LY 640) may need to initiate a global coherence transaction.

[0042] Globally consistent read transactions to SR or PR regions (reads that cannot be satisfied by local caches (e.g., caches L-1 620 to LY 640)) can utilize location information retrieved from its local CLB (e.g., CLB-1 610 to CLB-X 630) to directly access the data without involving the DIR 660 or communicating with any node outside of that node that can be identified by the location information. This is referred to herein as a direct-to-master access. Empirical studies have shown that 75% of all global consistency transactions for SR regions are direct-to-master read transaction accesses. Therefore, if 20% of the global transactions initiated by the CPU are for SR pages, and 75% do not require access to the DIR, then when using at least some of the cache structures and techniques mentioned above, 95% of the global consistency transactions do not require access to the DIR, while for traditional directory-based protocols, all global consistency transactions require access to the DIR.

[0043] Since an SR region has several nodes that track the location of its data units, the movement of their data units needs to be reflected in all nodes that track the region (i.e., those nodes that have active CLB entries for the region) and the location information of the moved data units updated in these nodes. The location information of the CLBs of different nodes that track the data units should be updated in a consistent manner so that the CLBs agree on where the data is located (called its primary location). It may also be highly likely or optionally guaranteed that the data unit location accessed based on the location information retrieved from the CLB contains the correct data (called determinism).

[0044] A common reason for such data unit movement is a global coherent write, i.e., a requesting node that does not currently have write permission for a data unit requests write permission through a global coherent request (e.g., an invalidate request or an exclusive read request). After completing the request, the data unit will reside only in the requesting node.

[0045] A global consistency write may be sent by a requesting node (e.g., 601) to a directory 660, which (locates the corresponding directory entry) retrieves the corresponding PB bit for the region and forwards the request to all nodes (except the requesting node) with the corresponding PB bit set, which are referred to as slave nodes (e.g., nodes 690 and 699). The slave node sends an ACK message when it ensures that any future request for the data unit originating from the slave node will be directed to the requesting node. This may be achieved, for example, by changing the location information of the data unit in their CLB to point to the requesting node (601), which will become the new master node. The ACK message may be sent to the DIR 660 or directly to the requesting node 601, in which case the DIR 660 aggregates the ACK message and sends an ACK to the requesting node once all ACKs are received. Once the requesting node knows that all ACKs have been received, it has obtained exclusive write permission for the cache line and completes the request. After completing the request, a completion message may be sent to the DIR 660.

[0046] Another common reason for data movement is eviction (also called replacement). Node-local evictions (e.g., eviction from L-1 620 to LY 640) are handled locally, tracked by their local CLB entries, and are not visible outside the node. However, the global eviction of a master data unit (e.g., from location 641 in LY 640 to a new location 671 in LLC 670) must be reflected by all nodes tracking the region (i.e., all nodes with CLB entries for the region). Global eviction can be achieved by first copying the value of the data unit stored in its old location (641) to the new location (671) while keeping the data stored in the old location (641) valid. Then, a global consistency eviction request with information about the new location (671) is sent from the requesting node (e.g., 601) to the DIR (660), which forwards the request to the slave nodes (e.g., 690 and 699). Once the slave nodes update their corresponding location information to the new location (671), they send ACK messages. Once the requesting node knows that all ACKs have been sent, it obtains permission to evict the data unit and can reclaim the old position and complete the request. Once the request is completed, a completion message can be sent to the DIR 660.

[0047] The slave node may not send an ACK message until some outstanding requests for the requested cache line (eg, all requests directly to the master) have completed.

[0048] The directory 660 may implement a blocking mechanism that ensures that there is at most one outstanding global request of a particular type per data unit. Examples of such request types may be global consistency writes and global consistency eviction requests. The blocking of a cache line ends after the request is completed, or as otherwise specified by the consistency protocol. The blocking mechanism may be exact, such as implemented by one lock per data unit in the directory, or may be highly approximate, where addresses hash to a limited pool of locks, and a block on a data unit will block access to all other data units that hash to the same lock.

[0049] Blocking can be done at region granularity instead of data unit granularity, and some CLB / directory overflow / fill requests also need to be blocked until their updates have completed. This ensures that no globally consistent write requests are processed while nodes and directories are overflowing / filling CLB information.

[0050] Another useful region classification is a region where no PB bit associated with the region is set in DIR 660. This means that the region data units will not exist in any of the node's caches L-1 to LY, and no node can currently access its data units. This is called a non-tracking region (UR). The data in the UR region can still be cached in the LLC. The data units in the UR region can be evicted from the LLC 670 without any global consistency request. Regions that do not have corresponding entries in DIR 660 are classified as memory regions (MR). The data units in the MR region can neither be cached in the node nor in the LLC. Replacing the CLT entry from DIR 660 means that all data units in the region should be forcefully evicted from the LLC.

[0051] The cache system of FIG. 6 may be a tag-less cache system, i.e., a cache system in which data units stored in a cache (e.g., caches L-1 to LY and LLC of a node) do not have address tags associated therewith. Instead, location information having address tags associated therewith will identify the location where the data unit is stored. The conventional caches (LO-1 and LO-D) included in FIG. 6 may still have address tags associated therewith for data units of the cache.

[0052] To summarize the above discussion regarding Figures 3 to 6, those skilled in the art will appreciate that a cache hierarchy can be implemented using a tagged-less cache, which can provide a more efficient way to represent a cache. In a tagged-less cache, data units (cache lines) do not have address tags associated with them. Instead, a back pointer points to a CLB entry, which tracks the cache line by "pointing" to its location using a location information pointer. However, if a cache line needs to be quickly deleted from the cache, the tagged-less cache does not provide a simple way to place the cache line into a traditional buffer (such as a victim buffer). Typically, cache lines in a traditional victim buffer need to be searchable, so additional address tags are required.

[0053] Therefore, it is desirable to provide systems and methods that provide efficient buffer functionality in a tagged-less cache hierarchy. Summary of the invention

[0054] According to at least some example embodiments conceived in the present invention, a data management method for a computer system, the computer system comprising at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, the method comprising: selecting a victim cache line to be evicted from the first cache; finding a victim buffer position corresponding to the victim cache line from the VB; copying data of the victim cache line to a data field at the VB position; copying a back pointer (BP) associated with the victim cache line to a BP field at the VB position; and reclaiming the victim space of the first cache using the VB.

[0055] According to at least some example embodiments conceived in the present invention, a multiprocessor system includes: a memory; a plurality of nodes, each of the plurality of nodes including at least one processor, a plurality of caches and a plurality of cache location buffers (CLBs); and one or more victim buffers (VBs), wherein a processor of an Nth node among the plurality of nodes is configured to: find, from a VB among the one or more VBs, a victim buffer location corresponding to a victim cache line evicted from a first cache of the plurality of caches of the Nth node; copy data of the victim cache line and a back pointer associated with the victim cache line to a field at the VB location, and reclaim the victim space of the first cache using the VB.

[0056] According to at least some example embodiments conceived in the present invention, a non-transitory computer-readable storage medium including computer-executable instructions, when the computer-executable instructions are executed by at least one processor, causes the at least one processor to perform the following operations: select a victim cache line to be evicted from a first cache assigned to the at least one processor; find a victim buffer (VB) position corresponding to the victim cache line from a victim buffer (VB) assigned to the at least one processor; copy data of the victim cache line to a data field of the VB position; copy a back pointer (BP) associated with the victim cache line to a BP field of the VB position; reclaim the victim space of the first cache using the VB; and control a write-back operation for a second cache assigned to the at least one processor, or control a write-back operation for a memory assigned to the at least one processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and other features and advantages of the exemplary embodiments of the present invention will become more apparent by describing in detail the exemplary embodiments of the present invention with reference to the accompanying drawings. The accompanying drawings are intended to describe the exemplary embodiments of the present invention and should not be interpreted as limiting the intended scope of the claims. Unless explicitly stated, the accompanying drawings should not be considered to be drawn to scale.

[0058] FIG1 is a block diagram showing a portion of a computer system;

[0059] FIG2 is a block diagram for explaining an example cache hierarchy of a computer system;

[0060] 3 is a block diagram for explaining a conventional implementation of a two-level cache hierarchy including a set-associative cache and a set-associative data translation lookaside buffer (TLB);

[0061] FIG4 is a block diagram illustrating an example implementation of a sparsely tagged cache;

[0062] 5 is a block diagram illustrating a portion of a computer system including two CPUs connected to a two-level cache hierarchy and a two-level cache location buffer (CLB) hierarchy;

[0063] 6 is a block diagram illustrating a portion of a computer system including a sparsely tagged cache hierarchy having a single monolithic last level cache;

[0064] Figure 7 is a block diagram illustrating a portion of a computer system including a tag-less cache hierarchy having a single monolithic last level cache and a victim buffer according to at least some example embodiments of the inventive concepts; and

[0065] Figure 8 is a block diagram illustrating a portion of a computer system according to at least some example embodiments of the inventive concepts, the computer system including two CPUs connected to a two-level cache hierarchy and a two-level CLB hierarchy, and a victim buffer. DETAILED DESCRIPTION

[0066] According to the tradition in the field of the present invention, the embodiment is described in terms of functional blocks, units and / or modules and shown in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case of blocks, units and / or modules implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. Moreover, without departing from the scope of the present invention, each block, unit and / or module of the embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules.

[0067] Cache lines that reside in the cache may be evicted and may be replaced by other cache lines. Therefore, the evicted cache line may need to be removed from the cache to make room for the new cache line. If the evicted cache line is dirty, the evicted cache line may need to be written back to the next level cache or memory.

[0068] As shown in Figures 4 and 5, one advantage of a sparsely tagged cache is that there is no forced inclusion between cache levels. Cache lines residing in L1 cache 430 or 514 do not need to have space allocated in the next level L2 cache 440 and 523, respectively. A sparsely tagged cache may also not require cache lines to have space allocated in the next level L3 or last level cache (LLC) 670, as shown in Figure 6. Therefore, cache lines evicted from a sparsely tagged L1 cache may need to be written back to memory. In a multiprocessor implementation of a sparsely tagged cache, the evicting of dirty cache lines from the L1 cache to memory may be performed in three steps: first, the cache line is copied to memory; once it can be guaranteed that the copy has been performed globally on the memory, a NewMaster message is sent to other nodes with cache location buffer (CLB) entries for the corresponding region to notify other nodes that the memory is not the new master location of the cache line; finally, the location of the cache line in the L1 cache may be reclaimed. Since memory is relatively slow and often located far away, the time it takes from initiating an L1 cache eviction to completing the L1 cache eviction can be substantial and much longer than the time it takes to obtain a new cache line from the L2 cache. Therefore, it would be advantageous to determine a more efficient way to handle evicted cache lines in order not to delay the progress of execution.

[0069] Computer systems can use victim buffers (VBs) to quickly dispose of victims from L1 caches. VB is a small associative buffer for storing cache lines (and their address tags) to be evicted. Based on certain read requests and external requests from the rest of the system, the address tags of the cache lines in VB need to be searched for matching. In the case of a match, the read request can be satisfied by reading the corresponding cache line. The advantage of VB is that the evicted cache lines can be quickly removed from the L1 cache, and the previous position of the evicted cache line in the L1 cache can be reused by the new cache line within a few cycles. However, in a less-tagged system, not all requests carry the complete address of the cache line they request, which is why it may be difficult or (alternatively) impossible to perform a victim buffer search based on the address in a computer system that implements a less-tagged cache hierarchy. In addition, the less-tagged cache avoids expensive address-based associative searches to provide energy-saving implementations. Therefore, it would be advantageous to develop a new less-tagged buffer solution.

[0070] Figure 7is a block diagram illustrating a portion of a computer system including a tag-less cache hierarchy having a single monolithic last level cache and a victim buffer according to at least some example embodiments of the inventive concepts. Figure 8 is a block diagram illustrating a portion of a computer system according to at least some example embodiments of the inventive concepts, the computer system including two CPUs connected to a two-level cache hierarchy and a two-level CLB hierarchy, and a victim buffer.

[0071] Reference Figure 8 , Figure 8 The computer system in may have a structure similar to that of the computer system of FIG. 4. According to at least some example embodiments, Figure 8 The computer system of FIG. 4 may differ from the computer system of FIG. 4 in that: Figure 8 The computer system of the present invention is extended with a tag-less set-associative victim buffer VB (buffer 860). VB is indexed in a manner similar to the L1 cache and the L2 cache. The index may be formed by a virtual index using virtual ADDR bits 802 (assuming that ADDR is a virtual address), formed as a physical index from ADDR 802 (assuming that ADDR is a physical address), or formed as a physical address based on the use of some of the physical addresses (PA) stored as part of the region information (RI) 813 associated with each region. In addition, according to at least some example embodiments of the present inventive concept, way information for the set-associative VB 860 is generated in a manner similar to the way information for the L1 cache and the L2 cache is generated. The way information for the set-associative VB 860 is stored as part of the location information (LI) and is carried by the level / way information 814. According to at least some example embodiments of the present inventive concept, VB860 looks like another set-associative cache level that can be associated with CLB1. However, the associativity of VB 860 may be different from the associativity of one or both of the L1 cache and the L2 cache. Thus, the format of the LI encoding for entries of VB 860 may be different than the format of entries for one or both of the L1 cache and the L2 cache.

[0072] Therefore, according to at least some example embodiments of the present inventive concepts, Figure 8The computer system shown in can receive a request for a victim cache line. In response to the request for the victim cache line, the computer system can match an address included in the request with a plurality of entries in a CLB associated with at least one of a first cache (e.g., an L1 cache) and a second cache (e.g., an L2 cache). In addition, the computer system can generate level and / or way information based on the matching of the address included in the request; and read data of the requested victim cache line from a VB (e.g., VB 860) using the generated level and / or way information.

[0073] According to at least one example embodiment of the inventive concept, each entry in VB 860 is formed of at least three parts: cache line data DAT, a back pointer BP for identifying a CLB entry storing the LI associated with the VB, and a victim space identifier (VS) storing the LI of a higher-level cache to which the victim cache line should be written, or an address in a memory to which the victim cache line should be written. According to at least some example embodiments of the inventive concept, a special state machine drains the VB of its entry and performs the actual write-back operation.

[0074] According to at least one example embodiment of the inventive concept, VB 860 is used to retain victims (i.e., evicted cache lines) from L1 cache and L2 cache, even though only the L1 cache eviction function is explained below, but its target is a higher level cache (e.g., L3 or LLC) or memory.

[0075] According to at least one example embodiment of the inventive concepts, a cache line is evicted from the L1 cache 830 by the following steps:

[0076] 1) Select a dirty cache line 831 from the L1 cache 830 for eviction.

[0077] 2) Find a free location with way=W in VB 860 in the VB group corresponding to the selected cache line, which is called the VB location.

[0078] 3) DATA 831 is copied to the DATA field at the VB location, and the back pointer (BP) associated with the victim cache line is written to the BP field at the VB location.

[0079] 4) BP 832 is used to find the corresponding area within the CLB of tracking DATA 831 (no address comparison is required to find the area).

[0080] 5) The location information in the region is changed to point to the VB location. For example, the LI in the region is changed to point to the VB location (level = VB, way = W); and the physical address portion (i.e., the portion of the RI that includes the physical address) is read from the RI 813 of the region.

[0081] 6) The victim space in the L1 cache can now be reclaimed.

[0082] 7) In the case of sacrifice to memory, the physical address is written to the VS field of the VB location. Alternatively, for example, in the case of sacrifice to another cache (which may be a higher-level cache, such as an L2 cache, according to at least some example embodiments of the inventive concepts), the LI for the destination (e.g., location information for the L2 cache) is written to the VS field.

[0083] 8) Perform write-back operations. For example, the state machine may start its write-back work and copy the cache line to a memory location or a higher-level cache location (e.g., an L2 cache location); send NewMaster; and change the LI in the CLB to point to memory (i.e., by storing the value "Mem" as the LI value). Find the CLB entry using the BP in the VB associated with the victim cache line.

[0084] 9) When the above write-back operation is completed, the VB position can be released.

[0085] According to at least some example embodiments conceived by the present invention, the above-mentioned write-back operation may include: reading a physical address from the victim space identifier field of the VB position; and copying the data of the victim cache line of the data field to the space corresponding to the physical address in the memory. According to at least some example embodiments conceived by the present invention, the above-mentioned write-back operation may include: finding an entry in the CLB pointed to by the BP of the BP field; and changing the location information of the entry to point to the space in the memory where the write-back operation is performed. According to at least some example embodiments conceived by the present invention, the above-mentioned write-back operation may include: reading the location information from the victim space identifier field of the VB position; and copying the data of the victim cache line of the data field to the entry of the second cache corresponding to the location information.

[0086] VB can be located at the edge of the level 2 cache hierarchy (such as Figure 8 ), may be located between the L1 cache and the L2 cache (not shown), or may be located between the private caches L-1 720 to LY 740 and the shared cache LLC 770 of the multiprocessor node 701 in the multiprocessor system (as shown). Figure 7 In this configuration, the VB buffer can be used to quickly process cache lines that are evicted from the node's local cache, such as in conjunction with Figure 8 As discussed, however, forced eviction from NODE 701 may also be accelerated.

[0087] like Figure 7 As shown in , according to at least some example embodiments of the inventive concepts, a computer system may include a memory; a plurality of nodes (e.g., nodes NODE 1 to NODE N), wherein each of the plurality of nodes includes at least one processor (e.g., CPUs CPU-1 and CPU-2), a plurality of caches (e.g., caches L-1 to LY in nodes NODE 1 to NODE N), and a plurality of cache location buffers (CLBs) (e.g., CLBs CLB-1 to CLB-X in nodes NODE 1 to NODE N). According to at least some example embodiments of the inventive concepts, Figure 7 The computer system shown also includes one or more victim buffers (VB) (e.g., VB BUFF 1 and BUFF 2). In addition, according to at least some example embodiments of the inventive concept, the processor includes: a processor of an Nth node among a plurality of nodes (e.g., nodes NODE 1 to NODE N) (e.g., Figure 7 The CPU (not shown) of NODE N in the Nth node is configured to: find a victim cache line (e.g., VB BUFF 1 and BUFF 2) from a VB in one or more VBs (e.g., VB BUFF 1 and BUFF 2) that is evicted from the first cache of the plurality of caches of the Nth node. Figure 7 The VB position corresponding to the L-1 cache (not shown) of NODE N in the first cache; the data of the victim cache line and the BP associated with the victim cache line are copied to the field of the VB position; and the victim space of the first cache is reclaimed using the VB.

[0088] According to at least some example embodiments of the present invention, the processor of the Nth node may also be configured to: find an area of ​​a cache location buffer (CLB) in the Nth node for tracking data of a victim cache line using a back pointer (BP); and change the location information in the area to point to the VB position. According to at least some example embodiments of the present invention, the processor of the Nth node may also be configured to: read location information for a second cache from the area information of the area (the second cache is an upper level cache of the first cache in the Nth cache); write the location information for the second cache in a field at the VB position; and control a write-back operation for the second cache using the VB.

[0089] According to at least some example embodiments of the present inventive concept, the processor of the Nth node may also be configured to: in response to receiving a request for a victim cache line, match the address included in the request with multiple entries of multiple CLBs respectively; generate level and / or way information based on the matching of the address included in the request; and read data of the victim cache line using the generated level and / or way information.

[0090] According to at least some example embodiments of the present inventive concepts, a plurality of nodes (e.g., nodes NODE 1 to NODE N) share one or more VBs (e.g., VB BUFF 1 and BUFF 2). Alternatively, according to at least some example embodiments of the present inventive concepts, each of the plurality of nodes (e.g., nodes NODE 1 to NODE N) includes its own VB.

[0091] 6 , according to at least some example embodiments of the inventive concepts, if an entry in CLB-X 630 is evicted, all data of the corresponding region should be evicted from caches L-1 620 to LY 640. In addition, all CLB entries under the same node to CLB-1 610 also need to be evicted. This is called forced eviction.

[0092] Nonetheless, according to at least some example embodiments of the present inventive concept, the replacement algorithm for CLB-X should make forced evictions quite rare, with the worst-case forced eviction potentially requiring the eviction of up to 16 dirty cache lines. During a forced eviction, some cache lines of the evicted region may already reside in the VB and may already be on their way to being evicted. If forced evictions are not handled carefully, forced evictions may take a long time and may also compromise the correctness of the system by losing track of cache lines as they are being evicted.

[0093] Reference Figure 7 According to at least one example embodiment of the inventive concept, when forcing eviction, the above Figure 8 The dirty cache lines in the node 701 region are quickly transferred to VB 771 by following the steps outlined in the VB eviction process of FIG. 7. The evicted region is then forced to leave to free up space in CLB-X for another region. During this step, any LI in the region still pointing to the VB 771 location will change the corresponding location LI in the corresponding CLT 762 in the DIR and any corresponding CLB locations in Node 2 790 to Node N 799 to also point to that VB location before the evicted region can complete its eviction.

[0094] It should be noted that a cache line residing in the less-tagged cache hierarchy can be found by using the following manner: read requests and external requests are made by using the normal manner of locating cache lines in the less-tagged cache, while the cache line residing in the less-tagged VB is located in the VB: the LI is found through a normal CLB lookup, and then the LI is followed to access the cache line from the identified location.

[0095] Although, for clarity, much of the description herein generally describes techniques for locating a cache line and returning it to a requesting CPU, it will be apparent to those skilled in the art that there are various methods by which a requested word contained within a cache line may be selected and returned to the CPU.

[0096] For clarity, most of the descriptions herein describing the processing of data in a cache hierarchy describe an exclusive cache hierarchy. Those skilled in the art will appreciate that one or more of the example embodiments may be extended to also cover inclusive and non-exclusive memory hierarchies.

[0097] Although one or more of the example embodiments of the inventive concepts described above may be related to single-processor systems and multi-processor systems, such as the systems shown and described above with respect to FIG. 1 and FIG. 2 , respectively, one or more of the example embodiments of the inventive concepts are primarily shown in conjunction with single-processor systems. However, those skilled in the art will appreciate that one or more of the example embodiments of the inventive concepts shown in conjunction with single-processor systems are not limited to such implementations. For example, although for simplicity, Figure 8 shows a single CPU, but Figure 8 The portion of the computer system shown in FIG. 1 may be a portion of a multi-processor system according to at least some example embodiments of the inventive concepts.

[0098] Although described above in the context of certain example computer architectures, caches exist in Figure 7 and Figure 8The example computer system shown in and many other settings outside, and those skilled in the art will appreciate that at least some of the example embodiments of the above-described inventive concept in the context of a computer system may also be applied to such other contexts. An example of such use is a virtual memory system that caches data from a slow, high-capacity memory (e.g., a disk or FLASH memory) into a faster and smaller high-capacity memory that can be implemented using dynamic RAM. Other examples of caching in a computer system include (but are not limited to) a disk cache, a web cache, and a name cache. The organization and caching mechanism of such a cache may be different from the cache discussed above, for example, there are variations in the size of the group, the implementation of the group, and the associativity. Regardless of the implementation of the caching mechanism itself, at least some of the example embodiments of the present invention concept are equally applicable to implementing various caching schemes.

[0099] The methods or flow charts provided in the present application may be implemented in a computer program, software or firmware clearly embodied in a computer-readable storage medium for execution by a general-purpose computer or processor.

[0100] Thus having described the exemplary embodiments of the inventive concept, it will be apparent that the exemplary embodiments of the inventive concept may be modified in a variety of ways. These changes should not be regarded as departing from the intended spirit and scope of the exemplary embodiments of the inventive concept, and all such modifications apparent to those skilled in the art are intended to be included within the scope of the appended claims.

Claims

1. A data management method for a computer system, the computer system comprising at least one processor and at least a first cache, a second cache, a victim buffer, and a memory allocated to the at least one processor, the method comprising: selecting a victim cache line to be evicted from said first cache; Finding a victim buffer location corresponding to the victim cache line from the victim buffer; copying data of the victim cache line to a data field of the victim buffer location; copying a back pointer associated with the victim cache line to a back pointer field of the victim buffer location; as well as reclaiming victim space of the first cache using the victim buffer, Wherein, reclaiming the sacrifice space includes: finding a region in a cache location buffer that uses the back pointer to track data of the victim cache line, and changing the location information in the region to point to the victim buffer location; In case the victim cache line is sacrificed to the memory, reading a physical address for the memory from the region information of the region and writing the physical address into a victim space identifier field of the victim buffer location; and In case the victim cache line sacrifices to the second cache, location information for the second cache is read from the region information of the region and written into a victim space identifier field of the victim buffer location.

2. The data management method according to claim 1, wherein: The second cache is at a higher level than the first cache.

3. The data management method according to claim 1, further comprising: A write-back operation is performed on the memory or the second cache using the victim buffer.

4. The data management method according to claim 3, wherein: Performing a write-back operation on the memory includes: reading a physical address from a victim space identifier field of the victim buffer location; and The data of the victim cache line of the data field is copied to a space in the memory corresponding to the physical address.

5. The data management method according to claim 3, wherein: Performing the write-back operation on the memory includes: finding an entry in the cache location buffer pointed to by the back pointer of the back pointer field; and The location information of the entry is changed to point to a space in the memory where the write-back operation is performed.

6. The data management method according to claim 3, wherein: Performing the write-back operation on the second cache includes: reading position information from a victim space identifier field of the victim buffer location; and The data of the victim cache line of the data field is copied to an entry of the second cache corresponding to the location information.

7. The data management method according to claim 3, further comprising: When the write-back operation is completed, the victim buffer position of the victim buffer is released.

8. The data management method according to claim 1, wherein: The associativity of the victim buffer is different from the associativity of the first cache and the associativity of the second cache.

9. The data management method according to claim 1, further comprising: receiving a request for the victim cache line; responsive to a request for the victim cache line, matching an address included in the request with a plurality of entries in a cache location buffer associated with at least one of the first cache and the second cache; generating level and / or way information based on matching the address included in the request; as well as Data of the victim cache line is read from the victim buffer using the generated level and / or way information.

10. A multiprocessor system comprising: Memory; a plurality of nodes, each of the plurality of nodes comprising at least one processor, a plurality of caches, and a plurality of cache location buffers; as well as one or more sacrificial buffers, in, The processor of the Nth node among the plurality of nodes is configured to: finding, from a victim buffer of the one or more victim buffers, a victim buffer location corresponding to a victim cache line evicted from a first cache of the plurality of caches of the Nth node; copying the victim cache line's data and a back pointer associated with the victim cache line to a field of the victim buffer location; and reclaiming victim space of the first cache using the victim buffer; Wherein, reclaiming the sacrifice space includes: Finding, in the Nth node, a region of the plurality of cache location buffers for tracking data of the victim cache line using the back pointer, and changing the location information in the region to point to the victim buffer location; and and Position information for a second cache is read from the region information of the region, and the position information for the second cache is written into a field of the victim buffer position.

11. The multiprocessor system according to claim 10, wherein: The processor of the Nth node is further configured to: A write-back operation using the victim buffer for the second cache is controlled, wherein the second cache is an upper level cache of the first cache among the caches of the Nth node.

12. The multiprocessor system according to claim 10, wherein: The processor of the Nth node is further configured to: in response to receiving a request for the victim cache line, matching the address included in the request with a plurality of entries of the plurality of cache location buffers respectively; generating level and / or way information based on matching the address included in the request; and Data of the victim cache line is read using the generated level and / or way information.

13. The multiprocessor system according to claim 10, wherein: The plurality of nodes are configured to share at least one victim buffer of the one or more victim buffers.

14. The multiprocessor system according to claim 10, wherein: The one or more victim buffers are a plurality of victim buffers, and the plurality of victim buffers are respectively included in the plurality of nodes.

15. The multiprocessor system according to claim 10, wherein: The encoding format of the location information of the victim buffer is different from the encoding format of the location information of the plurality of caches.

16. A non-transitory computer-readable storage medium comprising computer-executable instructions, which when executed by at least one processor, cause the at least one processor to: selecting a victim cache line to be evicted from a first cache assigned to the at least one processor; finding a victim buffer location corresponding to the victim cache line from a victim buffer assigned to the at least one processor; copying data of the victim cache line to a data field of the victim buffer location; copying a back pointer associated with the victim cache line to a back pointer field of the victim buffer location; reclaiming victim space of the first cache using the victim buffer, and controlling a write-back operation for a second cache memory assigned to the at least one processor, or controlling a write-back operation for a memory assigned to the at least one processor, in, Reclaiming the sacrifice space includes: finding a region in a cache location buffer that uses the back pointer to track data of the victim cache line, and changing the location information in the region to point to the victim buffer location; In the event that the victim cache line is to be written back to the memory, reading a physical address for the memory from the region information for the region and writing the physical address into a victim space identifier field of the victim buffer location; and In the event that the victim cache line is to be written back to the second cache, location information for the second cache is read from the region information of the region and written into a victim space identifier field of the victim buffer location.

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