Display panel and method for manufacturing the same

Abstract

The present application discloses a display panel and a method for manufacturing a display panel. The display panel includes a base layer, and the base layer includes a first region and a second region. At least one inorganic layer disposed on the base layer overlaps with the first region and the second region. The at least one inorganic layer includes a lower groove. A first thin film transistor is disposed on the at least one inorganic layer. The first thin film transistor includes a silicon semiconductor pattern. A second thin film transistor is disposed on the at least one inorganic layer. The second thin film transistor includes an oxide semiconductor pattern. A plurality of insulating layers overlap with the first region and the second region. An upper groove extends from the lower groove. A signal line is electrically connected to the second thin film transistor. An organic layer is disposed in the lower groove and the upper groove. A light emitting element is disposed on the organic layer.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a display panel, and more particularly, to a method of manufacturing a display panel. Background Art

[0002] A display panel may include a plurality of pixels and a driving circuit (e.g., a scan driving circuit or a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels may include a display element and a driving circuit of the pixel, wherein the driving circuit of the pixel may control the display element. The driving circuit of the pixel may include a plurality of thin film transistors that are relatively closely connected to each other.

[0003] Display panels have evolved from flat types to various shapes, such as curved types, rollable types, or foldable types. As the shape of the display panel changes, the panel design may also change. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a display panel having pixels with improved speed and reliability, and the display panel may have improved flexibility.

[0005] Exemplary embodiments of the present invention provide a method of manufacturing a display panel, which reduces the number of masks used in the manufacturing process.

[0006] In an exemplary embodiment of the present invention, the display panel includes a base layer, wherein the base layer includes a first region and a second region extending from the first region. The second region is curved from the first region. At least one inorganic layer overlaps with the first region and the second region. At least one inorganic layer is disposed on the base layer. A lower groove overlapping with the second region is defined in at least one inorganic layer. A first thin film transistor is disposed on at least one inorganic layer. The first thin film transistor includes a silicon semiconductor pattern overlapping with the first region. A second thin film transistor may have a bottom gate structure. The second thin film transistor is disposed on at least one inorganic layer. The second thin film transistor includes an oxide semiconductor pattern overlapping with the first region. A plurality of insulating layers overlap with the first region and the second region. An upper groove extending from the lower groove is defined in the plurality of insulating layers. A signal line is electrically connected to the second thin film transistor. An organic layer overlaps with the first region and the second region. The organic layer is disposed in the lower groove and the upper groove. A light emitting element is disposed on the organic layer, and the light emitting element overlaps with the first region.

[0007] In an exemplary embodiment of the present invention, a portion of the signal line overlapping with the second region may be disposed on the organic layer.

[0008] In an exemplary embodiment of the present invention, the display panel may include a connection electrode, wherein the connection electrode is disposed on the organic layer and is connected to an output electrode of the first thin film transistor through a contact hole formed in the organic layer.

[0009] In an exemplary embodiment of the present invention, a passivation layer may be disposed on the organic layer.

[0010] In an exemplary embodiment of the present invention, an electrode of the light-emitting element may be connected to the connection electrode through a contact hole formed in the passivation layer.

[0011] In an exemplary embodiment of the present invention, the passivation layer may be disposed on the signal line. A portion of the passivation layer overlapping with the second region may be in direct contact with the signal line.

[0012] In an exemplary embodiment of the present invention, the first insulating layer may substantially cover the upper surface of the silicon semiconductor pattern of the first thin-film transistor. The second insulating layer may be disposed on the first insulating layer. The second insulating layer may substantially cover the upper surface and the side surface of the control electrode of the first thin-film transistor. The third insulating layer may be disposed on the second insulating layer. The third insulating layer may substantially cover the upper surface and the side surface of the control electrode of the second thin-film transistor. The fourth insulating layer may be disposed on the third insulating layer. The fourth insulating layer may substantially cover the upper surface and the side surface of the input electrode of the second thin-film transistor. The fourth insulating layer may substantially cover the upper surface and the side surface of the output electrode of the second thin-film transistor. The fourth insulating layer may substantially cover the upper surface of the oxide semiconductor pattern of the second thin-film transistor.

[0013] In an exemplary embodiment of the present invention, a first portion and a second portion of the oxide semiconductor pattern may be respectively disposed on the input electrode and the output electrode of the second thin-film transistor.

[0014] In an exemplary embodiment of the present invention, the input electrode and the output electrode of the second thin-film transistor may be respectively disposed above the first portion and the second portion of the oxide semiconductor pattern. A third portion of the oxide semiconductor pattern may be exposed from the input electrode and the output electrode of the second thin-film transistor.

[0015] In an exemplary embodiment of the present invention, the display panel may include an upper electrode, wherein the upper electrode is disposed between the second insulating layer and the third insulating layer. The upper electrode may overlap with the control electrode of the first thin-film transistor.

[0016] In an exemplary embodiment of the present invention, the display panel may include a light-blocking pattern, wherein the light-blocking pattern is disposed on the organic layer. The light-blocking pattern may overlap with the oxide semiconductor pattern of the second thin-film transistor.

[0017] In an exemplary embodiment of the present invention, at least one inorganic layer may include a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer and the silicon oxide layer are alternately disposed.

[0018] In an exemplary embodiment of the present invention, a portion of the top surface of at least one inorganic layer may be in direct contact with the organic layer.

[0019] In an exemplary embodiment of the present invention, a method for manufacturing a display panel includes: forming at least one inorganic layer on a base layer, wherein the base layer includes a first region and a second region extending from the first region, and the at least one inorganic layer overlaps the first region and the second region in a direction orthogonal to the upper surface of the base layer. The method includes: forming a silicon semiconductor pattern on the at least one inorganic layer to overlap the first region in a direction orthogonal to the upper surface of the base layer. The method includes: forming a first control electrode on a first insulating layer to overlap the silicon semiconductor pattern in a direction orthogonal to the upper surface of the base layer. The first insulating layer overlaps the first region and the second region in a direction orthogonal to the upper surface of the base layer. The method includes: forming a second control electrode spaced apart from the first control electrode on a second insulating layer, wherein the second insulating layer overlaps the first region and the second region in a direction orthogonal to the upper surface of the base layer. The second insulating layer substantially covers the upper surface and the side surface of the first control electrode. The method includes: forming a third insulating layer, wherein the third insulating layer overlaps the first region and the second region in a direction orthogonal to the upper surface of the base layer. The third insulating layer substantially covers the upper surface and the side surface of the second control electrode. The method includes: performing a first etching, wherein the first etching partially removes the first insulating layer, the second insulating layer, and the third insulating layer to form a first contact hole and a second contact hole respectively exposing a first portion and a second portion of the silicon semiconductor pattern. The first etching forms a first upper groove in the second region exposing at least one inorganic layer. The method includes: forming an oxide semiconductor pattern on the third insulating layer, wherein the oxide semiconductor pattern overlaps the second control electrode in a direction orthogonal to the upper surface of the base layer. The method includes: forming a first input electrode and a first output electrode on the third insulating layer, and forming a second input electrode and a second output electrode on the third insulating layer, wherein the first input electrode and the first output electrode are respectively connected to the silicon semiconductor pattern through the first contact hole and the second contact hole, and the second input electrode and the second output electrode are connected to the oxide semiconductor pattern. The method includes: forming a fourth insulating layer on the third insulating layer. The fourth insulating layer overlaps the first region and the second region in a direction orthogonal to the upper surface of the base layer. The method includes: performing a second etching, wherein the second etching partially removes the fourth insulating layer to form a third contact hole exposing the first output electrode in the fourth insulating layer. The second etching includes: forming a second upper groove in the second region exposing at least one insulating layer. The method includes: performing a third etching, wherein the third etching removes a portion of the at least one inorganic layer overlapping the second region to form a lower groove in the at least one inorganic layer aligned with the first upper groove in a direction orthogonal to the upper surface of the base layer. The method includes: forming an organic layer, wherein the organic layer is disposed on the fourth insulating layer within the first region, and is disposed within the first upper groove, the second upper groove, and the lower groove within the second region.The method includes: performing a fourth etch, wherein the fourth etch partially removes the organic layer to form a fourth contact hole connected to the third contact hole in the organic layer. The method includes: forming a light-emitting element on the organic layer that is electrically connected to the first output electrode.

[0020] In an exemplary embodiment of the present invention, after forming the oxide semiconductor pattern, a second input electrode and a second output electrode are formed, wherein the second input electrode and the second output electrode are spaced apart from each other, and each of the second input electrode and the second output electrode may overlap the oxide semiconductor pattern in a direction orthogonal to the upper surface of the base layer.

[0021] In an exemplary embodiment of the present invention, after forming the second input electrode and the second output electrode spaced apart from each other, an oxide semiconductor pattern is formed, wherein the oxide semiconductor pattern partially overlaps the second input electrode and the second output electrode in a direction orthogonal to the upper surface of the base layer.

[0022] In an exemplary embodiment of the present invention, the method may include: forming a connection electrode and a signal line on the organic layer, wherein the connection electrode is connected to the first output electrode, and the signal line overlaps the second region in a direction orthogonal to the upper surface of the base layer. The method may include: forming a passivation layer on the organic layer that substantially covers the upper surface of the connection electrode and the upper surface of the signal line. The method may include: performing a fifth etch, wherein the fifth etch partially removes the passivation layer to form a fifth contact hole exposing the connection electrode. The light-emitting element may be connected to the first output electrode through the connection electrode.

[0023] In an exemplary embodiment of the present invention, forming the light-emitting element may include: forming a first electrode of the light-emitting element on the passivation layer, wherein the first electrode of the light-emitting element is connected to the connection electrode. Forming the light-emitting element may include: forming a pixel defining layer on the passivation layer, wherein the pixel defining layer has an opening exposing the first electrode of the light-emitting element.

[0024] In an exemplary embodiment of the present invention, a portion of the passivation layer that overlaps the second region in a direction orthogonal to the upper surface of the base layer may be in direct contact with the signal line.

[0025] In an exemplary embodiment of the present invention, when forming the second control electrode, an upper electrode may be formed on the second insulating layer, wherein the upper electrode overlaps the first control electrode in a direction orthogonal to the upper surface of the base layer.

[0026] In an exemplary embodiment of the present invention, the method may include: forming a light-blocking pattern on the organic layer, wherein the light-blocking pattern overlaps the oxide semiconductor pattern in a direction orthogonal to the upper surface of the base layer.

[0027] In an exemplary embodiment of the present invention, a part of the top surface of at least one inorganic layer may be in direct contact with the organic layer.

[0028] In an exemplary embodiment of the present invention, the method may include: bending a second region.

[0029] In an exemplary embodiment of the present invention, a method for manufacturing a display panel includes: forming at least one inorganic layer on a base layer, wherein the base layer includes a first region and a second region extending from the first region, and the at least one inorganic layer overlaps the first region and the second region in a direction orthogonal to the upper surface of the base layer. The method includes: forming a first insulating layer to a third insulating layer on the at least one inorganic layer, and forming a silicon semiconductor pattern on the at least one inorganic layer, wherein the first insulating layer to the third insulating layer overlap the first region and the second region in a direction orthogonal to the upper surface of the base layer, and the silicon semiconductor pattern overlaps the first region in a direction orthogonal to the upper surface of the base layer. The method includes: performing a first etching, wherein the first etching partially removes the first insulating layer to the third insulating layer to expose a part of the silicon semiconductor pattern and a part of the at least one inorganic layer that overlaps the second region in a direction orthogonal to the upper surface of the base layer. The method includes: forming an oxide semiconductor pattern and a plurality of electrodes connected to the oxide semiconductor pattern and the silicon semiconductor pattern above the first insulating layer to the third insulating layer. The method includes: forming a fourth insulating layer on the first insulating layer to the third insulating layer, wherein the fourth insulating layer substantially covers the upper surface, the upper surface and the side surfaces of the plurality of electrodes of the oxide semiconductor pattern. The method includes: performing a second etching, wherein the second etching partially removes the fourth insulating layer such that at least one of the plurality of electrodes and a part of the at least one inorganic layer that overlaps the second region in a direction orthogonal to the upper surface of the base layer are exposed. The method includes: performing a third etching, wherein the third etching partially removes a part of the at least one inorganic layer that overlaps the second region in a direction orthogonal to the upper surface of the base layer. The method includes: forming an organic layer, wherein the organic layer is located on the fourth insulating layer within the first region, and is disposed in the region where the at least one inorganic layer is removed and the region where the first insulating layer to the fourth insulating layer are removed within the second region. The method includes: performing a fourth etching on the organic layer, wherein the fourth etching partially removes the organic layer such that at least one of the plurality of electrodes is exposed. The method includes: forming a light-emitting element on the organic layer that is electrically connected to at least one of the plurality of electrodes and a signal line. The method includes: bending the second region.

[0030] In an exemplary embodiment of the present invention, the signal line may be a data line, wherein the data line includes a first part connected to a pixel, a second part, and a third part connected to a signal pad. The second part may connect the first part and the third part to each other.

[0031] In an exemplary embodiment of the present invention, the bottom surface of the first portion of the data line facing the base layer may be positioned above the base layer at the same height as the bottom surface of the third portion of the data line facing the base layer.

[0032] In an exemplary embodiment of the present invention, the bottom surface of the first portion of the data line facing the base layer may be positioned above the base layer at a different height from the bottom surface of the third portion of the data line facing the base layer.

[0033] In an exemplary embodiment of the present invention, the second region may include a curvature region. The thickness of the second region may be less than the thickness of the first region.

[0034] In an exemplary embodiment of the present invention, the curvature region may be permanently maintained in a curved state. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] By describing the exemplary embodiments of the present invention in detail with reference to the drawings, the above and other features of the present invention will become more apparent. In the drawings:

[0036] Figure 1A and Figure 1B is a perspective view of a display panel according to an exemplary embodiment of the present invention;

[0037] Figure 2 is a plan view of a display panel according to an exemplary embodiment of the present invention;

[0038] Figure 3A is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention;

[0039] Figure 3B and Figure 3C is a cross-sectional view of a part of a pixel according to an exemplary embodiment of the present invention;

[0040] Figure 4A and Figure 4B is a cross-sectional view of a bending region of a display panel according to an exemplary embodiment of the present invention;

[0041] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K , Figure 5L , Figure 5M , Figure 5N and Figure 5Ois a cross-sectional view of a process for manufacturing a display panel according to an exemplary embodiment of the present invention;

[0042] Figure 6 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention;

[0043] Figure 7 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention;

[0044] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D and Figure 8E is a cross-sectional view showing a part of a display panel according to an exemplary embodiment of the present invention; and

[0045] Figure 9 is a cross-sectional view of a part of a display panel according to an exemplary embodiment of the present invention. Detailed Embodiments

[0046] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In this regard, the exemplary embodiments may have different forms and should not be construed as being limited to the exemplary embodiments of the present invention described herein.

[0047] It should be understood that when an element such as a region, a layer, or a portion is referred to as being "on" another element, the element may be directly on the other element or there may also be an intermediate element.

[0048] Throughout the specification and the drawings, like reference numerals indicate like elements. For the sake of clarity of description, the dimensions of the elements in the drawings may be enlarged.

[0049] It should be understood that although the terms "first" and "second" may be used herein to describe various components, these components should not be limited by these terms.

[0050] Figure 1A and Figure 1B is a perspective view of a display panel according to an exemplary embodiment of the present invention. Figure 2 is a plan view of a display panel according to an exemplary embodiment of the present invention. Figure 2 Schematically shows the connection relationship between the pixel PX, the driving circuit GDC, and the signal line SGL.

[0051] In the unfolded state, the display panel DP may include a front surface DP-FS parallel to the surface defined by the first direction axis DR1 and the second direction axis DR2. As an example, the front surface DP-FS may have a substantially rectangular shape; however, the exemplary embodiments of the present invention are not limited thereto. The normal direction of the front surface DP-FS of the display surface DS (e.g., the thickness direction of the display panel DP) may extend along the third direction axis DR3. Thus, the third direction axis DR3 may be orthogonal to the first direction axis DR1 and the second direction axis DR2. The front surface and the bottom surface (e.g., the rear surface) of the display panel DP may face each other along the third direction axis DR3. Thus, each of the plurality of stacked layers of the display panel DP may include a front surface and a rear surface facing each other along the third direction axis DR3 (e.g., when the display panel DP is in the unfolded state). Herein, the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 may be referred to as the first direction, the second direction, and the third direction, respectively, and may include the same reference numerals herein.

[0052] Referring to Figure 1A , the display panel DP may include a display area DP-DA and a non-display area DP-NDA on the front surface DP-FS, wherein pixels PX are displayed on the display area DP-DA. The non-display area DP-NDA may be an area where no pixels are arranged. Thus, each of the pixels PX may be located in the display area DP-DA. A part of the driving circuit GDC and / or a part of the signal line SGL may be arranged on the non-display area DP-NDA.

[0053] The display area DP-DA may have a rectangular shape. When viewed along the third direction DR3 in a plan view, the non-display area DP-NDA may surround the display area DP-DA (e.g., be located on the four sides of the display area DP-DA). However, the exemplary embodiments of the present invention are not limited to the specific shapes of the display area DP-DA or the non-display area DP-NDA. For example, the shapes of the display area DP-DA and the non-display area DP-NDA may each be changed as needed. For example, the non-display area DP-NDA may be arranged only on the areas facing each other in the first direction DR1. Alternatively, the non-display area DP-NDA may be arranged on three sides of the display area DP-DA (e.g., not on the side where the second area BA, which will be described in more detail below, extends). As an example, the display area DP-DA may have a circular shape.

[0054] According to an exemplary embodiment of the present invention, compared with the width of the display area DP-DA, a part of the non-display area DP-NDA may have a relatively narrow width (e.g., the length in the second direction DR2). Thus, the surface area of the bending area, which will be described in more detail below, can be reduced.

[0055] Referring to Figure 1B , the display panel DP can be bent or curled (e.g., to form a "C" shape), and when it is bent, the display panel DP can include a first region NBA (e.g., a non-bent region) and a second region BA (e.g., a bent region). The second region BA can include a curvature region CA having a predetermined curvature in the bent state and a facing region FA facing the first region NBA in the bent state. As an example, the display panel DP can be bent along a bending axis BX. The bending axis BX can extend along a second direction DR2. The second direction DR2 can be perpendicular to each of a first direction DR1 and a third direction DR3.

[0056] Referring to Figure 2 , the display panel DP can include a driving circuit GDC, a plurality of signal lines SGL (e.g., which can be referred to as signal lines herein), a plurality of signal pads DP-PD (e.g., which can be referred to as signal pads herein), and a plurality of pixels PX (e.g., which can be referred to as pixels herein).

[0057] The pixels PX can be divided into a plurality of groups according to the colors displayed thereon. The pixels PX can include, for example, red pixels, green pixels, or blue pixels. The pixels PX can include white pixels. Although the pixels can be divided into different groups according to the colors displayed thereon, the pixel driving circuits of the pixels can be the same as each other.

[0058] The driving circuit GDC can include a scan driving circuit. The scan driving circuit can generate a plurality of scan signals (e.g., which can be referred to as scan signals herein) and can sequentially output the scan signals to a plurality of scan lines GL (e.g., which can be referred to as scan lines herein). The scan driving circuit can also output another control signal to the driving circuit of the pixels PX.

[0059] The scan driving circuit can include a plurality of thin film transistors, wherein the plurality of thin film transistors are formed by a process substantially the same as the process of the driving circuit of the pixels PX (e.g., a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide process).

[0060] The signal lines SGL can include scan lines GL, data lines DL, power lines PL, and / or control signal lines CSL. Each of the scan lines GL can be connected to a corresponding one of the pixels PX among the pixels PX, and each of the data lines DL can be connected to a corresponding one of the pixels PX among the pixels PX. The power lines PL can be connected to the pixels PX. The control signal lines CSL can provide control signals to the scan driving circuit. Each of the signal pads DP-PD can be connected to a corresponding one of the signal lines SGL.

[0061] The circuit board can be electrically connected to the display panel DP. The circuit board can be a rigid circuit board or a flexible circuit board. The driving chip can be mounted on the circuit board.

[0062] The driving chip can be mounted on the display panel DP. When the driving chip is mounted on the display panel DP, the design of the signal line SGL can be changed. The driving chip can be connected to the data line DL, and a signal line connecting the driving chip to the signal pad DP-PD can also be provided.

[0063] Figure 3A is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention. Figure 3B and Figure 3C is a cross-sectional view of a part of the pixel PX according to an exemplary embodiment of the present invention. Figure 4A and Figure 4B is a cross-sectional view of a bent area of the display panel according to an exemplary embodiment of the present invention.

[0064] Referring to Figure 3A , any one of the scan lines GL, any one of the data lines DL, and the power line PL can be connected to the pixel PX. Although the pixel PX according to the exemplary embodiment of the present invention can be a light-emitting pixel, the exemplary embodiment of the present invention is not limited thereto. For example, as the light-emitting element, the pixel PX can include an organic light-emitting diode or a quantum dot light-emitting diode. The light-emitting layer of the organic light-emitting diode can include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting diode can include quantum dots and quantum rods. Hereinafter, as an example, the pixel PX will be described as an organic light-emitting pixel.

[0065] The pixel PX can include an organic light-emitting diode OLED and a pixel driving circuit for driving the organic light-emitting diode OLED. The organic light-emitting diode OLED can be referred to as a light-emitting element herein. The organic light-emitting diode OLED can be a front-emitting diode or a back-emitting diode. In the exemplary embodiment of the present invention, the pixel driving circuit can include a first thin-film transistor T1 (e.g., a driving transistor), a second thin-film transistor T2 (e.g., a switching transistor), and a capacitor Cst. A first power supply voltage ELVDD can be provided on the first thin-film transistor T1, and a second power supply voltage ELVSS can be provided on the organic light-emitting diode OLED. The second power supply voltage ELVSS can be less than the first power supply voltage ELVDD.

[0066] The first thin film transistor T1 may be connected to the organic light emitting diode OLED. The first thin film transistor T1 may control the driving current flowing in the organic light emitting diode OLED in correspondence with the amount of electric charge stored in the capacitor Cst. The second thin film transistor T2 may output the data signal applied to the data line DL in response to a scan signal applied to the scan line GL. The capacitor Cst may hold a voltage corresponding to the data signal received from the second thin film transistor T2.

[0067] The exemplary embodiments of the present invention are not limited to the configuration of the pixel PX described with reference to Figure 3A The configuration of the pixel PX may be changed as needed. For example, the pixel circuit for controlling the organic light emitting diode OLED may include, for example, six or seven thin film transistors. The organic light emitting diode OLED may be connected between the power supply line PL and the second thin film transistor T2.

[0068] Figure 3B is a partial configuration of the pixel PX, which shows a cross-sectional view corresponding to the first thin film transistor T1, the second thin film transistor T2, and the organic light emitting diode OLED. The first thin film transistor T1 may have a top gate structure. The second thin film transistor T2 may have a bottom gate structure. Referring to Figure 3B , the display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display panel DP may include functional layers such as a reflective protection layer and a refractive index adjustment layer. The circuit element layer DP-CL may include a plurality of insulating layers and circuit elements. As an example, the insulating layer may include an organic layer and / or an inorganic layer.

[0069] The circuit elements may include signal lines SGL and a driving circuit of the pixel. The circuit element layer DP-CL may be formed via a process of forming insulating layers, semiconductor layers, and conductive layers by coating and deposition and a process of patterning the insulating layers, semiconductor layers, and conductive layers by a photolithography process.

[0070] The display element layer DP-OLED may include light emitting elements. The display element layer DP-OLED may further include an organic layer such as a pixel defining layer PDL.

[0071] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, although the synthetic resin layer may include a polyimide-based resin layer, the exemplary embodiments of the present invention are not limited thereto. The synthetic resin layer may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a silicone-based resin, a polyamide-based resin, and a dinaphthylphenyl resin. The base layer BL may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0072] Reference Figure 1A 、 Figure 1B and Figure 2 The area of the display panel DP described can be defined in the base layer BL in substantially the same manner as the above-described manner for the display panel DP. For example, the base layer BL may include a first area NBA and a second area BA that is curved from the first area NBA.

[0073] According to an exemplary embodiment of the present invention, the second area BA may extend from the first area NBA. The second area BA may include a curvature area CA. The thickness of the second area BA (e.g., in the third direction DR3) may be less than the thickness of the first area NBA. Thus, the bending or curling of the curvature area CA in the second area BA can be achieved by applying a relatively small amount of force to the second area BA, and the stress applied to the connection between the first area NBA and the second area BA can be relatively small. The curvature area CA may be permanently maintained in a bent state or may be maintained as bendable.

[0074] At least one inorganic layer may be disposed on the top surface of the base layer BL. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. The inorganic layer may have a single-layer or multi-layer structure. The multi-layer inorganic layer may include a barrier layer BRL and / or a buffer layer BFL, which will be described in more detail below. The barrier layer BRL and the buffer layer BFL may be selectively disposed as needed. Thus, either the barrier layer BRL or the buffer layer BFL may be individually referred to as the inorganic layer. Alternatively, the barrier layer BRL and the buffer layer BFL may be collectively referred to as the inorganic layer.

[0075] The barrier layer BRL may prevent foreign substances from being introduced from the outside. The barrier layer BRL may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be provided as multi-layers. The silicon oxide layer and the silicon nitride layer may be alternately and repeatedly stacked.

[0076] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may increase the bonding force between the base layer BL and the conductive pattern or the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately and repeatedly stacked.

[0077] A first semiconductor pattern OSP1 may be disposed on a buffer layer BFL. The first semiconductor pattern OSP1 may include a silicon semiconductor. Accordingly, the first semiconductor pattern OSP1 may be referred to as a silicon semiconductor pattern. The first semiconductor pattern OSP1 may include a polycrystalline silicon semiconductor. However, the exemplary embodiments of the present invention are not limited thereto. For example, the first semiconductor pattern OSP1 may include amorphous silicon. The first semiconductor pattern OSP1 may include an input region (e.g., a first portion), an output region (e.g., a second portion), and a channel region (e.g., a third portion) defined between the input region and the output region. The channel region of the first semiconductor pattern OSP1 may be defined to correspond to a first control electrode GE1, which will be described in more detail hereinafter. For example, the first control electrode GE1 and the first semiconductor pattern OSP1 may at least partially overlap each other (e.g., may be completely aligned with each other) along a third direction DR3. Since the input region and the output region are doped with a dopant, the conductivity of each of the input region and the output region may be relatively higher than that of the channel region. The input region and the output region may be doped with an n-type dopant. In the exemplary embodiments of the present invention, although an n-type first thin film transistor T1 is exemplarily described, the first thin film transistor T1 may be a p-type transistor.

[0078] A first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with each of a plurality of pixels PX (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL; for example, see Figure 1A ). The first insulating layer 10 may substantially cover the upper surface and the side surfaces of the first semiconductor pattern OSP1. The upper surface of the first semiconductor pattern OSP1 may face away from the base layer BL in the third direction DR3, and the side surfaces of the first semiconductor pattern OSP1 may face each other along a first direction DR1 perpendicular to the third direction DR3. The upper surfaces of other layers to be described in more detail hereinafter may indicate the surfaces facing away from the base layer BL in the third direction DR3, and the side surfaces may indicate the surfaces facing each other in the first direction DR1. The first insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0079] In the exemplary embodiments of the present invention, the first insulating layer 10 may include an inorganic layer, and may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. In the exemplary embodiments of the present invention, the first insulating layer 10 may be a single layer including silicon oxide.

[0080] A first control electrode GE1 may be disposed on the first insulating layer 10. The first control electrode GE1 may overlap with the channel region of the first semiconductor pattern OSP1 (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL).

[0081] The second insulating layer 20 may substantially cover the upper surface and the side surfaces of the first control electrode GE1 disposed on the first insulating layer 10. The second insulating layer 20 may overlap with each of the plurality of pixels PX (e.g., along a third direction DR3 orthogonal to the upper surface of the base layer BL; for example, see Figure 1A ). The second insulating layer 20 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0082] In an exemplary embodiment of the present invention, the second insulating layer 20 may include an inorganic layer, and may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. In an exemplary embodiment of the present invention, the second insulating layer 20 may be a single layer including silicon oxide.

[0083] A second control electrode GE2 may be disposed on the second insulating layer 20. The second control electrode GE2 may not overlap with the first control electrode GE1. Thus, the second control electrode GE2 may be spaced apart from the first control electrode GE1 (e.g., along a first direction DR1). In an exemplary embodiment of the present invention, an upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the first control electrode GE1 (e.g., along a third direction DR3 orthogonal to the upper surface of the base layer BL). Since the second control electrode GE2 and the upper electrode UE may be formed by the same process, the second control electrode GE2 and the upper electrode UE may include the same material and may have the same stacked structure. In an exemplary embodiment of the present invention, the upper electrode UE may be omitted.

[0084] A third insulating layer 30 may be disposed on the second insulating layer 20, and the third insulating layer 30 substantially covers the upper surface and the side surfaces of the second control electrode GE2 and the upper surface and the side surfaces of the upper electrode UE. The third insulating layer 30 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0085] In an exemplary embodiment of the present invention, the third insulating layer 30 may include an inorganic layer, and may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. In an exemplary embodiment of the present invention, the third insulating layer 30 may be a single layer including silicon oxide.

[0086] On the third insulating layer 30, a second semiconductor pattern OSP2 overlapping with the second control electrode GE2 (e.g., along a third direction DR3 orthogonal to the upper surface of the base layer BL) may be disposed. The second semiconductor pattern OSP2 may include an oxide semiconductor. Thus, the second semiconductor pattern OSP2 may be referred to as an oxide semiconductor pattern. The second semiconductor pattern OSP2 may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include: metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti); metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti); or mixtures thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), or zinc tin oxide (ZTO).

[0087] The second semiconductor pattern OSP2 may include an input region (e.g., a first portion), an output region (e.g., a second portion), and a channel region (e.g., a third portion) defined between the input region and the output region. Each of the input region and the output region may include impurities. The channel region of the second semiconductor pattern OSP2 may be defined as a region exposed from the second input electrode DE2 and the second output electrode SE2, which will be described in more detail below.

[0088] The impurities of the second semiconductor pattern OSP2 may be a reduced metal material. Each of the input region and the output region of the second semiconductor pattern OSP2 may include a metal material reduced from the metal oxide contained in the channel region. Thus, the second thin film transistor T2 may reduce leakage current and may be used as a switching element having on-off characteristics and improved accuracy and reliability.

[0089] On the third insulating layer 30, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2 may be disposed. Since the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 may be formed by the same process as each other, each of the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 may include the same material as each other and may have the same stack structure as each other.

[0090] The first input electrode DE1 and the first output electrode SE1 may be connected to the first semiconductor pattern OSP1 through the first contact hole CH1 and the second contact hole CH2, respectively, wherein the first contact hole CH1 and the second contact hole CH2 expose the input region and the output region of the first semiconductor pattern OSP1, respectively. The first contact hole CH1 and the second contact hole CH2 may penetrate through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0091] The second input electrode DE2 and the second output electrode SE2 may be connected to opposite ends of the second semiconductor pattern OSP2, respectively. At least a part of the second input electrode DE2 may be directly disposed on the input region of the second semiconductor pattern OSP2, and at least a part of the second output electrode SE2 may be directly disposed on the output region of the second semiconductor pattern OSP2.

[0092] A fourth insulating layer 40 substantially covering the upper surfaces and side surfaces of each of the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0093] In an exemplary embodiment of the present invention, the fourth insulating layer 40 includes an inorganic layer, and may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. The fourth insulating layer 40 may include a silicon oxide layer.

[0094] A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may include an organic layer. A connection electrode CNE may be disposed on the fifth insulating layer 50. The connection electrode CNE may be connected to the first output electrode SE1 through a third contact hole CH3, wherein the third contact hole CH3 penetrates through the fourth insulating layer 40 and the fifth insulating layer 50. A sixth insulating layer 60 substantially covering the upper surface and side surface of the connection electrode CNE may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be referred to as a passivation layer. The sixth insulating layer 60 may include an organic layer, and may have a single-layer or multi-layer structure.

[0095] In an exemplary embodiment of the present invention, each of the fifth insulating layer 50 and the sixth insulating layer 60 may have a single-layer structure including a polyimide-based resin layer. However, the exemplary embodiments of the present invention are not limited thereto. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose-based resin, a silicone-based resin, a polyamide-based resin, and a binaphthyl-based resin.

[0096] The organic light-emitting diode OLED can be disposed on the sixth insulating layer 60. The anode AE of the organic light-emitting diode OLED can be disposed on the sixth insulating layer 60. The anode AE can be connected to the connection electrode CNE through the fourth contact hole CH4 penetrating the sixth insulating layer 60. A pixel definition layer PDL can be disposed on the sixth insulating layer 60.

[0097] The opening OP of the pixel definition layer PDL can expose at least a part of the anode AE. The opening OP of the pixel definition layer PDL can define the light-emitting region PXA of the pixel. For example, a plurality of pixels PX (for example, see Figure 1A ) can be arranged on the plane of the display panel DP (for example, see Figure 1A ) according to a predetermined rule. For example, a plurality of pixels PX can be arranged in a matrix configuration having rows and columns extending along a first direction DR1 and a second direction DR2. The region on which a plurality of pixels PX are disposed can be defined as a pixel region, and one pixel region can include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA can surround the light-emitting region PXA (for example, when viewed in a third direction DR3 orthogonal to the upper surface of the base layer BL in a plan view).

[0098] The display area DP-DA (for example, see Figure 1A and Figure 1B ) can include a plurality of pixel regions. For example, the display area DP-DA can include a plurality of light-emitting regions PXA and non-light-emitting regions NPXA surrounding the plurality of light-emitting regions PXA.

[0099] A hole control layer HCL can be commonly disposed on the light-emitting region PXA and the non-light-emitting region NPXA. The common layer of the hole control layer HCL can connect two or more of the plurality of pixels PX to each other. The hole control layer HCL can include a hole transport layer and a hole injection layer.

[0100] An organic light-emitting layer EML can be disposed on the hole control layer HCL. The organic light-emitting layer EML can be disposed only on the region corresponding to the opening OP. The organic light-emitting layer EML can be separately disposed on each of the plurality of pixels PX.

[0101] The organic light-emitting layer EML can be disposed on two or more of the plurality of pixels PX. The organic light-emitting layer EML can generate white light. The organic light-emitting layer EML can have a multi-layer structure.

[0102] An electron control layer ECL can be disposed on the organic light-emitting layer EML. The electron control layer ECL can include an electron transport layer and an electron injection layer. A cathode CE can be disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE can be commonly disposed on the plurality of pixels PX.

[0103] The thin film encapsulation layer TFE may be disposed on the cathode CE. The thin film encapsulation layer TFE may be disposed on two or more of the plurality of pixels PX. According to an exemplary embodiment of the present invention, the thin film encapsulation layer TFE may substantially cover the upper surface of the cathode CE. In an exemplary embodiment of the present invention, the cover layer may also substantially cover the upper surface of the cathode CE. The cover layer may include an organic layer. In an exemplary embodiment of the present invention, an inorganic layer may be formed on the cover layer by a sputtering method. In an exemplary embodiment of the present invention, the stacked structure of the organic light emitting diode OLED may have a structure inverted with respect to the structure described with reference to Figure 3B The described structure is inverted.

[0104] The thin film encapsulation layer TFE may include at least an inorganic layer or an organic layer. In an exemplary embodiment of the present invention, the thin film encapsulation layer TFE may include two inorganic layers, and an organic layer may be disposed between the two inorganic layers. In an exemplary embodiment of the present invention, the thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers, wherein the plurality of inorganic layers and the plurality of organic layers are alternately and repeatedly stacked.

[0105] The inorganic layer of the thin film encapsulation layer TFE protects the organic light emitting diode OLED from the influence of moisture / oxygen, and the organic layer of the thin film encapsulation layer TFE protects the organic light emitting diode OLED from foreign substances such as dust particles. Although the inorganic layer of the thin film encapsulation layer TFE may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, the exemplary embodiments of the present invention are not limited thereto. Although the organic layer of the thin film encapsulation layer TFE may include an acrylic-based organic layer, the exemplary embodiments of the present invention are not limited thereto.

[0106] According to an exemplary embodiment of the present invention, the first thin film transistor T1 may include a silicon semiconductor (e.g., a polysilicon semiconductor), and thus, the first thin film transistor T1 may have a relatively high electron mobility. The first thin film transistor T1 may have improved voltage-current accuracy and reliability. The second thin film transistor T2 may include an oxide semiconductor, and thus, the occurrence of leakage current may be reduced. Therefore, the driving voltage of the pixel PX can be reduced (e.g., see Figure 3A ), and the occurrence of its failure can be reduced or prevented.

[0107] Since the input electrode DE1 and the output electrode SE1 of the first thin film transistor T1, which are disposed on the same layer as the input electrode DE2 and the output electrode SE2 of the second thin film transistor T2, can be directly connected to the first semiconductor pattern OSP1 through the first contact hole CH1 and the second contact hole CH2, respectively, where the first contact hole CH1 and the second contact hole CH2 penetrate through the first insulating layer 10 to the third insulating layer 30, misalignment can be reduced. When the input electrode DE1 and the output electrode SE1 are disposed on the same layer as the layer of the upper electrode UE (e.g., in the display panel according to the comparative example), a process of forming the connection electrode CNE on the same layer as the input electrode DE2 and the output electrode SE2 of the second thin film transistor T2 can be performed. The connection electrode CNE can be connected to the input electrode DE1 and the output electrode SE1 disposed on the same layer as the layer of the upper electrode UE. Therefore, misalignment may occur during the formation of the connection electrode CNE. Since the input electrode DE2 and the output electrode SE2 of the second thin film transistor T2 and the input electrode DE1 and the output electrode SE1 of the first thin film transistor T1 are formed through separate processes, the number of masks used in the manufacturing process can be increased.

[0108] Referring to Figure 3C , the display panel according to an exemplary embodiment of the present invention may further include a capacitor Cst, where the capacitor Cst is formed through the same process as the process of the components of the first thin film transistor T1.

[0109] The first electrode E1 of the capacitor Cst may be disposed on the first insulating layer 10. The first electrode E1 may be formed through the same process as the process of the first control electrode GE1. The first electrode E1 may be connected to the first control electrode GE1.

[0110] The second insulating layer 20 may substantially cover the upper surface and the side surface of the first electrode E1. The second electrode E2 of the capacitor Cst may be disposed on the second insulating layer 20. In an exemplary embodiment of the present invention, the upper electrode UE may be electrically connected to the second electrode E2. The upper electrode UE and the second electrode E2 may be formed through the same process as each other, and thus, the upper electrode UE and the second electrode E2 may include the same material as each other and may include the same structure as each other (e.g., a single-layer or multi-layer structure). The third insulating layer 30 that substantially covers the second electrode E2 and the upper electrode UE may be disposed on the second insulating layer 20.

[0111] Figure 4A and Figure 4B is a view showing Figure 2 a cross-section of the curvature region CA in the first direction DR1 in Figure 4A shows a cross-section overlapping with the signal line DL, and Figure 4B shows a cross-section of a region where the signal line DL is not disposed. InFigure 4A In this case, the data line DL is shown as the signal line DL.

[0112] Referring to Figure 4A and Figure 4B , in a cross-section, the second region BA may have a stacked structure similar to that of the first region NBA (e.g., see Figure 1A , Figure 1B and Figure 2 ). For example, the display region DP-DA (e.g., see Figure 1A , Figure 1B and Figure 2 ). The barrier layer BRL, the buffer layer BFL, and the first insulating layer 10 to the sixth insulating layer 60 may be sequentially arranged from the top surface of the base layer BL (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL).

[0113] A groove GV-1 (e.g., which may be referred to as a lower groove herein) overlapping the second region BA (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL) may define the barrier layer BRL and / or the buffer layer BFL. The lower groove GV-1 may be defined in the curvature region CA. Referring to Figure 1A , Figure 1B and Figure 2 , the barrier layer BRL and the buffer layer BFL disposed below the first semiconductor pattern OSP1 may overlap the display region DP-DA (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL) and may extend to the second region BA. The lower groove GV-1 may be formed by removing a part of the barrier layer BRL and the buffer layer BFL such that at least a part of the barrier layer BRL and the buffer layer BFL overlaps the second region BA (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL). The base layer BL exposed through the lower groove GV-1 may have a width in the first direction DR1, and this width is smaller than the width of the curvature region CA in the first direction DR1.

[0114] Grooves GV-2 (e.g., which may be referred to as upper grooves herein) overlapping the second region BA (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL) may be defined in the first insulating layer 10 to the fourth insulating layer 40. The upper grooves GV-2 may be defined in the curvature region CA. The top surface of the uppermost inorganic layer in the inorganic layer included in the barrier layer BRL and the buffer layer BFL may be exposed from the first insulating layer 10 to the fourth insulating layer 40.

[0115] In a cross-section, each of the side surfaces of the barrier layer BRL and the buffer layer BFL that define the lower groove GV-1 may have a predetermined slope. In a cross-section, each of the side surfaces of the first insulating layer 10 to the fourth insulating layer 40 that define the upper groove GV-2 may have a predetermined slope.

[0116] In an exemplary embodiment of the present invention, the width of the upper groove GV-2 in the first direction DR1 corresponding to the fourth insulating layer 40 may be greater than the width of the curvature region CA in the first direction DR1.

[0117] A fifth insulating layer 50 including an organic layer may be disposed in the upper groove GV-2 and the lower groove GV-1. Accordingly, the fifth insulating layer 50 may be referred to as an organic layer. The fifth insulating layer 50 may be in direct contact with the top surface of the base layer BL, the inclined surfaces of the lower groove GV-1, and the inclined surfaces of the upper groove GV-2. The fifth insulating layer 50 may be in direct contact with a portion of the top surface of the buffer layer BFL that may be exposed from the first insulating layer 10 to the fourth insulating layer 40.

[0118] Since the lower groove GV-1 and the upper groove GV-2 are defined in the barrier layer BRL, the buffer layer BFL, and the insulating layers 10 to 40 in the curvature region CA, and the fifth insulating layer 50 is disposed in the lower groove GV-1 and the upper groove GV-2, the bending region BA may have enhanced flexibility. Since the fifth insulating layer 50 is disposed on the bending region BA and the non-bending region NBA, the display panel DP may have a simplified structure. Accordingly, a relatively small number of masks may be used in the formation process of the fifth insulating layer 50. For example, the fifth insulating layer 50 may be formed in the bending region BA and the non-bending region NBA through a single continuous process. Accordingly, the manufacturing cost can be reduced and the occurrence of defects can be reduced.

[0119] At least a portion of the signal line DL may be disposed on the fifth insulating layer 50. A sixth insulating layer 60 may substantially cover the upper surface of the signal line DL, which may protect the signal line DL. Another portion of the signal line DL (e.g., another portion disposed on the display area DP-DA) may be disposed on a layer different from the sixth insulating layer 60. For example, another portion of the signal line DL may be disposed on the third insulating layer 30. The at least a portion and the another portion of the signal line DL may be connected through a contact hole penetrating the fourth insulating layer 40 and the fifth insulating layer 50. The contact hole may be disposed on the non-display area DP-NDA of the first region NBA.

[0120] In an exemplary embodiment of the present invention, a layer extending from a layer disposed on the display area DP-DA may be further disposed on the top surface of the sixth insulating layer 60. In an exemplary embodiment of the present invention, the sixth insulating layer 60 may not be disposed in the curvature region CA.

[0121] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K , Figure 5L , Figure 5M , Figure 5N and Figure 5O are cross-sectional views of a process for manufacturing a display panel according to an exemplary embodiment of the present invention. Figures 5A to 5O Each of Figure 3B and Figure 4A comparatively shows a region corresponding to the region described above with reference to Figure 1A , Figure 1B , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4A and Figure 4B The repeated description of components that are the same as or substantially the same as the components described above with reference to

[0122] Referring to Figure 5A , at least one inorganic layer may be formed on the first region NBA and the second region BA of the base layer BL. During the manufacturing process, the base layer BL may be disposed on a working substrate. After the display panel is manufactured, the working substrate may be removed.

[0123] The inorganic layer may be formed by depositing, coating, or printing an inorganic material. The barrier layer BRL may be formed by sequentially forming a silicon oxide layer and a silicon nitride layer. The buffer layer BFL may be formed by sequentially forming a silicon oxide layer and a silicon nitride layer on the barrier layer BRL.

[0124] A first preliminary semiconductor pattern OSP1-P may be formed on the inorganic layer. The first preliminary semiconductor pattern OSP1-P may include a silicon semiconductor material. A semiconductor layer may be formed and then patterned to form the first preliminary semiconductor pattern OSP1-P. The semiconductor layer may be crystallized. For example, the semiconductor layer may be crystallized before or after being patterned to form the first preliminary semiconductor pattern OSP1-P. The first preliminary semiconductor pattern OSP1-P may be doped.

[0125] Referring to Figure 5B, a first insulating layer 10 may be formed on a first region NBA and a second region BA of the inorganic layer. The first insulating layer 10 may be formed by deposition, coating, or printing. The insulating layer disposed on the first insulating layer 10 may also be formed by deposition, coating, or printing.

[0126] A first control electrode GE1 may be formed on the first insulating layer 10. The first control electrode GE1 may be formed by forming a conductive layer on the first insulating layer 10 and then patterning it. The first electrode E1 of the capacitor Cst may be formed by the same process as that of the first control electrode GE1 (for example, see Figure 3C ).

[0127] The first preliminary semiconductor pattern OSP1-P may be doped by using the first control electrode GE1 as a mask. The region overlapping with the first control electrode GE1 (for example, along a third direction DR3 orthogonal to the upper surface of the base layer BL) (for example, which may be referred to as a channel region herein) may not be doped, and the opposite side regions of the channel region (for example, an input region and an output region) may be doped. In an exemplary embodiment of the present invention, the doping may be performed by using an n-type dopant (for example, a pentavalent element). Thus, the first semiconductor pattern OSP1 may be formed.

[0128] Referring to Figure 5C , a second insulating layer 20 may be formed on the first region NBA and the second region BA of the first insulating layer 10 to substantially cover the first control electrode GE1. A second control electrode GE2 that does not overlap with the first control electrode GE1 (for example, along a third direction DR3 orthogonal to the upper surface of the base layer BL) may be formed on the second insulating layer 20. The upper electrode UE may be formed by the same process as that of the second control electrode GE2. The second electrode E2 of the capacitor Cst may be formed by the same process as that of the upper electrode UE (for example, see Figure 3C ).

[0129] Referring to Figure 5D , a third insulating layer 30 substantially covering the second control electrode GE2 and the upper electrode UE may be formed on the first region NBA and the second region BA of the second insulating layer 20.

[0130] Referring to Figure 5E, a part of the removable insulating layer 10 to 30 (e.g., which may be referred to as the first etching process herein) can be removed. Contact holes CH1 and CH2 that respectively expose the input region and the output region of the first semiconductor pattern OSP1 can be defined. In the same process, the first upper groove GV-21 can be formed by partially removing the second region BA of the first insulating layer 10 to the third insulating layer 30. Since the process of forming the contact holes in the first region NBA and the process of forming the grooves in the second region BA are performed in a single process, the number of masks used in the manufacturing process can be reduced.

[0131] Referring to Figure 5F , a second preliminary semiconductor pattern OSP2-P can be formed on the third insulating layer 30. The second preliminary semiconductor pattern OSP2-P can include a metal oxide semiconductor material. The second preliminary semiconductor pattern OSP2-P can be formed from a metal oxide semiconductor layer by a photolithography process.

[0132] According to an exemplary embodiment of the present invention, the order of performing the process described with reference to Figure 5E and the process described with reference to Figure 5F can be interchanged. In an exemplary embodiment of the present invention, the first contact hole CH1, the second contact hole CH2, and the first upper groove GV-21 can be defined after the second preliminary semiconductor pattern OSP2-P is formed.

[0133] Referring to Figure 5G , electrodes DE1, SE1, SE2, and DE2 (e.g., which may be referred to as the electrode formation process herein) can be formed on the third insulating layer 30. After a conductive layer is formed by a deposition process, the electrodes DE1, SE1, SE2, and DE2 can be formed by a patterning process.

[0134] The process of patterning the conductive layer can be performed by an etching gas including plasma. The etching gas can include oxygen-containing plasma. The etching gas can reduce the hydrogen concentration in the regions of the second preliminary semiconductor pattern OSP2-P exposed from the second input electrode DE2 and the second output electrode SE2. Therefore, the regions of the second preliminary semiconductor pattern OSP2-P exposed from the second input electrode DE2 and the second output electrode SE2 can be changed into channel regions, where the channel regions have semiconductor characteristics while the resistance of the channel regions is greater than the resistance of the regions of the second preliminary semiconductor pattern OSP2-P covered by the second input electrode DE2 and the second output electrode SE2. Therefore, a second semiconductor pattern OSP2 including an input region and an output region can be formed from the second preliminary semiconductor pattern OSP2-P, where the input region and the output region are spaced apart from each other and there is a channel region between the input region and the output region.

[0135] Referring to Figure 5H, a fourth insulating layer 40 can be formed on the third insulating layer 30 to substantially cover the electrodes DE1, SE1, SE2, and DE2. A part of the fourth insulating layer 40 can be disposed in the first upper groove GV-21.

[0136] Reference Figure 5I , a part of the fourth insulating layer 40 can be removed (for example, which can be referred to as the second etching process herein). A contact hole CH3-40 exposing the first output electrode SE1 can be formed. In the same process, a second upper groove GV-22 can be formed by partially removing a second region BA of the fourth insulating layer 40. Since the process of forming the contact hole in the first region NBA and the process of forming the groove in the second region BA are performed in a single process, the number of masks used in the manufacturing process can be reduced.

[0137] Although the inner surface of the second upper groove GV-22 and the inner surface of the first upper groove GV-21 can be aligned with each other, the exemplary embodiments of the present invention are not limited thereto. For example, the top surface of the third insulating layer 30 can be exposed from the fourth insulating layer 40. For example, the inner surface of the second upper groove GV-22 can be spaced apart from the inner surface of the first upper groove GV-21 along a first direction DR1 to expose the top surface of the third insulating layer 30 facing away from the base layer BL.

[0138] Refer to Figure 5J , a part of the barrier layer BRL and the buffer layer BFL can be removed (for example, which can be referred to as the third etching process herein). A lower groove GV-1 can be formed by partially removing a second region BA of the barrier layer BRL and the buffer layer BFL using an etching gas. The top surface of the uppermost inorganic layer in the inorganic layers included in the barrier layer BRL and the buffer layer BFL can be exposed from the first insulating layer 10 to the fourth insulating layer 40. In the exemplary embodiments of the present invention, the inner surface of the lower groove GV-1 can be aligned with the inner surface of the first upper groove GV-21.

[0139] Refer to Figure 5K , a fifth insulating layer 50 can be formed on the fourth insulating layer 40. The fifth insulating layer 50 can overlap with the first region NBA and the second region BA (for example, along a third direction DR3 that can be orthogonal to the upper surface of the base layer BL). The fifth insulating layer 50 is disposed in the lower groove GV-1 and the upper groove GV-2. The fifth insulating layer 50 can partially fill the contact hole CH3-40.

[0140] Refer to Figure 5L, a part of the fifth insulating layer 50 can be removed (for example, which may be referred to as the fourth etching process herein). A contact hole CH3-50 can be formed in the fifth insulating layer 50 to expose the first output electrode SE1 that is substantially covered by the fifth insulating layer 50. The contact hole CH3-50 of the fifth insulating layer 50 can be aligned with the contact hole CH3-40 of the fourth insulating layer 40. Accordingly, the contact holes CH3-40 and CH3-50 can define the third contact hole CH3.

[0141] Referring to Figure 5M , a connection electrode CNE can be formed on the fifth insulating layer 50. A portion of the signal line DL that overlaps with the second region BA (for example, along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL) can be formed by the same process as the process for the connection electrode CNE.

[0142] Referring to Figure 5N , a sixth insulating layer 60 can be formed on the fifth insulating layer 50 to substantially cover the connection electrode CNE and the portion of the signal line DL that overlaps with the second region BA. A fourth contact hole CH4 that exposes the top surface of the connection electrode CNE can be formed in the sixth insulating layer 60.

[0143] Referring to Figure 5O , an organic light-emitting diode OLED can be formed on the sixth insulating layer 60. An anode AE connected to the connection electrode CNE through the fourth contact hole CH4 can be formed on the sixth insulating layer 60. A pixel defining layer PDL that exposes the central portion of the anode AE can be formed on the sixth insulating layer 60. After the preliminary pixel defining layer is formed on the sixth insulating layer 60, an opening OP can be formed in the preliminary pixel defining layer.

[0144] A hole control layer HCL, an organic light-emitting layer EML, an electron control layer ECL, and a cathode CE can be sequentially formed on the first region NBA of the pixel defining layer PDL. The hole control layer HCL, the organic light-emitting layer EML, the electron control layer ECL, and the cathode CE can at least overlap with the display region DP-DA (for example, along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL; for example, see Figure 2 ).

[0145] A thin film encapsulation layer TFE can be formed on the cathode CE. The organic layer and / or inorganic layer of the thin film encapsulation layer TFE can be formed by a deposition or inkjet printing process. Although the thin film encapsulation layer TFE can be formed on the first region NBA and may not be formed on the second region BA, exemplary embodiments of the present invention are not limited thereto.

[0146] Figure 6 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention. Figure 7 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention.Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E are cross-sectional views showing a part of a display panel according to an exemplary embodiment of the present invention. Figure 9 is a cross-sectional view of a part of a display panel according to an exemplary embodiment of the present invention.

[0147] Hereinafter, with reference to the above Figure 1A , Figure 1B , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K , Figure 5L , Figure 5M , Figure 5N and Figure 5O repeated descriptions of components that are the same as or substantially the same as the components described above may be omitted.

[0148] Referring to Figure 6 , the arrangement relationship between the second semiconductor pattern OSP2 and both the second input electrode DE2 and the second output electrode SE2 may be changed. Since the second semiconductor pattern OSP2 may be formed after the second input electrode DE2 and the second output electrode SE2 are formed, opposite ends of the second semiconductor pattern OSP2 may be directly disposed on the second input electrode DE2 and the second output electrode SE2.

[0149] Referring to Figure 7 , the connection electrode CNE and the sixth insulating layer 60 may be omitted. The anode AE may be directly disposed on the fifth insulating layer 50 and connected to the first output electrode SE1 through the third contact hole CH3. A portion of the signal line DL that overlaps with the second region BA (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL) may be directly disposed on the fifth insulating layer 50.

[0150] The portion of the signal line DL that overlaps with the second region BA may be formed by the same process as the anode AE. Therefore, the portion of the signal line DL that overlaps with the second region BA and the anode AE may include the same material and may have the same layer structure as each other.

[0151] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E illustrate a display panel DP corresponding to the display panel DP described with reference to Figure 5O . The display panel DP described with reference to Figures 8A to 8E and the display panel DP described with reference to Figure 5O may differ in the shape of the signal line DL.

[0152] Referring to Figures 8A to 8E , a signal line (e.g., a data line DL) may include a first portion DL-P1, a second portion DL-P2, and a third portion DL-P3. The first portion DL-P1 may be connected to a pixel PX (e.g., see Figure 2 ), and the third portion DL-P3 may be connected to a corresponding signal pad DP-PD (e.g., see Figure 2 ) or a driving chip. The second portion DL-P2 may connect the first portion DL-P1 to the third portion DL-P3 through a fifth contact hole CH5 and a sixth contact hole CH6. The second portion DL-P2 may overlap with the curvature region CA (e.g., along a third direction DR3 that may be orthogonal to the upper surface of the base layer BL).

[0153] Referring to Figures 8A to 8E , according to an exemplary embodiment of the present invention, the fifth contact hole CH5 may extend in a direction orthogonal to the upper surface of the base layer BL to a depth substantially the same as the depth of the sixth contact hole CH6. The bottom surface of the first portion DL-P1 of the signal line DL facing the base layer BL may be positioned above the base layer BL at a first depth substantially the same as the depth of the bottom surface of the third portion DL-P3 of the signal line DL facing the base layer BL.

[0154] Alternatively, according to an exemplary embodiment of the present invention, the bottom surface of the first portion DL-P1 of the signal line DL facing the base layer BL may be positioned above the base layer BL at a depth different from the depth of the bottom surface of the third portion DL-P3 of the signal line DL facing the base layer BL.

[0155] Referring to Figure 8A , the first portion DL-P1 and the third portion DL-P3 may be formed by the same process as the input electrodes DE1 and DE2 and the output electrodes SE1 and SE2, and may be disposed on the same layer as the input electrodes DE1 and DE2 and the output electrodes SE1 and SE2. Each of the fifth contact hole CH5 and the sixth contact hole CH6 may penetrate through the fourth insulating layer 40 and the fifth insulating layer 50. Each of the fifth contact hole CH5 and the sixth contact hole CH6 may be formed by the same process as the third contact hole CH3.

[0156] Referring to Figure 8B , the first part DL-P1 and the third part DL-P3 can be formed by the same process as that of the upper electrode UE, and can be disposed on the same layer as the layer of the upper electrode UE. Each of the fifth contact hole CH5 and the sixth contact hole CH6 can penetrate the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. Each of the fifth contact hole CH5 and the sixth contact hole CH6 can be formed by the same process as that of the third contact hole CH3, and can further penetrate the third insulating layer 30. In an exemplary embodiment of the present invention, a photolithography process for forming the fifth contact hole CH5 and the sixth contact hole CH6 can be performed.

[0157] Referring to Figure 8C , the first part DL-P1 and the third part DL-P3 can be formed by the same process as that of the first control electrode GE1, and can be disposed on the same layer as the layer of the first control electrode GE1. Each of the fifth contact hole CH5 and the sixth contact hole CH6 can penetrate the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. Each of the fifth contact hole CH5 and the sixth contact hole CH6 can be formed by the same process as that of the third contact hole CH3, and can further penetrate the second insulating layer 20 and the third insulating layer 30. In an exemplary embodiment of the present invention, a photolithography process for forming the fifth contact hole CH5 and the sixth contact hole CH6 can be performed.

[0158] One of the first part DL-P1 and the third part DL-P3 can be formed by the same process as one of the first input electrode DE1, the upper electrode UE, and the first control electrode GE1, and can be disposed on the same layer as the layer of the one of the first input electrode DE1, the upper electrode UE, or the first control electrode GE1, and the other of the first part DL-P1 and the third part DL-P3 can be formed by the same process as one of the first input electrode DE1, the upper electrode UE, and the first control electrode GE1, and is disposed on the same layer as the layer of the one of the first input electrode DE1, the upper electrode UE, or the first control electrode GE1. According to the position of each of the first part DL-P1 and the third part DL-P3, the insulating layer through which each of the fifth contact hole CH5 and the sixth contact hole CH6 penetrates can be changed. Each of the fifth contact hole CH5 and the sixth contact hole CH6 can be formed by the same process as that of the third contact hole CH3. Therefore, the depths of the fifth contact hole CH5 and the sixth contact hole CH6 can be controlled in different ways.

[0159] For example, referring to Figure 8D, the first part DL-P1 can be formed by the same process as that of the upper electrode UE and can be disposed on the same layer as the layer of the upper electrode UE. The third part DL-P3 can be formed by the same process as that of the first input electrode DE1 and can be disposed on the same layer as the layer of the first input electrode DE1. The fifth contact hole CH5 can penetrate through the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50, and the sixth contact hole CH6 can penetrate through the fourth insulating layer 40 and the fifth insulating layer 50.

[0160] Referring to Figure 8E , the first part DL-P1 can be formed by the same process as that of the first control electrode GE1 and can be disposed on the same layer as the layer of the first control electrode GE1. The third part DL-P3 can be formed by the same process as that of the upper electrode UE and can be disposed on the same layer as the layer of the upper electrode UE. The fifth contact hole CH5 can penetrate through the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50, and the sixth contact hole CH6 can penetrate through the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50.

[0161] Although the second part DL-P2 can be formed by the same process as that of the connection electrode CNE and can be disposed on the same layer as the layer of the connection electrode CNE, the exemplary embodiments of the present invention are not limited thereto. The second part DL-P2 can be formed by the same process as that of the anode AE and can be disposed on the same layer as the layer of the anode AE. Referring to Figure 9 , the display panel DP may include a light blocking pattern LSP, wherein the light blocking pattern LSP is disposed between the fifth insulating layer 50 and the sixth insulating layer 60 and overlaps with the second semiconductor pattern OSP2 (for example, along a third direction DR3 that can be orthogonal to the upper surface of the base layer BL).

[0162] The light blocking pattern LSP may include a material having a relatively high light absorption rate or a relatively high light reflectivity. The light blocking pattern LSP may be disposed above the second semiconductor pattern OSP2 to block the light generated by the organic light emitting diode OLED and then reflected from entering the second semiconductor pattern OSP2.

[0163] The light blocking pattern LSP may include the same material as that of the connection electrode CNE. For example, the light blocking pattern LSP may include a metal.

[0164] As described above, the leakage current of the switching transistor can be reduced. Therefore, the voltage-current accuracy and reliability of the driving transistor can be improved. Since the input and output electrodes of the driving transistor disposed on the same layer as the input and output electrodes of the switching transistor can be directly connected to the silicon semiconductor pattern through contact holes penetrating the insulating layer, the occurrence of misalignment can be reduced or eliminated.

[0165] Since the groove can be defined in the inorganic layer of the bending region and the organic layer can be disposed in the corresponding groove, the bending region of the display panel can have improved flexibility. Since the organic layer can be disposed in each of the bending region and the non-bending region, the display panel can have a simplified structure (for example, it can be manufactured using a relatively small number of etching masks).

[0166] Since the process of forming contact holes exposing a part of the semiconductor pattern disposed on the display region and the process of removing the insulating layer of the bending region can be performed in a single process, the number of masks used in the manufacturing process can be reduced. Since the input and output electrodes of the switching transistor and the input and output electrodes of the driving transistor can be formed in a single process, the manufacturing process can be simplified.

[0167] Although the present invention has been shown and described with reference to exemplary embodiments of the present invention, those of ordinary skill in the art will clearly understand that various changes can be made in form and detail without departing from the scope and spirit of the present invention.

Claims

1. Display panel, comprising: a base layer, the base layer including a first region and a second region, wherein the second region extends from and is curved from the first region; at least one inorganic layer, the at least one inorganic layer overlapping with the first region and the second region and disposed on the base layer; a first thin film transistor, the first thin film transistor disposed on the at least one inorganic layer and including a silicon semiconductor pattern overlapping with the first region and a first gate located above the silicon semiconductor pattern, the silicon semiconductor pattern including a first input region, a first output region, and a first channel region disposed between the first input region and the first output region, the first gate overlapping with the first channel region; a second thin film transistor, the second thin film transistor disposed on the at least one inorganic layer, and wherein the second thin film transistor includes an oxide semiconductor pattern overlapping with the first region and a second gate located below the oxide semiconductor pattern, the oxide semiconductor pattern including a second input region, a second output region, and a second channel region disposed between the second input region and the second output region; a plurality of insulating layers, the plurality of insulating layers overlapping with the first region and the second region; signal lines, the signal lines electrically connected to the first thin film transistor and the second thin film transistor; an organic layer, the organic layer overlapping with the first region and the second region and having a single-layer structure; a connection electrode, disposed on the organic layer and electrically connected to the first output region; and a light-emitting element, the light-emitting element disposed on the organic layer, overlapping with the first region and electrically connected to the connection electrode, and wherein, an opening is defined in the at least one inorganic layer and the plurality of insulating layers, and the opening is positioned in the second region, a part of the organic layer is disposed in the opening, the connection electrode is in contact with the organic layer, a part of the signal line is disposed on the part of the organic layer and the part of the signal line is in contact with the part of the organic layer, the plurality of insulating layers includes a first insulating layer between the first thin film transistor and the second thin film transistor, the silicon semiconductor pattern is disposed below the first insulating layer, and the oxide semiconductor pattern is disposed above the first insulating layer.

2. The display panel according to claim 1, wherein, the silicon semiconductor pattern and the oxide semiconductor pattern are disposed on different layers from each other.

3. The display panel according to claim 1, wherein, the opening penetrates through the at least one inorganic layer and the plurality of insulating layers.

4. The display panel according to claim 1, wherein, the organic layer contacts the base layer through the opening.

5. The display panel according to claim 1, wherein, the connection electrode is electrically connected to the first output region through a contact hole penetrating through at least one insulating layer of the organic layer and the plurality of insulating layers.

6. The display panel according to claim 5, further comprising: A passivation layer, the passivation layer being disposed on the organic layer.

7. The display panel according to claim 6, wherein, an electrode of the light-emitting element is electrically connected to the connection electrode through a contact hole formed in the passivation layer.

8. The display panel according to claim 6, wherein, the passivation layer is disposed on the signal line, and a part of the passivation layer overlaps with the second region.

9. The display panel according to claim 1, wherein, the plurality of insulating layers include: a second insulating layer that covers an upper surface of the silicon semiconductor pattern of the first thin-film transistor; a third insulating layer that is disposed on the first insulating layer and covers an upper surface and side surfaces of the second gate; and a fourth insulating layer that is disposed on the third insulating layer and covers the oxide semiconductor pattern of the second thin-film transistor.

10. The display panel according to claim 9, wherein, the oxide semiconductor pattern of the second thin-film transistor is disposed on the third insulating layer.

11. The display panel according to claim 9, wherein, the second thin-film transistor further includes a first electrode and a second electrode, and the second input region and the second output region of the oxide semiconductor pattern are respectively disposed on the first electrode and the second electrode.

12. The display panel according to claim 9, wherein, the second thin-film transistor further includes a first electrode and a second electrode, and the first electrode and the second electrode are respectively disposed above the second input region and the second output region, and the second channel region is exposed from the first electrode and the second electrode.

13. The display panel according to claim 9, further comprising: an upper electrode that is disposed between the first insulating layer and the third insulating layer and overlaps with the first gate.

14. The display panel according to claim 1, wherein, the at least one inorganic layer includes a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer and the silicon oxide layer are alternately disposed.

15. The display panel according to claim 1, wherein, a part of a top surface of the at least one inorganic layer is in direct contact with the organic layer.

16. The display panel according to claim 1, wherein, the opening includes inclined surfaces and step portions defined in each of the inclined surfaces.

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