Semiconductor device

Abstract

In these embodiments, a semiconductor device includes a substrate having a well structure with n-type doping, and an epitaxial silicon germanium fin formed on the substrate. The epitaxial silicon germanium fin has a lower portion and an upper portion. The germanium content of the lower portion is less than the germanium content of the upper portion. A channel is formed by the epitaxial silicon germanium fin. A gate is formed on the epitaxial silicon germanium fin. Doped source / drain are formed proximate to the channel.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to semiconductor devices and methods of forming them, and more particularly to forming different portions of fins with different germanium contents. Background Technology

[0002] As the semiconductor industry advances to nanometer technology nodes in pursuit of higher device density and better performance, three-dimensional designs such as fin field-effect transistors (FETs) have been adopted in many semiconductor integrated circuit devices. One type of fin field-effect transistor can be fabricated from multiple fin structures extending vertically from the substrate surface. These fin structures are separated by shallow trench isolation regions. Each fin structure has a source / drain region and a channel region formed between the source / drain regions. A metal gate surrounds the channel region of each fin structure, allowing for better current control from three sides of the channel region. Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor device comprising: a substrate having an n-type doped well structure; an epitaxial silicon-germanium fin formed on the n-type doped well structure, wherein the epitaxial silicon-germanium fin has a lower portion and an upper portion, wherein the germanium content of the lower portion is less than the germanium content of the upper portion; a channel located in the epitaxial silicon-germanium fin; and a lightly doped source / drain region formed by the epitaxial silicon-germanium fin. Attached Figure Description

[0004] Figure 1A and Figure 1B These are perspective and cross-sectional views of one stage in the formation of the fin field-effect transistor structure.

[0005] Figure 2 This is a flowchart of a method for forming a semiconductor device in some embodiments.

[0006] Figures 3A to 3D These are cross-sectional views of substrates having n-type and p-type wells in some embodiments.

[0007] Figures 4A to 4C These are cross-sectional views of a substrate having silicon-germanium fins and silicon fins in some embodiments.

[0008] Figures 5A to 5D These are various figures illustrating, in some embodiments, a substrate having silicon-germanium fins and dummy gate stacks formed thereon.

[0009] Figures 6A to 6C These are cross-sectional views of the exposed silicon-germanium fins and dummy gate structure in some embodiments.

[0010] Figure 7 These are cross-sectional views of the doped source / drain electrodes and recessed silicon-germanium fins in some embodiments.

[0011] Figures 8A to 8E These are cross-sectional views of the source / drain in some embodiments.

[0012] Figure 8F This is a graph showing the germanium concentration versus boron concentration in the source / drain electrodes in some embodiments.

[0013] Figure 9 This is a graph showing the germanium concentration in silicon-germanium fins in some embodiments.

[0014] Figure 10 This is a graph showing the germanium concentration in the silicon-germanium source / drain in some embodiments.

[0015] Explanation of reference numerals in the attached figures:

[0016] L1, 792: First silicon-germanium layer

[0017] L2-1, 794: Second silicon-germanium layer

[0018] L2-2, 796: Third silicon-germanium layer

[0019] L3, 797: Cap layer

[0020] 1-1, 2-2, 3-3, 4-4: Plane

[0021] 100: Fin Field-Effect Transistor Structure

[0022] 102: Fins

[0023] 104: Gate structure

[0024] 106: Shielding effect

[0025] 140: Method

[0026] 150, 160, 170, 180: Steps

[0027] 202: Substrate

[0028] 204: n-type well

[0029] 205: p-type trap

[0030] 206: Epitaxial silicon layer

[0031] 206E: Thinned epitaxial silicon layer

[0032] 207, 322: Mask layer

[0033] 209: Seed crystal layer

[0034] 210: Semiconductor alloy film

[0035] 212: Lower part

[0036] 214: Upper part

[0037] 215: Channel

[0038] 216: Padding layer

[0039] 318: Cap layer

[0040] 320: Interface Layer

[0041] 324: Opening

[0042] 330: Contains silicon-germanium fins

[0043] 331: Silicon fins

[0044] 332, 840: Trench

[0045] 340: Insulating materials

[0046] 350: Dummy Gate Stack

[0047] 360: Virtual Gate Structure

[0048] 418: Dielectric layer

[0049] 460: First hard mask layer

[0050] 462: Second hard mask layer

[0051] 670: Compensation spacer

[0052] 680: Gate spacer

[0053] 682: Depression

[0054] 702: Injection

[0055] 790: Source / Drain

[0056] 798: Lightly doped source / drain regions

[0057] 798B: Lightly doped source / drain regions at the bottom

[0058] 798M: Lightly doped source / drain region in the middle

[0059] 798T: Lightly doped source / drain regions at the top

[0060] 820: Etching Stop Layer

[0061] 830, 870: Interlayer dielectric layer

[0062] 850: Gate Stack

[0063] 852: Gate dielectric layer

[0064] 854: Metal backing layer

[0065] 856: Conductive gate

[0066] 860: Dielectric capping layer

[0067] 880: Contact

[0068] 890, 900, 1000: Charts

[0069] 892, 894, 910, 1010: Line segments

[0070] 1020: Top Floor

[0071] 1030: Bottom Layer Detailed Implementation

[0072] The different embodiments or examples provided in this invention can implement different structures of the invention. The specific components and arrangements described are intended to simplify the invention and not limit it. For example, a description of a first component being formed on a second component includes direct contact between the two, or the two being separated by other additional components rather than in direct contact. Furthermore, reference numerals may be repeated in various examples disclosed herein, but these repetitions are only for simplification and clarity and do not represent a identical correspondence between units with the same reference numerals in different embodiments and / or arrangements.

[0073] In addition, spatial relative terms such as "below," "under," "lower side," "above," "upper side," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90° or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0074] Figure 1A and Figure 1B These are perspective and cross-sectional views of a stage in the formation of a fin field-effect transistor structure 100. The fin field-effect transistor structure 100 includes two fins 102 and two gate structures 104 on the fins 102 (which may be gate structures formed by a gate-first process and / or dummy gate structures). The portion of the fins 102 covered by the gate structures 104 defines a transistor channel region. One method of forming a p-type fin field-effect transistor device includes implanting p-type impurities, such as boron, into the fins 102 to form lightly doped source / drain regions. Figure 1B yes Figure 1AA cross-sectional view of plane 1-1, which passes through one of the fins 102 and the gate structure 104. The gate structure 104 provides a shielding effect 106 for the fins 102. Due to the shielding effect 106 of the gate structure 104 on the fins 102, implanted p-type impurities may cause poor impurity concentration levels on the sides and bottom of the fins, potentially forming poorly doped source / drain regions. When the fins 102 are composed of silicon-germanium, the germanium content can reduce the diffusion of boron-type impurities such as boron. For example, as the germanium content of the silicon-germanium fins increases, both the concentration and depth of diffused boron decrease. Poor doping levels on the sides and bottom of the fins 102 can cause high source / drain resistance. Conversely, implanted impurities may cause excessively high impurity concentrations on the top of the fins 102. Excessively high impurity concentrations on the top of the fins 102 can cause impurities to diffuse significantly into the transistor channels, resulting in a short-channel effect. Implanting impurities to form lightly doped source / drain regions may also damage the gate structure 104 and the structure and layers of other substrates.

[0075] These embodiments provide finned field-effect transistor structures comprising silicon-germanium fins. The channel region formed by the silicon-germanium fins has an increased impurity concentration. For example, these embodiments include finned transistor structures and methods of forming them. The method of forming the finned field-effect transistor structure can control the germanium content of the fins, increasing the impurities diffused to the sidewalls and bottom of the fins, and forming impurities in the lightly doped source / drain regions.

[0076] Figure 2 This is a flowchart of method 140, in some embodiments, for forming a semiconductor device (such as a fin field-effect transistor structure) on a substrate. Method 140 will be combined with... Figures 3A to 8F illustrate. Figures 3A to 8F These are figures illustrating various stages in forming a semiconductor device (such as a fin field-effect transistor structure) on a substrate in some embodiments. Figures 3A to 3D These are cross-sectional views of substrate 202 in some embodiments. Substrate 202 may be a semiconductor wafer such as a silicon wafer. Substrate 202 may be modified or additionally comprised of semiconductor elemental materials, semiconductor compound materials, and / or semiconductor alloy materials. For example, examples of semiconductor elemental materials may include, but are not limited to, silicon or germanium, which may be single-crystal or polycrystalline. Examples of semiconductor compound materials include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of semiconductor alloy materials include, but are not limited to, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide.

[0077] An n-type impurity can be doped into the substrate 202 to form an n-type well 204 for a p-type field-effect transistor, and a p-type impurity can be doped into the substrate 202 to form a p-type well 205 for an n-type field-effect transistor. For example, an n-type impurity can be implanted into the substrate 202 through an opening in a developed first photoresist to form the n-type well 204, and other portions of the developed first photoresist mask substrate 202. A p-type impurity can also be implanted into the substrate 202 through an opening in a developed second photoresist to form the p-type well 205. The n-type impurity concentration in the n-type well 204 is between approximately 5 × 10⁻⁶. 16 cm⁻³ to approximately 1×10⁻³ 19 cm -3 The concentration of p-type impurities in p-type trap 205 is between 5 × 10⁻⁶ and 10⁻⁶. 16 cm -3 To approximately 1×10 19 cm -3 between.

[0078] An epitaxial silicon layer 206 can be deposited on a substrate 202, such as on an n-type well 204 and a p-type well 205 in the substrate 202. The deposition method for the epitaxial silicon layer 206 can be chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma-enhanced chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, any other suitable deposition process, or a combination of the above. In some embodiments, the epitaxial silicon layer 206 can be intrinsic silicon (such as undoped silicon).

[0079] A mask layer 207, such as a silicon oxide layer, can be formed on the epitaxial silicon layer 206. The mask layer 207 can be formed by an oxidation process, such as oxidizing the epitaxial silicon layer, and / or a deposition process, such as chemical vapor deposition, physical vapor deposition, spin coating, or similar methods.

[0080] The epitaxial silicon layer 206 on the n-type well 204 can be thinned or removed. In an exemplary example, the epitaxial silicon layer 206 on the n-type well 204 is thinned to form a thinned epitaxial silicon layer 206E. As part of the thinning or removal of the epitaxial silicon layer 206, a photolithography and etching process can be performed to pattern a mask layer 207, such that the mask layer 207 remains on the epitaxial silicon layer 206 on the p-type well 205, but exposes the epitaxial silicon layer 206 on the n-type well 204. By using the patterned mask layer 207 and etching the epitaxial silicon layer 206, the epitaxial silicon layer 206 on the n-type well 204 can be thinned or removed. The etching process can be time-limited or controlled etching, which can be reactive ion etching, neutral beam etching, or another suitable etching process. If the epitaxial silicon layer 206 on the n-type well 204 is thinned rather than completely removed, the thickness of the thinned epitaxial silicon layer 206E can be between about 2 nm and about 20 nm.

[0081] In step 150 of method 140, selective epitaxial growth can be performed to deposit a semiconductor alloy film 210 on the thinned epitaxial silicon layer 206E exposed by the patterned mask layer 207, such as Figure 3B As shown. The elemental content of the semiconductor alloy film 210 varies with depth. An example of the semiconductor alloy film 210 is a silicon-germanium film. Deposition methods include chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma-enhanced chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, any other suitable deposition process, or combinations thereof.

[0082] For example, the selective epitaxial growth process in other embodiments may include in-situ epitaxial deposition and in-situ partial etching processes, which reduce growth on amorphous surfaces and reduce crystal defects in the grown epitaxial film to facilitate selective epitaxial growth on crystalline surfaces. For example, the partial etching process may employ etching gases such as hydrogen chloride, chlorine, other suitable etching gases, and / or any combination thereof. The partial etching process removes amorphous deposited material from amorphous surfaces at a higher rate than it removes epitaxial material. In this way, the epitaxial film can remain primarily on the surface of the thinned epitaxial silicon layer 206E.

[0083] In one example of a silicon-germanium epitaxial growth process, the epitaxial growth process temperature is between about 500°C and about 800°C. In another example, the epitaxial growth process pressure may be between about 1 Torr and about 100 Torr. The process gas may include hydrogen chloride, dichlorosilane, silane, germane, hydrogen, nitrogen, carrier gas, other silicon precursors, other germanium precursors, other etching gases, other carrier gases, or combinations thereof.

[0084] In these embodiments, a seed layer 209 is deposited on a thinned epitaxial silicon layer 206E to facilitate the formation of a semiconductor alloy film 210. For the silicon-germanium semiconductor alloy film 210, the seed layer 209 may comprise silicon, silicon-germanium carbide, silicon-germanium, or other suitable materials. The deposition method for the seed layer 209 may be chemical vapor deposition, physical vapor deposition, epitaxial growth, any other suitable deposition process, or any combination thereof. In these embodiments, the silicon-germanium epitaxial growth process includes a baking process, deposition of the seed layer 209, and growth of the silicon-germanium semiconductor alloy film 210 on the seed layer 209. The process temperatures for the baking process, deposition of the seed layer 209, and growth of the silicon-germanium semiconductor alloy film 210 may be the same or different.

[0085] In other embodiments, the semiconductor alloy film 210 is formed directly on the thinned epitaxial silicon layer 206E without a seed layer. In these embodiments, the deposition method for forming the seed layer can be similar to the deposition method for growing the semiconductor alloy film 210.

[0086] In these embodiments, the semiconductor alloy film 210 is formed by growing a lower portion 212 and an upper portion 214 on an epitaxial silicon layer 206E thinned on an n-type well 204. The lower portion 212 of the semiconductor alloy film 210 is grown close to the n-type well 204, while the upper portion 214 of the semiconductor alloy film 210 is grown on the lower portion 212.

[0087] In these embodiments where the semiconductor alloy film 210 comprises silicon-germanium, the percentage of germanium atoms (also referred to herein as content) in the lower portion 212 of the semiconductor alloy film 210 is lower than the percentage of germanium atoms in the upper portion 214. The low germanium content in the lower portion 212 of the semiconductor alloy film 210 can increase impurities diffused into the lower portion of the silicon-germanium semiconductor alloy film 210. In these embodiments, the higher germanium content in the upper portion 214 of the silicon-germanium semiconductor alloy film 210 results in higher strain at the top of the channel formed from the silicon-germanium semiconductor alloy film 210. In these embodiments, the germanium content in the lower portion 212 of the semiconductor alloy film 210 is between 10% and 30%, for example, between 15% and 25%. In these embodiments, the germanium content in the upper portion 214 of the semiconductor alloy film 210 is between 20% and 40%. The germanium content in the lower portion 212 and the upper portion 214 can increase the electron mobility of the channel defined by the gate structure. The germanium content of the lower portion 212 of the semiconductor alloy film 210 is lower than that of the upper portion 214, which helps to increase the impurity concentration in the lower portion 212. The impurities originate from impurity diffusion from the implanted and / or doped source / drain electrodes. In these embodiments, the germanium content of the lower portion 212 of the semiconductor alloy film 210 may gradually increase from the bottom of the lower portion 212 towards the top of the lower portion 212. In these embodiments, the gradual increase may be a gradually increasing profile. For example, in a gradually increasing profile, the small increase in germanium content is less than or equal to about 0.5%. In these embodiments, the gradual increase may be a stepped increasing profile. For example, in a stepped increasing profile, one or more steps of the germanium content have a large increase greater than or equal to 5%. In some examples, the germanium content increases from about 15% at the bottom of the lower portion 212 to about 25% at the top of the lower portion 212. In these embodiments, the upper portion 214 of the semiconductor alloy film 210 has a consistent or substantially consistent germanium content (e.g., a germanium content varying to 2%), which can improve the strain characteristics of the channel formed by the semiconductor alloy film 210. In some examples, the germanium concentration of the upper portion 214 is consistent, at approximately 25% (2%).

[0088] The lower portion 212 and upper portion 214 of the semiconductor alloy film 210 can be grown to a desired height. In some embodiments, a seed layer 209 is located below the lower portion 212 and upper portion 214, and the height H3 of the seed layer 209, the height H2 of the lower portion 212, and the height of the upper portion 214 define the fin height (H1+H2+H3). In these embodiments, the height H2 of the lower portion 212 is greater than the height H1 of the upper portion. In other words, the height of the lower portion 212 in the final semiconductor device structure is greater than the height of the upper portion 214, which can increase the impurity concentration of the lower portion 212 and increase the impurities diffused into the lower portion 212 of the semiconductor alloy film 210. For example, the height of the lower portion 212 in the final semiconductor device structure can be between about 30 nm and about 60 nm, while the height of the upper portion 214 can be between about 20 nm and about 50 nm. In another embodiment, the ratio between the height of the lower portion 212 and the height of the upper portion 214 may be between about 1:1 and about 10:1. A height ratio between the lower portion 212 and the upper portion 214 may be greater than or equal to 1:1 to provide an upper portion 214 with germanium content, thereby increasing the electron mobility of the channel defined by the gate structure. A height ratio between the lower portion 212 and the upper portion 214 may be less than or equal to 10:1 to provide a fin with germanium content, and the increased concentration of impurities from implantation and / or diffusion in the fin reduces the contact resistance between the lower portion 212 of the fin and the source / drain region.

[0089] By changing deposition parameters such as the temperature of the substrate heater, deposition pressure, and the gas flow rate ratio between the substrate heater and the germanium and silicon precursors, the germanium content of the epitaxially grown semiconductor alloy film 210 in its lower portion 212 can be less than that in its upper portion 214.

[0090] In these embodiments, the first deposition temperature of the lower portion 212 of the silicon-germanium semiconductor alloy film 210 can be between about 600°C and about 750°C, while the second deposition temperature of the upper portion 214 of the silicon-germanium semiconductor alloy film 210 can be between about 550°C and about 650°C. For example, the initial deposition temperature of the lower portion 212 of the silicon-germanium semiconductor alloy film 210 can be about 700°C, and gradually or progressively decrease to a final temperature of about 600°C. For example, the deposition temperature of the upper portion 214 of the silicon-germanium semiconductor alloy film 210 can be fixed at about 600°C.

[0091] In another embodiment, in the step of forming the lower portion 212 of the silicon-germanium semiconductor alloy film 210, the precursor gas and the etching gas have a first ratio; while in the step of forming the upper portion 214 of the silicon-germanium semiconductor alloy film 210, the precursor gas and the etching gas have a second ratio. For example, in the step of forming the lower portion 212 of the silicon-germanium semiconductor alloy film 210, the ratio of germanium precursor to germanium precursor plus etching gas (e.g., GeH4 / (GeH4+HCl)) is between about 0.9 and about 1.0; while in the step of forming the upper portion 214 of the silicon-germanium semiconductor alloy film 210, the ratio of germanium precursor to germanium precursor plus etching gas (e.g., GeH4 / (GeH4+HCl)) is between about 0.6 and about 0.8. In another example, in the step of forming the lower portion 212 of the silicon-germanium semiconductor alloy film 210, the first ratio of silicon precursor to silicon precursor plus etching gas (e.g., SiH4 / (SiH4+Cl2H2Si)) is between about 0.9 and about 1.0; while in the step of forming the upper portion 214 of the silicon-germanium semiconductor alloy film 210, the second ratio of silicon precursor to silicon precursor plus etching gas (e.g., SiH4 / (SiH4+Cl2H2Si)) is between about 0.2 and about 0.6.

[0092] By changing one or more deposition parameters while maintaining the same one or more deposition parameters, the germanium content of the lower portion 212 of the epitaxially grown semiconductor alloy film 210 in this embodiment can be less than the germanium content of the upper portion 214. For example, when growing the lower portion 212, the substrate temperature can be the same, and the ratio between the precursor gas and the etching gas can be changed. In another example, the substrate temperature and the ratio between the precursor gas and the etching gas can be changed when growing the lower portion 212.

[0093] exist Figure 3C In the process, a planarizable substrate 202 can be used, and the planarization process can be a chemical mechanical polishing process. The planarization process can remove... Figure 3B The patterned mask layer 207 is used to smooth the upper surface of the semiconductor alloy film 210 and the epitaxial silicon layer 206.

[0094] A capping layer 318, such as a silicon layer, can be deposited on a planarized substrate. For example, the epitaxial growth method of the capping layer 318 may employ chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma-enhanced chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, any other suitable deposition process, or a combination thereof.

[0095] An interface layer 320, such as silicon oxide, may be formed on at least a portion of the capping layer 318, and / or at least a portion of the capping layer 318 may be consumed to form the interface layer 320. For example, at least a portion of the capping layer 318 may be oxidized to form the silicon oxide interface layer 320. A mask layer 322, such as a silicon nitride layer, may be deposited on the interface layer 320. The interface layer 320 may serve as an adhesion layer between the capping layer 318 and the mask layer 322. The mask layer 322 may serve as a hard mask in a subsequent etching process. The mask layer 322 may be formed using low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other deposition processes. Using suitable photolithography and etching processes, the mask layer 322 may be patterned to form openings 324.

[0096] exist Figure 3D In the process, substrate 202 is etched through opening 324 of mask 322 to form silicon-germanium fins 330 from silicon-germanium semiconductor alloy film 210 and silicon fins 331 from epitaxial silicon layer 206. The formation of silicon-germanium fins 330 and silicon fins 331 can be achieved by etching portions through mask layer 322, interface layer 320, semiconductor alloy film 210, epitaxial silicon layer 206, n-type well 204, and p-type well 205 to form trenches 332. The method of etching trenches 332 to form silicon-germanium fins 330 and silicon fins 331 can be dry etching (such as plasma etching, reactive ion etching, or similar etching) or other etching methods. For example, dry etching may include plasma etching, where the process gas includes, but is not limited to, carbon tetrafluoride, chlorine, nitrogen trifluoride, sulfur hexafluoride, and / or helium.

[0097] Figure 3D Two silicon-germanium fins 330 for forming a p-type field-effect transistor device and a silicon fin 331 for forming an n-type field-effect transistor device are shown, but the number of fins can be adjusted and formed as needed for the application. Although not shown, in some embodiments, the width of the silicon-germanium fins 330 and the silicon fin 331 may increase from the bottom of the fin to the top of the fin. In other embodiments, the fins formed on the p-type well 205 may be silicon carbide fins or fins of other suitable materials to form an n-type field-effect transistor device.

[0098] Figure 9 Chart 900 illustrates the germanium content in the silicon-germanium fin 330 in some embodiments. Line segment 910 represents the percentage germanium atom content in the silicon-germanium fin 330, starting from the top (depth 0) of the silicon-germanium fin 330. As shown in Chart 900, in at least one embodiment, the germanium content at a depth of the upper portion 214 of the silicon-germanium fin 330 is approximately 25%. The germanium content from the top to the bottom of the lower portion 212 of the silicon-germanium fin 330 may smoothly transition from approximately 25% to approximately 15%.

[0099] In step 160 of method 140, a gate structure (such as a gate structure formed by a gate-first process, or a dummy gate structure) may be formed on the silicon-germanium fin 330 and the silicon fin 331 to define Figures 4A to 4C The channel shown. Figures 4A to 4C This is a cross-sectional view of a substrate 202 having silicon-germanium fins 330 and silicon fins 331 in some embodiments. Figure 4A In this process, a removable mask layer 322 is provided. An insulating material 340 can be formed to fill the trench 332 between the silicon-germanium fin 330 and the silicon fin 331. The insulating material 340 can form a shallow trench isolation structure. The insulating material 340 may be composed of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, other dielectric layers, or multiple layers thereof. For example, the insulating material 340 may include a silicon nitride pad layer and silicon oxide deposited on the silicon nitride pad layer.

[0100] The insulating material 340 can be formed using flowable chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, monolayer deposition, plasma pulsed chemical vapor deposition, or other deposition processes. The insulating material can be etched such that individual portions of the silicon-germanium fins 330 and silicon fins 331 protrude from between adjacent insulating materials 340. For example, at least a portion of the lower portion 212 and the upper portion 214 of the silicon-germanium fins 330 can be exposed. The method of etching the insulating material 340 can be dry etching (such as plasma etching, reactive ion etching, or similar etching), wet etching, or other etching methods. In some embodiments, the insulating material 340 surrounds a portion of the silicon-germanium fins 330 including an n-type well, while a portion of the silicon-germanium fins 330 including a semiconductor alloy film 210 protrudes from the insulating material 340. The insulating material 340 forms an isolation structure that can prevent electrical interference or crosstalk between different fins or between different fin field-effect transistor devices.

[0101] exist Figure 4B In this process, a substrate layer 216, such as a silicon substrate layer, can be deposited on the exposed silicon-germanium fin 330 to control germanium diffusion outward from the silicon-germanium fin 330. For example, the deposition thickness of the silicon substrate layer can be between about 0.5 nm and about 5 nm. The substrate layer 216 can be formed by selective epitaxial growth on the silicon-germanium fin 330. The deposition method can include chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma-enhanced chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, any other suitable deposition process, or a combination of the above.

[0102] The dielectric layer 418 may be deposited on the pad layer 216, or directly on the silicon-germanium fins 330 and 331 (if no pad layer is formed). The dielectric layer 218 may comprise silicon oxide, silicon nitride, a high-dielectric-constant dielectric material (if used in a gate-first process), the like, or a multilayer thereof. The high-dielectric-constant dielectric material has a dielectric constant greater than about 7.0 and may comprise metal oxides or metal silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, a multilayer thereof, or a combination thereof. The deposition method of the dielectric layer may be plasma-enhanced chemical vapor deposition, atomic layer deposition, molecular beam deposition, or another compliant deposition process.

[0103] exist Figure 4C In this process, a dummy gate stack 350 can be formed on the dielectric layer 418. The dummy gate stack 350 may include one or more dummy films (such as polysilicon films), which can be formed by deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

[0104] Figures 5A to 5D This is a cross-sectional view of a substrate 202 having silicon-germanium fins 330 and dummy gate stacks 350 formed on the silicon-germanium fins 330 in some embodiments. For clarity, substrate 220 will be described with reference to various stages of forming the silicon-germanium fins 330. It should be understood that similar processes can be used for silicon fins 331 to form n-type field-effect transistor devices. Figure 5A In this configuration, a first hard mask layer 460 and a second hard mask layer 462 are formed on the dummy gate stack 350. A photoresist layer is formed on the second hard mask layer 462, and the photoresist layer is patterned to form a patterned photoresist layer (not shown). Figure 5A As shown, a portion of the dummy gate stack 350 is removed to form a dummy gate structure 360, and the removal method can be a dry etching process.

[0105] Alternatively, a portion of the dummy gate structure 350 and a portion of the dielectric layer 418 may be removed to expose a portion of the silicon-germanium fin 330. In some embodiments, the pad layer 216 may also be exposed. Figure 5B yes Figure 5A A cross-sectional view of the mid-plane 2-2, which extends over the exposed silicon-germanium fins 330 and the exposed padding layer 216. Figure 5C yes Figure 5AThe cross-sectional view in midplane 3-3 extends over the channel 215 formed by the silicon-germanium fin 330 and the pad layer 216, and the dummy gate structure 360. Channel 215 includes portions of the lower portion 212 and the upper portion 214 of the semiconductor alloy film 210, formed within the pad layer 216 and the silicon-germanium fin 330 beneath the dummy gate stack 350. The area covered by the dummy gate structure 360 ​​defines channel 215. Figure 5D yes Figure 5A A cross-sectional view of midplane 4-4, which extends over the exposed silicon-germanium fin 330 and the dummy gate structure 360. In this view, channel 215 includes the upper portion 214 of semiconductor alloy film 210 and a portion of padding layer 216.

[0106] In step 170 of method 140, a doped source / drain may be formed near channel 215, such as Figures 6A to 6C As shown. Figures 6A to 6C This is a cross-sectional view through plane 4-4 of the exposed silicon-germanium fin 330 and the dummy gate structure 360 ​​in some embodiments.

[0107] like Figure 6A As shown, a compensation spacer 670 (such as a silicon nitride compensation spacer) can be formed along the sidewalls of the dummy gate structure 360 ​​before implantation 702 to avoid implantation too close to the metal gate to be formed. In these embodiments, impurities can be implanted to form lightly doped source / drain regions. Performing one or more implantations 702 can introduce impurities into the silicon-germanium fin 330 and the pad layer 216 to form a top lightly doped source / drain region 798T on top of the silicon-germanium fin 330. Implantation 702 may contain implanted boron impurities, such as boron difluoride. The implantation energy can be between approximately 1 keV and approximately 10 keV, and the dose can be between approximately 1 × 10⁻⁶. 13 cm -2 Approximately 1×10 16 cm -2 The tilt angle can be between approximately 0 degrees and approximately 5 degrees, and the depth measured from the top of the silicon-germanium fin 330 is between approximately 10 nm and approximately 20 nm.

[0108] In these embodiments, the step of implanting impurities to form lightly doped source / drain regions can be omitted because subsequent stages of semiconductor device fabrication can form p-type doped source / drain regions and diffuse impurities.

[0109] like Figure 6BAs shown, a layered structure for the gate spacer 680 is compliantly formed on the compensation spacer 670 along the sidewall of the dummy gate structure 360. The gate spacer 680 and the compensation spacer 670 may be composed of the same or different materials. The gate spacer 670 may be composed of silicon carbonitride, silicon nitride, silicon carbide, silicon oxynitride, silicon oxide, other feasible materials, or combinations thereof. The deposition method for the layered structure for the gate spacer 680 may be chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. The layered structure for the gate spacer 680 and the compensation spacer 670 may be anisotropically etched to retain the gate spacer 680 and the compensation spacer 670 along the sidewall of the dummy gate structure 360.

[0110] The silicon-germanium fins 330 not covered by the dummy gate structure 360, gate spacer 680, or compensation spacer 670 are etched to form a recess 682, and the etching method can be a dry etching process and / or a wet etching process. For example, the recess 682 can be formed using an anisotropic wet etchant, such as tetramethylammonium hydroxide. Tetramethylammonium hydroxide produces... <111> The plane is in the recess 682 to form a V-shaped or diamond-shaped recess. In these embodiments, the substrate 202 can be etched using a tetramethylammonium hydroxide etchant containing an aqueous solution, wherein the concentration of tetramethylammonium hydroxide in the aqueous solution is between 1% and 30%, and the etching temperature is between 20°C and 90°C.

[0111] The bottom and / or sidewalls of the recess 682 may have angular, rounded, or flat shapes. The recess 682 formed in the silicon-germanium fin 330 may have a desired depth. For example, the depth of the recess 682 may be between 30 nm and 100 nm. In these embodiments, the recess 682 is formed in at least some portions of the lower portion 212 of the semiconductor alloy film 210.

[0112] like Figure 6C As shown, epitaxial material is deposited in the recess 682 to form a doped source / drain 790. The epitaxial material may be a silicon-containing material such as silicon-germanium, and its formation method may be selective epitaxial growth in the recess 682. In one embodiment, the doped source / drain 790 comprises a first silicon-germanium layer (L1) 792, a second silicon-germanium layer (L2-1) 794, and a third silicon-germanium layer (L2-2) 796. Deposition methods include chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma-enhanced chemical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, any other suitable deposition process, or a combination thereof.

[0113] For example, selective epitaxial growth in one embodiment may include multiple in-situ epitaxial deposition and in-situ partial etching processes to facilitate selective epitaxial growth on crystalline surfaces and reduce crystal defects in the grown epitaxial film. For example, the partial etching process may employ etching gases such as hydrogen chloride, chlorine, other suitable etching gases, and / or any combination thereof. The partial etching process removes amorphous material from amorphous surfaces at a higher rate than it removes epitaxial or crystalline material. In this way, the epitaxial film can be primarily retained on the surface... Figure 6B On the surface of the depression 682.

[0114] In some embodiments, the step of depositing silicon-containing material may include in-situ doping of the silicon-containing material. The dopant species includes p-type impurities such as boron or antimony. In-situ doping may include monolayer doping, solid-state doping, plasma doping, selective epitaxy, or other suitable doping processes. For example, an in-situ boron-doped silicon-germanium source / drain may be formed using a selective epitaxial growth process at a temperature between 550°C and 800°C. In another example, the pressure of the epitaxial growth process may be between 10 Torr and 100 Torr. The process gas may include hydrogen chloride, dichlorosilane, silane, germane, boron difluoride, diborane, hydrogen carrier gas, other silicon precursors, other germanium precursors, other boron precursors, other etching gases, other carrier gases, or combinations thereof. By employing an in-situ doping process, the doping concentration (or level) of the doped source / drain 790 can be controlled as needed. In other embodiments, impurities may be implanted to dope the source / drain 790.

[0115] Figure 7 This is a cross-sectional view of plane 2-2 in some embodiments, passing over the doped source / drain 790 and the recessed silicon-germanium fin 330. The doped source / drain 790 may comprise a first silicon-germanium layer (L1) 792, a second silicon-germanium layer (L2-1) 794, and a third silicon-germanium layer (L2-2) 796. The first silicon-germanium layer 792, the second silicon-germanium layer 794, and the third silicon-germanium layer 796 may be in-situ doped with boron. In these embodiments, the boron concentration of the first silicon-germanium layer (L1) 792 is less than the boron concentration of the second silicon-germanium layer (L2-1) 794, and the boron concentration of the second silicon-germanium layer (L2-1) 794 is less than the boron concentration of the third silicon-germanium layer (L2-2) 796, for example, the boron concentration of the first silicon-germanium layer (L1) 792 < the boron concentration of the second silicon-germanium layer (L2-1) 794 < the boron concentration of the third silicon-germanium layer (L2-2) 796.

[0116] In these embodiments, the first silicon-germanium layer (L1) 792 can be deposited with a boron concentration such as 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3In these embodiments, the second silicon-germanium layer (L2-1) 794 can be deposited with a boron concentration such as 5 × 10⁻⁶. 19 cm -3 Up to 2×10 21 cm -3 In these embodiments, the third silicon-germanium layer (L2-2) 796 can be deposited with a boron concentration such as 1×10⁻⁶. 20 cm -3 Up to 2×10 21 cm -3 .

[0117] Although the doped source / drain 790 shown in the figure has three layers, the doped source / drain 790 is not limited to these layers. In other embodiments, the doped source / drain 790 may include one or two silicon-germanium layers. In other embodiments, the doped source / drain 790 may include additional layers such as a fourth silicon-germanium layer, a fifth silicon-germanium layer, or the like.

[0118] In these embodiments, the doped source / drain 790 may have a capping layer (L3) 797. In these embodiments, the capping layer (L3) 797 helps reduce the outward diffusion of germanium or boron from the first silicon-germanium layer 792, the second silicon-germanium layer 794, and the third silicon-germanium layer 796. The capping layer (L3) 797 may comprise silicon, silicon-germanium, silicon-germanium boride, or other suitable materials. For example, the capping layer (L3) 797 may comprise silicon-germanium boride with a germanium concentration between 45% and 55% and a boron concentration between 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The thickness is between 5nm and 15nm.

[0119] In these embodiments, the doped source / drain 790 comprises silicon germanium, and the germanium content increases from the bottom of the doped source / drain towards the top of the source / drain. For example, the doped source / drain region 790 comprises a bottom layer (such as a first silicon germanium layer (L1) 792) with a germanium concentration between 30% and 50%, and a top layer (such as a third silicon germanium layer (L2-2) 796) with a germanium concentration between 50% and 70%.

[0120] The epitaxially grown doped source / drain 790 has a germanium concentration that increases from the bottom layer to the top layer. The method for forming the source / drain 790 described above can vary deposition parameters such as substrate heater temperature, deposition pressure, or the gas flow rate ratio between the germanium precursor and the silicon precursor. For example, in these embodiments, the first deposition temperature of the bottom layer of the silicon-germanium source / drain region 790 is between 500°C and 600°C, while the second deposition temperature of the top layer of the silicon-germanium source / drain region 790 is between 700°C and 800°C.

[0121] The doped source / drain 790 can induce stress in channel 215. For example, the doped source / drain 790 contains silicon germanium, which can induce compressive stress in the silicon germanium-containing channel 215. In these embodiments, the germanium content of the doped source / drain region 790 is greater than the germanium content of channel 215.

[0122] A capping layer (such as a silicon capping layer) may be formed on the doped source / drain 790, depending on the application. In these embodiments, the capping layer helps protect the underlying silicon-germanium from environmental influences such as oxidation and moisture. The capping layer may also be used to form a better ohmic contact with a metal that forms an electrical contact with the doped source / drain 790.

[0123] Figure 10 Figure 1000 shows the germanium content in the silicon-germanium source / drain 790 in some embodiments. Line segment 1010 represents the percentage of germanium atoms in the silicon-germanium source / drain 790, starting from the top of the source / drain (depth 0). As shown in Figure 1000, the germanium concentration in the top layer 1020 of the silicon-germanium source / drain 790 is approximately 55%, while the germanium concentration in the bottom layer 1030 of the silicon-germanium source / drain 790 is approximately 40%.

[0124] like Figure 7 As shown, the doped source / drain 790 is a merged doped source / drain. In these embodiments, among adjacent doped source / drain 790s, the first silicon-germanium layer (L1) 792 is not merged, while the second silicon-germanium layer (L2-1) 794 and its upper layers (such as the third silicon-germanium layer (L2-2) 796, etc.) are merged. In these embodiments, the unmerged first silicon-germanium layer (L1) 792 and the merged second silicon-germanium layer (L2-1) 794 can improve the induced strain characteristics of channel 215.

[0125] In other embodiments, the doped source / drain may be an unbonded doped source / drain. The doped source / drain 790 may be grown into other shapes depending on the lower surface of the recess 682, and the horizontal and vertical growth of the selective epitaxial growth of the doped source / drain 790.

[0126] Figures 8A to 8E This is a cross-sectional view of plane 4-4 through the source / drain 790 in some embodiments. Figure 8AIn this process, an etch stop layer 820 can be deposited on the source / drain 790, the gate spacer 680, and the dummy gate structure 360. The deposition method for the etch stop layer 820 can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. The etch stop layer 820 may comprise silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, the like, or combinations thereof.

[0127] An interlayer dielectric layer 830 can be deposited on the etch stop layer 820, and its deposition process can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, or plasma-enhanced chemical vapor deposition. For example, the interlayer dielectric layer 830 can be silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or other dielectric layers. Removal processes such as chemical mechanical polishing can be performed to planarize the interlayer dielectric layer 830 and the etch stop layer 820 and remove them. Figure 6C The first hard mask layer 460 and the second hard mask layer 462.

[0128] exist Figure 8B Remove Figure 8A The dummy gate structure 360 ​​is used to form the trench 840, and the removal method can be a dry etching process and / or a wet etching process.

[0129] exist Figure 8C In this process, a gate stack 850 is filled into a trench 840. The gate stack includes a compliant gate dielectric layer 852. The gate dielectric layer 852 may be silicon oxide, silicon nitride, or a multilayer thereof. In these embodiments, the gate dielectric layer 852 may comprise a high dielectric constant dielectric material, such as a gate dielectric layer with a dielectric constant greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, titanium, yttrium, scandium, diurethane, gadolinium, strontium, dysprosium, calcium, or samarium, or combinations thereof. For example, the high dielectric constant dielectric material may comprise, but is not limited to, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, or other feasible dielectric materials. The formation method of the gate dielectric layer 852 may include atomic layer deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0130] The gate stack 850 includes one or more metal pad layers 854, such as capping layers, barrier metal layers, and / or work function metal layers. The capping and barrier metal layers serve to prevent impurities from entering the underlying layers. The capping and / or barrier metal layers may comprise tantalum nitride, titanium nitride, the like, or combinations thereof, and their deposition method may be atomic layer deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0131] The work function layer is selected to adjust its work function, thus forming a transistor with the desired threshold voltage Vt. Examples of work function metal layers for n-type devices include titanium, silver, aluminum tantalum, aluminum tantalum carbide, aluminum titanium nitride, tantalum carbide, tantalum carbonitride, silicon tantalum nitride, manganese, zirconium, other suitable work function materials, or combinations thereof. Examples of work function metal layers for p-type devices include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicon, molybdenum silicon, tantalum silicon, nickel silicon, tungsten nitride, other suitable work function materials, or combinations thereof. Methods for compliantly depositing work function metal layers can include chemical vapor deposition processes, such as atomic layer deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0132] A conductive gate 856 may be formed on a metal pad layer 854. The conductive gate 856 may include a metallic material such as titanium nitride, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, aluminum titanium nitride, aluminum titanium carbide, aluminum titanium oxide, combinations thereof, or multiple layers thereof. The deposition method for the conductive gate 856 may be a suitable process, such as chemical vapor deposition, physical vapor deposition or sputtering, atomic layer deposition, plasma-enhanced chemical vapor deposition, electroplating, or other deposition techniques. The gate stack 850 covers the sides and top of the silicon-germanium fin 330 to form a channel.

[0133] A dielectric capping layer 860, such as a silicon oxynitride layer, can be formed on the conductive gate 856. In other fabrication stages, the dielectric capping layer can be removed, and a contact layer can be deposited on the conductive gate 856.

[0134] like Figure 8D As shown, an interlayer dielectric layer 870 can be deposited on the substrate 202, and the deposition method can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, or plasma-enhanced chemical vapor deposition. For example, the interlayer dielectric layer 870 can be silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or other dielectric layers.

[0135] The interlayer dielectric layer 870 can be patterned to form openings, and then a metal such as copper, tungsten, or other suitable material can be filled into the openings to form contacts 880 that connect the source / drain 790. The deposition method of the contacts 880 can be physical vapor deposition, electroplating deposition, chemical vapor deposition, a combination of the above, or other suitable deposition processes.

[0136] Figure 8E In some embodiments, Figure 8D A partially enlarged view of the lightly doped source / drain regions is shown. In these embodiments, impurities can diffuse from the doped source / drain region 790 into the upper portion 214 to form the middle lightly doped source / drain region 798M. Impurities can diffuse from the doped source / drain region 790 into the lower portion 212 to form the bottom lightly doped source / drain region 798B. The top lightly doped source / drain region 798T is formed primarily by implanting impurities onto the top of the upper portion 214 of the silicon-germanium fin 330. The top lightly doped source / drain region 798T, the middle lightly doped source / drain region 798M, and the bottom lightly doped source / drain region 798B can be collectively referred to as the lightly doped source / drain region 798. The impurity profiles of the intermediate lightly doped source / drain region 798M and the bottom lightly doped source / drain region 798B, formed by impurity diffusion, can continuously decrease from the interface (e.g., the interface between the source / drain 790 and the semiconductor alloy film 210) towards the device channel. The impurity profile of the top lightly doped source / drain region 798T, mainly formed by implantation, can remain substantially consistent before decreasing from the interface (e.g., the interface between the source / drain 790 and the semiconductor alloy film 210) towards the device channel.

[0137] In these embodiments, the widths of the top lightly doped source / drain region 798T, the middle lightly doped source / drain region, and the bottom lightly doped source / drain region 798B are less than or equal to The width of the lightly doped source / drain region 798 depends on the required width of channel 215. A smaller width of the lightly doped source / drain region helps maintain the width of channel 215 to reduce short-channel effects.

[0138] For example, in step 180 of method 140, impurities can diffuse during in-situ doping of the source / drain 790 to the silicon-germanium fin 330 to form a lightly doped source / drain region 798. In these embodiments, annealing processes such as rapid thermal annealing and / or laser annealing can be performed to activate the doped source / drain 790 and / or to diffuse impurities into the silicon-germanium fin 330 to form a lightly doped source / drain region 798. In some embodiments, the annealing temperature is higher than the melting point of the silicon-germanium source / drain 790 and the silicon-germanium fin 330. For example, the annealing temperature may be between about 500°C and about 700°C, and the annealing time may be between about 5 seconds and about 30 seconds. Because the lower portion 212 of the silicon-germanium fin 330 has a lower germanium content, the impurity profile at the bottom of the silicon-germanium fin 330 can be improved, thereby forming lightly doped source / drain regions 798 in at least some portions of the lower portion 212 of the silicon-germanium fin 330. The lightly doped source / drain regions 798 formed in at least some portions of the lower portion 212 of the silicon-germanium fin 330 can improve transistor characteristics.

[0139] Figure 8F This is a graph 890 showing the germanium and boron content in the source / drain 790 in some embodiments. Line segment 892 represents the germanium atomic percentage content in the source / drain 790, starting from the top of the third silicon-germanium layer (L2-2) 796, then to the second silicon-germanium layer (L2-1) 794, the first silicon-germanium layer (L1) 792, and the lower portion 212 of the recessed silicon-germanium fin 330.

[0140] Segment 894 represents the boron concentration in the source / drain 790, starting from the top of the third silicon-germanium layer (L2-2) 796, then extending to the second silicon-germanium layer (L2-1) 794, the first silicon-germanium layer (L1) 792, and the lower portion 212 of the recessed silicon-germanium fin 330.

[0141] exist Figure 8F In the embodiments, the germanium content of the third silicon-germanium layer (L2-2) 796 may be between about 45% and about 65%. The boron content of the third silicon-germanium layer (L2-2) 796 may be between about 1×10⁻⁶. 20 cm -3 Up to 2×10 21 cm -3 The thickness of the third silicon-germanium layer (L2-2) 796 can be between approximately 10 nm and approximately 20 nm.

[0142] exist Figure 8F In the embodiments, the germanium content of the second silicon-germanium layer (L2-1) 794 may be between about 35% and about 55%. The boron content of the second silicon-germanium layer (L2-1) 794 may be between about 5 × 10⁻⁶. 19 cm -3 Up to 2×1021 cm -3 The thickness of the second silicon-germanium layer (L2-1) 794 can be between approximately 30 nm and approximately 40 nm.

[0143] exist Figure 8F In the embodiments, the germanium content of the first silicon-germanium layer (L1) 792 is between about 25% and about 35%. The boron content of the first silicon-germanium layer (L-1) 792 may be between about 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The thickness of the first silicon-germanium layer (L-1)792 can be between approximately 10 nm and approximately 20 nm.

[0144] It should be understood that, Figures 5A to 8F The two fins and two gate structures shown are for illustrative purposes only. The number of fins and gate structures can be any desired number, depending on the application. The gate structure fabrication method described herein uses a gate substitution process; however, those skilled in the art will understand that the gate structure can also be fabricated using a gate-first process. The source / drain fabrication method described herein uses recessed fins, but the source / drain can be fabricated on the doped fins by in-situ doping or implantation without forming a recess within the fins.

[0145] It should be understood that semiconductor devices and their formation methods may also include additional layers such as photoresist layers, mask layers, diffusion barrier layers, capping layers, silicide regions, etch stop layers, dielectric layers, adhesive layers, and other suitable layers. Semiconductor devices and methods may also include additional processes such as photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying, hard baking, inspection, planarization, chemical mechanical polishing, wet cleaning, ashing, and / or other feasible processes.

[0146] It should be understood that p-type field-effect transistor devices can also be integrated into the process of forming n-type field-effect transistor devices. It should be understood that the substrate may include multiple layers (such as conductive layers, semiconductor layers, insulating layers), and / or multiple structures (such as doped regions or well regions, fins, source / drain regions, isolation regions, shallow trench isolation structures, gate structures, interconnect lines, vias, and other suitable structures) formed in and / or on the substrate. Multiple layers and / or structures are used to fabricate semiconductor devices and integrated circuits. In the methods described herein, its steps, and the accompanying drawings, the substrate may also include additional material formed thereon and / or therein.

[0147] like Figures 3A to 8FIn the embodiments shown, the lightly doped source / drain regions 798 of the silicon-germanium fin 330 can have improved impurity characteristics. Since the lower portion 212 of the semiconductor alloy film 210, with its lower germanium content, forms the silicon-germanium fin 330, boron diffuses into the lower portion 212 of the silicon-germanium fin 330. For example, the lower portion of the silicon-germanium fin may contain diffused impurities from the doped source / drain 790 to form the lightly doped source / drain regions 798. Impurities diffused into the upper portion 214 and the lower portion 212 can form a more uniform lightly doped source / drain regions 798 on the silicon-germanium fin 330. This is because the impurity concentration is less affected by the shielding effect of the gate structure 360 ​​(including gate structures formed by gate-first processes, dummy gate structures, or substitution gate structures). Therefore, the critical voltage variation of the fin field-effect transistor device is less. In these embodiments, the impurities in the lightly doped source / drain region 798B at the bottom are increased, thereby reducing the source / drain resistance.

[0148] In these embodiments, a strain-induced doped source / drain 790 can provide a channel 215 with partial or full strain. In these embodiments, the channel 215 and the doped source / drain 790 comprise silicon and germanium, wherein the doped source / drain 790 contains a higher germanium content to induce partial or full strain in the channel 215.

[0149] In these embodiments, an improved interface can be formed between the doped source / drain 790 and the silicon-germanium fin 330, thereby improving transistor characteristics. In these embodiments, recessing the silicon-germanium fin 330 and forming the doped source / drain 790 on the recessed silicon-germanium fin 330 can reduce source / drain resistance.

[0150] In these embodiments, if the silicon-germanium fin 330 has a gradient germanium content, the implantation step for forming lightly doped source / drain regions can be omitted. This avoids excessively high impurity concentration at the top of the silicon-germanium fin 330 in channel 215, thereby reducing short-channel effects.

[0151] In these embodiments, the semiconductor device includes: a substrate having an n-type doped well structure; and an epitaxial silicon-germanium fin formed on the n-type doped well structure. The epitaxial silicon-germanium fin has a lower portion and an upper portion, wherein the germanium content of the lower portion is less than that of the upper portion. Channels are located in the epitaxial silicon-germanium fin. Lightly doped source / drain regions are formed by the epitaxial silicon-germanium fin.

[0152] In one embodiment, the germanium content of the upper portion of the semiconductor device is between about 20% and about 40%.

[0153] In one embodiment, the germanium content of the lower portion of the semiconductor device is between about 10% and about 30%.

[0154] In one embodiment, the germanium content of the lower portion of the semiconductor device increases from the bottom of the lower portion toward the top of the lower portion.

[0155] In one embodiment, the germanium content in the lower portion of the semiconductor device gradually increases.

[0156] In one embodiment, the germanium content in the lower portion of the semiconductor device increases in steps, and the increase in one or more steps is greater than or equal to 5%.

[0157] In one embodiment, the height of the lower portion of the semiconductor device is greater than the height of the upper portion.

[0158] In these embodiments, the semiconductor device includes: an epitaxial silicon-germanium fin formed on a substrate, the epitaxial silicon-germanium fin having a lower portion and an upper portion, wherein the germanium content of the lower portion is less than the germanium content of the upper portion; a channel formed by the epitaxial silicon-germanium fin; a gate formed on the epitaxial silicon-germanium fin; and a doped source / drain formed near the channel.

[0159] In one embodiment, the semiconductor device includes a lightly doped source / drain region formed in the lower portion of an epitaxial silicon-germanium fin, and the region is formed by impurity diffusion from the doped source / drain.

[0160] In one embodiment, the semiconductor device includes a lightly doped source / drain region formed in the upper portion of an epitaxial silicon-germanium fin, and the region is formed by impurity diffusion from the doped source / drain.

[0161] In one embodiment, the semiconductor device includes a lightly doped source / drain region formed in the upper portion of the top of an epitaxial silicon-germanium fin, and the formation method is implantation.

[0162] In one embodiment, the height ratio of the lower portion to the upper portion of the epitaxial silicon-germanium fin of the semiconductor device is between 1:1 and about 10:1.

[0163] In one embodiment, the doped source / drain of the semiconductor device comprises a bottom layer with a germanium content of about 30% to about 50%, and a top layer with a germanium content of about 50% to about 70%.

[0164] In one embodiment, the source / drain electrodes of the semiconductor device are doped with boron or antimony.

[0165] In one embodiment, the doped source / drain of the semiconductor device comprises three or more layers.

[0166] In one embodiment, the doped source / drain of the semiconductor device includes a first layer, a second layer on the first layer, and a third layer on the second layer, wherein the impurity concentration in the third layer is greater than the impurity concentration in the second layer, and the impurity concentration in the second layer is greater than the impurity concentration in the first layer.

[0167] In one embodiment, the germanium content of the doped source / drain of the semiconductor device increases from the bottom of the doped source / drain towards the top of the doped source / drain.

[0168] In these embodiments, the method of forming a semiconductor device includes: forming an epitaxial silicon-germanium fin on an n-type well structure. The epitaxial silicon-germanium fin has a lower portion and an upper portion. The germanium content of the lower portion is lower than that of the upper portion. A dummy gate structure is formed on the epitaxial silicon-germanium fin. A doped source / drain is formed, with the doped source / drain close to a channel. Impurities are diffused from the doped source / drain into the epitaxial silicon-germanium fin to form a lightly doped source / drain region.

[0169] In one embodiment, the above method changes the deposition parameters to form a larger germanium content in the epitaxial silicon-germanium fins, and the deposition parameters are substrate heater temperature, pressure, and the ratio of gas flow rate between the germanium precursor and the silicon precursor.

[0170] In one embodiment, the method for forming a larger germanium content in the epitaxial silicon-germanium fins in the above method is that the first deposition temperature of the epitaxial deposition is between about 500°C and about 750°C, and the second deposition temperature is between about 700°C and about 800°C.

[0171] In these embodiments, the semiconductor device includes: a substrate having an n-type doped well structure; and an epitaxial silicon-germanium fin formed on the n-type doped well structure. The epitaxial silicon-germanium fin has a lower portion and an upper portion, wherein the germanium content of the lower portion is less than that of the upper portion. A channel is formed by the epitaxial silicon-germanium fin. Lightly doped source / drain regions are formed by the epitaxial silicon-germanium fin. The lightly doped source / drain regions are located adjacent to the channel.

[0172] In these embodiments, the semiconductor device includes: a substrate having an n-type well structure; and an epitaxial silicon-germanium fin formed on the n-type well structure. The epitaxial silicon-germanium fin has a lower portion and an upper portion. The germanium content of the lower portion is less than that of the upper portion. A channel is formed by the epitaxial silicon-germanium fin. A gate is formed on the epitaxial silicon-germanium fin. Doped source / drain electrodes are formed near the channel.

[0173] The features of the above embodiments are beneficial for those skilled in the art to understand the embodiments of the present invention. Those skilled in the art should understand that the embodiments of the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A substrate having an n-type doped well structure; An epitaxial silicon-germanium fin is formed on the n-type doped well structure, and the epitaxial silicon-germanium fin has a lower side portion and an upper side portion, wherein the germanium content of the lower side portion is less than the germanium content of the upper side portion, and the germanium content of the lower side portion increases from the bottom of the lower side portion to the top of the lower side portion, while the upper side portion has a uniform germanium content. A padding layer is located on the epitaxial silicon-germanium fin; A channel is located within the epitaxial silicon-germanium fin; A doped source / drain is formed near the channel; as well as A lightly doped source / drain region, formed by the epitaxial silicon-germanium fin and the padding layer, is sandwiched between the doped source / drain and the channel. The lightly doped source / drain region extends into the epitaxial silicon-germanium fin. The lightly doped source / drain region includes a top lightly doped source / drain region, an intermediate lightly doped source / drain region below the top lightly doped source / drain region, and a bottom lightly doped source / drain region below the intermediate lightly doped source / drain region. The top lightly doped source / drain region is formed by an implantation process and has a consistent shape. The doping concentration of the intermediate lightly doped source / drain region and the bottom lightly doped source / drain region are respectively formed by dopants diffused from the doped source / drain to the upper and lower portions. The intermediate lightly doped source / drain region has a doping concentration that decreases from an interface between the doped source / drain and the epitaxial silicon-germanium fin toward the channel. The top lightly doped source / drain region extends from the pad layer into an upper portion of the upper portion, while the intermediate lightly doped source / drain region is located in a lower portion of the upper portion.

2. The semiconductor device of claim 1, wherein the germanium content of the upper portion is between 20% and 40%.

3. The semiconductor device of claim 1, wherein the germanium content of the lower portion is between 10% and 30%.

4. The semiconductor device of claim 1, wherein the germanium content in the lower portion gradually increases.

5. The semiconductor device of claim 1, wherein the germanium content in the lower portion increases in a stepped manner, and the increase in one or more steps is greater than or equal to 5%.

6. The semiconductor device of claim 1, wherein the height of the lower portion is greater than the height of the upper portion.

7. A semiconductor device, comprising: An epitaxial silicon-germanium fin is formed on a substrate. The epitaxial silicon-germanium fin has a lower side portion and an upper side portion, wherein the germanium content of the lower side portion is less than the germanium content of the upper side portion, and the germanium content of the lower side portion increases from the bottom of the lower side portion to the top of the lower side portion, while the upper side portion has a uniform germanium content. A padding layer is located on the epitaxial silicon-germanium fin; A channel is formed by the epitaxial silicon-germanium fin; A gate is formed on the epitaxial silicon-germanium fin and the pad layer; A doped source / drain is formed near the channel; as well as A lightly doped source / drain region is sandwiched between the doped source / drain and the channel. The lightly doped source / drain region extends into the epitaxial silicon-germanium fin and the padding layer. The lightly doped source / drain region includes a top lightly doped source / drain region, an intermediate lightly doped source / drain region below the top lightly doped source / drain region, and a bottom lightly doped source / drain region below the intermediate lightly doped source / drain region. The top lightly doped source / drain region is formed by an implantation process and has a uniform doping concentration. The intermediate lightly doped source / drain region and the bottom lightly doped source / drain region are formed by dopants diffused from the doped source / drain to the upper and lower portions, respectively. The intermediate lightly doped source / drain region has a doping concentration that decreases from an interface between the doped source / drain and the epitaxial silicon-germanium fin toward the channel. The top lightly doped source / drain region extends from the pad layer into an upper portion of the upper portion, while the intermediate lightly doped source / drain region is located in a lower portion of the upper portion.

8. The semiconductor device of claim 7, wherein the height ratio of the lower portion to the upper portion of the epitaxial silicon-germanium fin is between 1:1 and 10:

1.

9. The semiconductor device of claim 7, wherein the doped source / drain comprises a bottom layer with a germanium content of 30% to 50% and a top layer with a germanium content of 50% to 70%.

10. The semiconductor device of claim 7, wherein the doped source / drain is doped with an impurity selected from the group consisting of boron and antimony.

11. The semiconductor device of claim 7, wherein the doped source / drain comprises three or more layers.

12. The semiconductor device of claim 7, wherein the doped source / drain comprises a first layer, a second layer on the first layer, and a third layer on the second layer, wherein the impurity concentration in the third layer is greater than the impurity concentration in the second layer, and the impurity concentration in the second layer is greater than the impurity concentration in the first layer.

13. The semiconductor device of claim 7, wherein the germanium content of the doped source / drain increases from the bottom of the doped source / drain toward the top of the doped source / drain.

14. A method for manufacturing a semiconductor device, comprising: An epitaxial silicon-germanium fin is formed on an n-type well structure. The epitaxial silicon-germanium fin has a lower side portion and an upper side portion, wherein the germanium content of the lower side portion is lower than that of the upper side portion, and the germanium content of the lower side portion increases from the bottom of the lower side portion to the top of the lower side portion, while the upper side portion has a uniform germanium content. A padding layer is formed on the epitaxial silicon-germanium fin; A dummy gate structure is formed on the epitaxial silicon-germanium fin and the pad layer; Implantation is performed to form an upper-side lightly doped source / drain region in the epitaxial silicon-germanium fin and the pad layer; Adjacent to the dummy gate structure, a recess is formed in the epitaxial silicon-germanium fin and the pad layer. The recess passes through the upper lightly doped source / drain region and removes a portion of the upper lightly doped source / drain region to form a top lightly doped source / drain region. A doped source / drain is formed in the recess, and the doped source / drain is close to a channel; as well as Annealing diffuses impurities from the doped source / drain into the epitaxial silicon-germanium fin to form an intermediate lightly doped source / drain region in the upper portion and a bottom lightly doped source / drain region in the lower portion. The intermediate lightly doped source / drain region is located below the top lightly doped source / drain region, and the bottom lightly doped source / drain region is located below the intermediate lightly doped source / drain region. The doping concentration of the intermediate lightly doped source / drain region decreases as it extends from the doped source / drain toward a channel region of the epitaxial silicon-germanium fin. The top lightly doped source / drain region has a uniform doping concentration and extends from the pad layer into an upper portion of the upper portion, while the intermediate lightly doped source / drain region is located in a lower portion of the upper portion.

15. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the greater germanium content of the epitaxial silicon-germanium fin is formed by changing a deposition parameter selected from the group consisting of a substrate heater temperature, a pressure, and a gas flow rate ratio between a germanium precursor and a silicon precursor.

16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the method of forming a larger germanium content in the epitaxial silicon-germanium fin is a first deposition temperature between 500°C and 750°C, and a second deposition temperature between 700°C and 800°C.

17. A semiconductor device, comprising: An epitaxial silicon-germanium fin is formed on a substrate. The epitaxial silicon-germanium fin has a lower side portion and an upper side portion, wherein the germanium content of the lower side portion is less than the germanium content of the upper side portion, and the germanium content of the lower side portion increases from the bottom of the lower side portion to the top of the lower side portion, while the upper side portion has a uniform germanium content. An epitaxial silicon layer is located on the epitaxial silicon-germanium fin; A channel is located within the epitaxial silicon-germanium fin; A gate is formed on the epitaxial silicon-germanium fin and the epitaxial silicon layer; An epitaxial source / drain region is formed along both sides of the gate and the epitaxial silicon layer, and the epitaxial source / drain region is doped with a p-type impurity. as well as A lightly doped drain region is sandwiched between the epitaxial source / drain region and the channel, extending into the epitaxial silicon layer and into the epitaxial silicon-germanium fin. The lightly doped drain region includes a top lightly doped drain region, an intermediate lightly doped drain region below the top lightly doped drain region, and a bottom lightly doped drain region below the intermediate lightly doped drain region. The top lightly doped drain region is formed by an implantation process and has a uniform doping concentration. The intermediate lightly doped drain region and the bottom lightly doped drain region are formed by p-type impurities diffused from the epitaxial source / drain region to the upper and lower portions, respectively. The intermediate lightly doped drain region has a doping concentration that decreases from an interface between the epitaxial source / drain region and the epitaxial silicon-germanium fin towards the channel. The top lightly doped drain region extends from the epitaxial silicon layer into an upper portion of the upper portion, while the intermediate lightly doped drain region is located in a lower portion of the upper portion.

18. The semiconductor device of claim 17, wherein the germanium content of the lower portion is less than that of the epitaxial source / drain region.

19. The semiconductor device of claim 18, wherein the germanium content of the upper portion is less than that of the epitaxial source / drain region.

20. A method for manufacturing a semiconductor device, comprising: An epitaxial silicon-germanium fin is formed on an n-type well structure. The epitaxial silicon-germanium fin has a lower portion and an upper portion, wherein the germanium content of the upper portion is greater than that of the lower portion, and the germanium content of the lower portion increases from the bottom of the lower portion to the top of the lower portion, while the upper portion has a uniform germanium content. A padding layer is formed on the epitaxial silicon-germanium fin; A dummy gate structure is formed in a channel region of the epitaxial silicon-germanium fin and on the pad layer; Implantation is performed to form an upper-side lightly doped source / drain region in the epitaxial silicon-germanium fin and the pad layer; Adjacent to the dummy gate structure, a recess is formed in the epitaxial silicon-germanium fin and the pad layer. The recess passes through the upper lightly doped source / drain region and removes a portion of the upper lightly doped source / drain region to form a top lightly doped source / drain region. A doped source / drain is formed, and the doped source / drain is close to the channel region; as well as Annealing diffuses impurities from the doped source / drain into the epitaxial silicon-germanium fin to form an intermediate lightly doped source / drain region in the upper portion and a bottom lightly doped source / drain region in the lower portion. The intermediate lightly doped source / drain region is located below the top lightly doped source / drain region, and the bottom lightly doped source / drain region is located below the intermediate lightly doped source / drain region. The doping concentration of the intermediate lightly doped source / drain region decreases as it extends from the doped source / drain towards a channel region of the fin. The top lightly doped source / drain region has a uniform doping concentration and extends from the pad layer into an upper portion of the upper portion, while the intermediate lightly doped source / drain region is located in a lower portion of the upper portion.

21. The method of manufacturing a semiconductor device as claimed in claim 20, wherein the greater germanium content of the epitaxial silicon-germanium fin is formed by changing a deposition parameter selected from a group including a substrate heater temperature, a pressure, and a gas flow rate ratio between a germanium precursor and a silicon precursor.

22. The method of manufacturing a semiconductor device as claimed in claim 20, wherein the method of forming a larger germanium content in the epitaxial silicon-germanium fin is a first deposition temperature between 500°C and 750°C, and a second deposition temperature between 700°C and 800°C.

23. The method of manufacturing a semiconductor device as claimed in claim 20, wherein the height of the lower portion is greater than the height of the upper portion.

24. A method for manufacturing a semiconductor device, comprising: A fin is formed protruding from a substrate. The fin has a lower portion and an upper portion, wherein the germanium content of the upper portion is greater than that of the lower portion, and the germanium content of the lower portion increases from the bottom of the lower portion to the top of the lower portion, while the upper portion has a uniform germanium content. A liner is formed on the fin; A gate structure is formed on the fin and the pad layer; Implantation is performed to form an upper-side lightly doped drain region in the fin and the liner layer; Multiple recesses are formed along both sides of the gate structure in the fin and the pad layer. The recesses pass through the upper lightly doped drain region and remove a portion of the upper lightly doped drain region to form a top lightly doped drain region. Multiple source / drain regions are epitaxially grown in the recess, and the source / drain regions include various impurities; as well as Annealing diffuses the impurity from the source / drain region to individual lightly doped drain regions, wherein the lightly doped drain regions include a bottom lightly doped drain region in the lower portion of the fin and an intermediate lightly doped drain region in the upper portion of the fin, the intermediate lightly doped drain region being located below the top lightly doped drain region and the bottom lightly doped drain region being located below the intermediate lightly doped drain region, wherein the doping concentration of the intermediate lightly doped drain region decreases as the intermediate lightly doped drain region extends from the source / drain region toward a channel region of the fin, while the top lightly doped drain region has a uniform doping concentration, the top lightly doped drain region extending from the pad layer into an upper portion of the upper portion, and the intermediate lightly doped drain region being located in a lower portion of the upper portion.

25. The method of manufacturing a semiconductor device as claimed in claim 24, wherein the formation of the fin comprises epitaxially growing one or more semiconductor layers on the substrate.

26. The method of manufacturing a semiconductor device as claimed in claim 25, wherein the epitaxial growth of the one or more semiconductor layers includes epitaxially growing a first silicon-germanium layer on the substrate, the first silicon-germanium layer having a first germanium content.

27. The method of manufacturing a semiconductor device as claimed in claim 26, wherein the epitaxial growth of the one or more semiconductor layers includes epitaxially growing a second silicon-germanium layer on the first silicon-germanium layer, the second silicon-germanium layer having a second germanium content greater than the first germanium content.

28. The method of manufacturing a semiconductor device as claimed in claim 27, further comprising depositing the pad layer on the second silicon-germanium layer.

29. The method of manufacturing a semiconductor device as claimed in claim 24, wherein the gate structure is a dummy gate structure, and further comprising replacing the gate structure with a replacement gate structure.

30. The method of manufacturing a semiconductor device as claimed in claim 24, wherein the source / drain region comprises silicon germanium and the fin comprises silicon germanium, wherein the germanium content of the source / drain region is higher than the germanium content of the fin.

31. The method of manufacturing a semiconductor device as claimed in claim 24, wherein the width of the lightly doped drain region is 5 angstroms or less.

32. The method of manufacturing a semiconductor device as claimed in claim 24, wherein at least a portion of the diffusion of the impurity is performed by a rapid thermal annealing or laser annealing process.

33. The method of manufacturing a semiconductor device as claimed in claim 24, wherein the doping concentration of the bottom lightly doped drain region decreases as the bottom lightly doped drain region extends from the source / drain region toward the channel region.

34. A method for manufacturing a semiconductor device, comprising: A fin is formed that protrudes from a substrate. The fin has a lower portion and an upper portion, wherein the germanium content of the upper portion is greater than that of the lower portion, and the germanium content of the lower portion increases from the bottom of the lower portion to the top of the lower portion, while the upper portion has a uniform germanium content. A liner is formed on the fin; A dummy gate structure is formed on the fin and the pad layer; Implantation is performed to form an upper-side lightly doped drain region in the fin and the liner layer; Adjacent to the dummy gate structure, a recess is formed in the fin and the pad layer. The recess passes through the upper lightly doped drain region and removes a portion of the upper lightly doped drain region to form a top lightly doped drain region. An epitaxial source / drain region is grown in the recess, the source / drain region including various impurities of a first conductivity form; as well as Annealing diffuses the impurity of the first conductivity form from the source / drain region to an intermediate lightly doped drain region in the upper portion of the fin and a bottom lightly doped drain region in the lower portion of the fin. The intermediate lightly doped drain region is located below the top lightly doped drain region, and the bottom lightly doped drain region is located below the intermediate lightly doped drain region. The doping concentration of the impurity of the first conductivity form in the intermediate lightly doped drain region decreases as the intermediate lightly doped drain region extends from the source / drain region toward a channel region of the fin. The top lightly doped drain region has a uniform doping concentration and extends from the pad layer into an upper portion of the upper portion, while the intermediate lightly doped drain region is located in a lower portion of the upper portion.

35. The method of manufacturing a semiconductor device as claimed in claim 34, wherein the fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer includes a semiconductor material different from the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer include silicon germanium with different germanium concentrations.

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