Method of forming a semiconductor structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same. The method includes forming a first insulating material layer in a portion of a trench between a first protrusion structure and a second protrusion structure on a substrate, and performing a pretreatment process on the first insulating material layer. The method also includes performing a first insulating material conversion process on the first insulating material layer, and forming a second insulating material layer to cover the first insulating material layer in the trench. Furthermore, a first distance between an upper portion of the first protrusion portion and the second protrusion portion before the first insulating material conversion process is performed is different from a second distance between the upper portion of the first protrusion portion and the second protrusion portion after the first insulating material conversion process is performed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same, and more particularly to addressing issues of inward or outward bowing of raised structures. BACKGROUND

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced dramatic increases in the functional density of integrated circuits. However, these advances have also resulted in increased complexity of processing and operating these devices. For

[0003] Despite the advances in materials and processing, planar devices such as metal oxide semiconductor field effect transistor devices still face challenges. To overcome these challenges, circuit designers have sought new structures to improve performance, resulting in three-dimensional designs such as fin field effect transistors. Fin field effect transistors have vertical fins (or fin structures) extending from a substrate. Channels of the fin field effect transistors are formed in the vertical fins. Gates are located over the fins so that the gates can control the channels from multiple sides. Advantages of fin field effect transistors include reduced short channel effects, reduced leakage current, and increased current. SUMMARY

[0004] One embodiment of the present application provides a method of forming a semiconductor structure, comprising: forming a first insulating material layer in a portion of a trench between a first raised structure and a second raised structure on a substrate; performing a pre-treatment process on the first insulating material layer; performing a first insulating material conversion process on the first insulating material layer; and forming a second insulating material layer to cover the first insulating material layer in the trench, wherein a first distance between an upper portion of the first raised portion and an upper portion of the second raised portion before the first insulating material conversion process is performed is different from a second distance between the upper portion of the first raised portion and the upper portion of the second raised portion after the first insulating material conversion process is performed. BRIEF DESCRIPTION OF DRAWINGS

[0005] FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , and FIG. 10 are cross-sectional views of various stages in a method of forming a semiconductor structure in some examples.

[0006] FIG. 11AIn some embodiments, the process stages shown in FIGS. 1A-1E are performed. FIG. 10 A perspective view of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 1A-1E.

[0007] FIG. 11B In some embodiments, the process stages shown in FIGS. 2A-2E are performed. FIG. 11A A cross-sectional view along section line A-A' of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 2A-2E. FIG. 10 A perspective view of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 2A-2E.

[0008] FIG. 11C In some embodiments, the process stages shown in FIGS. 3A-3E are performed. FIG. 11A A cross-sectional view along section line B-B' of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 3A-3E. FIG. 10 A perspective view of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 3A-3E.

[0009] FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , and FIG. 5 In some embodiments, the process stages shown in FIGS. 4A-4E are performed.

[0010] FIG. 6 In some embodiments, the process stages shown in FIGS. 5A-5E are performed. FIG. 7 A perspective view of the fin field effect transistor structure of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 5A-5E.

[0011] FIG. 8 In some embodiments, the process stages shown in FIGS. 6A-6E are performed. FIG. 9 A cross-sectional view along section line A-A' of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 6A-6E. FIG. 10 A perspective view of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 6A-6E.

[0012] FIG. 11A In some embodiments, the process stages shown in FIGS. 7A-7E are performed. FIG. 10 A cross-sectional view along section line B-B' of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 7A-7E. FIG. 11B A perspective view of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 7A-7E.

[0013] FIG. 11A , FIG. 10 , FIG. 11C , FIG. 11A , FIG. 10 , and FIG. 1 In some embodiments, the process stages shown in FIGS. 8A-8E are performed.

[0014] FIG. 1 In some embodiments, the process stages shown in FIGS. 9A-9E are performed. FIG. 2 A perspective view of the fin field effect transistor structure of the semiconductor structure at a stage in the formation process after the process stages shown in FIGS. 9A-9E.

[0015] FIG. 1 In some embodiments, along the FIG. 2 Cross-sectional view along the section line A-A' of Fig. 1, which is a stage in the method of forming the semiconductor structure shown in Fig. 1. FIG. 1 Cross-sectional view along the section line B-B' of Fig. 1, which is a stage in the method of forming the semiconductor structure shown in Fig. 1.

[0016] FIG. 1 In some embodiments, along the FIG. 3 Cross-sectional view along the section line B-B' of Fig. 1, which is a stage in the method of forming the semiconductor structure shown in Fig. 1. FIG. 4 Cross-sectional view along the section line B-B' of Fig. 1, which is a stage in the method of forming the semiconductor structure shown in Fig. 1.

[0017] Legend:

[0018] Section line A-A', B-B'

[0019] Distance D1, D2, D3, D4, D5, D6

[0020] Height H1, H2

[0021] First pitch P1

[0022] Second pitch P2

[0023] Thickness T1, T2, T3

[0024] 200 substrate

[0025] 204 fin structure

[0026] 205, 255 sidewall surface

[0027] 206 isolation structure

[0028] 207, 217, 227, 235, 287, 322, 383 upper surface

[0029] 208 patterned pad oxide

[0030] 209 patterned pad nitride

[0031] 210 patterned mask

[0032] 211-1, 211-2 trench

[0033] 213 bottom

[0034] 218 gate spacer

[0035] 220 source / drain structure

[0036] 221 contact etch stop layer

[0037] 222, 260 interlayer dielectric layer

[0038] 226 insulating material

[0039] 228 opening

[0040] 230, 252 gate dielectric layer

[0041] 232 gate

[0042] 234 dummy gate structure

[0043] 236 mask pattern

[0044] 240 source / drain silicide layer

[0045] 242 adhesion layer

[0046] 244 contact plug

[0047] 254 gate layer

[0048] 256 metal gate structure

[0049] 280 liner layer

[0050] 282, 382 first insulating material layer

[0051] 282-1, 382-1 first processed insulating material layer

[0052] 282-2, 382-2 first converted insulating material layer

[0053] 286 second insulating material layer

[0054] 286-1 second converted insulating material layer

[0055] 311 gap

[0056] 320 insulating material layer

[0057] 320-1 processed insulating material layer

[0058] 320-2 converted insulating material layer

[0059] 370, 470 pre-processing process

[0060] 372, 374 insulating material conversion process

[0061] 378 annealing process

[0062] 500A, 500B, 500C fin field effect transistor

[0063] 600A, 600B, 600C semiconductor structure DETAILED DESCRIPTION

[0064] Different embodiments provided below can implement different structures of the present application. The embodiments of particular structures and arrangements are used to simplify the present application and are not meant to limit the embodiments of the present application. For example, the statement that a first structure is formed on a second structure includes both direct contact and other intervening structures disposed between the two structures. In addition, various instances of the present application can repeat reference numerals, but these repetitions are merely used to simplify and clarify the description and do not imply that the elements with the same reference numerals have the same correspondence between different embodiments and / or arrangements.

[0065] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", or the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0066] The present application describes some embodiments. Additional steps can be performed before, during, and / or after the steps described in these embodiments. Different embodiments can replace or omit some of the steps described. Additional structures can be added to the semiconductor device structures. Different embodiments can replace or omit some of the structures described below. Although the steps of some embodiments are performed in a particular sequence, these steps can be performed in another logical sequence.

[0067] The fins can be patterned by any suitable method. For example, the method of patterning the fins can employ one or more photolithography processes, including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography and a self-alignment process that produces a pattern pitch that is smaller than the pattern pitch produced using a single, direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and employs a photolithography process to pattern the sacrificial layer. A self-alignment process is employed to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed and the remaining spacers are employed to pattern the fins.

[0068] Embodiments of the present application provide semiconductor structures and methods of forming the same. An insulating material layer can be formed on a space between two raised structures in a semiconductor structure, and an insulating material conversion process can be performed on the insulating material layer. The raised structures can be curved outwardly or inwardly by the insulating material conversion process to counteract stress in subsequent processes, to adjust the shape of the raised structures, and thus to improve the performance of the semiconductor structure. The raised structures can be fin structures, gate structures, or the like.

[0069] FIG. 3 、 FIG. 3 、 FIG. 4 、 FIG. 5 、 FIG. 4 、FIG. 4 、 FIG. 6 、 FIG. 1 to FIG. 4 、 FIG. 7 、With FIG. 5 are cross-sectional views of various stages of a method of forming a semiconductor structure 600A in some embodiments. Notably, the cross-sectional views of the semiconductor structure are across the channel direction of a fin structure (e.g., fin structure 204) of the semiconductor structure. FIG. 6 are perspective views of the semiconductor structure 600A at stages in the formation process after the process stages shown in FIG. 3 . FIG. 6 are cross-sectional views along section line A-A' of FIG. 7 , which are cross-sectional views of the semiconductor structure 600A at stages in the formation process after the process stages shown in FIG. 8 . FIG. 7 are cross-sectional views along section line B-B' of FIG. 9 , which are cross-sectional views of the semiconductor structure 600A at stages in the formation process after the process stages shown in FIG. 8 .

[0070] In some embodiments, a gate replacement (gate-last) process is employed to fabricate a semiconductor structure 600A, such as a fin field effect transistor structure. The substrate 200 included in the semiconductor structure 600A can be used to form a fin field effect transistor 500A thereon.

[0071] As shown in FIG. 10 , a substrate 200 including a fin structure is received. In some embodiments, the substrate 200 can be a semiconductor substrate, such as a semiconductor bulk, a semiconductor-on-insulator substrate, or the like, which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 200 can be a wafer, such as a silicon wafer. In general, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer can be located on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as a multi-layer substrate or a compositionally graded substrate, can also be employed. In some embodiments, the semiconductor material of the substrate 200 can include silicon, germanium, a semiconductor compound (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide indium), or a combination thereof. In some embodiments, the substrate 200 can include silicon.

[0072] In some embodiments, the substrate 200 can be used to form a p-type device or an n-type device. For example, the p-type device can be a p-type metal oxide semiconductor field effect transistor, and the n-type device can be an n-type metal oxide semiconductor field effect transistor. In this way, the fin field effect transistor 500 can be referred to as a p-type fin field effect transistor or an n-type fin field effect transistor.

[0073] As shown in some embodiments, FIG. 11A The fin structures 204 are raised portions (raised from the main surface of the substrate 200) of the substrate 200. In some embodiments, the fin structures 204 are formed by a patterning process using the patterned masks 210 as etching masks. For example, each patterned mask 210 includes a patterned pad oxide 208 and a patterned pad nitride 209. The portions of the substrate 200 not covered by the patterned masks 210 can be removed to form trenches 211-1 and 211-2. The patterned pad oxide 208 and the patterned pad nitride 209 can be formed on the substrate 200. The patterned pad oxide 208 can be silicon oxide formed by a thermal oxidation process. The patterned pad nitride 209 can be a patterned adhesion layer between the substrate 200 and the underlying patterned pad oxide 208. For example, the patterned pad nitride 209 can be composed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, the like, or a combination thereof, and can be formed by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.

[0074] In some embodiments, the fin structures 204 can be configured to have different pitches. For example, some of the fin structures 204 are separated from each other by the trenches 211-1 and can be configured to have a first pitch P1. The first pitch P1 can be equal to the minimum (critical) space between two adjacent fin structures defined by design rules. In some embodiments, the first pitch P1 is between about 20 nm and about 50 nm. Some of the fin structures 204 are separated from each other by the trenches 211-2, which can be configured to have a second pitch P2, and the second pitch P2 is different from the first pitch P1. The second pitch P2 can be greater than the first pitch P1. The trenches 211-1 and 211-2 can have different widths to correspond to the pitches of the fin structures 204 (e.g., the first pitch P1 and the second pitch P2). For example, the width of the trenches 211-1 is less than the width of the trenches 211-2.

[0075] As shown in some embodiments, FIG. 10In some embodiments shown, a padding layer 280 is formed to pad the sidewall surface 205 of the fin structure 204 (exposed from the patterned mask 210). The padding layer 280 may be compliantly formed on the fin structure 204. The padding layer 280 may contain a suitable dielectric material that reduces or avoids oxidation of the fin structure. In some embodiments, the padding layer 280 is composed of a nitride-containing material. For example, the padding layer 280 may be a single layer of silicon nitride or silicon oxynitride, or a multilayer (comprising layers of silicon oxide and silicon nitride and / or silicon oxynitride). In some embodiments, the padding layer 280 is formed by a deposition process including chemical vapor deposition, physical vapor deposition, atomic layer deposition, similar methods, or combinations thereof.

[0076] like FIG. 11B In some embodiments shown, a first insulating material layer 282 is then compliantly formed on the fin structure 204. In some embodiments, the first insulating material layer 282 is formed in portions of trenches 211-1 and 211-2 between the fin structures 204. Furthermore, the first insulating material layer 282 is compliantly formed on the padding layer 280.

[0077] The first insulating layer 282 may be silicon oxide formed by low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or flowable chemical vapor deposition. In flowable chemical vapor deposition, a dielectric material in a flowable form is deposited. As the name suggests, the flowable dielectric material can flow during deposition to fill gaps or spaces with high aspect ratios. Various chemicals are typically added to the silicon-containing precursor to make the deposited film flowable. In some embodiments, hydrogen nitride bonds are added. In some embodiments, the flowable dielectric precursor (particularly a flowable silicon oxide precursor) comprises silicates, methylsilsesquioxanes, hydrosilsesquioxanes, methylsilsesquioxanes and hydrosilsesquioxanes, perhydrosilazanes, perhydropolysilazanes, tetraethoxysilanes, or silylamines such as trisilylamines.

[0078] For example, the flowable dielectric precursor used to form the first insulating layer 282 may comprise a perhydropolysilazane. In some embodiments, the thickness T1 of the first insulating layer 282 may be between about 1 nm and about 5 nm.

[0079] like FIG. 10 Some embodiments shown depict a first insulating material layer 282 ( FIG. 11A) to form a first treated insulating material layer 282-1. The pre-treatment process 370 can employ an ultraviolet light source (e.g., an ultraviolet lamp). Further, the ultraviolet light (wavelength less than about 400 nm) used in the pre-treatment process 370 can come from the ultraviolet light source that helps to break the silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer 282 and promote the formation of silicon-silicon bonds. In some embodiments, after performing the pre-treatment process 370, silicon-silicon bonds are formed in the first treated insulating material layer 282-1. The volume of the first treated insulating material layer 282-1 can be less than the volume of the first insulating material layer 282. Thus, the thickness T2 of the first treated insulating material layer 282-1 can be less than the thickness T1 of the first insulating material layer 282. FIG. 11A For example, the thickness T2 of the first treated insulating material layer 282-1 can be between about 0.5 nm to about 4.5 nm. In some embodiments, the pre-treatment process 370 can last between about 3 minutes to about 10 minutes, such as about 4 minutes.

[0080] As shown in some embodiments, FIG. 11B A second insulating material layer 286 is then formed to cover a portion of the first treated insulating material layer 282-1 and fill the bottom of the trench 211-1. In some embodiments, the second insulating material layer 286 is formed on the sidewall bottom of the fin structure 204. In some embodiments, the material and / or process of the second insulating material layer is similar or the same as the material and / or process of the first insulating material layer 282. For example, the second insulating material layer 286 is a flowable chemical vapor deposition process formed silicon oxide.

[0081] Because the aspect ratio of the trench 211-1 is greater than the aspect ratio of the trench 211-2 (because the width of the trench 211-1 is less than the width of the trench 211-2), the second insulating material layer 286 deposited by the flowable chemical vapor deposition process can first fill the trench 211-1 but not the trench 211-2. Thus, controlling the process time of the flowable chemical vapor deposition can control the second insulating material layer 286 to fill a portion of each trench 211-1 but not a portion of the trench 211-2. In some embodiments, the upper surface 287 of each second insulating material layer 286 is lower than the upper surface 207 of the fin structure 204. In some embodiments, the upper surface 287 of each second insulating material layer 286 is at about one-third to about one-fourth of the height H1 of each fin structure 204. Further, the height H1 is the distance between the upper surface 207 of the fin structure 204 and the lower surface of the trench 211-1 (or the trench 211-2).

[0082] As shown in some embodiments, FIG. 11CSome embodiments are shown, followed by the first treated insulating material layer 282-1 and the second insulating material layer 286 ( FIG. 11A An insulating material conversion process 372 is performed on the first treated insulating material layer 282-1. This process helps to break the silicon-silicon bonds in the first treated insulating material layer 282-1 and the silicon-nitrogen and silicon-hydrogen bonds in the second insulating material layer 286. Furthermore, the process 372 can convert silicon-silicon bonds, silicon-nitrogen bonds, and silicon-hydrogen bonds into silicon-oxygen bonds. Therefore, after the process 372, the first treated insulating material layer 282-1 can be converted into a first-converted insulating material layer 282-2. Similarly, the second insulating material layer 286 can be converted into a second-converted insulating material layer 286-1. Furthermore, after the process 372, silicon-oxygen bonds are formed in both the first-converted insulating material layer 282-2 and the second-converted insulating material layer 286-1. After the process 372, the volume of the first-converted insulating material layer 282-2 can be increased. In some embodiments, the thickness T2 of the insulating material layer 282-1 after the first treatment prior to the insulating material conversion process 372 is smaller than the thickness T3 of the insulating material layer 282-2 after the first conversion following the insulating material conversion process 372. For example, the thickness T3 of the first-converted insulating material layer 282-2 may be between about 1 nm and about 5 nm. Furthermore, after the insulating material conversion process 372, the second-converted insulating material layer 286-1 may be densified.

[0083] After the insulation material conversion process 372, the first converted insulation material layer 282-2 can use the second converted insulation material layer 286-1 as a fulcrum to apply an outward bending force to the fin structure 204 adjacent to the trench 211-1. The outward bending force can bend the fin structure 204, so that the sidewalls of the fin structure 204 before and after the insulation material conversion process 372 extend in different directions. In some embodiments, the sidewalls of the fin structure 204 before the insulation material conversion process 372 extend in a first direction, while the sidewalls of the fin structure 204 after the insulation material conversion process 372 extend in a second direction, which is different from the first direction. In some embodiments, the upper surface 287 of each second insulation material layer 286 is located at approximately one-third to one-quarter of the height H1 of each fin structure 204. The trench 211-1 may have sufficient space to allow the tensile stress induced by the first converted insulating material layer 382-2 and the second converted insulating material layer 286-1 to cause the upper portion of the adjacent fin structure 204 to bend outward. In some embodiments, the distance D1 between the upper portions of the adjacent fin structures 204 prior to the insulating material conversion process 372 is... FIG. 11B), unlike the distance D2 between the upper portions of adjacent fin structures 204 after the insulation material conversion process 372. FIG. 11C Since the insulating material layer 286-1 of the second conversion is located at the bottom 213 of the trench 211-1, the distance D2 can be greater than the distance D1.

[0084] In some embodiments, the insulation material conversion process 372 includes an annealing process or a plasma treatment process. For example, the annealing process may include a wet annealing process, such as a wet steam annealing process, followed by a dry annealing process. In some embodiments, the wet annealing process is a wet steam annealing process (e.g., a hot annealing process performed in a steam-containing environment), with a temperature range between about 400°C and about 700°C, and a duration between about half an hour and about four hours. For example, in the wet annealing process, oxygen from the wet steam can oxidize the first treated insulation material layer 282-1 and the second insulation material layer 286. Furthermore, a dry annealing process is performed in a nitrogen-containing atmosphere, with a temperature range between about 600°C and about 800°C, and a duration between about one hour and about two hours. For example, the plasma treatment process may include an induced-coupled plasma treatment process. The process gas used in the induced-coupled plasma treatment process may include argon, oxygen, helium, hydrogen, ammonia, or the like.

[0085] like FIG. 11A In some embodiments shown, insulating material 226 is then formed to cover the insulating material layer 282-2 of the first transition in trench 211-1. FIG. 11C Insulating material 226 is completely formed on the fin structure 204. Furthermore, insulating material 226 is formed to fill trenches 211-1 and 211-2. FIG. 11A The insulating material 226 is covered with fin-like structure 204, padding layer 280, first-conversion insulating material layer 282-2, and second-conversion insulating material layer 286-1. The insulating material 226 may be composed of oxides such as silicon oxide, nitrides, similar substances, or combinations thereof, and its formation method may be high-density plasma chemical vapor deposition, flowable chemical vapor deposition, similar methods, or combinations thereof. Other insulating materials and / or other formation processes may also be used.

[0086] like FIG. 11B In some embodiments shown, an additional insulation material conversion process 374 is then performed to harden (densify) the insulation material 226. The insulation material conversion process 374 can form silicon-oxygen bonds in the insulation material 226. Furthermore, the insulation material conversion process 374 facilitates further hardening (densification) of the first-converted insulation material layer 282-2 and the second-converted insulation material layer 286-1. The conditions for the insulation material conversion process 374 can be the same as those for the insulation material conversion process 372, therefore the relevant details are not repeated here.

[0087] In some embodiments, the process of forming the shallow trench isolation material (e.g., the insulating material 226) can induce a tensile stress to the adjacent fin structures (e.g., the fin structures 204). As a result, the adjacent fin structures can bend inward. The inwardly bent fin structures disposed next to the narrow trenches (e.g., the trenches 211-1) can result in a narrow distance between the upper portions of the adjacent fin structures. As such, it can be difficult to fill the gate structures into the gap between the inwardly bent fin structures. To address the above issue, the process (including the flowable chemical vapor deposition process of the insulating material, the ultraviolet pre-treatment process, and the insulating material conversion process) can be performed to form the first converted insulating material layer 282-2 and the second converted insulating material layer 286-1 to compensate for the fin inward bending effect. Before the insulating material 226 is formed, the first converted insulating material layer 282-2 and the second converted insulating material layer 286-1 can together exert an outward bending force to the adjacent fin structures 204. After the insulating material conversion process 374 of the shallow trench isolation material (e.g., the insulating material 226) is performed, the densified insulating material 226 can cause the outwardly bent fin structures (e.g., the fin structures 204 next to the trenches 211-1) to bend inward. As such, as shown in some embodiments, the fin structures 204 can be straight. The sidewalls of the fin structures 204 can extend along different directions before and after the insulating material conversion process 374 is performed. In some embodiments, the sidewalls of the fin structures 204 before the insulating material conversion process 374 is performed extend along a second direction, while the sidewalls of the fin structures 204 after the insulating material conversion process 374 is performed extend along a third direction, and the third direction is different from the second direction. FIG. 11C FIG. 11A

[0088] FIG. 11B FIG. 11C FIG. 10 FIG. 11A

[0089] FIG. 11B ​​​​​​​​Some embodiments are shown. The insulating material 226, the first-transformed insulating material layer 282-2, and the padding layer 280 above the upper surface of the fin structure 204 are then removed using a planarization process. Planarization processes such as chemical mechanical polishing can be performed until the upper surface 217 of the patterned mask 210 is exposed. After the planarization process, the upper surface 227 of the insulating material 226 can be aligned with the upper surface 217 of the patterned mask 210.

[0090] like FIG. 11C Some embodiments shown depict the removal of patterned mask 210 using a removal process. FIG. 11C The patterned pad nitride 209. In some embodiments, the etching process includes a wet etching process using phosphoric acid. Thus, an opening 228 formed in the insulating material 226 exposes the upper surface of the patterned pad oxide 208. Furthermore, a removal process can remove portions of the pad layer 280 and the first-transformed insulating material layer 282-2 above the upper surface of the fin structure 204.

[0091] like FIG. 11A Some embodiments shown employ an etching process to make the insulating material 226 ( FIG. 11A A recess is formed to create an isolation structure 206, such as a shallow trench isolation structure. The isolation structure 206 may cover the lower portion of the fin structure 204, while the upper portion of the fin structure 204 is higher than the isolation structure 206. Furthermore, the etching process may remove the padding layer 280 and the first-transformed insulating material layer 282-2 above the upper portion of the fin structure 204. Additionally, the upper surface of the isolation structure 206 may be flush with the upper surface 287 of the second-transformed insulating material layer 286-1. In some embodiments, the etching process includes a dry etching process using etching gases including ammonia and hydrofluoric acid.

[0092] like FIG. 7 In some embodiments shown, dummy gate structures 234 are subsequently formed on the channel regions of the fin structure 204. Each dummy gate structure 234 may include a gate dielectric layer 230 and a gate 232 on the gate dielectric layer 230. The dummy gate structure 234 may be formed by a deposition process followed by a patterning process (using a mask pattern 236 on the dummy gate structure 234).

[0093] The gate dielectric layer 230 may be silicon oxide. For example, silicon oxide is a thermally grown oxide. In some embodiments, the gate dielectric layer 230 is composed of a high-dielectric-constant dielectric material. The dielectric constant of the high-dielectric-constant dielectric material is higher than that of silicon oxide. Examples of high-dielectric-constant dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, silicon oxynitride, hafnium-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-dielectric-constant material, or combinations thereof. In some embodiments, the gate 232 comprises polysilicon, polysilicon germanium, metal nitride, metal silicide, metal oxide, metal, or other suitable layers. In some embodiments, the gate 232 is composed of polysilicon. For example, the mask pattern 236 may be composed of silicon nitride or the like.

[0094] FIG. 12 It is a perspective view, which is used for... FIG. 13 Following the process stages shown, the fin field-effect transistor 500A of the semiconductor structure 600A is in the formation process stage. FIG. 14 and 11C Is to carry out FIG. 15 Following the process stages shown, the fin field-effect transistor 500A of the semiconductor structure 600A is formed during the process stage. In some embodiments, the p-type metal-oxide-semiconductor region and the n-type metal-oxide-semiconductor region are subjected to... FIG. 16 , 11B The process is the same as shown in 11C, and some materials (such as dopants for the source / drain regions, or the work function layer of the metal gate) are adjusted to conform to the device shape in individual regions (such as p-type fin field-effect transistors or n-type fin field-effect transistors).

[0095] like FIG. 12 , FIG. 13 ,and FIG. 14 In some embodiments shown, gate spacers 218 are subsequently formed on the sidewalls of the dummy gate structure 234, extending onto the fin structure 204. The gate spacers 218 may comprise a single layer or multiple layers. The gate spacers 218 may be composed of a material with a low dielectric constant (e.g., dielectric constant less than 5), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, another suitable material, or a combination thereof. In some embodiments, the gate spacers 218 are formed by a deposition process followed by an etching process. The deposition process may include chemical vapor deposition, physical vapor deposition, spin coating, another feasible process, or a combination thereof. The etching process may include a dry etching process.

[0096] like FIG. 15 , FIG. 16 ,and FIG. 17AIn some embodiments shown, a source / drain structure 220 is then formed in the fin structure 204. The source / drain structure 220 is formed by etching the fin structure 204 to form a recess (not shown), followed by epitaxial growth of material in the recess. The epitaxial growth of the material can be performed using suitable methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, similar methods, or combinations thereof. In some embodiments, the source / drain structure 220 formed in a p-type metal-oxide-semiconductor region (e.g., for a p-type fin field-effect transistor) comprises silicon germanium and p-type impurities (e.g., boron or indium). In some embodiments, the source / drain structure 220 formed in an n-type metal-oxide-semiconductor region (e.g., for an n-type fin field-effect transistor) comprises silicon carbide, silicon phosphide, phosphorus-doped silicon carbide, or the like.

[0097] like FIG. 16 and FIG. 17B In some embodiments shown, a contact etch stop layer 221 is subsequently deposited compliantly on the source / drain structure 220 and the gate spacer 218 using a thin-film deposition process. The contact etch stop layer 221 can serve as an etch stop layer for subsequent etch processes forming source / drain contact vias (not shown). In some embodiments, the contact etch stop layer 221 can be a single layer or multiple layers. The composition of the contact etch stop layer 221 can be silicon carbide, silicon nitride, silicon carbonitride, silicon carbide, silicon carbonitride, tetraethoxysilane oxide, or another feasible material. In some embodiments, the contact etch stop layer 221 has a bilayer structure comprising a tetraethoxysilane oxide layer formed on a silicon carbide layer. The tetraethoxysilane oxide layer has a higher moisture barrier capability than the silicon carbide layer. Furthermore, the silicon carbide layer can serve as an adhesion layer to improve adhesion between the underlying layer and the tetraethoxysilane oxide layer. In some embodiments, the contact etch stop layer 221 is formed by plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, or another feasible process.

[0098] like FIG. 17A , FIG. 16 ,and FIG. 17C In some embodiments shown, an interlayer dielectric layer (such as interlayer dielectric layer 222) is then formed on the fin structure 204. Interlayer dielectric layer 222 may be formed on the contact etch stop layer 221, the first transition insulating material layer 282-2, and the second transition insulating material layer 286-1. Furthermore, interlayer dielectric layer 222 may fill the gaps between the dummy gate structures 234. The composition of interlayer dielectric layer 222 may be a dielectric material such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or flowable chemical vapor deposition.

[0099] As FIG. 17A , FIG. 16 , and FIG. 13 illustrate, the dummy gate structures 234 are replaced with metal gate structures 256 in a gate replacement process. In the gate replacement process, the dummy gate structures 234 FIG. 1 ) and the mask pattern 236 are replaced with the metal gate structures 256 by a removal process, a deposition process, and a subsequent planarization process. In some embodiments, the metal gate structures 256 surrounded by the gate spacers 218 include a gate dielectric layer 252 and a gate layer 254 on the gate dielectric layer 252. The source / drain structures 220 can be adjacent to the metal gate structures 256. In some embodiments, the gate spacers 218 are on the sidewall surfaces on both sides of the metal gate structures 256.

[0100] In some embodiments, the gate dielectric layer 252 includes a single layer or multiple layers. In some embodiments, the gate dielectric layer 252 is U-shaped or rectangular. In some embodiments, the gate dielectric layer 252 is composed of silicon oxide, silicon nitride, or a high-k dielectric material (a dielectric constant greater than 7.0) such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or a combination thereof. The formation of the gate dielectric layer 252 can include molecular beam deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, or the like.

[0101] In some embodiments, the gate layer 254 is composed of a metal-containing material such as titanium nitride, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, a combination thereof, or multiple layers thereof, and its formation can be a deposition process such as electroplating, electroless plating, or another suitable method.

[0102] In some embodiments, a work function layer (not shown) can be formed in each of the metal gate structures 256. The work function layer can include an n-type work function layer or a p-type work function layer. The p-type work function layer can include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, another suitable p-type work function material, or a combination thereof. The n-type work function layer can include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, another suitable n-type work function material, or a combination thereof. For example, the work function layer in one of the metal gate structures 256 can include a p-type work function layer, while another of the metal gate structures 256 can include an n-type work function layer.

[0103] As FIG. 13 , FIG. 12 , and FIG. 14In some embodiments shown, an additional interlayer dielectric layer (such as interlayer dielectric layer 260) is formed on interlayer dielectric layer 222 and metal gate structure 256. For example, interlayer dielectric layer 260 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, interlayer dielectric layer 260 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0104] like FIG. 13 In some embodiments shown, a source / drain silicide layer 240 is formed on the source / drain structure 220 by a patterning process followed by a silicide process. A patterning process can be performed to form openings (not shown) through the interlayer dielectric layers 222 and 260 and the contact etch stop layer 221 to expose the source / drain structure 220. For example, the patterning process includes a photolithography process followed by an etching process. The photolithography process may include applying photoresist (e.g., spin coating), soft baking, aligning a mask, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). In some embodiments, the etching process is a dry etching process. The silicide process may include a sequential metal deposition process and an annealing process. In some embodiments, the deposition process of the silicide process includes a physical vapor deposition process, an atomic layer deposition process, or another feasible process. In some embodiments, the annealing process temperature of the silicide process ranges from about 300°C to about 800°C. After the annealing process, unreacted metal material is removed.

[0105] In some embodiments, the source / drain silicide layer 240 is composed of cobalt silicide (such as CoSi, CoSi2, Co2Si, or Co3Si, collectively referred to as cobalt silicide), titanium silicide (such as Ti5Si3, TiSi, TiSi2, TiSi3, or Ti6Si4, collectively referred to as titanium silicide), or nickel silicide (such as Ni3Si, Ni...). 31 Si 12 Ni2Si, Ni3Si2, NiSi, or NiSi2 are collectively referred to as nickel silicides, and copper silicides (such as Cu). 17 Si3, Cu 56 Si 11 Cu5Si, Cu 33 Si7, Cu4Si, Cu 19 Si6, Cu3Si, or Cu 87 Si 13 One or more of the following: copper silicides, tungsten silicides (such as W5Si3 or WSi2, collectively referred to as tungsten silicides), and molybdenum silicides (such as Mo3Si, Mo5Si3, or MoSi2, collectively referred to as molybdenum silicides).

[0106] As FIG. 15 With 11C In some embodiments, as shown in FIG. 1C, an adhesion layer 242 and a contact plug 244 are formed through the ILD layers 222 and 260 and connected to the source / drain structure 220. The adhesion layer 242 surrounds the contact plug 244, respectively. The ILD layers 222 and 260 surround the contact plug 244. In addition, the contact plug 244 is formed on the source / drain structure 220. Furthermore, the contact plug 244 can be electrically connected to the source / drain structure 220.

[0107] In some embodiments, the adhesion layer 242 and the contact plug 244 are formed by a deposition process, followed by a planarization process such as chemical mechanical polishing. The adhesion layer 242 can comprise a conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, or the like, and it can be formed by a chemical vapor deposition process such as plasma-enhanced chemical vapor deposition. However, other processes such as sputtering or metal-organic chemical vapor deposition, physical vapor deposition, or atomic layer deposition can also be used to form the adhesion layer 242. In some embodiments, the contact plug 244 can comprise cobalt. In some other embodiments, the contact plug 244 can comprise a conductive material such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or another suitable material. The contact plug 244 can be formed by any suitable deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or plating such as electroplating.

[0108] After the above processes are performed, the finFET 500A is formed on the fin structure 204. In addition, as FIG. 13 , 11B , and 11C, a semiconductor structure 600A comprising the finFET 500A (such as a p-type finFET or an n-type finFET) is formed.

[0109] In some embodiments, before the shallow trench isolation structure (such as the isolation structure 206) is formed, the semiconductor structure 600A employs the first converted insulating material layer 282-2 and the second converted insulating material layer 286-1 to apply a tensile stress to the adjacent fin structure 204 next to the trench 211-1. Thus the fin structure 204 can be curved outwardly. After the conversion process of the shallow trench isolation material (such as the insulating material conversion process 374) is performed, the densified insulating material 226 can allow the curved outwardly fin structure to be curved inwardly. Thus, as shown in some embodiments of FIG. 1D, after the shallow trench isolation structure (such as the isolation structure 206) is formed, the fin structure 204 can be straightened. In addition, the straightened fin structure 204 can facilitate the subsequent filling process of dummy gate material or metal gate material, and can increase the tolerance of the gate filling process. The above method can improve the device performance. FIG. 13 In some embodiments, before the shallow trench isolation structure (such as the isolation structure 206) is formed, the semiconductor structure 600A employs the first converted insulating material layer 282-2 and the second converted insulating material layer 286-1 to apply a tensile stress to the adjacent fin structure 204 next to the trench 211-1. Thus the fin structure 204 can be curved outwardly. After the conversion process of the shallow trench isolation material (such as the insulating material conversion process 374) is performed, the densified insulating material 226 can allow the curved outwardly fin structure to be curved inwardly. Thus, as shown in some embodiments of FIG. 1D, after the shallow trench isolation structure (such as the isolation structure 206) is formed, the fin structure 204 can be straightened. In addition, the straightened fin structure 204 can facilitate the subsequent filling process of dummy gate material or metal gate material, and can increase the tolerance of the gate filling process. The above method can improve the device performance.

[0110] FIG. 14 , FIG. 15 , FIG. 15 , FIG. 15 ,and FIG. 14 It is a cross-sectional view along the channel direction across the fin structure 204. FIG. 15 , FIG. 16 , FIG. 16 , FIG. 17A ,and FIG. 16 These are some of the stages of the method for forming the semiconductor structure 600B in some embodiments. FIG. 17B It is a perspective view, which is used for... FIG. 17A Following the process stages shown, the fin field-effect transistor 500B of the semiconductor structure 600B is in the formation process stage. FIG. 16 It is along FIG. 17C The sectional view along the middle section line A-A' is for... FIG. 17A Following the process stages shown, the semiconductor structure 600B is in the formation process stage. FIG. 16 It is along FIG. 17A A sectional view along section line B-B', which is for... FIG. 17A Following the process stages shown, the semiconductor structure 600B is in the formation process stage.

[0111] like FIG. 17B In some embodiments shown, after the liner layer 280 is formed, a first insulating material layer 382 is formed in portions of the trenches 211-1 between the fin structures 204. Since the aspect ratio of trenches 211-1 is greater than that of trenches 211-2, the first insulating material layer 382 formed by the flowable chemical vapor deposition process can fill trenches 211-1 first, but not trenches 211-2. Therefore, by controlling the process time of the flowable chemical vapor deposition process, the first insulating material layer 382 can fill a portion of each trench 211-1, but not a portion of each trench 211-2. In some embodiments, the first insulating material layer 382 fills the bottom 213 of the trench 211-1. In some embodiments, the upper surface 383 of each first insulating material layer 382 may be lower than the upper surface 207 of the fin structure 204. For example, the upper surface 383 of the first insulating material layer 382 may be located at approximately one-third to one-quarter of the height H1 of the fin structure 204.

[0112] In some embodiments, the material and / or process of the first insulating layer 382 may be consistent with... FIG. 17C The first insulating layer 282 is made of a similar or identical material and / or process. For example, the first insulating layer 382 is silicon oxide formed by a flowable chemical vapor deposition process.

[0113] like FIG. 10 Some embodiments are shown, followed by the first insulating material layer 382 (FIG. 11A A pretreatment process 470 (such as an ozone pretreatment process) is performed on the insulating material layer 382 to form a first treated insulating material layer 382-1. The pretreatment process 470 can break some of the silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer 382. Furthermore, the pretreatment process 470 can convert silicon-nitrogen bonds and silicon-hydrogen bonds into silicon-oxygen bonds. Therefore, after the pretreatment process 470, silicon-oxygen bonds can be formed in the first treated insulating material layer 382-1. The volume of the first treated insulating material layer 382-1 can be the same as the volume of the first insulating material layer 382 after the pretreatment process 470. In some embodiments, the pretreatment process 470 may use a process gas containing argon, ozone, oxygen, helium, nitrogen, or the like. The process temperature range is between 25°C and 500°C.

[0114] like FIG. 11B Some embodiments are shown, followed by the first treated insulating material layer 382-1 ( FIG. 11C An insulating material conversion process 372 is performed on the first treated insulating material layer 382-1. This process helps to break the remaining silicon-nitrogen and silicon-hydrogen bonds in the first treated insulating material layer 382-1. Furthermore, the process 372 converts the silicon-nitrogen and silicon-hydrogen bonds into silicon-oxygen bonds. Therefore, after the insulating material conversion process 372, the first treated insulating material layer 382-1 can be converted into a first-converted insulating material layer 382-2. Compared to the first treated insulating material layer 382-1, the first-converted insulating material layer 382-2 has a denser structure and a reduced volume.

[0115] exist FIG. 17A In some embodiments shown, after the insulation material conversion process 372, compressive stress can be applied to the adjacent fin structure 204 of the first converted insulation material layer 382-2. The upper surface 383 of each first insulation material layer 382 (see...) FIG. 17B The trench 211-1 may be located at approximately one-third to one-quarter of the height H1 of the fin structure 204. The trench 211-1 may have sufficient space to allow the compressive stress induced by the first-transformed insulating material layer 382-2 to cause the upper portion of the adjacent fin structure 204 to bend inward. In some embodiments, prior to the insulating material transformation process 372, there may be a distance D1 between the upper portions of adjacent fin structures 204 (see...). FIG. 17C After the insulation material conversion process 372, the upper portions of adjacent fin structures 204 may have a distance D2 (see...). FIG. 12 Distance D1 may be different from distance D2. For example, distance D1 may be greater than distance D2.

[0116] like FIG. 13In some embodiments shown, an insulating material 226 is then formed to cover the insulating material layer 382-2 of the first transition in trench 211-1. The insulating material 226 is completely formed on the fin structure 204. Furthermore, the insulating material 226 fills trenches 211-1 and 211-2 (see...). FIG. 14 ), and covers the fin structure 204, the padding layer 280, and the insulating material layer 382-2 of the first conversion.

[0117] like FIG. 18 In some embodiments shown, an insulating material conversion process 374 is then performed to harden or densify the insulating material 226. The insulating material conversion process 374 can form silicon-oxygen bonds in the insulating material 226. Furthermore, the insulating material conversion process 374 facilitates the hardening (densification) of the first-converted insulating material layer 382-2. As previously described, the densification process (such as the insulating material conversion process 374) of the shallow trench isolation material (such as the insulating material 226) can apply tensile stress to adjacent fin structures (such as fin structures 204) disposed next to narrow trenches (such as trenches 211-1). Adjacent fin structures 204 can be further bent inwards. In some embodiments, the distance D2 between the upper portions of adjacent fin structures 204 before the insulating material conversion process 374 ( FIG. 19 ), unlike the distance D3 between the upper portions of adjacent fin structures 204 after the insulation material conversion process 374. FIG. 20 For example, distance D2 can be greater than distance D3.

[0118] like FIG. 21 Some embodiments are shown, after which the patterned mask is removed and the insulating material 226 ( FIG. 22 A recess is formed to create an isolation structure 206. The isolation structure 206 covers the lower portion of the fin structure 204, while the upper portion of the fin structure 204 is higher than the isolation structure 206. Furthermore, an etching process removes a portion of the padding layer 280 that is higher than the upper portion of the fin structure 204. On the other hand, the upper surface of the isolation structure 206 may be flush with the upper surface 383 of the first-transformed insulating material layer 382-2.

[0119] FIG. 23 It is a perspective view, which is used for... FIG. 24A Following the process stages shown, the fin field-effect transistor 500B of the semiconductor structure 600B is in the formation process stage. FIG. 23 It is along FIG. 24B The sectional view along the middle section line A-A' is for... FIG. 24A Following the process stages shown, the fin field-effect transistor 500B of the semiconductor structure 600B is in the formation process stage. FIG. 23 It is along FIG. 24C A sectional view along section line B-B', which is for...FIG. 24A After the process stages shown, the fin field effect transistors 500B of the semiconductor structure 600B are at a stage in the formation process. In some embodiments, the p-type metal oxide semiconductor regions and the n-type metal oxide semiconductor regions are adjusted to conform to the device configuration (e.g., p-type fin field effect transistor or n-type fin field effect transistor) in the respective regions. FIG. 23 、 17B , the processes shown in FIGS. 17A, 17B, 17C, and adjusting some materials (e.g., dopants for the source / drain regions, or work function layers for the metal gates) to conform to the device configuration (e.g., p-type fin field effect transistor or n-type fin field effect transistor) in the respective regions.

[0120] As shown in some embodiments, such as the embodiment shown in FIG. 18A, the processes shown in FIGS. 18A, 18B, 18C, and adjusting some materials (e.g., dopants for the source / drain regions, or work function layers for the metal gates) to conform to the device configuration (e.g., p-type fin field effect transistor or n-type fin field effect transistor) in the respective regions. FIG. 18 、 FIG. 24A , and FIG. 24B , the processes shown in FIGS. 19A, 19B, 19C, and adjusting some materials (e.g., dopants for the source / drain regions, or work function layers for the metal gates) to conform to the device configuration (e.g., p-type fin field effect transistor or n-type fin field effect transistor) in the respective regions. FIG. 18 、 FIG. 18 、 FIG. 18 , and FIG. 1 , similar or identical processes can be performed to form the metal gate structures 256, the gate spacers 218, the source / drain structures 220, the contact etch stop layers 221, the interlayer dielectric layers 222 and 260, the adhesion layers 242, and the contact plugs 244. The metal gate structures 256 are formed on the fin structures 204. For example, the gate spacers 218 can be located on the sidewalls of both sides of the metal gate structures 256. The source / drain structures 220 can be located in the fin structures 204 and on both sides of the metal gate structures 256. In some embodiments, adjacent source / drain structures 220 on the inwardly curved fin structures 204 can merge. The contact etch stop layers 221 can be conformally deposited on the source / drain structures 220 and the gate spacers 218. The interlayer dielectric layers 222 and 260 can be formed on the contact etch stop layers 221 and the first converted insulating material layer 382-2. The source / drain silicide layers 240 can be formed on the source / drain structures 220. The adhesion layers 242 and the contact plugs 244 can be formed through the interlayer dielectric layers 222 and 260 and connect the source / drain structures 220.

[0121] After the above processes are performed, the fin field effect transistors 500B are formed on the fin structures 204. In addition, as shown in some embodiments, such as the embodiment shown in FIG. 20A, the semiconductor structure 600B containing the fin field effect transistors 500B (e.g., p-type fin field effect transistors or n-type fin field effect transistors) is formed. FIG. 2 、 FIG. 19 , and FIG. 18 .

[0122] In some embodiments, the semiconductor structure 600B applies an inwardly curved force (compressive stress) to the adjacent fin structures 204 of the semiconductor structure 600B with the first converted insulating material layer 382-2. The fin structures 204 are configured next to the trenches and are closely spaced from each other. The process of applying the inwardly curved force is shown in FIG. 21A.FIG. 20 、 FIG. 19 、with FIG. 20 a flowable chemical vapor deposition process including an insulating material, an ozone pre-treatment process, and an insulating material conversion process. The inwardly curved fin structure 204 facilitates formation of a merged source / drain structure 220 of the fin field effect transistor 500B. The merged source / drain structure helps to reduce resistance of the contact plug. The above-described method can improve device performance.

[0123] FIG. 18 、 FIG. 18 、 FIG. 20 、 FIG. 21 、 FIG. 20 、with FIG. 22 is a cross-sectional view along the longitudinal direction (channel length direction of the fin field effect transistor) of the fin structure 204 of various stages of a method of forming a semiconductor structure 600C in some embodiments. FIG. 18 to 20 is a perspective view of the semiconductor structure 600C at a stage in the formation process after the process stages shown in FIG. 22 . FIG. 20 is a cross-sectional view along the cross-sectional line A-A’ in FIG. 23 of the fin field effect transistor 500C of the semiconductor structure 600C at a stage in the formation process after the process stages shown in FIG. 20 . FIG. 22 is a cross-sectional view along the cross-sectional line B-B’ in FIG. 18 of the semiconductor structure 600C at a stage in the formation process after the process stages shown in FIG. 22 .

[0124] As shown in some embodiments in FIG. 23 , a substrate 200 including a fin structure 204 is received. An isolation structure (such as the isolation structure 206 shown in FIG. 24A and FIG. 23 ) surrounds a lower portion of the fin structure 204, while an upper portion of the fin structure 204 protrudes from the isolation structure.

[0125] As shown in some embodiments in FIG. 24B , a dummy gate structure 234, a gate spacer 218, a source / drain structure 220, and a contact etch stop layer 221 are then formed on the fin structure 204. The dummy gate structure 234, the gate spacer 218, the source / drain structure 220, and the contact etch stop layer 221 of the semiconductor structure 600C can be similar or identical to the corresponding elements of the semiconductor structure 600A or 600B, and thus relevant details are not repeated here.

[0126] As shown in some embodiments in FIG. 24AIn some embodiments shown, the dummy gate structures 234 are spaced apart by a gap 311. For example, the distance of the gap 311 may be equal to the minimum (critical) space between two adjacent dummy gate structures 234 as defined by design rules.

[0127] like FIG. 23 In some embodiments shown, a flowable chemical vapor deposition process is then performed to fill the bottom of the gap 311 between two adjacent dummy gate structures 234 on the fin structure 204 with an insulating material layer 320. Since the gap 311 can have a high aspect ratio, the insulating material layer 320 deposited by the flowable chemical vapor deposition process can fill the gap 311 first, rather than being deposited outside the dummy gate structures 234. Therefore, by controlling the process time of the flowable chemical vapor deposition process, the insulating material layer can fill a portion of the gap 311. For example, the upper surface 322 of each insulating material layer 320 is lower than the upper surface 235 of the dummy gate structure 234. In some embodiments, the upper surface of each insulating material layer 320 can be located between the upper surface 235 and the lower surface (and) of the dummy gate structure 234. FIG. 24C The upper surface 207 of the fin structure 204 is flush with the fin structure 204. For example, the upper surface 322 of each insulating material layer 320 may be located at about one-third to about one-quarter of the total height H2 of the dummy gate structure 234 and the mask pattern 236.

[0128] In some embodiments, the material and / or process of the insulating layer 320 may be consistent with... FIG. 24A The first insulating layer 282 is made of a similar or identical material and / or process. For example, the insulating layer 320 is silicon oxide formed by a flowable chemical vapor deposition process.

[0129] by FIG. 23 Examples of some embodiments shown are given, followed by the use of insulating material layer 320 (see FIG. 24A A pretreatment process 470 (such as an ozone pretreatment process) is performed on the insulating material layer 320 to form a treated insulating material layer 320-1. The pretreatment process 470 can break some of the silicon-nitrogen and silicon-hydrogen bonds in the insulating material layer 320. Furthermore, the pretreatment process 470 can transfer silicon-nitrogen and silicon-hydrogen bonds into silicon-oxygen bonds. Thus, after the pretreatment process 470, silicon-oxygen bonds can be formed in the treated insulating material layer 320-1. The volume of the treated insulating material layer 320-1 can be the same as the volume of the insulating material layer 320 after the pretreatment process 470.

[0130] Then as FIG. 24B Some embodiments shown depict the treated insulating material layer 320-1 (see...). FIG. 24CThe insulating material conversion process 372 can help break the silicon-nitrogen bonds and silicon-hydrogen bonds remaining in the processed insulating material layer 320-1. In addition, the insulating material conversion process 372 can also convert the silicon-nitrogen bonds and silicon-hydrogen bonds to silicon-oxygen bonds. Thus, after the insulating material conversion process 372, the processed insulating material layer 320-1 can be converted to a converted insulating material layer 320-2. In addition, silicon-oxygen bonds can be formed in the converted insulating material layer 320-2. The converted insulating material layer 320-2 can have a densified structure and a reduced volume.

[0131] As shown in some embodiments, FIG. 24A the upper surface 322 of each insulating material layer 320 can be located at about one-third to about one-fourth of the total thickness H2 of the dummy gate structure 234 and the mask pattern 236. The gap 311 can have enough space such that the compressive stress induced by the converted insulating material layer 320-2 can cause the upper side portions of the adjacent dummy gate structures 234 to bend inward. In some embodiments, the distance D4 between the upper side portions of the adjacent dummy gate structures 234 before the insulating material conversion process 372 is different from the distance D5 between the upper side portions of the adjacent dummy gate structures 234 after the insulating material conversion process 372. For example, the distance D5 is less than the distance D4. FIG. 11A FIG. 24A FIG. 24B

[0132] As shown in embodiments, FIG. 24C the interlayer dielectric layer 222 can be located on the converted insulating material layer 320-2. In this way, the converted insulating material layer 320-2 can be located between the contact etch stop layer 221 and the interlayer dielectric layer 222, and the contact etch stop layer 221 and the interlayer dielectric layer 222 can surround the converted insulating material layer 320-2. In addition, the flowable dielectric material can fill the gaps 311 between the dummy gate structures 234. ​ ​​​The process of depositing a flowable dielectric material can fill small trenches and gaps with high aspect ratios between structures. In some embodiments, the process of depositing the flowable dielectric material includes introducing a silicon-containing compound and an oxygen-containing compound. The silicon-containing compound and the oxygen-containing compound react to form a flowable dielectric material to fill the trenches. The interlayer dielectric layer 222 may be composed of a dielectric material such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or flowable chemical vapor deposition. In some embodiments, the converted insulating layer 320-2 and the interlayer dielectric layer 222 are composed of different materials.

[0133] like ​ In some embodiments shown, an annealing process 378 is then performed to treat (or densify) the interlayer dielectric layer 222. The annealing process 378 converts the flowable dielectric material (at least partially) into a dense oxide material in the interlayer dielectric layer 222. In some embodiments, the annealing process 378 includes a wet steam annealing process (e.g., a thermal annealing process performed in a steam-containing environment) at a temperature ranging from about 500°C to about 700°C for about two to about three hours. For example, in a wet steam annealing process, oxygen from the wet steam helps oxidize the interlayer dielectric layer 222.

[0134] In commonly used gate replacement processes, the densification process (e.g., annealing process 378) of the interlayer dielectric layer (e.g., interlayer dielectric layer 222) can apply tensile stress to the gate spacers of adjacent dummy gate structures, which are configured to be spaced apart by gaps with a high aspect ratio (e.g., gap 311). Therefore, after removing the dummy gate structure, the gate spacers can be bent outwards toward the gaps (not shown), arranged to accommodate the subsequently formed metal gate structure. The outward bending of the gate spacers causes the gap width to narrow. This makes it difficult to fill the gaps between the gate spacers with a metal gate structure (e.g., metal gate structure 256). To solve this problem, a method can be used... ​ The process shown forms a converted insulating material layer 320-2, and includes a flowable chemical vapor deposition process for the insulating material, an ozone pretreatment process, and an insulating material conversion process. Before forming the interlayer dielectric layer, the converted insulating material layer 320-2 may be subjected to an inward bending force (compressive stress) to adjacent gate spacers. This is followed by an annealing process 378 (see...). ​ Afterwards, the densified interlayer electrical layer 222 allows the inwardly bent gate spacers 218 (e.g.) ​ The gate spacers 218, spaced apart by a gap 311, bend outwards. In this way, in some embodiments, the gate spacers 218 can stand upright, facilitating subsequent filling of the metal gate structure 256 (see...).​ The steps are as follows.

[0135] In some embodiments, prior to annealing process 378, the upper portions of adjacent dummy gate structures 234 may have a distance D5 (see...). ​ After annealing process 378, the upper portions of adjacent fin structures 204 may have a distance D6 (see...). ​ The distance D5 may differ from the distance D6. For example, the distance D6 may be greater than the distance D5. Furthermore, prior to the insulation material conversion process 372, there may be a distance D4 between the upper portions of adjacent fin structures 204 (see...). ​ After annealing process 378, a distance D6 may be present between the upper portions of adjacent fin structures 204 (see...). ​ Distance D4 can be the same as distance D6.

[0136] like ​ In some embodiments shown, a metal gate structure 256 is then formed using a gate replacement process to replace the dummy gate structure 234. For example, the gate replacement process may include a removal process, a deposition process, and a subsequent planarization process. Each metal gate structure 256 may include a gate dielectric layer 252 and a gate layer 254 on the gate dielectric layer 252. A source / drain structure 220 may be adjacent to the metal gate structure 256. In some embodiments, gate spacers 218 are located on the sidewall surfaces 255 on both sides of the metal gate structure 256.

[0137] ​ It is a perspective view, which is used for... ​ Following the process stages shown, the fin field-effect transistor 500C of the semiconductor structure 600C is in the formation process stage. ​ It is along ​ The sectional view along the center section line A-A' is for... ​ Following the process stages shown, the fin field-effect transistor 500C of the semiconductor structure 600C is in the formation process stage. ​ It is along ​ A sectional view along section line B-B', which is for... ​ Following the process stages shown, the fin field-effect transistor 500C of the semiconductor structure 600C is formed during the process stage. In some embodiments, the p-type metal-oxide-semiconductor region and the n-type metal-oxide-semiconductor region are subjected to... ​ , ​ ,and ​ The process is shown, and some materials (such as dopants for the source / drain regions or work function layers for the metal gate) are adjusted to conform to the device configuration in individual regions (such as p-type fin field-effect transistors or n-type fin field-effect transistors).

[0138] Afterwards, as shown in some embodiments shown in FIGS. 24A and 24B, a process similar or identical to the process shown in FIG. 11C is performed to form an interlayer dielectric layer 260, a source / drain silicide layer 240, an adhesion layer 242, and a contact plug 244. For example, the interlayer dielectric layer 260 can be formed on the interlayer dielectric layer 222. The source / drain silicide layer 240 can be formed on the source / drain structure 220. The adhesion layer 242 and the contact plug 244 between the metal gate structures 256 can be formed through the interlayer dielectric layer 260, the interlayer dielectric layer 222, and the converted insulating material layer 320-2. The adhesion layer 242 and the contact plug 244 can connect the source / drain structure 220. In addition, the interlayer dielectric layer 260, the interlayer dielectric layer 222, and the converted insulating material layer 320-2 can surround the contact plug 244 between the metal gate structures 256. ​ 24B ​ 11B

[0139] After the above process is performed, a fin field effect transistor 500C is formed on the fin structure 204. In addition, as shown in some embodiments shown in FIGS. 24A and 24B, a semiconductor structure 600C including the fin field effect transistor 500C (e.g., a p-type fin field effect transistor or an n-type fin field effect transistor) is also formed. ​ ​ ​

[0140] In some embodiments, before the interlayer dielectric layer 222 is formed, the semiconductor structure 600C is subjected to an inward bending force (compressive stress) to the adjacent gate spacers 218 with the converted insulating material layer 320-2. After the annealing process 378 is performed, the densified interlayer dielectric layer 222 can allow the inwardly bent gate spacers 218 to bend outwardly. In this way, the gate spacers 218 can stand up and facilitate the subsequent step of filling the metal gate structures 256, and increase the process tolerance of filling the metal gate. The above approach can improve device performance.

[0141] ​​​​​​​As previously described, a method for forming a semiconductor structure (e.g., semiconductor structure 600A and 600B) includes forming a first insulating material layer (e.g., first insulating material layer 282 and 382) in a portion of a trench (e.g., trench 211-1) between a first fin structure and a second fin structure (e.g., fin structures adjacent to trench 211-1) that protrude from a substrate (e.g., substrate 200). The method includes performing a pre-treatment process (e.g., pre-treatment process 370 and 470) and an insulating material conversion process (e.g., insulating material conversion process 372) on the first insulating material layer. Performing the insulating material conversion process on the first insulating material layer can induce a stress (e.g., a compressive stress or a tensile stress) to the adjacent fin structures on the sides of the trench. Thus, a first distance (e.g., distance Dl) between an upper portion of the first fin structure and an upper portion of the second fin structure prior to performing the insulating material conversion process is different from a second distance (e.g., distance D2) between the upper portion of the first fin structure and the upper portion of the second fin structure after performing the insulating material conversion process. The outwardly curved or inwardly curved fin structures after the process of the shallow trench isolation structure can help reshape the shape of the fin structures. For example, the outwardly curved fin structures can facilitate a later filling of dummy gate material or metal material and increase the tolerance of a gate filling process. The inwardly curved fin structures can facilitate formation of a merged source / drain structure of a fin field effect transistor. The above-described method can improve device performance.

[0142] As previously described, a method for forming a semiconductor structure (e.g., semiconductor structure 600C) includes forming an insulating material layer (e.g., insulating material layer 320) on a first gate structure and a second gate structure (e.g., dummy gate structure 234 or metal gate structure 256) between fin structures (e.g., fin structure 204). The method also includes performing a pre-treatment process (e.g., pre-treatment process 470) on the insulating material layer. The method also includes performing an insulating material conversion process (e.g., insulating material conversion process 372) on the insulating material layer. Performing the insulating material conversion process on the insulating material layer prior to forming an interlayer dielectric layer can induce a compressive stress to an adjacent gate spacer (e.g., gate spacer 218). As such, a first distance (e.g., distance D4) between an upper portion of the first gate structure and an upper portion of the second gate structure prior to performing the insulating material conversion process is different from a second distance (e.g., distance D5) between the upper portion of the first gate structure and the upper portion of the second gate structure after performing the insulating material conversion process. An anneal process (e.g., anneal process 378) of the interlayer dielectric layer can cause the inwardly curved gate spacer to curve outwardly. Thus, the gate spacer can stand up and facilitate a later filling of a metal gate structure (e.g., metal gate structure 256) and increase the tolerance of a metal gate filling process.

[0143] Embodiments of semiconductor structures and methods of forming the same are provided. A method for forming a semiconductor structure includes forming a first insulating material layer in a portion of a trench between a first fin structure and a second fin structure that protrude from a substrate. The method includes performing a pretreatment process on the first insulating material layer. The method also includes performing a first insulating material conversion process on the first insulating material layer. A first distance between an upper portion of the first fin structure and the second fin structure prior to performing the first insulating material conversion process is different from a second distance between the upper portion of the first fin structure and the second fin structure after performing the second insulating material conversion process. The method also includes forming a shallow trench isolation structure to cover the first insulating material layer in the trench. Performing the pretreatment process and the first insulating material conversion process on the first insulating material layer prior to the process of the shallow trench isolation structure facilitates filling a gate material or forming a merged source / drain structure. The above-described method can improve device performance.

[0144] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a first insulating material layer in a portion of a trench between a first protruding structure and a second protruding structure on a substrate and performing a pretreatment process on the first insulating material layer. The method also includes performing a first insulating material conversion process on the first insulating material layer and forming a second insulating material layer to cover the first insulating material layer in the trench. In addition, a first distance between an upper portion of the first protruding portion and the second protruding portion prior to performing the first insulating material conversion process is different from a second distance between the upper portion of the first protruding portion and the second protruding portion after performing the first insulating material conversion process.

[0145] In some embodiments, the method further includes forming a gate structure over the first protruding structure and the second protruding structure and extending on the second insulating material layer, wherein the first protruding structure is a first fin structure, the second protruding structure is a second fin structure, and the second insulating material layer is an isolation structure.

[0146] In some embodiments, the first protruding structure is a first gate structure and the second protruding structure is a second gate structure.

[0147] In some embodiments, the method further includes forming a source / drain structure between the first gate structure and the second gate structure and forming an etch stop layer on the source / drain structure, wherein the first insulating material layer covers an upper surface of the etch stop layer and the second insulating material layer covers an upper surface of the first insulating material layer.

[0148] In some embodiments, the method further includes performing a second insulating material conversion process on the second insulating material layer, wherein a third distance between an upper portion of the first protruding structure and the second protruding structure after performing the second insulating material conversion process is substantially equal to the first distance.

[0149] In some embodiments, the method further includes forming a third insulating material layer on the first protrusion structure and the second protrusion structure before forming the first insulating material layer.

[0150] In some embodiments, a thickness of the third insulating material layer before the first insulating material conversion process is performed is less than a thickness of the third insulating material layer after the first insulating material conversion process is performed.

[0151] In some embodiments, the first insulating material layer fills the trench bottom, and an upper surface of the first insulating material layer is lower than upper surfaces of the first protrusion structure and the second protrusion structure.

[0152] In some embodiments, the pre-treatment process is an ozone treatment process, and the first distance is less than the second distance.

[0153] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a first protrusion structure, a second protrusion structure, and a third protrusion structure on a substrate, and performing a deposition process to form a first insulating material between the first protrusion structure and the second protrusion structure, but not between the second protrusion structure and the third protrusion structure. The method further includes performing an insulating material conversion process on the first insulating material to bend the first protrusion structure and the second protrusion structure in opposite directions, and forming a second insulating material layer on the first insulating material layer and between the second protrusion structure and the third protrusion structure. The method further includes performing a second insulating material conversion process on the second insulating material layer. In addition, a distance between the first protrusion structure and the second protrusion structure is less than a distance between the second protrusion structure and the third protrusion structure.

[0154] In some embodiments, the distance between the first protrusion structure and the second protrusion structure is between about 20 nm and about 50 nm.

[0155] In some embodiments, the first protrusion structure bends in a first direction when the first insulating material conversion process is performed, the first protrusion structure bends in a second direction when the second insulating material conversion process is performed, and the first direction is opposite to the second direction.

[0156] In some embodiments, the first protrusion structure is a first fin structure, the second protrusion structure is a second fin structure, the third protrusion structure is a third fin structure, and the second insulating material layer is an isolation structure.

[0157] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a first protrusion structure on a substrate, and a first sidewall of the first protrusion structure extends along a first direction. The method also includes forming a first insulating material layer on a bottom of the first sidewall of the first protrusion structure, and performing a first insulating material conversion process on the first insulating material layer to bend the first sidewall of the first protrusion structure such that the first sidewall of the first protrusion structure extends along a second direction, and the second direction is different from the first direction.

[0158] In one embodiment, the method further includes forming a second insulating material layer on the first insulating material layer, and performing a second insulating material conversion process on the second insulating material layer to extend the first sidewall of the first protrusion structure along a third direction, and the third direction is different from the second direction.

[0159] In one embodiment, the method further includes forming a gate structure over the first protrusion structure, and the gate structure extends on the second insulating material layer.

[0160] In one embodiment, the method further includes forming a second protrusion structure on the substrate, and the first insulating material layer is formed between a bottom of the first sidewall of the first protrusion structure and a bottom of a second sidewall of the second protrusion structure.

[0161] In one embodiment, the first protrusion structure and the second protrusion structure are bent in opposite directions when the first insulating material conversion process is performed.

[0162] In one embodiment, the method further includes performing a pretreatment process on the first insulating material layer before the first insulating material conversion process is performed.

[0163] In one embodiment, the pretreatment process is an ozone treatment process.

[0164] The features of the above embodiments are beneficial for those skilled in the art to understand the present application. Those skilled in the art should understand that other processes and structures can be designed and changed based on the embodiments of the present application to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent replacements do not deviate from the concept and scope of the embodiments of the present application, and can be changed, replaced, or modified without deviating from the concept and scope of the embodiments of the present application.

Claims

1. A method for forming a semiconductor structure, comprising: forming a source / drain structure on a substrate between a first raised structure and a second raised structure; forming a first insulating material layer in a portion of a trench between the first raised structure and the second raised structure and on the source / drain structure; performing a pre-treatment process on the first insulating material layer; performing a first insulating material conversion process on the first insulating material layer to break and convert silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer into silicon-oxygen bonds; forming a second insulating material layer to cover the first insulating material layer in the trench; and forming a contact plug through the first insulating material layer, wherein a first distance between an upper portion of the first raised structure and an upper portion of the second raised structure before the first insulating material conversion process is performed is different from a second distance between the upper portion of the first raised structure and the upper portion of the second raised structure after the first insulating material conversion process is performed, and wherein a topmost surface of the first insulating material layer is lower than an upper surface of the first raised structure before the pre-treatment process is performed.

2. The method for forming a semiconductor structure of claim 1, wherein the first raised structure is a first gate structure and the second raised structure is a second gate structure.

3. The method for forming a semiconductor structure of claim 2, further comprising: forming an etch stop layer on the source / drain structure, wherein the first insulating material layer covers an upper surface of the etch stop layer and the second insulating material layer covers an upper surface of the first insulating material layer.

4. The method for forming a semiconductor structure of claim 1, further comprising: forming a third insulating material layer on the first raised structure and the second raised structure before forming the first insulating material layer.

5. The method for forming a semiconductor structure of claim 4, wherein a thickness of the third insulating material layer before the first insulating material conversion process is performed is less than a thickness of the third insulating material layer after the first insulating material conversion process is performed.

6. The method for forming a semiconductor structure of claim 5, wherein the pre-treatment process is an ozone treatment process and the first distance is less than the second distance.

7. The method for forming a semiconductor structure of claim 1, wherein the contact plug further extends through the second insulating material layer.

8. A method for forming a semiconductor structure, comprising: forming a first raised structure, a second raised structure, and a third raised structure on a substrate; performing a deposition process to form a first insulating material layer between the first raised structure and the second raised structure but not between the second raised structure and the third raised structure; performing an insulating material conversion process on the first insulating material layer to break and convert silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer into silicon-oxygen bonds and to bend the first raised structure and the second raised structure in opposite directions; forming a second insulating material layer on the first insulating material layer and between the second raised structure and the third raised structure; and ​ and performing a second insulating material conversion process on the second insulating material layer to densify the second insulating material layer and the converted first insulating material layer, wherein a distance between the first protruding structure and the second protruding structure is less than a distance between the second protruding structure and the third protruding structure.

9. The method of claim 8, wherein the distance between the first protruding structure and the second protruding structure is between 20 nm and 50 nm.

10. The method of claim 8, wherein the first protruding structure bends in a first direction when the first insulating material conversion process is performed, the first protruding structure bends in a second direction when the second insulating material conversion process is performed, and the first direction is opposite to the second direction.

11. The method of claim 8, wherein the first protruding structure is a first fin structure, the second protruding structure is a second fin structure, the third protruding structure is a third fin structure, and the second insulating material layer is an isolation structure.

12. A method of forming a semiconductor structure, comprising: forming a first protruding structure on a substrate, wherein a first sidewall of the first protruding structure extends along a first direction; forming a first insulating material layer to cover a bottom portion of the first sidewall of the first protruding structure and expose an upper portion of the first sidewall of the first protruding structure; and performing a first insulating material conversion process on the first insulating material layer to break and convert silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer to silicon-oxygen bonds to bend the first sidewall of the first protruding structure along with the exposed upper portion of the first sidewall of the first protruding structure, extend the first sidewall of the first protruding structure along a second direction, and the second direction is different from the first direction.

13. The method of claim 12, further comprising: forming a second insulating material layer on the processed first insulating material layer; and performing a second insulating material conversion process on the second insulating material layer to densify the second insulating material layer and the processed first insulating material layer, and extend the first sidewall of the first protruding structure along a third direction, and the third direction is different from the second direction.

14. The method of claim 13, further comprising: forming a gate structure over the first protruding structure, and the gate structure extends on the second insulating material layer.

15. The method of claim 12, further comprising: forming a second protruding structure on the substrate, wherein the first insulating material layer is formed between a bottom portion of the first sidewall of the first protruding structure and a bottom portion of a second sidewall of the second protruding structure.

16. The method of claim 15, wherein the first protruding structure and the second protruding structure bend in opposite directions when the first insulating material conversion process is performed.

17. The method of claim 16, further comprising: forming a source / drain structure on the first insulating material layer, wherein the source / drain structure overlaps the first and second protrusion structures.

18. The method of forming a semiconductor structure of claim 12, further comprising: performing a pretreatment process on the first insulating material layer before performing the first insulating material conversion process.

19. The method of claim 18, wherein the pretreatment process is an ozone treatment process.

20. A method of forming a semiconductor structure, comprising: forming a first protrusion structure, a second protrusion structure, and a third protrusion structure on a substrate; performing a deposition process to form a first insulating material layer between the first and second protrusion structures, but not between the second and third protrusion structures: performing a first insulating material conversion process on the first insulating material layer to break and convert silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer to silicon-oxygen bonds, and to bend the first and second protrusion structures in opposite directions.

21. The method of claim 20, wherein a first distance between the first and second protrusion structures is less than a second distance between the second and third protrusion structures.

22. The method of claim 20, wherein the first and second protrusion structures are bent in opposite directions during the first insulating material conversion process.

23. The method of claim 20, wherein the first insulating material layer does not cover sidewalls of an upper portion of the first protrusion structure.

24. The method of claim 20, further comprising: forming a liner layer on the first protrusion structure; and forming an oxide layer on the liner layer, wherein the oxide layer is between the liner layer and the first insulating material layer.

25. The method of claim 20, further comprising: performing a pretreatment process on the first insulating material layer before performing the first insulating material conversion process.

26. The method of claim 25, wherein the pretreatment process is an ozone treatment process.

27. The method of claim 20, further comprising: forming a second insulating material layer on the first insulating material layer and between the second and third protrusion structures.

28. The method of claim 20, further comprising: forming a contact plug through the first insulating material layer.

29. The method of claim 20, wherein the first protrusion structure comprises a first gate structure and the second protrusion structure comprises a second gate structure.

30. A method of forming a semiconductor structure, comprising: forming a first protrusion structure and a second protrusion structure on a substrate; ​ forming a first insulating material layer between the first protrusion structure and the second protrusion structure, wherein the first insulating material layer does not cover the first sidewall of the upper portion of the first protrusion structure and the second sidewall of the upper portion of the second protrusion structure; and performing a first insulating material conversion process on the first insulating material layer to break and convert silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer into silicon-oxygen bonds, and to bend the first sidewall of the upper portion of the first protrusion structure and the second sidewall of the upper portion of the second protrusion structure.

31. The method of claim 30, further comprising: forming a liner layer on the first protrusion structure; and forming an oxide layer on the liner layer, wherein the oxide layer is between the liner layer and the first insulating material layer.

32. The method of claim 31, further comprising: forming a pad oxide on an upper surface of the first protrusion structure, wherein the liner layer is formed on sidewalls of the pad oxide, but the first insulating material layer is not on the sidewalls of the pad oxide.

33. The method of claim 30, further comprising: performing a pretreatment process on the first insulating material layer before performing the first insulating material conversion process.

34. The method of claim 30, further comprising: forming a contact plug through the first insulating material layer.

35. A method of forming a semiconductor structure, comprising: forming a first gate and a second gate on a substrate; forming a source / drain structure between the first gate and the second gate; forming a first insulating material layer on the source / drain structure; and performing a first insulating material conversion process on the first insulating material layer to break and convert silicon-nitrogen bonds and silicon-hydrogen bonds in the first insulating material layer into silicon-oxygen bonds, and to bend the first gate and the second gate.

36. The method of claim 35, further comprising: performing a pretreatment process on the first insulating material layer before performing the first insulating material conversion process.

37. The method of claim 36, wherein the pretreatment process is an ozone treatment process.

38. The method of claim 35, further comprising: forming an etch stop layer on the source / drain structure, wherein the first insulating material layer covers an upper surface of the etch stop layer.

39. The method of claim 35, further comprising: forming a contact plug through the first insulating material layer.

Images