Internally stacked NPN with segmented collector

Abstract

The present application discloses an internal stacked NPN with segmented collectors. An integrated circuit (100) includes a stacked NPN (104) having an upper NPN (106) connected to a lower NPN (108). The upper NPN (106) includes an upper collector (110), an upper base (112), and an upper emitter (114). The lower NPN (108) includes a lower collector (116), a lower base (118), and a lower emitter (120). The upper collector (110) includes collector segments (122), (124) on opposite sides of the lower emitter (120). The collector segments (122), (124) are laterally separated by collector separators (126), (132), and the collector separators (126), (132) are aligned with the orientation direction (128) in the collector segments (126), (132). The upper collector (110) has no collector separator that crosses the orientation direction (128).

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits. More specifically, the present disclosure relates to stacked NPN bipolar transistor pairs in integrated circuits. Background Art

[0002] An integrated circuit may include a clamping circuit to reduce voltage stress on a protected line, for example, during an electrostatic discharge (ESD) event. The clamping circuit may include a stacked NPN bipolar transistor pair (stacked NPN) having an upper NPN bipolar transistor (upper NPN) in series with a lower NPN bipolar transistor (lower NPN), wherein the collector of the upper NPN is coupled to the protected line, the emitter of the upper NPN is coupled to the collector of the lower NPN, and the emitter of the lower NPN is coupled to a ground node of the integrated circuit. Desirable characteristics of the clamping circuit may include low resistance and uniform current distribution during an ESD event, low area of ​​the stacked NPN, and consistent breakdown voltage. The integrated circuit may include analog circuits and may include logic circuits of complementary metal oxide semiconductor (CMOS) transistors, and it may be desirable to integrate the clamping circuit in the integrated circuit without introducing additional process steps. However, in an integrated circuit configuration, it is challenging to achieve this resistance value, current uniformity, and breakdown voltage in an integrated circuit with advanced CMOS transistors. Summary of the invention

[0003] The present disclosure introduces an integrated circuit including a stacked NPN bipolar transistor pair (stacked NPN) having an upper NPN bipolar transistor (upper NPN) connected to a lower NPN bipolar transistor (lower NPN). The upper NPN includes a collector (upper collector), a base (upper base), and an emitter (upper emitter). The lower NPN includes a collector (lower collector), a base (lower base), and an emitter (lower emitter). The upper emitter is coupled to the lower collector.

[0004] The upper collector includes collector segments. Each collector segment has an orientation direction pointing to the lower emitter. The collector segments are laterally separated by collector separators. Each collector separator is aligned with the orientation direction of an adjacent collector segment. The collector separator blocks current in the upper collector that flows crosswise with the collector separator. Each collector segment is continuous along the orientation direction through the collector segment. That is, the upper collector does not have a collector separator that crosses the orientation direction. The collector segments are located on at least two opposite sides of the lower emitter. A method of forming an integrated circuit is disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A and Figure 1Bis a diagram of an example integrated circuit including stacked NPNs.

[0006] FIG. 2A to FIG. 2F is a cross-section of an integrated circuit including stacked NPNs, depicted at stages of an example formation method.

[0007] Figure 3 is a top view of another example integrated circuit including stacked NPNs. DETAILED DESCRIPTION

[0008] The present disclosure is described with reference to the accompanying drawings. The accompanying drawings are not drawn to scale, and they are provided only for illustrating the present disclosure. Several aspects of the present disclosure are described below with reference to example applications for illustration. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited to the ordering of the actions or events described, as some actions may occur in different orders and / or simultaneously with other actions or events. In addition, not all described actions or events are necessary to implement the methods according to the present disclosure.

[0009] The integrated circuit includes a stacked NPN having a first NPN (hereinafter referred to as an upper NPN), the upper NPN being connected to a second NPN (hereinafter referred to as a lower NPN). The upper NPN includes a first collector (hereinafter referred to as an upper collector), a first base (hereinafter referred to as an upper base), and a first emitter (hereinafter referred to as an upper emitter). The lower NPN includes a second collector (hereinafter referred to as a lower collector), a second base (hereinafter referred to as a lower base), and a second emitter (hereinafter referred to as a lower emitter). The upper emitter can be adjacent to the lower collector. The stacked NPN can be part of a clamping circuit between a protected line and a ground line to, for example, reduce voltage stress on the protected line during an ESD event.

[0010] The upper collector is divided into collector segments by a collector separator; during operation of the integrated circuit, current cannot flow through the upper collector across the collector separator. During operation of the integrated circuit, current flows in each collector segment of the upper collector toward the lower NPN. The upper collector has an orientation direction that points to the lower emitter along the direction of current flow. Each collector separator is aligned with the orientation direction of the adjacent collector segment to allow current to flow along the orientation direction. Each collector segment is continuous along the orientation direction through the collector segment. The upper collector does not have a collector separator that crosses the orientation direction, which can increase the resistance in the upper collector. For the purposes of this disclosure, the term "across" extends to the configuration of the collector separator that prevents current along the orientation direction. The collector segments are located on at least two opposite sides of the lower emitter. Segmenting the upper collector can reduce current crowding and thus improve current uniformity. Segmenting the upper collector as described can advantageously reduce the resistance of the stacked NPN while providing the desired uniformity of current flow in the stacked NPN. Distributing the upper collector on the opposite side of the lower emitter may provide a desired width of the upper collector, thereby reducing the overall resistance of the upper collector, compared to an upper collector located on one side of the lower emitter.

[0011] The lower emitter may include an n-type semiconductor region laterally surrounded by a field oxide layer, wherein the n-type semiconductor region directly contacts the lower base. The lower emitter may have an emitter separator that is aligned with the orientation direction in the collector segment closest to the emitter separator. The emitter separator blocks the flow of current in the lower emitter that intersects the emitter separator. The lower emitter may not have an emitter separator that intersects the orientation direction in the lower emitter. Segmenting the lower emitter in this way can advantageously reduce current non-uniformity caused by current leakage around the lateral boundaries of each emitter segment.

[0012] A method for forming an integrated circuit is disclosed. A stacked NPN element can be formed simultaneously with similar elements in other circuits of the integrated circuit, advantageously reducing process complexity and cost.

[0013] For purposes of this disclosure, the term "top surface" of a substrate of an integrated circuit shall be understood to refer to the surface of the substrate at which active components such as transistors are formed. For purposes of this disclosure, the terms "lateral" and "laterally" shall be understood to refer to directions parallel to a plane of the top surface of the substrate. The term "vertical" shall be understood to refer to a direction perpendicular to a plane of the top surface of the substrate.

[0014] It should be noted that terms such as top, bottom, upper, lower, above, above, below and below can be used in the present disclosure. These terms should not be interpreted as limiting the position or orientation of structures or elements, but should be used to provide spatial relationships between structures or elements.

[0015] Figure 1A and Figure 1B is a diagram of an example integrated circuit including stacked NPNs. Figure 1A , which is a top view, an integrated circuit 100 has a substrate 102 that includes a semiconductor material such as silicon or other type IV semiconductor materials. Other semiconductor materials are within the scope of this example. The substrate 102 can be a portion of a semiconductor wafer, such as a monolithic semiconductor wafer, a silicon-on-insulator (SOI) wafer, or a semiconductor wafer with a semiconductor epitaxial layer. The integrated circuit 100 includes a stacked NPN 104.

[0016] Stacked NPN 104 has an upper NPN 106 and a lower NPN 108 connected in series. Upper NPN 106 has an upper collector 110 of n-type semiconductor material in substrate 102, an upper base 112 of p-type semiconductor material in substrate 102, and an upper emitter 114 of n-type semiconductor material in substrate 102. Lower NPN 108 includes a lower collector 116 of n-type semiconductor material in substrate 102, a lower base 118 of p-type semiconductor material in substrate 102, and a lower emitter 120 of n-type semiconductor material in substrate 102. Upper emitter 114 may be adjacent to lower collector 116.

[0017] The upper collector 110 is divided into a first collector segment 122 on a first side of the lower NPN 108 and into a second collector segment 124 on a second opposite side of the lower NPN 108. The first collector segment 122 is laterally separated by a first collector separator 126, which is aligned with a first orientation direction 128 in the first collector segment 122. The first orientation direction 128 points to the lower NPN 108. In this example, the first orientation directions 128 can be parallel to each other. Similarly, the second collector segment 124 is laterally separated by a second collector separator 132, which is aligned with a second orientation direction 134 in the second collector segment 124. In this example, the second orientation directions 134 can be parallel to each other. Each first collector segment 122 is continuous along the first orientation direction 128 of the first collector segment 122. Similarly, each second collector segment 124 is continuous along a second orientation direction 134 of the second collector segment 124. The upper collector 110 does not have a collector separator 126 or 132 between the collector segments 122 and 124 that is positioned crosswise to the orientation directions 128 and 134, respectively. Each of the collector segments 122 and 124 may have a first lateral dimension (i.e., a length along the orientation directions 128 and 134) that is greater than a second lateral dimension (i.e., a width perpendicular to the orientation directions 128 and 134). In this example, the first collector separator 126 may include a field oxide layer 130 and may include a portion of the upper base 112 extending between the first collector segments 122. Each of the first collector segment 122 and the second collector segment 124 includes a first n-type well 136 in the substrate 102, and a first n-type active region 138 on the first n-type well 136. The first n-type active region 138 may be coupled to the protected line 140 through a contact 142 on the first n-type active region 138 .

[0018] In this example, upper base 112 extends below upper collector 110 to upper emitter 114. Upper base 112 may include a first p-type well in substrate 102 laterally surrounding first n-type well 136, and a first portion of p-type semiconductor material extending below first n-type well 136 in substrate 102.

[0019] In this example, the upper emitter 114 includes a first portion of the second n-type active region 144 on a first portion of the second n-type well 146. The upper emitter 114 also includes a first portion of the n-type buried layer ( Figure 1A The n-type buried layer is formed by a vertical n-type region ( Figure 1AThe deep trench 148 may be connected to the second n-type well 146 (also not shown). The vertical n-type region may laterally surround the deep trench 148. The deep trench 148 may advantageously provide segmentation in the upper emitter 114 to improve current uniformity through the upper emitter 114.

[0020] The lower collector 116 of the present example includes a second portion of the second n-type active region 144 on a second portion of the second n-type well 146. The lower collector 116 also includes a second portion of the n-type buried layer extending below the lower base 118. The lower collector 116 may be adjacent to the upper emitter 114 in the second n-type active region 144, the second n-type well 146, and the n-type buried layer.

[0021] The lower base 118 may include a second p-type well in the substrate 102 and a second portion of a p-type material above a second portion of an n-type buried layer in the lower collector 116. The lower base 118 extends below the lower emitter 120. The lower emitter 120 may be segmented into emitter segments 150 by emitter separators 152 that are aligned with the first orientation direction 128 or the second orientation direction 134. The emitter separators 152 prevent current in the lower emitter 120 from flowing across the emitter separators 152. The emitter separators 152 may include a field oxide layer 130 and may include portions of the lower base 118 extending between the emitter segments 150. The lower emitter 120 does not have emitter separators 152 between the emitter segments 150 that are perpendicular to the orientation directions 128 and 134. Each of the emitter segments 150 includes an emitter n-type active region 154 on the second p-type well of the lower base 118. The emitter n-type active region 154 may be coupled to a ground line 156 through an additional contact 142 on the first n-type active region 138.

[0022] Splitting upper collector 110 into first collector segment 122 and second collector segment 124 on opposite sides of lower NPN 108 may advantageously reduce resistance in upper collector 110 by increasing the width of upper collector 110, compared to a stacked NPN having an upper collector located on only one side of the lower NPN. Positioning first collector segment 122 and second collector segment 124 on opposite sides of lower NPN 108 may advantageously provide more uniform current flow in lower emitter 120 by allowing current to flow into lower NPN 108 from both sides, compared to a stacked NPN having an upper collector located on only one side of the lower NPN.

[0023] Segmenting the upper collector 110 into the first collector segment 122 and the second collector segment 124 can advantageously reduce current crowding, sometimes referred to as current hogging or current filamentation, from the upper collector 110 into the upper base 112. Not having collector dividers 126 or 132 in the upper collector 110 that intersect the orientation directions 128 and 134, respectively, can advantageously improve current uniformity for a version of the integrated circuit 100 that has a significant peripheral current component in the active region, i.e., the current around the periphery of the active region is higher than the current through the middle of the active region. Typically, as the technology node of the logic circuit advances, the depth of heavily doped regions (e.g., source and drain regions) in the active region becomes shallower, and the peripheral current as a portion of the total current increases as a result. Segmenting the lower emitter 120 into emitter segments 150 may yield similar benefits, wherein the emitter dividers 152 are aligned with the orientation directions 128 and 134 , rather than being perpendicular to the orientation directions 128 and 134 .

[0024] The stacked NPN 104 is surrounded by an isolation structure 158 that extends around the stacked NPN 104. One representation of the isolation structure 158 will be described in this example. Other architectures and configurations of the isolation structure 158 are within the scope of this example.

[0025] refer to Figure 1B , which is a cross section, the integrated circuit 100 has a substrate 102, the substrate 102 includes the aforementioned but not Figure 1A 1 and 2. The semiconductor material 160 is not shown in FIG. 1. In this example, the semiconductor material 160 is of p-type and may be part of a base wafer.

[0026] The upper collector 110 of the upper NPN 106 includes a first n-type well 136 in the substrate 102, and a first n-type active region 138 on the first n-type well 136. The first n-type active region 138 is separated by a field oxide layer 130. The field oxide layer 130 may have a shallow trench isolation (STI) structure, may have a local oxidation of silicon (LOCOS) structure, or may have another structure. In this example, the field oxide layer 130 has an STI structure having silicon dioxide disposed in an isolation trench in the substrate 102; the isolation trench has substantially straight sides and is wider at the top of the isolation trench than at the bottom of the isolation trench. The top surface of the field oxide layer 130 having the STI structure may be substantially coplanar with the top surface of the substrate 102 adjacent to the field oxide layer 130. The LOCOS structure has a silicon dioxide layer with a tapered edge (sometimes called a bird's beak); approximately half of the silicon dioxide is below the top surface of the adjacent substrate 102, while the remainder is above the top surface.

[0027] The upper base 112 includes a first portion of a p-type semiconductor material 160 , a first p-type well 162 laterally surrounding the first n-type well 136 , and a p-type upper base contact region 164 on the first p-type well 162 .

[0028] The upper emitter 114 includes a first portion of a second n-type active region 144 on a first portion of the second n-type well 146. The upper emitter 114 also includes a first portion of an n-type buried layer 166 extending below the upper base 112. The n-type buried layer 166 is connected to the second n-type well 146 by a vertical n-type region 168 surrounding the n-type region 168. Figure 1A deep trench 148 (if present).

[0029] The lower collector 116 includes a second portion of the second n-type active region 144 on a second portion of the second n-type well 146. The lower collector 116 also includes a second portion of an n-type buried layer 166 extending below the lower base 118. A vertical n-type region 168 connects the second portion of the second n-type well 146 with the second portion of the n-type buried layer 166.

[0030] The lower base 118 includes a second portion of the semiconductor material 160 over a second portion of the n-type buried layer 166 , and a second p-type well 170 beneath the lower emitter 120 .

[0031] The lower emitter 120 includes an emitter n-type active region 154 on a second p-type well 170. The emitter n-type active region 154 is laterally surrounded by a p-type lower base contact region 172 on the second p-type well 170. The emitter n-type active region 154 is laterally separated from the lower base contact region 172 by a field oxide layer 130.

[0032] The isolation structure 158 may include a deep trench 174 with a silicon dioxide liner 176 and a core 178 of p-type polysilicon in contact with the semiconductor material 160 below the n-type buried layer 166. A vertical n-type region 180 may be positioned around the deep trench 174. Other architectures of the isolation structure 158, such as a deep n-type region referred to as a sinker, are within the scope of the present example.

[0033] Dielectric layer 182 is disposed over substrate 102. Dielectric layer 182 may be, for example, a pre-metal dielectric (PMD) layer 182, which may include one or more dielectric material sublayers, for example, a PMD pad of silicon nitride directly over substrate 102, a main dielectric layer of a silicon dioxide-based material (e.g., phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG)) on the PMD pad, and a capping layer of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbide nitride on the main dielectric layer. Other layer structures and compositions for dielectric layer 182 are within the scope of this example.

[0034] The contact 142 is disposed through the dielectric layer 182 to provide an electrical connection to the elements of the stacked NPN 104. The contact 142 may include a titanium-containing liner, a barrier layer including tantalum nitride or titanium nitride on the liner, and a tungsten core on the barrier layer. The protected line 140 (which may be an interconnect line on the dielectric layer 182) is coupled to the upper collector 110 through an instance of the contact 142. Similarly, the ground line 156 (which may also be an interconnect line on the dielectric layer 182) is coupled to the lower emitter 120 through an instance of the contact 142. Any of the upper base 112, the upper emitter 114, and the lower collector 116 and the lower base 118 may be coupled to the trigger circuit through an instance of the contact 142.

[0035] FIG. 2A to FIG. 2F is a cross section of an integrated circuit including a stacked NPN, depicted at stages of an example formation method. Figure 2A , the integrated circuit 200 is formed in and on a substrate 202 including a semiconductor material 260. The substrate 202 may be, for example, a semiconductor wafer. In this example, the semiconductor material 260 is p-type.

[0036] An n-type buried layer 266 is formed in the substrate 202 in the region for the stacked NPN 204. The n-type buried layer 266 may be formed by implanting n-type dopants (such as antimony and possibly arsenic) into the base portion of the substrate 202, heating the base portion to diffuse the implanted n-type dopants, and forming an epitaxial layer on the base portion. For example, 5×10 14 cm -2 Up to 3×10 15 cm -2 The n-type dopant is implanted with a total dose of . During the formation of the epitaxial layer, the implanted n-type dopant further diffuses downward into the base portion and diffuses upward into the epitaxial layer to form an n-type buried layer 266. The base portion and the epitaxial layer provide a substrate 202. The epitaxial layer includes a p-type semiconductor material, which is a portion of the semiconductor material 260. Other methods of forming the n-type buried layer 266, such as implanting the n-type dopant into the substrate 202 at a high energy, are within the scope of the present example. The n-type buried layer 266 of the present example extends continuously across a region for the upper NPN 206 of the stacked NPN 204 and a region for the lower NPN 208 of the stacked NPN 204.

[0037] refer to Figure 2B , a deep trench mask 286 is formed over the substrate 202. The deep trench mask 286 may include a hard mask material, such as silicon dioxide or silicon nitride. The deep trench mask 286 exposes areas for the deep trenches 274 for the isolation structure 258. The areas for the deep trenches 274 for the isolation structure 258 laterally surround the areas for the stacked NPNs 204. The deep trench mask 286 also exposes areas for a plurality of deep trenches 248 that extend into the area of ​​the upper emitter 214 for the upper NPN 206 and into the area of ​​the lower collector 216 for the lower NPN 208. The areas for the upper emitter 214 and the lower collector 216 are contiguous. The areas for the deep trenches 248 are perpendicular to the substrate 202. Figure 2B The deep trench 274 and the plurality of deep trenches 248 may be formed simultaneously. The deep trench 274 and the plurality of deep trenches 248 may be formed by any of several deep reactive ion etching (DRIE) processes, including a continuous DRIE process (which forms a protective polymer on the sidewalls of the deep trench 274 and the plurality of deep trenches 248 while etching the semiconductor material 260 from the bottom of the deep trench 274 and the plurality of deep trenches 248), or a two-step DRIE process, sometimes referred to as a BoschDRIE process (which forms a protective polymer and etches the semiconductor material 260 in separate alternating steps).

[0038] The deep trench 274 of the isolation structure 258 laterally surrounds the area for the stacked NPN 204 and intersects the n-type buried layer 266 surrounding the perimeter of the area for the stacked NPN 204. The deep trench 248 is perpendicular to the Figure 2B extends in the line of the plane of Figure 2B The example of deep trench 248 shown is in Figure 2B The deep trench 274 and the plurality of deep trenches 248 are formed to extend below the n-type buried layer 266.

[0039] An n-type dopant 288 is implanted into the substrate 202 along the sidewalls of the deep trench 274 and the plurality of deep trenches 248 to form a vertical implant layer 290 that extends down along the sidewalls of the deep trench 274 and the plurality of deep trenches 248 to the n-type buried layer 266. The n-type dopant 288 may include phosphorus and arsenic and may be implanted in several steps at an inclination angle of 20 to 30 degrees from a vertical axis perpendicular to the top surface of the substrate 202. The n-type dopant 288 may be implanted at a rate of 3×10 14 cm -2 Up to 3×10 15 cm -2 A total dose of 200 N is implanted, for example, to obtain a desired conductivity in a subsequently formed vertical n-type region.

[0040] refer to Figure 2C A silicon dioxide liner 276 is formed on the sidewalls of the deep trench 274 and the plurality of deep trenches 248. The silicon dioxide liner 276 may be formed, for example, by a thermal oxidation process. Figure 2B The vertical injection layer 290 Figure 2B The implanted n-type dopant 288 is activated to form vertical n-type regions 268 along deep trenches 274 and to form a continuous vertical n-type region 280 surrounding the plurality of deep trenches 248. The thermal oxidation process may provide sufficient heat profile to activate the implanted n-type dopant 288; otherwise, additional annealing may be employed.

[0041] A core 278 is formed on the silicon dioxide liner 276 in the deep trench 274 and the plurality of deep trenches 248. The core 278 may include p-type polysilicon or other conductive materials. The core 278 is electrically connected to the semiconductor material 260 below the n-type buried layer 266. The deep trench mask 286 is removed. The deep trench mask 286 may be removed before or after the core 278 is formed.

[0042] refer to Figure 2D, a field oxide layer 230 is formed on the substrate 202. The field oxide layer 230 may be formed by an STI process, a LOCOS process, or other processes. An example STI process includes forming a CMP stop layer of silicon nitride over the substrate 202, etching an isolation trench through the CMP stop layer and into the substrate 202, and filling the isolation trench with silicon dioxide using a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate (TEOS), a high density plasma (HDP) process, a high aspect ratio process (HARP) using TEOS and ozone, an atmospheric chemical vapor deposition (APCVD) process using silane, or a sub-atmospheric pressure chemical vapor deposition (SACVD) process using dichlorosilane. Excess silicon dioxide is removed from over the CMP stop layer by an oxide chemical mechanical polishing (CMP) process, and then the CMP stop layer is removed, leaving the field oxide layer 230. An example LOCOS process includes forming a silicon nitride mask layer over the LOCOS pad oxide layer over the substrate 202. The silicon nitride mask layer is removed in the area for field oxide layer 230, exposing the LOCOS pad oxide. Silicon dioxide is formed by thermal oxidation in the area exposed by the silicon nitride mask layer to form field oxide layer 230. The silicon nitride mask layer is then removed, leaving field oxide layer 230 in place.

[0043] Field oxide layer 230 is positioned to provide a portion of a collector separator in the area of ​​upper collector 210 for upper NPN 206. Field oxide layer 230 also laterally separates the areas for upper collector 210, upper base 212, and upper emitter 214, all of upper NPN 206, and lower collector 216, lower base 218, and lower emitter 220, all of lower NPN 208. In this example, field oxide layer 230 does not separate the area for upper emitter 214 from the area for lower collector 216.

[0044] refer to Figure 2E , a first p-type well 262 is formed in the substrate 202 as a portion of the upper base 212. A second p-type well 270 is formed in the substrate 202 as a portion of the lower base 218. The first p-type well 262 and the second p-type well 270 can be formed simultaneously with other p-type wells including n-channel metal oxide semiconductor (NMOS) transistors in the integrated circuit 200. For example, a p-type dopant such as boron can be added at 3×10 13 cm -2 Up to 1×10 14 cm -2 A total dose of 200 Å is implanted into the substrate 202 to form a first p-type well 262 and a second p-type well 270 .

[0045] A plurality of first n-type wells 236 (one of which is in Figure 2E2) is formed in the substrate 202 as a part of the upper collector 210. The second n-type well 246 is formed in the substrate 202 as a part of the upper emitter 214 and a part of the lower collector 216. For example, n-type dopants such as phosphorus and arsenic can be added at 3×10 13 cm -2 Up to 1×10 14 cm -2 The total dose of 200 is implanted into the substrate 202 to form the first n-type well 236 and the second n-type well 246. The first n-type well 236 and the second n-type well 246 can be formed simultaneously with other n-type wells including p-channel metal oxide semiconductor (PMOS) transistors in the integrated circuit 200.

[0046] refer to Figure 2F , an n-type region is simultaneously formed in the substrate 202 to provide source and drain regions of the NMOS transistor, a contact region of the n-type well, etc. The n-type region includes a first n-type active region 238 on the first n-type well 236 in the upper collector 210, a second n-type active region 244 on the second n-type well 246 in the upper emitter 214 and the lower collector 216, and an emitter n-type active region 254 of the lower emitter 220 on the second p-type well 270 of the lower base 218. For example, n-type dopants such as phosphorus, arsenic, and antimony can be added at 3×10 14 cm -2 Up to 1×10 16 cm -2 A total dose of 200 Å is implanted into the substrate 202 to form an n-type region.

[0047] P-type regions are simultaneously formed in the substrate 202 to provide source and drain regions of the PMOS transistor, contact regions of the p-type well, etc. The p-type regions include an upper base contact region 264 on the first p-type well 262 of the upper base 212 and a lower base contact region 272 on the second p-type well 270 of the lower base 218. For example, p-type dopants such as boron, gallium, and possibly indium may be added at 3×10 14 cm -2 Up to 1×10 16 cm -2 A total dose of 200 Å is implanted into the substrate 202 to form a p-type region.

[0048] Simultaneously forming elements of stacked NPN 204 (e.g., p-type wells 262 and 270, n-type wells 236 and 246, n-type regions 238, 244, and 254, and p-type regions 264 and 272) and corresponding elements of NMOS and PMOS transistors may advantageously reduce manufacturing costs and complexity of integrated circuit 200.

[0049] Figure 33 is a top view of another example integrated circuit including stacked NPNs. Integrated circuit 300 is formed on substrate 302, for example, as shown in FIG. Figure 1A and Figure 1B As described. In the present example, the stacked NPN 304 has a concentric configuration in which the upper collector 310 has a collector segment 322 arranged radially at least partially around the lower emitter 320. The collector segment 322 is disposed on at least two opposing sides of the lower emitter 320; in the present example, the collector segment 322 is disposed on all sides of the lower emitter 320. Current flows to the lower emitter 320 through the collector segment 322, as shown by the orientation direction 328. Adjacent pairs of collector segments 322 are separated by a collector separator 326, which is aligned with the orientation direction 328 in the collector segment 322. The collector separator 326 prevents the current in the upper collector 310 from flowing across the collector separator 326. The collector separator 326 may include a field oxide, a p-type active region, or other current blocking structure. Each collector segment 322 is continuous along the orientation direction 328 of the collector segment 322. The upper collector 310 has no separators between adjacent pairs of collector segments 322 that intersect the orientation direction 328 in adjacent collector segments 322. The concentric configuration of the upper collector 310 can advantageously improve the current capacity of the stacked NPN 304 because the concentric configuration provides a greater width for the upper collector 310 while maintaining a low resistance path to the lower emitter 320.

[0050] The lower emitter 320 may optionally be divided into emitter segments 350 to reduce current crowding in the lower emitter 320. The lower emitter 320 is separated from the upper collector 310 by a combined upper emitter 314 and lower collector 316 disposed around the lower emitter 320. The combined upper emitter 314 and lower collector 316 may be segmented by deep trenches 348 to reduce current crowding in the combined upper emitter 314 and lower collector 316.

[0051] The upper collector 310 may be connected to a protected line 340 that extends over the collector segment 322. Similarly, the lower emitter 320 may be connected to a ground line 356 that extends over the emitter segment 350. Figure 3 Depicted in Figure 3 The concentric configuration depicted in can facilitate a short distance between the upper collector 310 and the protected line 340 , and a short distance between the lower emitter 320 and the ground line 356 , advantageously reducing the resistance between the protected line 340 and the ground line 356 through the stacked NPN 304 .

[0052] Although various embodiments of the present disclosure have been described above, it should be understood that they are presented only as examples and not limitations. Without departing from the spirit or scope of the present disclosure, many changes may be made to the disclosed embodiments according to the disclosure herein. Therefore, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. On the contrary, the scope of the present disclosure should be limited according to the appended claims and their equivalents.

Claims

1. An integrated circuit, comprising: A substrate comprising a semiconductor material; as well as A stacked NPN bipolar transistor pair, or stacked NPN, comprises: a first NPN bipolar transistor, ie, a first NPN, comprising a first collector, said first collector comprising a collector segment of a first n-type semiconductor material in said substrate; and a second NPN bipolar transistor, a second NPN, comprising a second collector coupled to the first emitter of the first NPN, and a second emitter of a second n-type semiconductor material included in the substrate; in: Each collector segment has an orientation direction pointing towards the second emitter; Adjacent collector segments are laterally separated by collector separators, said collector separators electrically isolating said adjacent collector segments from each other; each collector segment is continuous along the orientation direction of each collector segment; and The collector segment is located on at least two opposing sides of the second emitter. 2 . The integrated circuit of claim 1 , wherein each of the collector segments comprises an n-type well on the first base. 3 . The integrated circuit of claim 1 , wherein the collector separator comprises a p-type semiconductor material in the substrate.

4. The integrated circuit of claim 1 wherein the collector spacer comprises a portion of a field oxide layer. 5 . The integrated circuit of claim 1 , wherein the first emitter comprises a portion of an n-type buried layer, the portion of the n-type buried layer extending below the first base. 6 . The integrated circuit of claim 5 , wherein the first emitter comprises a portion of an n-type well connected to the portion of the n-type buried layer through a portion of a vertical n-type region. 7 . The integrated circuit of claim 1 , wherein the second collector comprises a portion of an n-type buried layer, the portion of the n-type buried layer extending below the second base. 8 . The integrated circuit of claim 7 , wherein the second collector comprises a portion of an n-type well connected to the portion of the n-type buried layer through a portion of a vertical n-type region.

9. The integrated circuit of claim 1, wherein the first emitter is adjacent to the second collector.

10. The integrated circuit of claim 7, wherein: The second base comprises a p-type well in the substrate; and The second emitter includes an n-type active region on the p-type well.

11. The integrated circuit of claim 1 , wherein: the collector segments comprising a first collector segment on a first side of the second emitter, wherein the orientation directions in the first collector segment are parallel to each other; and The collector segments include a second collector segment on a second side of the second emitter opposite to the first side, wherein the orientation directions in the second collector segments are parallel to each other.

12. The integrated circuit of claim 1, wherein the stacked NPN has a concentric configuration, wherein the collector segment is positioned to at least partially surround the second emitter.

13. The integrated circuit of claim 1, wherein the first collector is connected to a protected line of the integrated circuit, the protected line comprising an interconnect line.

14. The integrated circuit of claim 1, wherein the second emitter is connected to a ground line of the integrated circuit, the ground line comprising an interconnect line.

15. The integrated circuit of claim 1, wherein the second emitter includes emitter dividers, wherein each emitter divider is aligned with the orientation direction in adjacent collector segments, wherein the emitter dividers prevent current flow in the second emitter that crosses the emitter dividers.

16. A method of forming an integrated circuit, comprising: Providing a substrate including a semiconductor material, the substrate including a region for a stacked NPN bipolar transistor pair, i.e., a stacked NPN, the region for the stacked NPN including a region for a first NPN bipolar transistor, i.e., a first NPN, and a region for a second NPN bipolar transistor, i.e., a second NPN, the region for the first NPN including a region for a first collector, a region for a first base, and a region for a first emitter, the region for the second NPN including a region for a second collector, a region for a second base, and a region for a second emitter; as well as An n-type region is formed in the region for the first collector, wherein the n-type region comprises a collector segment, wherein: Each collector segment has an orientation direction pointing towards the second emitter; pairs of adjacent collector segments are laterally separated by collector dividers, said collector dividers being aligned with said orientation direction in said adjacent collector segments; the first collector has no collector separator adjacent to a collector segment wherein the collector separator is perpendicular to the orientation direction in the collector segment; and The collector segment is located on at least two opposing sides of the second emitter.

17. The method of claim 16, wherein forming the n-type region comprises forming first n-type wells, wherein each collector segment comprises at least one of the first n-type wells, and wherein the first n-type wells are formed simultaneously with other n-type wells comprising p-channel metal oxide semiconductor (PMOS) transistors in the integrated circuit.

18. The method of claim 16, further comprising forming a field oxide layer, wherein the collector spacer comprises a portion of the field oxide layer.

19. The method of claim 16 further comprises forming emitter separators in the region for the second emitter, wherein each emitter separator is aligned with the orientation direction in the collector segment closest to the emitter separator, wherein the emitter separator blocks current flow in the second emitter that crosses the emitter separator, and wherein the second emitter does not have an emitter separator that is perpendicular to the orientation direction in the collector segment closest to the emitter separator.

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