Apparatus and method for processing reciprocal square root operation

Abstract

The present application discloses an apparatus and method for processing a reciprocal square root operation. An apparatus and method for performing a reciprocal square root. For example, one embodiment of a processor includes: a decoder for decoding a reciprocal square root instruction to generate a decoded reciprocal square root instruction; a source register for storing at least one packed input data element; a destination register for storing a result data element; and a reciprocal square root execution circuit for executing the decoded reciprocal square root instruction, the reciprocal square root execution circuit for using a first portion of the packed input data element as an index to a data structure containing a plurality of coefficient sets to identify a first coefficient set from the plurality of sets, the reciprocal square root execution circuit for: generating a reciprocal square root of the packed input data element by using a combination of a coefficient and a second portion of the packed input data element.

Description

Field of the Invention

[0001] Embodiments of the present invention generally relate to the field of computer processors. More specifically, embodiments relate to apparatuses and methods for processing fractional reciprocals and reciprocal square roots operations. Background Art

[0002] An instruction set or instruction set architecture (ISA) is the programming-related portion of a computer architecture, including native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" generally refers to a macro-instruction in this document - that is, an instruction provided to the processor for execution - rather than a micro-instruction or micro-operation - that is, the micro-instruction or micro-operation is the result of the processor's decoder decoding a macro-instruction. A micro-instruction or micro-operation can be configured to instruct an execution unit on the processor to perform an operation to implement the logic associated with the macro-instruction.

[0003] The ISA is different from the microarchitecture, which is a collection of processor design techniques for implementing an instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Pentium 4 processor, Core TM (Core TM ) processors, and multiple processors from Advanced Micro Devices, Inc. in Sunnyvale, California implement nearly identical versions of the x86 instruction set (with some extensions added with updated versions), but have different internal designs. For example, the same register architecture of the ISA can be implemented in different ways using well-known techniques in different microarchitectures, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases "register architecture", "register file", and "register" are used in this document to refer to the register architecture, register file, and register that are visible to the software / programmer and the way instructions specify registers. In cases where a distinction is needed, the adjectives "logical", "architectural", or "software visible" will be used to indicate registers / register files in the register architecture, while different adjectives will be used to specify registers in a given microarchitecture (e.g., physical registers, reorder buffers, retirement registers, register pools).

[0004] Multiplication-accumulation is a common digital signal processing operation that multiplies two numbers and adds the product to an accumulation value. Existing single instruction multiple data (SIMD) microarchitectures implement the multiplication-accumulation operation by executing a sequence of instructions. For example, a multiplication-accumulation can be performed by using a multiplication instruction, followed by a 4-way addition, and then an accumulation with a destination quadword data to generate two 64-bit saturated results. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

[0006] Figure 1A and 1B is a block diagram illustrating a general vector friendly instruction format and its instruction templates according to an embodiment of the present invention;

[0007] Figure 2A -C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0008] Figure 3 is a block diagram of a register architecture according to an embodiment of the present invention; and

[0009] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, retire pipeline and an exemplary register-renamed out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0010] Figure 4B is a block diagram illustrating an exemplary embodiment of an in-order fetch, decode, retire core to be included in a processor and an exemplary register-renamed out-of-order issue / execution architecture core according to an embodiment of the present invention;

[0011] Figure 5A is a block diagram of a single processor core and its connection to an on-die interconnect network;

[0012] Figure 5B Illustrates according to an embodiment of the present invention Figure 5A an expanded view of a portion of the processor core in

[0013] Figure 6 is a block diagram of a single-core processor and a multi-core processor having an integrated memory controller and a graphics device according to an embodiment of the present invention;

[0014] Figure 7 Illustrates a block diagram of a system according to an embodiment of the present invention;

[0015] Figure 8 Illustrates a block diagram of a second system according to an embodiment of the present invention;

[0016] Figure 9Diagram of a third system according to an embodiment of the present invention;

[0017] Figure 10 Diagram of a system - on - chip (SoC) according to an embodiment of the present invention;

[0018] Figure 11 Diagram of converting binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to an embodiment of the present invention;

[0019] Figure 12 Diagram of a processor architecture on which embodiments of the present invention can be implemented;

[0020] Figure 13 Diagram of a plurality of packed data elements including real - valued and complex - valued according to one embodiment;

[0021] Figure 14 Diagram of an embodiment of an architecture on which reciprocal - of - fraction and reciprocal - square - root instructions can be implemented;

[0022] Figure 15 Diagram of an example of an embodiment for processing a reciprocal - of - fraction instruction;

[0023] Figure 16 Diagram of a method for processing a reciprocal - of - fraction operation according to an embodiment of the present invention;

[0024] Figure 17 Diagram of an example of an embodiment for processing a reciprocal - of - fraction instruction; and

[0025] Figure 18 Diagram of a method for processing a reciprocal - of - fraction operation according to an embodiment of the present invention. Detailed Description

[0026] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention described below. However, it will be apparent to one of ordinary skill in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well - known structures and devices are shown in block diagram form to avoid obscuring the basic principles of embodiments of the invention.

[0027] Exemplary Processor Architecture, Instruction Formats, and Data Types

[0028] The instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, position of bits) to specify the operation to be performed (opcode) and the operands on which the operation is to be performed, and so on. Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, an instruction template of a given instruction format can be defined as different subsets of the fields of that instruction format (the included fields are typically in the same order, but at least some fields have different bit positions because fewer fields are included), and / or defined as having a given field interpreted in a different way. Thus, each instruction of the ISA is expressed using a given instruction format (and if defined, according to a given one of the instruction templates in that instruction format), and includes fields for specifying the operation and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, and the specific instruction format includes an opcode field for specifying the opcode and operand fields for selecting the operands (source 1 / destination and source 2); and the appearance of the ADD instruction in the instruction stream will result in specific contents in the operand fields for selecting specific operands.

[0029] Embodiments of the (multiple) instructions described herein can be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are described in detail below. Embodiments of the (multiple) instructions can be executed on such systems, architectures, and pipelines, but are not limited to those systems, architectures, and pipelines detailed.

[0030] General vector-friendly instruction format

[0031] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., there are specific fields dedicated to vector operations). Although embodiments are described in which both vector and scalar operations are supported by the vector-friendly instruction format, alternative embodiments use only vector operations via the vector-friendly instruction format.

[0032] Figure 1A - Figure 1B is a block diagram illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention. Figure 1A is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction templates according to an embodiment of the present invention; while Figure 1B is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction templates according to an embodiment of the present invention. Specifically, Class A and Class B instruction templates are defined for the general vector-friendly instruction format 100, both of which include instruction templates for no memory access 105 and instruction templates for memory access 120. The term "general" in the context of the vector-friendly instruction format refers to an instruction format that is not tied to any specific instruction set.

[0033] While embodiments of the present invention will be described in which a vector-friendly instruction format supports the following: a 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector is composed of 16 double-word-sized elements, or alternatively, 8 quad-word-sized elements); a 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); a 32-byte vector operand length (or size) with a 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); and a 16-byte vector operand length (or size) with a 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., a 256-byte vector operand) with larger, smaller, or different data element widths (e.g., a 128-bit (16-byte) data element width).

[0034] Figure 1A The Class A instruction templates in include: 1) within the instruction templates without memory access 105, an instruction template showing a fully rounded control type operation 110 without memory access, and an instruction template of a data transformation type operation 115 without memory access; and 2) within the instruction templates with memory access 120, an instruction template showing the timeliness 125 of memory access and an instruction template of the non-timeliness 130 of memory access. Figure 1B The Class B instruction templates in Figure 1B include: 1) within the instruction templates without memory access 105, an instruction template showing a write mask controlled partial rounding control type operation 112 without memory access and an instruction template of a write mask controlled vsize type operation 117 without memory access; and 2) within the instruction templates with memory access 120, an instruction template showing the write mask control 127 of memory access.

[0035] The general vector-friendly instruction format 100 includes the following fields in the order listed as shown in Figure 1A - 1B as follows.

[0036] Format field 140 - The specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format and thus identifies that the instruction appears in the instruction stream in the vector-friendly instruction format. Thus, this field is optional in the sense that it is not required for an instruction set that only has the general vector-friendly instruction format.

[0037] Base operation field 142 - The content of which differentiates different base operations.

[0038] Register index field 144 - whose content directly or through address generation specifies the location of source or destination operands in registers or in memory. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N can be up to three source registers and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., may support up to two sources, where one of these sources also serves as a destination; may support up to three sources, where one of these sources also serves as a destination; may support up to two sources and one destination).

[0039] Modifier field 146 - whose content distinguishes instructions in general vector instruction format that specify memory access from those that do not; i.e., distinguishes between instruction templates with no memory access 105 and instruction templates with memory access 120. Memory access operations read and / or write to the memory hierarchy (in some cases, using values in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., sources and destinations are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculation, alternative embodiments may support more, fewer, or different ways to perform memory address calculation.

[0040] Extended operation field 150 - whose content distinguishes which one of various different operations to perform in addition to the base operation. This field is context-dependent. In one embodiment of the present invention, this field is divided into a class field 168, an α field 152, and a β field 154. The extended operation field 150 allows multiple sets of common operations to be performed in a single instruction rather than in 2, 3, or 4 instructions.

[0041] Scale field 160 - whose content allows the content of the index field used for memory address generation (e.g., for address generation using (2 比例 * index + base) to be scaled.

[0042] Displacement field 162A - whose content is used as part of memory address generation (e.g., for address generation using (2 比例 * index + base + displacement).

[0043] Displacement factor field 162B (note that the displacement field 162A directly juxtaposed on the displacement factor field 162B indicates the use of one or the other) - the content of which is used as part of address generation; it specifies the displacement factor that will scale the size (N) of the memory access - where N is the number of bytes in the memory access (e.g., for address generation using (2 比例 * index + base address + scaled displacement)). Redundant low-order bits are ignored, and thus the content of the displacement factor field is multiplied by the total size (N) of the memory operand to generate the final displacement that will be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the complete opcode field 174 (described later in this document) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used in instruction templates without memory access 105 and / or different embodiments may implement only one of the two or neither of the two.

[0044] Data element width field 164 - the content of which differentiates which of multiple data element widths will be used (used in all instructions in some embodiments; used in only some instructions in other embodiments). This field is optional in the sense that it is not required if only one data element width is supported and / or some aspect of the opcode is used to support the data element width.

[0045] Write mask field 170 - whose content controls, on a per data element position basis, whether the data element positions in the destination vector operand reflect the results of the base and extended operations. Class A instruction templates support merge-write masking, while Class B instruction templates support both merge-write masking and zero-write masking. When merging, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the base and extended operations); in another embodiment, the old value of each element of the destination in which the corresponding mask bit has 0 is maintained. Conversely, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and extended operations); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified), however, the elements being modified do not necessarily have to be contiguous. Thus, the write mask field 170 allows partial vector operations, which include loads, stores, arithmetic, logic, etc. Although embodiments of the invention have been described in which the content of the write mask field 170 selects one of a plurality of write mask registers that contains the write mask to be used (and thus, the content of the write mask field 170 indirectly identifies the masking to be performed), alternative embodiments alternatively or additionally allow the content of the mask write field 170 to directly specify the masking to be performed.

[0046] Immediate field 172 - whose content allows the specification of an immediate value. This field is optional in the sense that it does not exist in implementations of a general vector-friendly format that do not support immediates and does not exist in instructions that do not use immediates.

[0047] Class field 168 - whose content differentiates between different classes of instructions. Refer to Figure 1A - Figure 1B , the content of this field selects between Class A and Class B instructions. In Figure 1A - Figure 1B , rounded rectangles are used to indicate that a particular value exists in the field (e.g., Class A 168A and Class B 168B for the class field 168 in Figure 1A - Figure 1B respectively).

[0048] Class A instruction template

[0049] In the case of the instruction template for a Class A non-memory access 105, the α field 152 is interpreted as an RS field 152A whose content differentiates which of different extended operation types is to be performed (e.g., for the instruction templates of the rounding type operation 110 without memory access and the data transformation type operation 115 without memory access, rounding 152A.1 and data transformation 152A.2 are specified respectively), while the β field 154 differentiates which of the operations of the specified type is to be performed. In the instruction template for a non-memory access 105, the scale field 160, the displacement field 162A, and the displacement scale field 162B do not exist.

[0050] Instruction template for non-memory access - fully rounding control type operation

[0051] In the instruction template for a non-memory access fully rounding control type operation 110, the β field 154 is interpreted as a rounding control field 154A whose (multiple) content provides static rounding. Although in the described embodiment of the present invention the rounding control field 154A includes a suppress all floating-point exceptions (SAE) field 156 and a rounding operation control field 158, alternative embodiments may support both concepts, may encode both concepts into the same field, or have only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 158).

[0052] SAE field 156 - whose content differentiates whether to disable the reporting of exception events; when the content of the SAE field 156 indicates enabling suppression, a given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler.

[0053] Rounding operation control field 158 - whose content differentiates which of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 158 allows the rounding mode to be changed instruction by instruction. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides the register value.

[0054] Instruction template for non-memory access - data transformation type operation

[0055] In the instruction template for a non-memory access data transformation type operation 115, the β field 154 is interpreted as a data transformation field 154B whose content differentiates which of multiple data transformations is to be performed (e.g., no data transformation, mix, broadcast).

[0056] In the case of the instruction template for a Class A memory access 120, the α field 152 is interpreted as an eviction hint field 152B whose content differentiates which eviction hint is to be used (inFigure 1A In it, for the instruction template of memory access timeliness 125 and the instruction template of memory access non - timeliness 130, the timeliness 152B.1 and non - timeliness 152B.2 are respectively specified, and the β field 154 is interpreted as a data manipulation field 154C, the content of which differentiates which one of multiple data manipulation operations (also called primitives) is to be executed (for example, no manipulation, broadcast, up - conversion of the source, and down - conversion of the destination). The instruction template of memory access 120 includes a scale field 160 and optionally includes a displacement field 162A or a displacement - scale field 162B.

[0057] Vector memory instructions use conversion support to perform vector loads from memory and vector stores to memory. Like ordinary vector instructions, vector memory instructions transfer data to / from memory in a data - element - by - data - element manner, where the actually transferred elements are specified by the content of the vector mask selected as the write mask.

[0058] Instruction template for memory access - Timeliness

[0059] Timely data is data that may be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0060] Instruction template for memory access - Non - timeliness

[0061] Non - timely data is data that is unlikely to be reused quickly enough to benefit from cache operations in the first - level cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0062] Class B instruction template

[0063] In the case of the Class B instruction template, the α field 152 is interpreted as a write - mask control (Z) field 152C, the content of which differentiates whether the write masking controlled by the write - mask field 170 should be merged or zeroed.

[0064] In the case of the instruction template for a class B non-memory access 105, a part of the β field 154 is interpreted as an RL field 157A, the content of which differentiates which of different extended operation types is to be performed (e.g., for the instruction template of a write mask control partial rounding control type operation 112 without memory access and the instruction template of a write mask control VSIZE type operation 117 without memory access, rounding 157A.1 and vector length (VSIZE) 157A.2 are specified respectively), while the remaining part of the β field 154 differentiates which of the operations of the specified type is to be performed. In the instruction template for a non-memory access 105, the scale field 160, the displacement field 162A, and the displacement scale field 162B do not exist.

[0065] In the instruction template for a write mask control partial rounding control type operation 110 without memory access, the remaining part of the β field 154 is interpreted as a rounding operation field 159A, and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler).

[0066] The rounding operation control field 159A - just like the rounding operation control field 158, the content of which differentiates which of a set of rounding operations is to be performed (e.g., rounding up, rounding down, rounding towards zero, and rounding to nearest). Thus, the rounding operation control field 159A allows the rounding mode to be changed instruction by instruction. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides the register value.

[0067] In the instruction template for a write mask control VSIZE type operation 117 without memory access, the remaining part of the β field 154 is interpreted as a vector length field 159B, the content of which differentiates which of multiple data vector lengths is to be performed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0068] In the case of the instruction template for a class B memory access 120, a part of the β field 154 is interpreted as a broadcast field 157B, the content of which differentiates whether a broadcast type data manipulation operation is to be performed, while the remaining part of the β field 154 is interpreted as a vector length field 159B. The instruction template for a memory access 120 includes a scale field 160 and optionally includes a displacement field 162A or a displacement scale field 162B.

[0069] For a general vector friendly instruction format 100, a full opcode field 174 is shown to include a format field 140, a base operation field 142, and a data element width field 164. Although one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes fewer than all of these fields. The full opcode field 174 provides an operation code (opcode).

[0070] An extended operation field 150, a data element width field 164, and a write mask field 170 allow these features to be specified on a per-instruction basis in the general vector friendly instruction format.

[0071] The combination of the write mask field and the data element width field creates various types of instructions because these instructions allow the mask to be applied based on different data element widths.

[0072] The various instruction templates that occur within classes A and B are beneficial in different scenarios. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or may support both classes. For example, a high-performance general out-of-order core intended for general computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both general computing and graphics and / or scientific (throughput) computing may support both class A and class B (of course, cores with some mix of templates and instructions from both classes, but not all templates and instructions from both classes are within the scope of the present invention). Similarly, a single processor may include multiple cores, all of which support the same class, or where different cores support different classes. For example, in a processor with separate graphics and general cores, one core in the graphics core intended primarily for graphics and / or scientific computing may support only class A, while one or more in the general core may be high-performance general out-of-order cores with register renaming that support only class B for general computing. Another processor without a separate graphics core may include one or more general in-order or out-of-order cores that support both class A and class B. Of course, in different embodiments of the present invention, features from one class may also be implemented in other classes. This will enable programs written in a high-level language to be (e.g., just-in-time compiled or statically compiled) into various different executable forms, which include: 1) a form that only has instructions of the (multiple) classes supported by the target processor for execution; or 2) a form that has alternative routines and control flow code, where the alternative routines are written using different combinations of instructions from all classes, and the control flow code selects these routines for execution based on the instructions supported by the processor currently executing the code.

[0073] VEX instruction format

[0074] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or more operand) syntax. For example, a previous two-operand instruction performed an operation that overwrote the source operand (such as A = A + B). The use of the VEX prefix enables the operands to perform a non-destructive operation, such as A = B + C.

[0075] Figure 2A Illustrates an exemplary AVX instruction format, including a VEX prefix 202, an opcode field 230, a Mod R / M byte 240, a SIB byte 250, a displacement field 262, and an IMM8 272. Figure 2B Illustrates which fields from Figure 2A constitute the complete opcode field 274 and the base operation field 241. Figure 2C Illustrates which fields from Figure 2A constitute the register index field 244.

[0076] The VEX prefix (bytes 0-2) 202 is encoded in a three-byte form. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (the unique value for distinguishing the C4 instruction format). The second - third bytes (VEX bytes 1-2) include multiple bit fields that provide dedicated capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bit [7] – R), the VEX.X bit field (VEX byte 1, bit [6] – X), and the VEX.B bit field (VEX byte 1, bit [5] – B). Other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, whereby Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode mapping field 215 (VEX byte 1, bits [4:0] – mmmmm) includes the content that encodes the implicit leading opcode byte. The W field 264 (VEX byte 2, bit [7] – W) is denoted by the notation VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1's complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1's complement form for certain vector displacements; or 3) VEX.vvvv does not encode any operand, and this field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2] - L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0] - pp) provides additional bits for the base operation field 241.

[0077] The real opcode field 230 (byte 3) is also referred to as the opcode byte. Parts of the opcode are specified in this field.

[0078] The MOD R / M field 240 (byte 4) includes the MOD field 242 (bits [7-6]), the Reg field 244 (bits [5-3]), and the R / M field 246 (bits [2-0]). The functions of the Reg field 244 may include the following: encoding a destination register operand or a source register operand (rrr in Rrrr); or being regarded as an opcode extension and not being used to encode any instruction operand. The functions of the R / M field 246 may include the following: encoding an instruction operand that references a memory address; or encoding a destination register operand or a source register operand.

[0079] The content of the Scale, Index, Base (SIB) - Scale field 250 (byte 5) includes SS252 (bits [7-6]) for memory address generation. The content of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) has been previously referenced for register indices Xxxx and Bbbb.

[0080] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0081] Exemplary Register Architecture

[0082] Figure 3 is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310 that are 512 bits wide; these registers are referenced as zmm0 to zmm31. The lower 256 bits of the lower 6 zmm registers overlap the registers ymm0 - 15. The lower 128 bits of the lower 6 zmm registers (the lower 128 bits of the ymm registers) overlap the registers xmm0 - 15.

[0083] General - purpose registers 325 - In the illustrated embodiment, there are sixteen 64 - bit general - purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0084] The scalar floating - point stack register file (x87 stack) 345, on which the MMX packed - integer flat register file 350 overlaps - In the illustrated embodiment, the x87 stack is an eight - element stack for performing scalar floating - point operations on 32 / 64 / 80 - bit floating - point data using the x87 instruction set extension; and the MMX registers are used to perform operations on 64 - bit packed - integer data and to save operands for some operations performed between the MMX and XMM registers.

[0085] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0086] Exemplary Core Architectures, Processors, and Computer Architectures

[0087] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores can include: 1) general-purpose in-order cores intended for general computing; 2) high-performance general-purpose out-of-order cores intended for general computing; 3) specialized cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors can include: 1) a CPU that includes one or more general-purpose in-order cores intended for general computing and / or one or more general-purpose out-of-order cores intended for general computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which can include: 1) a coprocessor on a chip separate from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case, such a coprocessor is sometimes referred to as specialized logic or as a specialized core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system-on-a-chip that can include the described CPU (sometimes referred to as (one or more) application cores or (one or more) application processors), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is then described, followed by exemplary processors and computer architectures. Circuits (units) including exemplary cores, processors, etc. are described in detail herein.

[0088] Exemplary Core Architecture

[0089] Figure 4A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renamed out-of-order issue / execution pipeline in accordance with embodiments of the present invention. Figure 4B is a block diagram showing an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register-renamed out-of-order issue / execution architecture core in accordance with embodiments of the present invention. Figure 4A - Figure 4B The solid boxes in illustrate the in-order pipeline and in-order core, while the optional addition of the dashed boxes illustrates the register-renamed, out-of-order issue / execution pipeline and core. Considering that the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0090] In Figure 4AIn [the figure], the processor pipeline 400 includes a fetch stage 402, a length decoding stage 404, a decoding stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also referred to as dispatch or issue) stage 412, a register read / memory read stage 414, an execution stage 416, a write-back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0091] Figure 4B A processor core 490 is shown. The processor core 490 includes a front-end unit 430 that is coupled to an execution engine unit 450, and both the front-end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 490 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0092] The front-end unit 430 includes a branch prediction unit 432 that is coupled to an instruction cache unit 434, the instruction cache unit 434 is coupled to an instruction translation lookaside buffer (TLB) 436, the instruction translation lookaside buffer 436 is coupled to an instruction fetch unit 438, and the instruction fetch unit 438 is coupled to a decoding unit 440. The decoding unit 440 (or decoder) can decode instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, or otherwise reflect, or are derived from the original instructions. The decoding unit 440 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, the core 490 includes a microcode ROM or other medium (e.g., in the decoding unit 440, or otherwise within the front-end unit 430) that stores microcode for certain macroinstructions. The decoding unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.

[0093] The execution engine unit 450 includes a rename / allocator unit 452 that is coupled to a retirement unit 454 and a collection 456 of one or more scheduler units. The (multiple) scheduler units 456 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The (multiple) scheduler units 456 are coupled to the (multiple) physical register file units 458. Each of the (multiple) physical register file units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, a status (e.g., an instruction pointer that is the address of the next instruction to be executed), and so on. In one embodiment, the (multiple) physical register file units 458 include a vector register unit and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The (multiple) physical register file units 458 are overlapped by the retirement unit 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using the (multiple) reorder buffers and the (multiple) retirement register files; using the (multiple) future files, the (multiple) history buffers, the (multiple) retirement register files; using register maps and register pools, and so on). The retirement unit 454 and the (multiple) physical register file units 458 are coupled to the (multiple) execution clusters 460. The (multiple) execution clusters 460 include a collection 462 of one or more execution units and a collection 464 of one or more memory access units. The execution units 462 can perform various operations (e.g., shift, add, subtract, multiply) and can operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). Although some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The (multiple) scheduler units 456, the (multiple) physical register file units 458, and the (multiple) execution clusters 460 are shown as potentially having multiple because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline that each has its own scheduler unit, (multiple) physical register file units, and / or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented where only the execution cluster of that pipeline has the (multiple) memory access units 464). It should also be understood that in the case of using separate pipelines, one or more of these pipelines can be out-of-order issue / execution, and the remaining pipelines can be in-order.

[0094] A set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472 that is coupled to a data cache unit 474, and the data cache unit 474 is coupled to a second-level (L2) cache unit 476. In one exemplary embodiment, the memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. An instruction cache unit 434 is also coupled to the second-level (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of caches and ultimately to the main memory.

[0095] As an example, an exemplary register-renaming out-of-order issue / execution core architecture may implement a pipeline 400 as follows: 1) Instruction fetch 438 performs a fetch stage 402 and a length decoding stage 404; 2) A decode unit 440 performs a decode stage 406; 3) A rename / allocator unit 452 performs an allocation stage 408 and a rename stage 410; 4) A (multiple) scheduler unit 456 performs a schedule stage 412; 5) A (multiple) physical register file units 458 and a memory unit 470 perform a register read / memory read stage 414; An execution cluster 460 performs an execution stage 416; 6) The memory unit 470 and the (multiple) physical register file units 458 perform a write-back / memory write stage 418; 7) Each unit may be involved in an exception handling stage 422; and 8) A retirement unit 454 and the (multiple) physical register file units 458 perform a commit stage 424.

[0096] The core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with more recent versions); the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, Calif.; the ARM instruction set of ARM Holdings, Inc., Sunnyvale, Calif. (with optional additional extensions such as NEON)), including the (multiple) instructions described herein. In one embodiment, the core 490 includes logic for supporting SIMD (e.g., AVX1, AVX2) instruction set extensions, thereby allowing operations used by many multimedia applications to be performed using SIMD data.

[0097] It should be understood that the core may support multithreading (executing a set of two or more parallel operations or threads), and this multithreading can be accomplished in various ways, including time division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads for which the physical core is simultaneously multithreading), or a combination thereof (e.g., time division fetching and decoding and thereafter such as Simultaneous multithreading in hyperthreading technology).

[0098] Although register renaming has been described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a first-level (L1) internal cache or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0099] Specific exemplary in-order core architecture

[0100] Figure 5A - Figure 5B A block diagram illustrating a more specific exemplary core architecture, which would be one of several logic blocks (including other cores of the same type and / or different types) in a chip. Depending on the application, the logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0101] Figure 5A A block diagram of a single processor core according to an embodiment of the present invention, its connection to the on-die interconnect network 502, and a local subset 504 of its second-level (L2) cache. In one embodiment, the instruction decoder 500 supports the x86 instruction set with a compact data instruction set extension. The L1 cache 506 allows low-latency access to cache memory for data entering the scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 508 and the vector unit 510 use separate register sets (scalar registers 512 and vector registers 514 respectively), and the data transferred between these registers is written to memory and then read back from the first-level (L1) cache 506, alternative embodiments of the present invention may use different methods (e.g., using a single register set or including a communication path that allows data to be transferred between the two register banks without being written and read back).

[0102] The local subset 504 of the L2 cache is part of a global L2 cache that is partitioned into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and dumped and cleared from other subsets as necessary. A ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide in each direction.

[0103] Figure 5B is part of a processor core according to an embodiment of the present invention Figure 5A exploded view. Figure 5B The L1 data cache 506A portion includes the L1 cache 504, and more details regarding the vector unit 510 and the vector registers 514. Specifically, the vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports mixing of register inputs through the mixing unit 520, numerical conversion through the numerical conversion units 522A-B, and copying of memory inputs through the copy unit 524.

[0104] A processor with an integrated memory controller and a graphics device

[0105] Figure 6 is a block diagram of a processor 600 according to an embodiment of the present invention that can have more than one core, can have an integrated memory controller, and can have an integrated graphics device. Figure 6 The solid box diagram in shows a processor 600 having a single core 602A, a system agent 610, and a set 616 of one or more bus controller units, while the optional addition of the dashed box diagram shows an alternative processor 600 having multiple cores 602A-N, a set 614 of one or more integrated memory controller units in the system agent unit 610, and dedicated logic 608.

[0106] Accordingly, different implementations of the processor 600 can include: 1) a CPU, where the dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the cores 602A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of both); 2) a coprocessor, where the cores 602A-N are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where the cores 602A-N are a large number of general-purpose in-order cores. Thus, the processor 600 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor can be implemented on one or more chips. The processor 600 can be part of one or more substrates, and / or can be implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0107] The memory hierarchy includes one or more cache levels within the cores 604A-N, a set 606 of one or more shared cache units, and external memory (not shown) coupled to a set 614 of integrated memory controller units. The set 606 of shared cache units can include one or more intermediate-level caches, such as a second-level (L2), third-level (L3), fourth-level (L4) or other-level caches, a last-level cache (LLC), and / or a combination of the foregoing. Although in one embodiment, the ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the set 606 of shared cache units, and the system agent unit 610 / (a plurality of) integrated memory controller units 614, alternative embodiments can use any number of well-known techniques to interconnect such units. In one embodiment, coherence is maintained between one or more cache units 606 and the cores 602A-N.

[0108] In some embodiments, one or more of the cores 602A-N are capable of implementing multithreading. The system agent 610 includes those components that coordinate and operate the cores 602A-N. The system agent unit 610 can include, for example, a power control unit (PCU) and a display unit. The PCU can be, or can include, the logic and components required to regulate the power states of the cores 602A-N and the integrated graphics logic 608. The display unit is used to drive one or more externally connected displays.

[0109] The cores 602A-N may be homogeneous or heterogeneous in terms of the architectural instruction set; i.e., two or more of the cores 602A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0110] Exemplary computer architecture

[0111] Figure 7 - 10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop devices, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.

[0112] Now referring Figure 7 , shown is a block diagram of a system 700 in accordance with an embodiment of the present invention. System 700 may include one or more processors 710, 715, which are coupled to a controller hub 720. In one embodiment, controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); GMCH 790 includes a memory and graphics controller to which a memory 740 and a coprocessor 745 are coupled; IOH 750 couples input / output (I / O) devices 760 to GMCH 790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), memory 740 and coprocessor 745 are directly coupled to processor 710, and controller hub 720 is in a single chip with IOH 750.

[0113] The optionality of the additional processor 715 is indicated by the dashed line in Figure 7 . Each processor 710, 715 may include one or more of the processing cores described herein and may be a certain version of processor 600.

[0114] Memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, controller hub 720 communicates with the (multiple) processors 710, 715 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 795.

[0115] In one embodiment, the coprocessor 745 is a specialized processor such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0116] There may be various differences in a series of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc. between the physical resources 710, 715.

[0117] In one embodiment, the processor 710 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within these instructions. The processor 710 identifies these coprocessor instructions as being of a type that should be executed by the attached coprocessor 745. Accordingly, the processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect to the coprocessor 745. The (multiple) coprocessor 745 receives and executes the received coprocessor instructions.

[0118] Now refer to Figure 8 , shown is a block diagram of a first more specific exemplary system 800 according to an embodiment of the present invention. As Figure 8 shown, the multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of the processors 870 and 880 may be a certain version of the processor 600. In one embodiment of the present invention, the processors 870 and 880 are the processors 710 and 715 respectively, and the coprocessor 838 is the coprocessor 745. In another embodiment, the processors 870 and 880 are the processor 710 and the coprocessor 745 respectively.

[0119] The processors 870 and 880 are shown as including integrated memory controller (IMC) units 872 and 882 respectively. The processor 870 also includes point-to-point (P-P) interfaces 876 and 878 as part of its bus controller unit; similarly, the second processor 880 includes P-P interfaces 886 and 888. The processors 870, 880 may exchange information via the P-P interface 850 using the point-to-point (P-P) interface circuits 878, 888. As Figure 8 shown, the IMCs 872 and 882 couple the processors to the respective memories, namely memories 832 and 834, which may be portions of the main memories locally attached to the respective processors.

[0120] Processors 870, 880 may each exchange information with chipset 890 via respective P-P interfaces 852, 854 using point-to-point interface circuits 876, 894, 886, 898. Chipset 890 may optionally exchange information with coprocessor 838 via high performance interface 892. In one embodiment, coprocessor 838 is a specialized processor such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0121] A shared cache (not shown) may be included in either processor, or external to both processors but connected to these processors via a P-P interconnect such that if a processor is placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0122] Chipset 890 may be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another I / O interconnect bus, but the scope of the present invention is not limited thereto.

[0123] As Figure 8 shown, various I / O devices 814 may be coupled to first bus 816 along with bus bridge 818 which couples first bus 816 to second bus 820. In one embodiment, one or more additional processors 815 such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a Digital Signal Processing (DSP) unit), a Field Programmable Gate Array or any other processor are coupled to first bus 816. In one embodiment, second bus 820 may be a Low Pin Count (LPC) bus. In one embodiment, various devices may be coupled to second bus 820 including, for example, keyboard and / or mouse 822, communication device 827, and storage unit 828 which may include, for example, a disk drive or other mass storage device with instructions / code and data 830. Additionally, audio I / O 824 may be coupled to second bus 820. Note that other architectures are possible. For example, instead of Figure 8 the point-to-point architecture, the system may implement a multi-branch bus or other such architecture.

[0124] Now referring Figure 9 , shown is a block diagram of a second more specific exemplary system 900 in accordance with an embodiment of the present invention. Figure 8 and 9 Like elements in Figure 9 are designated with like reference numerals and Figure 8certain aspects to avoid confusion Figure 9 other aspects of

[0125] Figure 9 As shown, processors 870, 880 may each include integrated memory and I / O control logic ("CL") 972 and 982. Thus, CL 972, 982 includes an integrated memory controller unit and includes I / O control logic. Figure 9 As shown, not only memories 832, 834 are coupled to CL 872, 882, but also I / O device 914 is coupled to control logic 872, 882. Conventional I / O device 915 is coupled to chipset 890.

[0126] Now referring to Figure 10 , shown is a block diagram of an SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in Figure 10 are denoted with similar reference numerals. Additionally, the dashed boxes are optional features on more advanced SoCs. In

[0127] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as a computer program or program code executing on a programmable system that includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0128] Program code (such as Figure 8The code 830) illustrated in the figure is applied to the input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0129] The program code can be implemented in a high-level procedural programming language or an object-oriented programming language in order to communicate with the processing system. If desired, the program code can also be implemented in assembly language or machine language. In fact, the mechanisms described herein are not limited to the scope of any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0130] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium that represent various logic in a processor, which when read by the machine cause the machine to fabricate logic for performing the techniques described herein. Such representations, referred to as “IP cores,” can be stored on a tangible machine-readable medium and supplied to various customers or production facilities to be loaded into the manufacturing machines that actually make the logic or processor.

[0131] Such machine-readable storage media can include, but are not limited to, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, which include storage media such as hard disks; any other type of disk, including floppy disks, optical disks, compact disk read only memory (CD-ROM), rewritable compact disks (CD-RW), and magneto-optical disks; semiconductor devices such as read only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read only memory (EPROM), flash memory, electrically erasable programmable read only memory (EEPROM); phase change memory (PCM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0132] Accordingly, embodiments of the present invention also include non-transitory, tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL), that define the structures, circuits, devices, processors, and / or system features described herein. These embodiments are also referred to as program products.

[0133] Emulation (including binary translation, code morphing, etc.)

[0134] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may transform (e.g., using static binary translation, dynamic binary translation including dynamic compilation), mutate, emulate, or otherwise convert an instruction or instructions to be processed by the core into one or more other instructions. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, off the processor, or partially on the processor and partially off the processor.

[0135] Figure 11 is a block diagram of an example of using a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 shows that a first compiler 1104 may be used to compile a program in the form of a high-level language 1102 to generate first binary code (e.g., x86) 1106 that can be natively executed by a processor 1116 having at least one first instruction set core. In some embodiments, the processor 1116 having at least one first instruction set core represents any processor that performs substantially the same functions as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise executing: 1) an essential portion of the instruction set of the Intel x86 instruction set core, or 2) a target code version of an application or other software targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 1104 represents a compiler operable to generate binary code 1106 (e.g., target code) of a first instruction set that can be executed on the processor 1116 having at least one first instruction set core with or without additional linking processing. Similarly, Figure 11It is shown that an alternative instruction set compiler 1108 can be used to compile a program in the form of a high-level language 1102 to generate alternative instruction set binary code 1110 that can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies, Inc. in Sunnyvale, California, and / or the ARM instruction set of ARM Holdings plc in Sunnyvale, California). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively executed by a processor 1114 that does not have a first instruction set core. The converted code is not likely to be the same as the alternative instruction set binary code 1110 because it is difficult to manufacture an instruction converter that can do so; however, the converted code will perform general operations and is composed of instructions from an alternative instruction set. Thus, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 1106 through emulation, simulation, or any other process.

[0136] Exemplary digital signal processing architecture

[0137] One embodiment of the present invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. Specifically, one embodiment includes a multiply-accumulate (MAC) architecture having eight 16x16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can process various multiplication and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. Additionally, certain instructions have direct support for highly efficient fast Fourier transform (FFT) and finite impulse response (FIR) filtering, as well as post-processing of accumulated data through shift, round, and saturation operations.

[0138] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix, and some of the SSE / SSE2 / AVX instructions that handle post-processing of data are used in conjunction with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands can have relaxed memory alignment requirements.

[0139] In one embodiment, the instructions also support various integer and fixed-point data types, including:

[0140] 1) Q31 data types with more than 16 bits, for signals that require analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC);

[0141] 2) Q15 data types commonly used in DSP algorithms;

[0142] 3) A 16-bit complex data type; and

[0143] 4) A 32-bit complex data type.

[0144] The instruction set architecture described herein is directed to a wide range of standard DSPs (e.g., FFT, filtering, pattern matching, correlation, polynomial evaluation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0145] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a wide range of instructions applicable to deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion using Kalman filtering, other major DSP applications, etc. Given a weight sequence {w 1 , w 2 , … w k} and an input sequence {x 1 , x 2 , x 3 , … x n}, many image processing and machine learning tasks require computing a result sequence {y i = w 1 x i + w 2 x i+1 + …………… + w k x i+k-1} defined by 1 , y 2 , y 3 , … y n+1-k}.

[0146] Figure 12 The illustration includes an exemplary processor 1255 on which embodiments of the present invention may be implemented. The exemplary processor 1255 includes multiple cores 0 - N for simultaneously executing multiple instruction threads. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within a decoder 1230 and DSP instruction execution circuitry / logic 1241 within an execution unit 1240. In response to the decoding and execution of DSP instructions, these pipeline components may perform the operations described herein. Although only the details of a single core (core 0) are shown in Figure 12 , it will be understood that each of the other cores of the processor 1255 may include similar components.

[0147] Before describing the specific details of embodiments of the present invention, a description of the components of an exemplary processor 1255 is provided directly below. Each of the plurality of cores 0-N may include a memory management unit 1290 for performing memory operations (such as load / store operations), a set 1205 of general-purpose registers (GPRs), a set 1206 of vector registers, and a set 1207 of mask registers. In one embodiment, a plurality of vector data elements are packed into each vector register 1206, and each vector register 1206 may have a width of 512 bits for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the basic principles of the present invention are not limited to any particular size / type of vector data. In one embodiment, the mask register 1207 includes eight 64-bit operand mask registers (e.g., implemented as mask registers k0-k7 as described herein) for performing bit mask operations on the values stored in the vector register 1206. However, the basic principles of the present invention are not limited to any particular mask register size / type.

[0148] Each of the cores 0-N may include a dedicated first-level (L1) cache 1212 and a second-level (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. The instructions and data stored in the processor caches are managed at the granularity of cache lines that may be of a fixed size (e.g., 64 bytes, 128 bytes, 512 bytes in length). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from the main memory 1200 and / or the shared third-level (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from the memory 1200 (or one of the caches); an instruction translation lookaside buffer (ITLB) 1204 for storing the mapping of the most recently used virtual-to-physical instruction addresses to improve the address translation speed; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0149] As mentioned, the decoding unit 1230 includes DSP instruction decoding circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops", and the execution unit 1240 includes DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. The writeback / retirement unit 1250 retires the executed instructions and writes back the results.

[0150] One embodiment of the first instruction is represented as VPRCPUFW xmm1,xmm2 / m128, where xmm2 / m128 is the source register or memory location storing the input word value whose reciprocal will be calculated, and xmm1 is the destination register for storing the reciprocal result. The second instruction, represented as VPRCPUFD xmm1,xmm2 / m128, takes the reciprocal of the double word value stored in xmm2 / m128 and stores the reciprocal in xmm1.

[0151] Figure 13 The figure illustrates exemplary data elements and bit distributions for exemplary source registers and / or destination registers (SRCx / DESTx). As illustrated, data elements can be packed into the source register and / or destination register as words (16 bits), double words (32 bits), and / or quad words (64 bits). In some embodiments dealing with complex numbers, the real and imaginary parts can be stored in adjacent data element positions. For example, the real part can be stored as data element A, and the corresponding imaginary part can be stored as data element B. However, in some of the embodiments described herein, including reciprocal instructions and reciprocal square root instructions, the packed data elements do not represent complex numbers. Instead, in these embodiments, the packed data elements are real words and double words.

[0152] Figure 14 The figure illustrates an exemplary architecture for performing various different DSP instructions, including at least some of the operations required for fractional reciprocal and reciprocal square root instructions. The general operation of the architecture will be described first, followed by the specific implementation of the reciprocal instructions. When executing a DSP instruction, one or more packed word, double word, or quad word values are stored in registers SRC 1401 and / or SRC 1402. A set of multipliers 1405 multiplies the selected packed data elements in SRC 1401 with the selected packed data elements in SRC2. Different data element sizes and different combinations of packed data elements can be selected for the multiplication based on the specific DSP instruction being executed. The adder networks 1410 - 1411 then add / subtract the resulting products of the multiplications in different combinations according to the instruction.

[0153] Depending on the instruction, accumulators 1420 - 1421 can combine the selected results generated by the multipliers 1405 and / or the adder networks 1410 - 1411 with the accumulated results in the SRC / DEST register 1460. The saturation units 1440 - 1441 generate saturated data elements from the accumulated results (again depending on the instruction), and the output multiplexer 1450 forwards the final result to the SRC / DEST register 1460.

[0154] Depending on the instruction, various other operations can be performed, such as shifting, extracting, loading, storing, permuting, zero extending, sign extending, and rounding, to name just a few. In addition, the product generated by the multiplier 1405 and the result generated by the adder network 1410 - 1411 can be stored in a temporary register or memory location (not shown). Some of these temporary storage locations are hereinafter designated by ftmp[n], where n is an integer identifying a particular temporary storage location.

[0155] In one embodiment, the following functions that operate on unsigned words and double words are used in fixed-point DSP algorithms:

[0156] y = 1 / x (fractional reciprocal); and

[0157] y = 1 / sqrt(x) (reciprocal square root).

[0158] An embodiment of the fractional reciprocal instruction is first described below in Part A. Then an embodiment of the reciprocal square root is described in Part B.

[0159] A. Example for performing a fractional reciprocal operation on packed data elements

[0160] One embodiment of the present invention includes a first instruction for determining the reciprocal of an unsigned word and a second instruction for determining the reciprocal of an unsigned double word. Within the source and destination registers described herein, word values can be stored as packed 16-bit data elements, and double word values can be stored as packed 32-bit data elements.

[0161] Given an input value x, one embodiment of the present invention calculates y = 1 / x. A first instruction (e.g., VPRCPUFD) can be executed for the double word value of x, and a second instruction (e.g., VPRCPUFW) can be executed for the word value of x. The double word implementation will be described first, followed by the word implementation.

[0162] 1. Exemplary double - word reciprocal operation

[0163] In one embodiment, the input x is a double word having an unsigned Q0.32 format. Q specifies a fixed-point number format, where the number of fractional bits and the number of potential integer bits are specified. For example, a Q1.14 number has 1 integer bit and 14 fractional bits. In the current application, the Q0.32 number format for x has 32 fractional bits and thus is scaled by 2 32 . In one embodiment, the range of x is set between 0.5 and 1 (i.e., [0.5, 1]) or [0x80000000, 0xFFFFFFFF]). In addition, in one embodiment, the result y is an unsigned Q1.31 number and thus is scaled by 2 31。In one embodiment, the allowable range of y is between 1 and 2 (i.e., [1, 2] or [0x80000000, 0xFFFFFFFF]). In one implementation, the maximum absolute error of the reciprocal operation is 1.09 ulp, and the reciprocal is estimated to be almost 16 bits using a 3rd degree polynomial.

[0164] Figure 15 FIG. illustrates an exemplary execution circuit 1240 for performing a fractional reciprocal instruction y = 1 / x in accordance with the above specification. Figure 15 The execution circuit in may include components from Figure 14 the DSP architecture and / or may use a different execution circuit. In one embodiment, the input value X includes a doubleword value (32 bits), where bits b30 and b29 are used to index the shown coefficient table. Each row in the coefficient table includes a different set of coefficients c3 n , c2 n , c1 n and c0 n , and one of the sets is selected based on the values of b30 and b29. In one embodiment, a permutation instruction such as VPERMILPS is executed to read the coefficients from the row of the coefficient table identified by the b30 and b29 values. For example, based on a specified control value, the VPERMILPS instruction may retrieve different coefficients from different registers or memory locations.

[0165] In one embodiment, the multiplier 1405 then reads a coefficient from one of the source registers 1401 - 1402 (via the input multiplexer 1403) and multiplies the packed value as Figure 15 indicated. For example, in the illustrated implementation, c3 2 is multiplied by R 3 , c2 2 is multiplied by R 2 , and c1 2 is multiplied by R. The resulting products c1 2 *R, c2 2 *R 2 , c3 2 *R 3 are added to c0 2 by the adder network 1410 - 1411 to generate the result: c0 2 + c1 2 *R + c2 2 *R 2 + c3 2 *R 3 .

[0166] In one embodiment, the Newton-Raphson logic / circuit 1510 applies Newton-Raphson approximation techniques to approximately double the accuracy of the result. This can be achieved by calculating the relative error for an initial approximation and then applying refinement steps to the approximation. However, the basic principles of the present invention do not require the Newton-Raphson technique. In one embodiment, for out-of-range inputs (e.g., x < 0.5), the output is 0xFFFFFFFF.

[0167] In one embodiment, the reciprocal word operation is implemented in a similar manner, but using word values instead of double-word values. The overall calculation is also y = 1 / x, where the input x is in unsigned Q0.16 format and is thus scaled by 2 16 . The x range is in [0.5, 1] or [0x8000, 0xFFFF], and the result y uses unsigned Q1.15 format and is thus scaled by 2 15 . The y range is in [1, 2] or [0x8000, 0xFFFF].

[0168] In the word implementation, the coefficient table 1505 is an 8-entry table, and the three leading bits of the input (i.e., bits 14, 13, and 12 in one embodiment) are used as a table index to retrieve coefficients c3 n , c2 n , c1 n and c0 n (where n is in the range [0, 7]). The remaining input bits [11:0] of the fraction R are used as the argument of the polynomial c3*R 3 +c2*R 2 +c1*R + c0. The result of evaluating this polynomial is the instruction output (for in-range inputs). For out-of-range inputs (e.g., x < 0.5), the output is 0xFFFF.

[0169] Similar to the double-word reciprocal instruction described above, the multiplier 1405 multiplies the input value (R) by the coefficients, and the results are added / subtracted by the adder network 1410 - 1411 (as shown in the code example below). As in the case of the double-word instruction, the Newton-Raphson logic / circuit 1510 can apply Newton-Raphson estimation techniques to the result to approximately double the accuracy. In one embodiment, this is achieved by calculating the relative error for an initial approximation and then applying refinement steps to the approximation. However, the basic principles of the present invention do not require the Newton-Raphson technique.

[0170] In Figure 16 illustrates a method according to an embodiment of the present invention. The method can be implemented within the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0171] At 1601, a reciprocal instruction is fetched, which has fields for an opcode, a packed data source operand, and a packed data destination operand. At 1602, the reciprocal instruction is decoded to generate a decoded reciprocal instruction (e.g., decoded into multiple micro-operations that perform the various operations described herein).

[0172] At 1603, the coefficient values required to perform the reciprocal operation are fetched (e.g., from a cache / memory) and stored in a temporary register or other storage location. Additionally, the input data is fetched and stored in a source register (e.g., SRC 1401). As mentioned, a double-word reciprocal instruction uses a double-word value to determine the reciprocal, while a word reciprocal instruction uses a word value to determine the reciprocal. Thus, the input data can be stored in the first source register as a packed double-word (32 bits) or a packed word (16 bits) value, depending on the implementation. As mentioned, in one embodiment, the source register is a 128-bit packed data register. The operations of the reciprocal instruction are scheduled. For example, the micro-operations into which the instruction is decoded can be queued for execution on multiple different functional units of the execution circuitry.

[0173] At 1604, a first decoded instruction is executed by using a first portion of the input data as an index value for identifying the coefficient to be used from a coefficient table. In one embodiment, the coefficient table is scattered across multiple temporary storage locations. In an alternative embodiment, it can be stored in Figure 14 one of the source registers shown. Regardless of where it is stored, a permutation instruction is executed by using the first portion of the input data as an index value (as described in detail below) to perform a lookup operation. In one embodiment, the first portion of the input data includes bits 29 and 30 for a double-word value, and the first portion of the input data includes bits 12, 13, and 14 for a word value. Thus, in a double-word implementation, bits 29 - 30 are used to index one of four entries in the coefficient table, and in a word implementation, bits 12 - 14 are used to index one of eight entries in the coefficient table.

[0174] Once the coefficient is identified, multiply the second portion (R) of the input data and / or the coefficient to determine the temporary values c3*R 3 、c2*R 2 and c1*R. Then add the temporary values and the coefficient according to the polynomial c3*R 3 +c2*R 2 +c1*R + c0 to generate a first result. If Newton-Raphson techniques are used, apply them to the first result to generate the final result. At 1605, store the final result in a packed destination register.

[0175] 2. Exemplary code sequence for double - word reciprocal operation

[0176] a. Reciprocal code sequence

[0177] In one embodiment, when a reciprocal fraction instruction is executed on a double-word input, the architecture performs the following sequence of operations:

[0178] unsigned RMASK[] = {0x1fffffff,0x1fffffff,0x1fffffff,0x1fffffff};

[0179] / / c3*2 31

[0180] unsigned __c3[] =

[0181] {0xA2D2ED1E,0x488414BD,0x250AB12B,0x14D9F815};

[0182] / / c2*2 31

[0183] unsigned __c2[] =

[0184] {0xF31A0690,0x7E7D71F9,0x49E7BA04,0x2ED42A03};

[0185] / / c1*2 31

[0186] unsigned __c1[] =

[0187] {0xFF661F9F,0xA39FA3BB,0x71AF5BD0,0x538BFD49};

[0188] / / c0*2 31

[0189] unsigned __c0[] =

[0190] {0xFFFEDDA3,0xCCCC631A,0xAAAA7D02,0x92490E4E};

[0191] / / (1 + small_correction)*2 63

[0192] unsigned ONE[] = {0xf0000000,0x80000000,0xf0000000,0x80000000};

[0193] / / For inverting the mask

[0194] unsigned NEG_MASK[] = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff};

[0195] / / Input data

[0196] vmovdqa ftmp0, xmm2 / m128

[0197] / / Reduced argument R

[0198] vandps ftmp6, ftmp0, XMMWORD PTR [RMASK]

[0199] / / Adjust scaling factor

[0200] vpaddd ftmp6, ftmp6, ftmp6

[0201] / / Index: Two leading fractional bits

[0202] vpsrld ftmp1, ftmp0, 29

[0203] / / vmovd eax, ftmp0

[0204] / / sar eax, 31

[0205] / / not eax

[0206] / / Get coefficient, sc 2 31

[0207] vmovdqa ftmp5, XMMWORD PTR [__c3]

[0208] vmovdqa ftmp3, XMMWORD PTR [__c1]

[0209] / / Equivalent to table lookup

[0210] vpermilps ftmp5, ftmp5, ftmp1 / / c3

[0211] vpermilps ftmp3, ftmp3, ftmp1 / / c1

[0212] / / c3 * R * 2 (32+31)

[0213] vpmuludq ftmp4, ftmp5, ftmp6

[0214] vmovdqa XMMWORD PTR [temp1], ftmp6

[0215] VPMULUDHHQ ftmp5, ftmp5, ftmp6

[0216] / / The mix instruction is used to combine the results from two MUL instructions into

[0217] / / one SIMD register (two 32x32 -> 64-bit MUL instructions are used for

[0218] / / each 4-way SIMD / / multiplication step)

[0219] / / c3*R*2 31

[0220] vpsrlq ftmp4, ftmp4, 32

[0221] vpblendw ftmp5, ftmp5, ftmp4, 0x33

[0222] / / c1*R*2 (32+31)

[0223] vpmuludq ftmp2, ftmp3, ftmp6

[0224] VPMULUDHHQ ftmp3, ftmp3, ftmp6

[0225] / / c1*R*2 31

[0226] vpsrlq ftmp2, ftmp2, 32

[0227] vpblendw ftmp3, ftmp3, ftmp2, 0x33

[0228] / / R 2 *2 64

[0229] vpmuludq ftmp7, ftmp6, ftmp6

[0230] VPMULUDHHQ ftmp6, ftmp6, ftmp6

[0231] / / R 2 *2 32

[0232] vpsrlq ftmp7, ftmp7, 32

[0233] vpblendw ftmp6,ftmp6,ftmp7,0x33

[0234] / / Table lookup

[0235] vmovdqa ftmp4,XMMWORD PTR[__c2]

[0236] vmovdqa ftmp2,XMMWORD PTR[__c0]

[0237] vpermilps ftmp4,ftmp4,ftmp1 / / c2

[0238] vpermilps ftmp2,ftmp2,ftmp1 / / c0

[0239] / / (c2 - c3*R)*2 31

[0240] vpsubd ftmp4,ftmp4,ftmp5

[0241] / / (c0 - c1*R)*2 31

[0242] vpsubd ftmp2,ftmp2,ftmp3

[0243] / / (c2 - c3*R)*R 2 *2 63

[0244] vpmuludq ftmp7,ftmp6,ftmp4

[0245] VPMULUDHHQ ftmp6,ftmp6,ftmp4

[0246] / / (c2 - c3*R)*R 2 *2 31

[0247] vpsrlq ftmp7,ftmp7,32

[0248] vpblendw ftmp6,ftmp6,ftmp7,0x33

[0249] / / (c0 - c1*R)*2 31 +(c2 - c3*R)*R 2 *2 31

[0250] vpaddd ftmp6,ftmp6,ftmp2

[0251] / / The starting approximation is now in ftmp6

[0252] vmovdqa ftmp4,XMMWORD PTR[ONE]

[0253] vmovdqa ftmp2,XMMWORD PTR[ONE]

[0254] / / x * rcp * 2 63

[0255] vpmuludq ftmp1,ftmp0,ftmp6

[0256] VPMULUDHHQ ftmp5,ftmp0,ftmp6

[0257] / / eps * 2 63 = (1 - x * rcp) * 2 63

[0258] vpsubq ftmp4,ftmp4,ftmp1

[0259] vpsubq ftmp2,ftmp2,ftmp5

[0260] / / The 64 - bit relative error terms are in (ftmp4, ftmp2)

[0261] / / Prepare the correction mask

[0262] vpsrad ftmp0,ftmp0,32

[0263] vpxor ftmp0,ftmp0,XMMWORD PTR[NEG_MASK]

[0264] / / For inputs in the range ftmp0 = 0, otherwise 0xFFFFFFFF

[0265] / / ****** Version 1: Slightly faster, accuracy 1.9 ulp

[0266] / / eps * 2 32

[0267] vpsrlq ftmp4,ftmp4,31

[0268] vpsllq ftmp2,ftmp2,1

[0269] vpblendw ftmp4,ftmp2,ftmp4,0x33

[0270] / / Get the symbol (eps)

[0271] vpsrad ftmp3,ftmp4,31

[0272] / / Since eps is signed, this is the required correction term, but using

[0273] / / Unsigned MUL operation

[0274] vpandn ftmp3,ftmp3,ftmp6

[0275] / / rcp*eps*2 63

[0276] vpmuludq ftmp2,ftmp6,ftmp4

[0277] VPMULUDHHQ ftmp6,ftmp6,ftmp4

[0278] / / rcp*eps*2 31

[0279] vpsrlq ftmp2,ftmp2,32

[0280] vpblendw ftmp6,ftmp6,ftmp2,0x33

[0281] / / Result

[0282] vpaddd ftmp6,ftmp6,ftmp3

[0283] / / Correction for out-of-range inputs (if out-of-range then ftmp0 = 0xFFFFFFFFF)

[0284] vpor xmm1,ftmp0,ftmp6

[0285] b. Analysis of the reciprocal code sequence

[0286] In the above code, each of the four possible values of the four coefficients c0, c1, c2, and c3 is specified. For example, the four possible values of c3 are 0xA2D2ED1E, 0x488414BD, 0x250AB12B, and 0x14D9F815. Additionally, the variables RMASK and NEG_MASK are set (i.e., initialized to 0xffffffff), and the variable 1 is also set (initialized to 0x80000000f0000000).

[0287] The variable "fmtpn" in the code identifies different temporary storage locations. For example, the initial instruction vmovdqa ftmp0,xmm2 / m128 moves the input value X from the xmm2 register (or 128-bit memory location) to the temporary storage location ftmp0.

[0288] The instruction vector AND instruction vandps then performs a bitwise AND operation on the source value X stored in fmtp0 and the RMASK value according to the requirements of the reciprocal calculation to reduce the source value to R. The resulting value is stored in ftmp6. Then, the vector AND instruction vpanddd is executed with both the source and destination set to ftmp6 to adjust the scaling factor for the reciprocal.

[0289] Then, the right shift packed data instruction vpsrld is executed to isolate the two leading bits of the fractional value from ftmp0. Specifically, the value is shifted right by 29, placing the two index bits (such as Figure 15 b29 and b30 as shown) in the least significant bit positions of the temporary storage ftmp1.

[0290] The following instruction sequence moves the coefficient data of c3 and c1 to ftmp5 and ftmp3 respectively:

[0291] vmovdqa ftmp5,XMMWORD PTR[__c3]

[0292] vmovdqa ftmp3,XMMWORD PTR[__c1]

[0293] The vpermilps permutation instruction then uses the index values in ftmp1 (including b29 and b30 or the input value) to select specific c3 and c1 packed data values from ftmp5 and ftmp3 respectively (which is equivalent to a table lookup using these index values):

[0294] vpermilps ftmp5,ftmp5,ftmp1 / / c3

[0295] vpermilps ftmp3,ftmp3,ftmp1 / / c1

[0296] The multiplication operation (c3 * 2 31 ) * (R * 2 32 ) is implemented by the following set of instructions:

[0297] vpmuludq ftmp4,ftmp5,ftmp6

[0298] vmovdqa XMMWORD PTR[temp1],ftmp6

[0299] vpmuludhhq ftmp5, ftmp5, ftmp6

[0300] In one embodiment, the mixed instruction can then be used to combine the results from these two multiplications into one SIMD register (two 32x32 -> 64-bit MUL instructions for each 4-way SIMD multiplication step). Specifically, the operation c3 * R * 2 31 is implemented by the right shift instruction vpsrlq, which shifts the 64-bit product in ftmp4 by 32 (to align the relevant 32 bits), followed by the mixed instruction vpblendw, which combines the relevant word data elements from ftmp4 and ftmp5 into ftmp5:

[0301] vpsrlq ftmp4, ftmp4, 32

[0302] vpblendw ftmp5, ftmp5, ftmp4, 0x33

[0303] The value c1 * R * 2 is determined using a double multiplication instruction (32+31) , where the double multiplication instruction multiplies the different components of c1 stored in ftmp3 by the components of the source value stored in ftmp6:

[0304] vpmuludq ftmp2, ftmp3, ftmp6

[0305] vpmuludhhq ftmp3, ftmp3, ftmp6

[0306] The value c1 * R * 2 is then determined by using a right shift followed by a blend, 31 as discussed above for c3:

[0307] vpsrlq ftmp2, ftmp2, 32

[0308] vpblendw ftmp3, ftmp3, ftmp2, 0x33

[0309] The value R2 * 2 is determined by using the double multiplication instruction discussed above, using the different components of the source data in ftmp6 64 :

[0310] vpmuludq ftmp7, ftmp6, ftmp6

[0311] VPMULUDHHQ ftmp6, ftmp6, ftmp6

[0312] The value R * 2 is then determined by using the right shift and blend instructions discussed above 2 * 232 :

[0313] vpsrlq ftmp7, ftmp7, 32

[0314] vpblendw ftmp6, ftmp6, ftmp7, 0x33

[0315] In one embodiment, the following instruction sequence moves coefficient data from c2 and c0 to ftmp4 and ftmp2 respectively, and then performs a table lookup on c2 and c0 respectively using the permutation instruction vpermilps (as discussed above for c3 and c1):

[0316] vmovdqa ftmp4, XMMWORD PTR [__c2]

[0317] vmovdqa ftmp2, XMMWORD PTR [__c0]

[0318] vpermilps ftmp4, ftmp4, ftmp1 / / c2

[0319] vpermilps ftmp2, ftmp2, ftmp1 / / c0

[0320] Use the subtraction instruction vpsubd ftmp4, ftmp4, ftmp5 to determine the value (c2 - c3 * R) * 2 31 , and use the subtraction instruction vpsubd ftmp2, ftmp2, ftmp3 to determine the value (c0 - c1 * R) * 2 31 .

[0321] In one embodiment, then determine the value (c2 - c3 * R) * R via the double multiplication operations vpmuludq ftmp7, ftmp6, ftmp4 and vpmuludhhq ftmp6, ftmp6, ftmp4 2 * 2 63 , and determine the value (c2 - c3 * R) * R by the right shift and blend operations vpsrlq ftmp7, ftmp7, 32 and vpblendw ftmp6, ftmp6, ftmp7, 0x33 2 * 2 31 . Use the addition instruction vpaddd ftmp6, ftmp6, ftmp2 to determine the value (c0 - c1 * R) * 2 31 + (c2 - c3 * R) * R 2 * 2 31 .

[0322] At this stage, the starting approximation is stored in ftmp6:

[0323] vmovdqa ftmp4,XMMWORD PTR[ONE]

[0324] vmovdqa ftmp2,XMMWORD PTR[ONE]

[0325] The values x*rcp*2 are determined by the double multiplication instructions vpmuludq ftmp1,ftmp0,ftmp6 and vpmuludhhq ftmp5,ftmp0,ftmp6 63 and the values eps*2 are determined via the subtraction instructions vpsubq ftmp4,ftmp4,ftmp1 and vpsubq ftmp2,ftmp2,ftmp5 63 =(1 - x*rcp)*2 63 .

[0326] In this example, the 64-bit relative error terms are in (ftmp4,ftmp2). In one embodiment, the correction mask is prepared as follows:

[0327] vpsrad ftmp0,ftmp0,32

[0328] vpxor ftmp0,ftmp0,XMMWORD PTR[NEG_MASK]

[0329] / / For inputs in the range ftmp0 = 0, otherwise 0xFFFFFFFF

[0330] The following instructions are used to improve the accuracy of eps*2 32 (e.g., as part of the Newton-Raphson technique mentioned above). The following two shift instructions shift the values in ftmp4 and ftmp2 to the right and left respectively by a specified amount (31 and 1 respectively):

[0331] vpsrlq ftmp4,ftmp4,31

[0332] vpsllq ftmp2,ftmp2,1

[0333] The blend instruction vpblendw then blends the selected data elements from ftmp4 and ftmp2 and stores them in ftmp4:

[0334] vpblendw ftmp4,ftmp2,ftmp4,0x33

[0335] The vpsrad instruction then uses vpsrad ftmp3, ftmp4, 31 to determine the sign of the value (eps) in ftmp4.

[0336] Since eps is signed, the following correction terms are then used, but an unsigned MUL operation is used:

[0337] vpandn ftmp3, ftmp3, ftmp6

[0338] Specifically, the AND NOT instruction is used with the values from ftmp6 and ftmp3 and the result is stored in ftmp3.

[0339] The following two multiplication instructions are used to determine the value rcp * eps * 2 63 , multiplying the selected elements from ftmp4 and ftmp6:

[0340] vpmuludq ftmp2, ftmp6, ftmp4

[0341] vpmuludhhq ftmp6, ftmp6, ftmp4

[0342] The value rcp * eps * 2 is then determined by performing right shift and blend instructions 31 :

[0343] vpsrlq ftmp2, ftmp2, 32

[0344] vpblendw ftmp6, ftmp6, ftmp2, 0x33

[0345] The final result is then determined by adding the elements from ftmp3 to ftmp6 and storing the result in ftmp6:

[0346] vpaddd ftmp6, ftmp6, ftmp3

[0347] The ftmp6 result can be ORed with ftmp to correct for out-of-range inputs (i.e., if out of range then ftmp0 = 0xFFFFFFFFF):

[0348] vpor xmm1, ftmp0, ftmp6

[0349] 3. Exemplary code sequence for word reciprocal operation

[0350] a. Reciprocal code sequence

[0351] As mentioned, the overall calculation is y = 1 / x, where the input x is in unsigned Q0.16 format and is thus scaled by 2 16 . The x range is in [0.5, 1] or [0x8000, 0xFFFF], and the result y uses unsigned Q1.15 format and is thus scaled by 2 15 . The y range is in [1, 2] or [0x8000, 0xFFFF].

[0352] Coefficient table 1505 is an 8-entry table, and the three leading bits of the input (i.e., in one embodiment, bits 14, 13, and 12) are used as a table index to retrieve coefficients c3 n , c2 n , c1 n and c0 n (where n is in the range [0, 7]). The remaining input bits [11:0] of fraction R are used as the argument of the polynomial c3*R 3 +c2*R 2 +c1*R + c0. The result of evaluating this polynomial is the instruction output (for inputs within the range). For inputs outside the range (e.g., x < 0.5), the output is 0xFFFF.

[0353]

[0354]

[0355]

[0356]

[0357] b. Analysis of the code sequence

[0358] As can be seen from the above code, many of the same techniques used for double-word instructions are used for the reciprocal instruction. The overall calculation is y = 1 / x, where the input x is in unsigned Q0.16 format and is thus scaled by 2 16 . The x range is in [0.5, 1] or [0x8000, 0xFFFF], and the result y uses unsigned Q1.15 format and is thus scaled by 2 15 . The y range is in [1, 2] or [0x8000, 0xFFFF].

[0359] In the word implementation, the coefficient table is an 8-entry table, and the three leading bits of the input (i.e., in one embodiment, bits 14, 13, and 12) are used as a table index to retrieve coefficients c3 n , c2 n , c1 n and c0 n(where n is in the range [0, 7]). Thus, the codes are c3 n 、c2 n 、c1 n and c0 n specify eight different values. For example, the values 0xC9EC, 0x8146, 0x5690, 0x3C20, 0x2B0E, 0x1FA2, 0x17C3, and 0x1232 are specified for c3. The remaining input bits [11:0] of the fraction R are used as the argument of the polynomial c3*R 3 +c2*R 2 +c1*R + c0. The result of evaluating this polynomial is the instruction output for the input within the range. For inputs outside the range (e.g., x < 0.5), the output is 0xFFFF.

[0360] B. Example for performing a square - root reciprocal operation on packed data elements

[0361] An embodiment of the present invention includes a first instruction for performing a reciprocal square root on an unsigned doubleword and a second instruction for performing a reciprocal square root on an unsigned word. Within the source and destination registers described herein, doubleword values can be stored as packed 32-bit data elements, and doubleword values can be stored as packed 16-bit data elements.

[0362] An embodiment of the first instruction is represented as VPRSQRTUFD xmm1, xmm2 / m128, which takes the reciprocal square root of the doubleword value stored in xmm2 / m128 and stores the reciprocal in xmm1. An embodiment of the second instruction is represented as VPRSQRTUFW xmm1, xmm2 / m128, where xmm2 / m128 is the source register or memory location storing the input word value for which the reciprocal square root will be calculated, and xmm1 is the destination register for storing the reciprocal result.

[0363] These instructions can be executed on the architecture described and Figure 14 shown above. As previously described, when executing DSP instructions, one or more packed word, doubleword, or quadword values are stored in registers SRC 1401 and / or SRC 1402. A set of multipliers 1405 multiplies the selected packed data elements in SRC 1401 with the selected packed data elements in SRC2. Different data element sizes and different combinations of packed data elements can be selected for the multiplication based on the specific DSP instruction being executed. The adder networks 1410 - 1411 can then add / subtract the products of the multiplications in different combinations according to the instruction.

[0364] Depending on the instruction, accumulators 1420 - 1421 can combine the selected result generated by multiplier 1405 and / or adder network 1410 - 1411 with the accumulated result in SRC / DEST register 1460. Saturation units 1440 - 1441 generate saturated data elements from the accumulated result (again depending on the instruction), and output multiplexer 1450 forwards the final result to SRC / DEST register 1460.

[0365] Various other operations can be performed depending on the instruction being executed, such as shifting packed data elements left / right, extracting, loading, storing, permuting, zero - extending, sign - extending, rounding, and performing bitwise operations (e.g., AND, OR, NAND, etc.), to name just a few. Additionally, the product generated by multiplier 1405 and the results generated by adder network 1410 - 1411 can be stored in temporary registers or memory locations not shown. Some of these temporary storage locations are designated by FTMPx hereinafter (where x is an integer identifying a specific temporary storage area).

[0366] 1. Exemplary double - word square - root reciprocal operation

[0367] In one embodiment, the value y = 1 / sqrt(x) is determined, where the input x is an unsigned Q0.32 value scaled by 2 32 . The range of x is in [0.25, 1] or [0x40000000, 0xFFFFFFFF], and the result y is in unsigned Q1.31 format scaled by 2 31 . The range of y is in [1, 2] or [0x80000000, 0xFFFFFFFF]. In one embodiment, the maximum absolute error is 1.26 ulp and can be further improved with a penalty of about 2 cycles as described herein. The reciprocal square root can be approximated to almost 7.65 bits (linear interpolation). As in the case of the reciprocal instruction described above, a permute instruction can be used to retrieve 16 - bit coefficients from a table (e.g., VPERMW). The relative error is calculated and then a 3 - degree polynomial is applied.

[0368] In one embodiment, if the initial input is x < 0.5, the input x is "normalized" to [0.5, 1] and bit 31 is set to 0. Then, the leading bits (bits 31, 30, 29) of the "normalized input" are used as a table index to retrieve coefficients c0, c1 from an 8 - entry table. The remaining input bits (R = bits 28, 27, …, 0) are used as the argument of c0 + c1*R, which is the starting approximation of the reciprocal square root (RS) and is good to about 7.65 bits. After calculating the relative error eps, the final output is evaluated as RS+RS*eps*(pc1 + pc2*eps + pc3*eps 2) where pc1, pc2, and pc3 are constant coefficients.

[0369] Figure 17 FIG. shows an exemplary execution circuit 1240 for performing a reciprocal square root instruction y = 1 / sqrt(x) according to the above specification. Specifically, the input value X includes the "normalized" input described above, which is a double-word (32-bit) value, where bits b31, b30, and b29 are used to index the shown coefficient table 1705. Each row in the coefficient table 1705 includes a different pair of coefficients c1 n and c0 n , and one of the pairs is selected from the row based on the values of b31, b30, and b29. In one embodiment, a permutation instruction is executed to read the coefficients from the row of the coefficient table identified by the b31, b30, and b29 values. The remaining input bits (R = bits 28, 27,..., 0) are used as the independent variable of c0 + c1*R. Specifically, the multiplier 1405 performs the multiplication c1*R, and the adder network 1410 - 1411 determines c0 + c1*R.

[0370] The error evaluation circuit / logic 1710 determines the relative error value eps. After calculating the relative error, the final output is evaluated as RS + RS*eps*(pc1 + pc2*eps + pc3*eps 2 ), where pc1, pc2, and pc3 are constant coefficients and RS = c0 + c1*R. Thus, the multiplier 1405 performs the operations pc2*eps and pc3*eps 2 , and the adder network 1410 - 1411 performs the operation pc1 + pc2*eps + pc3*eps 2 . The multiplier 1405 uses this value to perform the operation RS*eps*(pc1 + pc2*eps + pc3*eps 2 ) and the adder network generates the final result: RS + RS*eps*(pc1 + pc2*eps + pc3*eps 2 ).

[0371] In one embodiment, the word implementation of the reciprocal square root instruction operates in a similar manner as described above. In this embodiment, the input x is a word value in unsigned Q0.16 format, scaled by 2 16 . The value x is in the range of [0.25, 1] or [0x4000, 0xFFFF], and the result y is an unsigned Q1.15 value, scaled by 2 15。The y value is within the range [1, 2] or [0x8000, 0xFFFF]. In one embodiment, the maximum absolute error is 1.23 ulp (which can be further improved with a loss of approximately 2 cycles). The reciprocal square root is approximated as a 3rd degree polynomial, where, as in the previous embodiment, the coefficients are extracted from a lookup table.

[0372] In one embodiment, if the initial input is x < 0.5, the input x is "normalized" to [0.5, 1] and bit 15 is set to 0. Then, the leading bits (bits 15, 14, 13) of the "normalized input" are used as a table index to retrieve the coefficients c3, c2, c1, c0 from an 8-entry table. The remaining input bits (fraction R = bits 11, 10, …, 0) are used as the argument for the following polynomial c3*R 3 + c2*R 2 + c1*R + c0. The result of evaluating this polynomial is the instruction output (for inputs within the range). For inputs outside the range (x < 0.5), the output is 0xFFFF.

[0373] In Figure 18 illustrates a method according to an embodiment of the present invention. The method can be implemented within the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0374] At 1801, a reciprocal square root (SR) instruction is fetched, which has fields for an opcode, a packed data source operand, and a packed data destination operand. At 1802, the reciprocal square root instruction is decoded to generate a decoded reciprocal square root instruction (e.g., decoded into multiple micro-operations that perform the remaining operations of the method).

[0375] At 1803, the coefficient values required to perform the reciprocal square root and the input data for the reciprocal square root instruction are fetched and stored in a packed data source register or a temporary storage location. The operations of the reciprocal instruction are scheduled. For example, the micro-operations generated during the decode stage can be queued and scheduled for execution on multiple functional units of the execution circuitry.

[0376] At 1804, the decoded reciprocal instruction is executed by using the first part of the input data as an index to identify the coefficients. For a double-word implementation, the index includes c0 and c1, and for a word implementation, the index includes c0, c1, c2, and c3. Additionally, for a double-word implementation, the constant values pc1, pc2, and pc3 are read from storage. Then, by using the coefficients, the constants (for double-word), and the second part of the input data (R), multiplication and addition are performed to determine RS*eps*(pc1 + pc2*eps + pc3*eps 2 ) for a double-word or c3*R for a word 3+c2*R 2 +c1*R + c0。

[0377] At 1805, store the result in the packed destination register.

[0378] 2. Exemplary code sequence for double - word square - root reciprocal

[0379] a. Square - root reciprocal code sequence

[0380] When executing a double - word reciprocal square root instruction, one embodiment performs the following sequence of operations:

[0381]

[0382]

[0383]

[0384]

[0385]

[0386]

[0387]

[0388] b. Analysis of the code sequence

[0389] Thus, eight potential values for the coefficients c0 and c1 are first specified. For example, depending on the index value used to look up a table, c1 can be set to 0x6bdb, 0x4fad, 0x3df4, 0x31f4, 0x4c44, 0x3857, 0x2bcf, or 0x235. Specify polynomial coefficients pc1, pc2, and pc3, and specify another constant (CRANGE) for a correction operation.

[0390] Perform a sequence of multiplication, mixing, and shift operations using the coefficients and a mask value (ABSMASK) to generate a starting approximation, which is stored in ftmp6 (identified as R in the subsequent code). Determine a relative error term (e.g., eps) and store it in fmtp4. Then initiate the evaluation of pc1*eps + pc2*eps 2 +pc3*eps 3 using 64 - bits to perform the calculation (e.g., PADDQ) for sufficient accuracy. Perform various shift operations to adjust the scaling factor, and mix to pack 32 - bit data elements into one SIMD register. Determine (pc1 + pc2*eps + pc3*eps 2) value, and the temporary variable P is used to represent eps * (pc1 + pc2 * eps + pc3 * eps 2 )。 Initially, the final result RS + RS * eps * (pc1 + pc2 * eps + pc3 * eps 2 ) is stored in ftmp6, and then it is ORed with the correction value calculated and stored in ftmp0. The final result is stored in the xmm1 register. Note that in the shown code sequence, R = RS.

[0391] 3. Exemplary code sequence for word square - root reciprocal

[0392] a. Square - root reciprocal code sequence

[0393] When executing the double - word reciprocal square root instruction, one embodiment performs the following sequence of operations:

[0394]

[0395]

[0396]

[0397]

[0398]

[0399] b. Analysis of the code sequence

[0400] Therefore, the mask values ABSMASK and CMASK, and the variables MONE and ZERO are initialized, and eight potential values of the coefficients c0, c1, c2, and c3 are specified first. For example, depending on the index value used to look up the table, c1 can be set to 0xffa8, 0xb70a, 0x8b49, 0x6e8c, 0xb4c6, 0x816e, 0x627d, or 0x4e2b. The polynomial coefficients pc1, pc2, and pc3 for the double - word reciprocal are not used.

[0401] The sequence of multiplication, mixing, and shift operations is performed starting with a move operation to transfer the input value from xmm2 to ftmp0 using the coefficients and mask values. After transferring the coefficients to the temporary storage locations (ftmpn), a sequence of permutation operations (vpermw) is performed to perform a table lookup to determine the correct set of coefficients to use. As mentioned, bits 15, 14, and 13 are used to perform the table lookup. The remaining input bits (the fraction R = bits 11, 10, …, 0) are used as the argument of the polynomial c3 * R 3 + c2 * R 2 + c1 * R + c0.

[0402] In one implementation, the two leading bits of c0 are removed to improve accuracy. These bits are not accommodated in the lower 16 bits of c0*2 stored in the table. 18 When x is in [0.25, 0.5], these leading bits are 11, and for x in [0.5, 1] they are 10. In the example code, they are stored in ftmp1 and subsequently added to the result stored in ftmp0. The result in ftmp0 is then ORed with a correction mask value from ftmp4, which is set to 0xFFFF for out-of-range inputs, and the final result c3*R 3 +c2*R 2 +c1*R + c0 (for in-range inputs) or 0xFFFF (for out-of-range inputs) is stored in xmm1. In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments of the invention. However, it will be apparent that various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0403] Embodiments of the invention may include the steps described above. These steps may be embodied in machine-executable instructions that are usable to cause a general-purpose or special-purpose processor to execute these steps. Alternatively, these steps may be performed by a special-purpose hardware component that includes hardwired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0404] As described herein, an instruction may refer to a specific configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform certain operations or having a predetermined function, or software instructions stored in a memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the figures may be implemented using code and data stored on and executed on one or more electronic devices (e.g., a terminal station, a network element, etc.). Such electronic devices use computer machine-readable media such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash devices; phase change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals - such as carrier waves, infrared signals, digital signals, etc.) to store and communicate (internally and / or over a network with other electronic devices) code and data. Additionally, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., a keyboard, a touchscreen, and / or a display), and network connections. The coupling of the set of processors to the other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage device and the signal carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on the set of one or more processors of the electronic device. Of course, one or more portions of embodiments of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without some of these specific details. In some instances, well-known structures and functions are not described in detail so as not to obscure the subject matter of the present invention. Accordingly, the scope and spirit of the present invention should be determined according to the appended claims.

Claims

1. A processor, comprising: a decoder for decoding an instruction to generate a decoded instruction; a source register for storing at least one packed input data element; a destination register for storing a result data element; and an execution circuit for executing the decoded instruction, the execution circuit being configured to use a first portion of the packed input data element as an index to a data structure comprising a plurality of coefficient sets to identify a first coefficient set from the plurality of coefficient sets, The execution circuit is configured to: generate a reciprocal square root of the packed input data element by using a combination of the coefficient and a second part of the packed input data element, and store the reciprocal square root in the destination register as the result data element, wherein combining the coefficient and the second part of the packed input data element includes: determining a relative error value based on the second part of the packed input data element, and using the relative error value to estimate the reciprocal square root, wherein using the relative error value to estimate the reciprocal square root includes: determining a value c0 + c1*R + (c0 + c1*R)*eps*(pc1 + pc2*eps + pc3*eps 2 ), where c0 and c1 are the coefficients, R includes the second part of the packed input data element, pc1, pc2, and pc3 include constant values, and eps includes the relative error value.

2. The processor according to claim 1, wherein, the packed input data element comprises a doubleword data element.

3. The processor according to claim 1, wherein, combining the coefficient with the second portion of the packed input data element comprises: evaluating a polynomial function using the coefficient as a polynomial coefficient and the second portion of the packed input data element as an input to the polynomial function.

4. The processor according to claim 3, wherein, The polynomial function includes c3*R 3 +c2*R 2 +c1*R + c0, where c0, c1, c2, and c3 are the coefficients, and R is the second part of the compacted input data element.

5. The processor according to claim 1 or 4, wherein, the execution circuit comprises a plurality of multipliers for multiplying one or more of the first coefficient set by the second portion of the packed input data element or a data value derived from the second portion of the packed input data element, the multiplying generating a plurality of temporary products.

6. The processor according to claim 5, wherein, the execution circuit further comprises an adder network for adding the temporary products to generate a result stored as a packed data element in the destination register.

7. The processor according to claim 6, wherein, the adder network is further configured to add one or more additional values to the temporary products to generate the result.

8. The processor according to claim 7, wherein, the one or more additional values comprise at least one of the coefficients.

9. A method for a computer processor, comprising: decoding an instruction; storing at least one packed input data element in a source register; executing the decoded instruction, wherein the executing step comprises using a first portion of the packed input data element of the source register as an index to a data structure comprising a plurality of coefficient sets to identify a first coefficient set from the plurality of coefficient sets, Generate the reciprocal square root of the packed input data element by using a combination of the coefficient and the second part of the packed input data element and store it in a destination register, and store the reciprocal square root in the destination register as a result data element, wherein combining the coefficient with the second part of the packed input data element includes: determining a relative error value based on the second part of the packed input data element, and using the relative error value to estimate the reciprocal square root, wherein using the relative error value to estimate the reciprocal square root includes: determining the value c0 + c1*R + (c0 + c1*R)*eps*(pc1 + pc2*eps + pc3*eps 2 ), where c0 and c1 are the coefficients, R includes the second part of the packed input data element, pc1, pc2, and pc3 include constant values, and eps includes the relative error value.

10. The method according to claim 9, wherein, the packed input data element comprises a doubleword data element.

11. The method according to claim 9, wherein, combining the coefficient with the second portion of the packed input data element comprises: evaluating a polynomial function using the coefficient as a polynomial coefficient and the second portion of the packed input data element as an input to the polynomial function.

12. The method according to claim 11, wherein, The polynomial function includes c3*R 3 +c2*R 2 +c1*R + c0, where c0, c1, c2, and c3 are the coefficients, and R is the second part of the compacted input data element.

13. The method according to claim 9 or 12, wherein, Generating a reciprocal square root includes multiplying one or more of the first set of coefficients by the second part of the packed input data element or a data value derived from the second part of the packed input data element, the multiplying generating a plurality of temporary products.

14. The method of claim 13, wherein, generating a reciprocal square root includes adding the temporary products to generate a result stored as a packed data element in the destination register.

15. The method of claim 14, wherein, further comprising: adding one or more additional values to the temporary products to generate the result.

16. The method of claim 15, wherein, the one or more additional values include at least one of the coefficients.

17. A machine-readable medium having program code stored thereon, the program code when executed by a machine causes the machine to perform the following operations: decoding an instruction to generate a decoded instruction; storing at least one packed input data element in a source register; executing the decoded instruction, wherein the steps of execution include using a first part of the packed input data element as an index into a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets of coefficients, generating a reciprocal square root of the packed input data element by using a combination of the coefficients and a second part of the packed input data element, and storing the reciprocal square root in a destination register as a result data element, wherein combining the coefficients and the second part of the packed input data element includes: Determine a relative error value based on the second part of the compacted input data element, and use the relative error value to estimate the reciprocal square root, wherein using the relative error value to estimate the reciprocal square root includes: determining a value c0 + c1*R+(c0 + c1*R)*eps*(pc1 + pc2*eps + pc3*eps 2 ), where c0 and c1 are the coefficients, R includes the second part of the compacted input data element, pc1, pc2, and pc3 include constant values, and eps includes the relative error value.

18. The machine-readable medium of claim 17, wherein, the packed input data element includes a double-word data element.

19. The machine-readable medium of claim 17, wherein, combining the coefficients and the second part of the packed input data element includes evaluating a polynomial function using the coefficients as polynomial coefficients and the second part of the packed input data element as an input to the polynomial function.

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