Semiconductor Equipment

Abstract

A semiconductor device that improves the interrupt capability of a virtual machine is required. The semiconductor device includes: a memory for storing multiple virtual machines and a virtual machine manager for managing the virtual machines; and a CPU for executing the virtual machines and the virtual machine manager. When information about the interrupt processing virtual machine (first information) is equal to information about the active virtual machine (second information), the CPU causes the active virtual machine to perform interrupt processing. When the first information is different from the second information, the CPU causes the virtual machine manager to stop the active virtual machine and operate the interrupt processing virtual machine to perform interrupt processing.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2017-247755 filed on December 25, 2017 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device configured with a virtual machine. Background Art

[0004] Virtualization technology allows one piece of hardware to be assumed to be multiple pieces of hardware. Virtualization technology is implemented by placing management software or a hypervisor called a VMM (virtual machine monitor or virtual machine manager) between an OS (operating system) and hardware (such as a processor or I / O) (Japanese unexamined patent application with publication number 2013-210962). For example, a VMM uses a scheduler function to periodically switch multiple virtual machines so that the virtual machines are executed.

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2013-210962

[0006] Patent Document 2: Japanese Translation of Unexamined PCT Application No. 2013-519169 Summary of the invention

[0007] When the active virtual machine is allowed to accept interrupts, the inactive virtual machine delays responding to the interrupts because the inactive virtual machine cannot accept interrupts until execution is switched from the active virtual machine to the inactive virtual machine. When the VMM is allowed to accept interrupts, the active virtual machine delays responding to interrupts because no interrupts are accepted until execution is switched from the active virtual machine to the VMM. These and other problems and novel features can be easily determined by referring to the following description and appended claims of the present disclosure.

[0008] The following description briefly explains an overview of representative aspects of the present disclosure. A semiconductor device includes: a memory for storing a plurality of virtual machines and a virtual machine manager for managing the virtual machines; and a CPU for executing the virtual machines and the virtual machine manager. When information about an interrupt handling virtual machine (first information) is equal to information about an active virtual machine (second information), the CPU causes the active virtual machine to perform interrupt handling. When the first information is different from the second information, the CPU causes the virtual machine manager to stop the active virtual machine and operate the interrupt handling virtual machine to perform interrupt handling.

[0009] The semiconductor memory device can improve the interrupt capability of the virtual machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram showing the concept of a virtual machine;

[0011] Figure 2A and Figure 2B is a diagram showing an interrupt accepted by a virtual machine according to a first comparative example;

[0012] Figure 3A and Figure 3B is a diagram showing an interrupt accepted by a virtual machine according to a second comparative example;

[0013] Figure 4A and Figure 4B is a diagram illustrating an interrupt accepted by a virtual machine according to an embodiment;

[0014] Figure 5 is a block diagram showing a configuration of a semiconductor device according to a working example;

[0015] Figure 6 Shows Figure 5 a CPU and an event determination unit of a semiconductor device in;

[0016] Figure 7 It is shown Figure 6 A block diagram of the configuration of the event determination unit in;

[0017] Figure 8 is a block diagram illustrating determination of information about an interrupt handling VM according to a first modification;

[0018] Fig. 9 Shows Figure 8 The VM information table in;

[0019] Fig.10 is a block diagram showing a configuration of a semiconductor device according to a second modification;

[0020] Fig.11 It is shown Fig.10 A block diagram of the configuration of the event determination unit in;

[0021] Fig.12 is a block diagram showing a configuration of an interrupt controller according to a third modification;

[0022] Fig.13 It is shown Fig.12 A block diagram of the configuration of the event determination unit in;

[0023] Fig.14 is a block diagram showing a configuration of a semiconductor device according to a fourth modification;

[0024] Fig.15A , Fig. 15B and Fig. 15C is a timing diagram illustrating the operation of the VMM scheduler;

[0025] Fig.16 is a block diagram showing an example in which the semiconductor device according to the working example is applied to a vehicle. DETAILED DESCRIPTION

[0026] The following description explains the embodiments with reference to the accompanying drawings. In the accompanying drawings, the same constituent elements are represented by the same reference numerals, and repeated descriptions may be omitted for the sake of brevity.

[0027] The following description refers to Figure 1 Describes the virtual machine. Figure 1 The concept of a virtual machine is shown.

[0028] like Figure 1 As shown, for example, one CPU (physical machine) includes a virtual machine manager (hereinafter referred to as VMM) composed of software programs. The software programs under the control of the VMM configure a plurality of virtual machines (hereinafter referred to as VMs). Figure 1 Three VMs are shown, namely a first virtual machine (hereinafter referred to as VM1), a second virtual machine (hereinafter referred to as VM2), and a third virtual machine (VM3). VM1, VM2, and VM3 execute corresponding applications (App1, App2, and App3). The VMM uses a scheduling function to periodically switch VM1, VM2, and VM3 to be executed.

[0029] Reference Figure 2A and Figure 2B , the following description illustrates an example of accepting interrupts on each VM (first comparative example). Figure 2A and Figure 2B is a conceptual diagram illustrating interruption acceptance according to the first comparative example. Figure 2A is a diagram showing interrupt requests issued to VM1 during the operation of VM1. Figure 2B is a diagram showing an interrupt request issued to VM2 during the operation of VM1. Figure 2A and Figure 2B In the figure, the horizontal thick black arrows indicate the operation in process (execution). The vertical thin arrows indicate switching VM or switching VMM. Figure 3A , Figure 3B , Figure 4A and Figure 4B .

[0030] According to Figure 2AIn the first comparative example shown, when an interrupt request is issued to VM1 during the operation of VM1, VM1 can accept the interrupt. However, when an interrupt request is issued to VM2 during the operation of VM1, VM2 cannot accept the interrupt. Figure 2B In the first comparative example shown, the VMM switches VM1 to the VMM and then to VM2 according to the scheduler, thereby starting the operation of VM2. Only after this, VM2 can accept the interrupt.

[0031] Reference Figure 3A and Figure 3B , the following description explains an example of accepting an interrupt on a VMM (a second comparative example). Figure 3A and Figure 3B is a conceptual diagram illustrating interruption acceptance according to the second comparative example. Figure 3A is a diagram showing interrupt requests issued to VM1 during the operation of VM1. Figure 3B is a diagram showing an interrupt request issued to VM2 during the operation of VM1.

[0032] According to Figure 3A In the second comparative example shown, the VMM is notified of an interrupt request issued to VM1 during the operation of VM1. The VMM switches VM1 to the VMM, and then switches to VM1, thereby starting the operation of VM1. Only after this, VM1 can accept the interrupt. Figure 3B In the second comparative example shown, the VMM is notified of an interrupt request issued to VM2 during the operation of VM1. The VMM switches VM1 to the VMM, and then switches to VM2, thereby starting the operation of VM2. Only after this, VM2 can accept the interrupt.

[0033] Compared with the second comparative example in which the VMM is allowed to accept interrupts once, according to the first comparative example, the active VM can directly accept interrupts and the interrupt capability can be ensured. However, when the inactive VM is interrupted, the occurrence status is recorded in the memory. The VMM when scheduled reads the status. The interrupt is processed by scheduling the VM. According to the first comparative example, the response of the inactive VM to accepting the interrupt depends on the VM scheduling cycle. The first comparative example is not suitable for ensuring the real-time capability of the VM interrupt.

[0034] The second comparative example allows the VM to accept all interrupts. Compared with the VM scheduling cycle, the inactive VM can receive interrupts while ensuring real-time capabilities. However, the active VM reduces interrupt performance because interrupts are always accepted through the mediation of the VMM.

[0035] Reference Figure 4A and Figure 4B , the following description explains interrupt acceptance according to an embodiment. Figure 4A and Figure 4Bis a conceptual diagram illustrating interrupt acceptance according to an embodiment. Figure 4A is a diagram showing an interrupt request issued to VM1 during the operation of VM1. Figure 4B is a diagram showing an interrupt request issued to VM2 during the operation of VM1.

[0036] according to Figure 4A In the illustrated embodiment, when an interrupt request is issued to VM1 during the operation of VM1, VM1 can accept the interrupt. Figure 4B In the embodiment shown, the VMM is notified of an interrupt request issued to VM2 during the operation of VM1. The VMM switches VM1 to the VMM, and then switches to VM2, thereby starting the operation of VM2. Only after this, VM2 can receive the interrupt.

[0037] When an interrupt is input to the same VM as the active VM, the active VM directly accepts the interrupt. When an interrupt is input to a VM different from the active VM, the VMM is started. The VMM switches processing to the VM to which the interrupt request is issued. The interrupt is thus accepted.

[0038] In other words, the CPU receives an interrupt from an active VM and then allows the active VM to accept the interrupt. The CPU receives an interrupt from an inactive virtual machine and then allows the VMM to accept the interrupt.

[0039] In particular, the semiconductor device according to the embodiment includes a memory for storing a plurality of VMs and VMMs, and a CPU for executing the VMs and VMMs. The CPU performs interrupt processing based on information about the VM for interrupt processing (first information) and information about the active VM (second information). That is, when the information about the VM for interrupt processing is equal to the information about the active VM, the CPU allows the active VM to perform interrupt processing. When the information about the VM for interrupt processing is different from the information about the active VM, the CPU allows the VMM to switch the active VM, and then allows the active VM to perform interrupt processing.

[0040] When the information about the VM that handles the interrupt is equal to the information about the active VM, the active VM itself can accept the interrupt. Compared with the technique of allowing the VMM to accept the interrupt once (the second comparative example), the interrupt performance can be ensured. In addition, even when the information about the VM that handles the interrupt is different from the information about the active VM, the VMM can accept the interrupt. Compared with the technique of accepting the interrupt in the VM scheduling cycle (the first comparative example), the real-time capability of the interrupt can be ensured.

[0041] Working Example

[0042] Reference Figure 5 , the following description illustrates the configuration of the above-mentioned embodiment. Figure 5is a block diagram showing a configuration of a semiconductor device according to a working example.

[0043] The semiconductor device 1 includes a CPU 10, an interrupt requester (IRS) 50, an interrupt controller (INTC) 20, and a memory 30. The CPU 10 executes a plurality of VMs. The interrupt requester 50 generates an interrupt request. The interrupt controller 20 receives the interrupt request from the interrupt requester 50 and outputs the interrupt request to the CPU 10. The memory 30 stores software programs for VM and VMM. The semiconductor device 1 further includes an event determination unit (EDU) 40, a peripheral unit (PERIPHERAL) 60, and a bus 70. The event determination unit 40 determines the behavior of the CPU 10 regarding the interrupt based on information about the interrupt processing VM and information about the active VM. The bus 70 is connected between the CPU 10, the memory 30, and the peripheral unit 60. The semiconductor device 1 is configured as a microcontroller composed of a single semiconductor chip. One or more CPUs 10 may be available. The event determination unit 40 is configured corresponding to the CPU 10. When the number of CPUs 10 is m (CPU#1 to m), the number of event determination units 40 is also m (event determination units #1 to m). The first CPU 10 (CPU#1) executes up to n1 VMs among VM1 to VMn1. The mth CPU 10 (CPU#m) executes up to nm VMs among VM1 to VMnm. Assume that n1 and nm are natural numbers, and n1 may or may not be equal to nm.

[0044] Figure 5 One memory 30 is shown, but multiple memories may be used. The memory 30 may not be directly connected to the bus 70 when there is an access path from the CPU 10. The memory 30 may be available as a volatile memory such as SRAM or a non-volatile memory such as a flash memory. Although one interrupt controller 20 is provided, there may be multiple interrupt controllers, each of which corresponds to a CPU. Although all CPUs 10 can execute multiple VMs as described, there may be a mixture of CPUs that execute only one VM and CPUs that do not have VMs. The event determination unit 40 may be included in the CPU 10 or the interrupt controller 20. In Figure 5 In FIG. 1 , interrupt requester 50 represents one or more peripheral units or external terminals.

[0045] Figure 6 Shows Figure 5 A CPU and an event determination unit in a semiconductor device.

[0046] The following description assumes that one CPU 10 and one event determination unit 40 are used, and two VMs operate on the CPU 10. However, the number of VMs is not limited to two.

[0047] The memory 30 stores software programs for VM1, VM2, and VMM. The programs for VM1 and VM2 include interrupt subroutines (hereinafter referred to as ISRs). The program for VMM includes an exception handler (EHNDL). The ISR includes a first end code (ENDC1) and a second end code (ENDC2) to branch to the return destination of the subroutine. The CPU 10 is assigned a software program for one of VM1, VM2, and VMM. The VMM performs the assignment of VM1 and VM2. The CPU 10 is composed of registers and includes a message box (MSGBX) 11 for performing communication between the VMM, VM1, and VM2. The VMM can read and write to the message box 11, and the VM can read from the message box 11. According to the working example, the message box 11 is composed of registers and is placed in the CPU 10. However, for example, the message box 11 can be set as a storage device accessible from the CPU, and can be placed in the memory 30 or in the peripheral unit 60 connected to the bus 70.

[0048] When an interrupt is notified from the interrupt requester 50, the interrupt controller 20 determines information (PVM) on a VM processing interrupt based on the interrupt information such as an interrupt channel number.

[0049] Reference Figure 7 , the following description illustrates an example of an event determination unit. Figure 7 It is shown Figure 6 4 is a block diagram of the configuration of the event determination unit in FIG. The event determination unit 40 allows the VM comparison circuit (VCMP) 41 to determine whether the information about the active VM (EVM) matches the information about the interrupt processing VM (PVM). The event determination unit 40 outputs the matching information (matching determination result) and the information about the interrupt processing VM (PVM) to the CPU 10 as an event instruction (EVNT).

[0050] The CPU 10 receives an interrupt request (IRQ) and an event instruction (EVNT), and determines a behavior according to the event instruction (EVNT). When the match determination result included in the event instruction (EVNT) indicates a match, the CPU 10 reads the ISR for the interrupt processing VM from the memory 30 and executes the interrupt processing. The ISR reads the message box 11. In this case, the VMM stores an instruction for selecting the first end code (ENDC1) in the message box 11. For example, the VMM previously stores an instruction for selecting the first end code (ENDC1) by default. The ISR executes the first end code (ENDC1) according to the instruction in the message box 11. The first end code (ENDC1) includes a branch for resuming processing before being interrupted by the ISR, and is executed to complete the interrupt processing.

[0051] When the match determination result included in the event instruction (EVNT) indicates a mismatch, the CPU 10 reads an exception handler (EHNDL) for the VMM from the memory 30. The exception handler (EHNDL) includes a program for switching VMs. The VMM assigns an interrupt processing VM to the CPU 10. The VM assigned to the CPU 10 accepts an interrupt request and reads its ISR from the memory 30 to perform interrupt processing. The ISR reads the message box 11. In this case, the VMM stores an instruction for selecting a second end code (ENDC2) in the message box 11. For example, the VMM stores an instruction for selecting a second end code (ENDC2) in the message box 11 before switching the VM. The ISR executes the second end code (ENDC2). The second end code (ENDC2) includes a process that allows the CPU 10 to execute the VMM, and is executed to operate the VMM. The VMM executes a specified termination process. For example, the VMM stores an instruction for selecting a first end code (ENDC1) in the message box 11, and assigns the VM executed before the input interrupt request to the CPU 10.

[0052] The following description specifically illustrates an example in which the CPU 10 executes VM 1. The interrupt controller 20 determines information on an interrupt processing VM (PVM) based on an input interrupt request.

[0053] When the information on the interrupt processing VM (PVM) corresponds to VM1, the match determination result from the event determination unit 40 indicates a match. VM1, which is the matching information and the information on the interrupt processing VM (PVM), is output as an event instruction (EVNT). The CPU 10 follows the event instruction (EVNT) and reads the ISR for VM1 from the memory 30 to perform interrupt processing. The ISR reads the message box 11. In this case, the VMM stores an instruction to select the first end code (ENDC1) in the message box 11. The ISR executes the first end code (ENDC1) according to the instruction in the message box 11 and returns to the process before the interrupt.

[0054] When the information on the interrupt processing VM (PVM) corresponds to VM2, the match determination result from the event determination unit 40 indicates mismatch. VM2, which is the matching information (mismatch information) and the information on the interrupt processing VM (PVM), is output as an event instruction (EVNT). The CPU 10 follows the event instruction (EVNT) and reads the exception handler (EHNDL) for the VMM from the memory 30. The VMM stores an instruction to select the second end code (ENDC2) in the message box 11 and allocates VM2 to the CPU 10. The CPU 10 reads the ISR for VM2 from the memory 30 and performs interrupt processing. The ISR reads the message box 11. In this case, the VMM stores an instruction to select the second end code (ENDC2) in the message box 11. The ISR executes the second end code (ENDC2) according to the instruction in the message box 11 and allocates the VMM to the CPU 10. The VMM stores an instruction to select the first end code (ENDC1) in the message box 11 and allocates VM1 to the CPU 10.

[0055] According to the working example, the active VM itself in the foregoing can accept interrupts, thereby ensuring interrupt performance compared to the technique of allowing the VMM to accept interrupts once (the second comparative example). Even when a VM other than the interrupt destination is executed, the VMM can accept interrupts, thereby ensuring the real-time capability of interrupts compared to the technique of accepting interrupts in the VM scheduling cycle (the first comparative example).

[0056] Revise

[0057] Representative modifications are described below. The following description of the modifications assumes that the same reference numerals as used for the above-described working examples may be used for components including configurations and functions similar to those described in the above-described working examples. The description of the above-described working examples is applicable to the description of those components as required within the scope of not departing from the technology. Within the scope of not departing from the technology, the components and all or part of the modifications of the above-described working examples are applicable to each other as required.

[0058] First Amendment

[0059] According to the working example, an interrupt is notified from the outside of the chip or the interrupt requester 50 such as the peripheral unit 60. Then, the interrupt controller 20 determines information (PVM) about the VM processing interrupt based on the interrupt information such as the interrupt channel number, but is not limited thereto.

[0060] Reference Figure 8 and Fig. 9 , the following description explains determination of information about an interrupt handling VM (PVM) according to the first modification. Figure 8 is a block diagram illustrating determination of information on an interrupt handling VM according to a first modification. Fig. 9 Shows Figure 8 The VM information table in .

[0061] The first modification determines the information about the interrupt processing VM (PVM) by using the interrupt controller 20A and the VM information table (VMT) 80. The interrupt controller 20A holds the attribute information (AI) for each type of input interrupt. The VM information table (VMT) 80 determines the relationship between the attribute information (AI) and the information about the interrupt processing VM (PVM). Fig. 9 As shown, the VM information table 80 determines information about the interrupt processing VM (PVM) based on the value corresponding to the attribute information (AI). Fig. 9 , "0" and "2" of the attribute information (AI) specify VM1 as the information on the interrupt processing VM (PVM), and "1" and "3" of the attribute information (AI) specify VM2 as the information on the interrupt processing VM (PVM). Fig. 9 The example in FIG. 8 provides one VM corresponding to the value of the attribute information (AI), but is not limited thereto. A plurality of VMs may be specified. The VM information table (VMT) 80 may be placed inside the event determination unit 40 .

[0062] Second Amendment

[0063] The event determination unit 40 according to the working example is simply configured. However, if the active VM is different from the interrupt request VM, the VM is inevitably switched. Whenever an interrupt request occurs, overhead occurs by switching the VM. The processing basically submitted to the CPU 10 may not be executed. In fact, all interrupts are unimportant and do not need to be executed at the expense of switching the active VM.

[0064] The second modification may select whether to switch the VM according to the type of interruption. The following description explains the event determination unit according to the second modification. Fig.10 and Fig.11 . Fig.10is a block diagram showing a configuration of a semiconductor device according to a second modification. Fig.11 It is shown Fig.10 A block diagram of the configuration of the event determination unit in FIG.

[0065] The semiconductor device 1B according to the second modification is equal to the semiconductor device 1 according to the working example except for the interrupt controller 20B and the event determination unit 40B.

[0066] The interrupt priority level (INTP) is output from the interrupt controller 20B and is input to the event determination unit 40B. The event determination unit 40B includes a register (REG) 44, a priority comparison circuit (PCMP) 42, and a VM comparison circuit (VCMP) 41. The register (REG) 44 stores a threshold value (TH) indicating whether the interrupt is higher than or equal to a specified priority level. The priority comparison circuit (PCMP) 42 compares the threshold value (TH) with the interrupt priority level (INTP). The VM comparison circuit (VCMP) 41 compares the information about the active VM (EVM) with the information about the interrupt processing VM (PVM). The event determination unit 40B further includes an event instruction generation circuit (EVNTG) 43 and a mask circuit (MSKC) 45. The event instruction generation circuit (EVNTG) 43 generates an event instruction (EVNT) based on the priority comparison result (PCO) of the priority comparison circuit 42 and the comparison result (VCO) of the VM comparison circuit 41. The mask circuit (MSKC) 45 enables or disables the interrupt request (IRQ) to be sent to the CPU 10. The comparison result (VCO) provides a match determination result and information about the interrupt processing VM (PVM). The event instruction (EVNT) provides an event instruction generation result (availability of VM switching) and information about the interrupt processing VM (PVM). The threshold value (TH) can be determined from the CPU 10 to the register 44 by using a software program, or can be fixed to hardware. The register 44 storing the threshold value (TH) may include a mechanism to limit the setting from the VM when the threshold value (TH) can be determined from the software program.

[0067] The second modification generates a priority comparison result (PCO) based on the interrupt priority (INTP) and the threshold value (TH). For example, the priority comparison result (PCO) includes an output indicating whether the interrupt priority (INTP) is greater than the threshold value (TH). The event instruction generation circuit 43 generates an event instruction (EVNT) based on the comparison result (VCO) of the VM comparison circuit (VCMP) 41 and the priority comparison result (PCO) of the priority comparison circuit 42. For example, when the comparison result (VCO) of the VM comparison circuit 41 shows a mismatch and the interrupt priority (INTP) is greater than the threshold value (TH), the event instruction generation circuit 43 generates an event instruction (EVNT) to switch VM, and generates a signal (MSK) to allow the interrupt request (IRQ) to be output to the CPU 10. When the result of the VM comparison circuit 41 shows a mismatch and the interrupt priority (INTP) is less than or equal to the threshold value (TH), the event instruction generation circuit 43 generates a signal (MSK) so as not to output the interrupt request (IRQ) to the CPU 10.

[0068] For example, when the comparison result (VCO) of the VM comparison circuit 41 shows a match, the event instruction generation circuit 43 generates an event instruction (EVNT) so as not to switch VM, and generates a signal (MSK) to allow an interrupt request (IRQ) to be output to the CPU 10 .

[0069] The second modification uses the interrupt priority (INTP) and the threshold (TH) as the condition for switching the VM, but is not limited thereto. For example, the interrupt controller 20 may include a capability to provide a setting for determining whether each channel for interruption is allowed to enable VM switching. The setting may be output to the event determination unit to generate an event instruction.

[0070] If the active VM is different from the interrupt request VM, the working example inevitably causes VM switching. Whenever an interrupt request (IRQ) occurs, overhead is generated by switching the VM. The processing basically submitted to the CPU 10 may not be executed. The second modification selects the availability of VM switching based on the interrupt type, thereby switching the VM limited by the interrupt request (IRQ) that needs to be executed at the expense of stopping the operation of the active VM. Therefore, excessive overhead can be prevented from occurring, and interrupt handling performance is improved. Interrupts that do not require VM switching do not need to select the second end code (ENDC2). The ISR can be configured to execute the first end code (ENDC1) without reading the message box 11.

[0071] Third Amendment

[0072] According to the second modification, when the comparison result (VCO) of the VM comparison circuit 41 shows a mismatch and the interrupt priority level (INTP) is less than or equal to the threshold value (TH), the CPU 10 does not accept the highest priority interrupt. However, even when the comparison result (VCO) of the VM comparison circuit 41 shows a match, lower priority interrupts may be suspended because the interrupt priority level (INTP) is less than or equal to the threshold value (VH).

[0073] Will refer to Fig.12 and Fig.13 An example (third modification) that solves this problem will be described. Fig.12 is a block diagram showing a configuration of an interrupt controller according to a third modification. Fig.13 It is shown Fig.12 A block diagram of the configuration of the event determination unit in FIG.

[0074] The semiconductor device according to the third modification is equal to the semiconductor device 1B according to the second modification except that the event determination unit is set inside the interrupt controller 20C. The interrupt controller 20C includes a priority comparison circuit to be supplied with information (EVM) about the active VM. In response to each interrupt request (IRQ) inside the interrupt controller 20C, the interrupt priority (INTP) and the threshold (TH) are compared. When there is no interrupt corresponding to the interrupt priority (INTP) greater than the threshold (TH), an interrupt request (IRQ) for the active VM is output.

[0075] In particular, the interrupt controller 20C includes an event determination unit 23 corresponding to the interrupt requester 21 for the first channel, an event determination unit 24 corresponding to the interrupt requester 22 for the second channel, and an interrupt selection circuit (IRQ_SLCT) 25. The interrupt requester 21 for the first channel outputs an interrupt request (IRQ), information about an interrupt processing VM (PVM), and an interrupt priority level (INTP) to the event determination unit 23. The interrupt requester 22 for the second channel outputs an interrupt request (IRQ), information about an interrupt processing VM (PVM), and an interrupt priority level (INTP) to the event determination unit 24.

[0076] Similar to the event determination unit 40B according to the second modification, the event determination units 23 and 24 each include a register (REG) 44, a priority comparison circuit (PCMP) 42, and a VM comparison circuit (VCMP) 41. The register (REG) 44 stores a threshold value (TH) indicating whether the interrupt is higher than or equal to a specified priority. The priority comparison circuit (PCMP) 42 compares the threshold value (TH) with the interrupt priority (INTP). The VM comparison circuit (VCMP) 41 compares the information (EVM) about the active VM with the information (PVM) about the interrupt processing VM. In addition, the event determination units 23 and 24 each include an event instruction generation circuit (EVNTG) 43C and a mask circuit (MSKC) 45. The event instruction generation circuit (EVNTG) 43 generates an event instruction (EVNT) based on the priority comparison result (PCO) of the priority comparison circuit 42 and the comparison result (VCO) of the VM comparison circuit 41. The mask circuit (MSKC) allows or prohibits the interrupt request (IRQ) from being sent to the CPU 10. The comparison result (VCO) provides a match determination result and information about the interrupt handling VM (PVM). The event instruction (EVNT) provides an event instruction generation result (availability of VM switching and interrupt priority less than or equal to a threshold) and information about the interrupt handling VM (PVM).

[0077] The event instruction generation circuit 43C generates an event instruction (EVNT) based on the comparison result (VCO) of the VM comparison circuit (VCMP) 41 and the priority comparison result (PCO) of the priority comparison circuit 42. For example, when the comparison result (VCO) of the VM comparison circuit 41 shows a mismatch and the interrupt priority (INTP) is greater than the threshold value (TH), the event instruction generation circuit 43C generates an event instruction (EVNT) to switch VMs, and generates a signal (MSK) to allow an interrupt request (IRQ) to be output to the CPU 10. When the result of the VM comparison circuit 41 shows a mismatch and the interrupt priority (INTP) is less than or equal to the threshold value (TH), the event instruction generation circuit 43C generates a signal (MSK) not to output the interrupt request (IRQ) to the CPU 10.

[0078] For example, when the comparison result (VCO) of the VM comparison circuit 41 shows a match, and the interrupt priority level (INTP) is greater than the threshold value (TH), the event instruction generation circuit 43C generates an event instruction (EVNT) so as not to switch the VM, and generates a signal (MSK) to allow the interrupt request (IRQ) to be output to the CPU 10. When the result of the VM comparison circuit 41 shows a match, and the interrupt priority level (INTP) is less than or equal to the threshold value (TH), the event instruction generation circuit 43C generates an event instruction (EVNT) indicating that the interrupt priority level (INTP) is less than or equal to the threshold value (TH) and to not switch the VM, and generates a signal (MSK) to allow the interrupt request (IRQ) to be output to the CPU 10.

[0079] The interrupt selection circuit 25 receives interrupt requests from the event determination units 23 and 24, i.e., an interrupt request including a match in the comparison result (VCO) from the VM comparison circuit 41, or an interrupt request including a mismatch in the comparison result (VCO) from the VM comparison circuit 41, and an event instruction (EVNT) generated to switch the VM. The interrupt selection circuit 25 selects an interrupt request (IRQ) to which the highest interrupt priority is assigned from the received interrupt requests, and outputs the interrupt request (IRQ) and the event instruction (EVNT) to the CPU 10. At this time, the event instruction (EVNT) includes information (PVM) on the VM, which processes the presence or absence of VM switching and interruption.

[0080] The situation described below is assumed as follows. The interrupt requester 21 for the first channel outputs an interrupt request (IRQ), VM1 as information about the interrupt processing VM (PVM), and an interrupt priority (INTP) less than or equal to the threshold value (TH). The interrupt requester 22 for the second channel outputs an interrupt request (IRQ), VM2 as information about the interrupt processing VM (PVM), and an interrupt priority (INTP) less than or equal to the threshold value (TH). The information about the active VM (EVM) is VM2.

[0081] According to the interrupt request (IRQ) from the interrupt requester 21 for the first channel, the information about the interrupt processing VM (PVM) is different from the information about the active VM (EVM). The interrupt priority (INTP) is less than or equal to the threshold value (TH). Therefore, the event determination unit 23 does not output the interrupt request (IRQ_CH1) and the event instruction (EVNT_CH1) to the interrupt selection circuit 25 (for example, IRQ_CH1=0 and EVNT_CH1=0).

[0082] According to the interrupt request (IRQ) from the interrupt requester 22 for the second channel, the information about the interrupt handling VM (PVM) matches the information about the active VM (EVM). The interrupt priority (INTP) is less than or equal to the threshold value (TH). Therefore, the event determination unit 24 outputs the interrupt request (IRQ_CH2) and the event instruction (EVNT_CH2) to the interrupt selection circuit 25. In this case, the event instruction (EVNT_CH2) indicates that there is no VM switching. The interrupt priority is less than or equal to the threshold value. The information about the interrupt handling VM (PVM) corresponds to VM2. The interrupt request is specified as IRQ_CH2=1.

[0083] The interrupt selection circuit 25 outputs the interrupt request (IRQ_CH2) and the event instruction (EVNT_CH2) from the event determination unit 24 to the CPU 10. Therefore, the interrupt request (IRQ) and the event instruction (EVNT) for the second channel are selected. In this case, the event instruction (EVNT) indicates that there is no VM switching. The information (PVM) about the interrupt processing VM corresponds to VM2. Even if the interrupt priority (INTP) for the first channel is higher than the interrupt priority (INTP) for the second channel, the interrupt request (IRQ) for the second channel is also output to the CPU 10. In other words, the interrupt request (IRQ) to which a high interrupt priority (INTP) is assigned, no VM switching, and the information (PVM) about the interrupt processing VM is different from the information (EVM) about the active VM does not prevent the interrupt request (IRQ) to which a low interrupt priority (INTP) is assigned, no VM switching, and the information (PVM) about the interrupt processing VM matches the information (EVM) about the active VM from being output to the CPU 10.

[0084] Fourth Amendment

[0085] The working example can maintain the periodic control of the VM scheduler by allowing the event instruction (EVNT) to generate an exception that transfers to the VMM, then executing the second end code (ENDC2), returning processing to the VMM, and assigning the VM to the CPU 10 before the interruption. However, the time window for the VM to be interrupted is consumed during the time that the ISR has been executed.

[0086] Reference Fig.14 , Fig.15A , Fig. 15B and Fig. 15C , the following description explains a semiconductor device according to a fourth modification to solve this problem. Fig.14 is a block diagram showing a configuration of a semiconductor device according to a fourth modification. Fig.15A , Fig. 15B and Fig. 15C is a timing diagram illustrating the operation of the VMM scheduler. Fig.15A The basic operation of the VMM scheduler is shown. Fig. 15B An operation upon accepting an interrupt according to a working example is shown. Fig. 15C An operation according to the fourth example is shown.

[0087] Before explaining the fourth modification, the following description explains the basic operation of the VM scheduler. Fig.15A As shown, one system period (SYSTEM PERIOD) of the VM scheduler starts with VMM operation. Then, the operation switches to VM1 and executes VM1. After a specified time has passed from the start of VM1 operation, the operation switches VM1 to VMM, and then switches to VM2 to execute VM2. After a specified time has passed from the start of VM2 operation, VM2 switches to VMM. The system period margin is set at the end of one system period.

[0088] The following description explains the operation of the VM scheduler when an interrupt request from VM2 is accepted during the operation of VM1 in the configuration of the semiconductor device according to the working example. Fig. 15B As shown, a system cycle (SYSTEM PERIOD) for the VM scheduler starts with VMM operation. Then, the operation switches to VM1 and executes VM1. In order to accept an interrupt request from VM2, the operation switches VM1 to the VMM, and then switches to VM2 to perform interrupt processing. After the interrupt processing on VM2, the operation switches VM2 to the VMM, and then switches to VM1 to execute VM1. After a specified time has passed from the start of the first VM1 operation, VM1 switches to the VMM, and then switches to VM2 to be executed. After a specified time has passed from the start of the VM2 operation, VM2 switches to the VMM. The system cycle margin is set at the end of one system cycle.

[0089] The fourth modification activates the performance measurement function before the VMM executes the ISR for the VM corresponding to the interrupt request. For example, the performance measurement function includes a function of counting the VM execution time by using a timer (TIMER) 61, and the VM can be started from the VMM and the counter value can be read. The performance measurement function includes a mechanism to prevent the VM from controlling the counter as needed. The VMM executes the ISR for the VM corresponding to the interrupt request, and then confirms the result of the performance measurement function. For example, the time (Tcount) consumed by processing the ISR for the VM corresponding to the interrupt request is provided during the system cycle margin at the end of a system cycle, and the interrupted VM is executed within the time (Tcount) consumed by processing the ISR for the VM corresponding to the interrupt request.

[0090] In particular, the following description explains the VM scheduler operation when an interrupt request from VM2 is accepted during the operation of VM1 in the configuration of the semiconductor device according to the fourth modification. Fig. 15C As shown, one system cycle (SYSTEM PERIOD) of the VM scheduler starts with VMM operation. Then, the operation switches to VM1 and executes VM1. In order to accept the interrupt request from VM2, the operation switches VM1 to VMM, and then switches to VM2 to perform interrupt processing. Switching VM1 to VMM starts counting timer (TIMER) 61 (COUNT START). After the interrupt processing on VM2, the operation switches VM2 to VMM, and then switches to VM1 to execute VM1. Switching VMM to VM1 stops counting timer (TIMER) 61 (COUNTSTOP). After a specified time has passed from the start of the first VM1 operation, VM1 switches to VMM, and then switches to VM2 to be executed. After a specified time has passed from the start of VM2 operation, VM2 switches to VMM. VM1 is executed within the time (Tcount) consumed by processing the ISR for VM2 corresponding to the interrupt request during the system cycle margin at the end of one system cycle. Therefore, the time window for VM1 interrupted by VMM and VM2 can be ensured.

[0091] By adding the time (Tcount) consumed to process the ISR for VM2 corresponding to the interrupt request to a periodic control counter for the VMM scheduler (such as the timer (TIMER) 12 in the CPU 10), the time window for the interrupted VM can be restored to the original estimated length. This technique extends the time used to preform one cycle of the VM scheduler. However, a watchdog timer (WDT) 62 can be provided for the VM scheduler to protect the execution time.

[0092] application

[0093] Fig.16 is a block diagram showing an example of applying a semiconductor device according to a working example to a vehicle. Fig.16 As shown, the vehicle 200 includes a semiconductor device (SEMICONDUCTOR DEVICE) 1, a sensor (SENSOR) 210 and a camera (CAMERA) 220. The semiconductor device 1 is set as a vehicle-mounted chip. The sensor 210 obtains specified information about the vehicle 200. The camera 220 obtains a video around the vehicle. The semiconductor device 1 is supplied with information obtained by the sensor 210 and the camera 220. The semiconductor device 1 performs a specified process based on the information obtained by the sensor 210 and the camera 220. The semiconductor device 1 can be replaced by any one of the semiconductor devices according to the first modification to the fourth modification.

[0094] Although the embodiment, working example, and modification of the present invention created by the inventors have been described, it should be clearly understood that the present invention is not limited to the embodiment, working example, and modification, but can be variously modified in other ways.

Claims

1. A semiconductor device comprising: A memory storing 1) a plurality of virtual machines and 2) a virtual machine manager for managing the virtual machines; message boxes to perform communication between the virtual machines, and A CPU executes the virtual machine and the virtual machine manager, wherein, in response to an interrupt request being issued, while a first virtual machine among the virtual machines is active and a second virtual machine among the virtual machines is inactive, and the interrupt request is to be processed by the second virtual machine, the virtual machine manager stops the first virtual machine and switches the second virtual machine from inactive to active, wherein each of the virtual machines includes an interrupt handling subroutine, wherein the interrupt handling subroutine includes a first end code and a second end code to branch to a return destination of the interrupt handling subroutine, The first end code includes: a branch process for resuming the process being executed by the virtual machine before the virtual machine processes the interrupt request, and The second end code includes: a process for causing the CPU to execute the virtual machine manager.

2. A semiconductor device comprising: A memory storing 1) a plurality of virtual machines and 2) a virtual machine manager for managing the virtual machines; A CPU, executing the virtual machine and the virtual machine manager; as well as Interrupt selection circuit, Wherein, in response to a first interrupt request having a first priority less than a threshold and a second interrupt request having a second priority less than the threshold and higher than the first priority being issued, while a first virtual machine among the virtual machines is active and a second virtual machine among the virtual machines is inactive, and the first interrupt request is to be processed by the first virtual machine and the second interrupt request is to be processed by the second virtual machine, then even if the second priority of the second interrupt request is higher than the first priority of the first interrupt request, the interrupt selection circuit selects the first interrupt request.

3. The semiconductor device according to claim 1, wherein the virtual machine manager includes an exception handler, The interrupt request has first information indicating a virtual machine that is to process the interrupt request, in, If the first information is equal to the second information indicating the active virtual machine, the CPU executes the interrupt handling subroutine for the active virtual machine, and If the first information is different from the second information, the exception handling program is executed to allocate the virtual machine indicated by the first information to the CPU, and the CPU executes an interrupt handling subroutine for the virtual machine indicated by the first information.

4. The semiconductor device according to claim 3, in, If the first information is equal to the second information, the interrupt handling subroutine for the active virtual machine includes: processing for executing the first end code according to the instruction of the message box, and Wherein, if the first information is different from the second information, the virtual machine manager includes: a processing for storing an instruction for selecting the second termination code in the message box, and the interrupt processing subroutine for the virtual machine indicated by the first information includes: a processing for executing the second termination code.

5. The semiconductor device according to claim 4, The second end code includes: An instruction to select the first end code in the message box is stored, and a virtual machine that has been active before the interrupt request is input is allocated to the CPU.

6. The semiconductor device according to claim 1 or 2, further comprising: An interrupt controller is configured to output information indicating a virtual machine among the virtual machines that is to process the interrupt request based on an interrupt channel.

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