Electronic device and method of manufacturing the same

Abstract

The present application relates to a method for manufacturing an electronic device including a semiconductor memory and an electronic device manufactured thereby. In a method for manufacturing an electronic device including a semiconductor memory, the method includes: forming a stacked structure, each stacked structure including a storage pattern; forming a gap filling layer, the gap filling layer filling the space between the stacked structures; and forming nanopores distributed in the gap filling layer by injecting an inert gas into the gap filling layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2017-0172080, filed on December 14, 2017, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a storage circuit or a storage device and applications thereof in electronic devices. Background Art

[0004] Recently, as electronic devices tend to be miniaturized, low-power, high-performance, and multifunctional, the art has required semiconductor devices that can store information in various electronic appliances such as computers and portable communication devices. Therefore, research on the development of such semiconductor devices has been conducted. Such semiconductor devices include semiconductor devices that can store data by switching between different resistance states according to an applied voltage or current. Examples of the semiconductor devices are resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses, etc. Summary of the invention

[0005] Embodiments of the present disclosure provide an electronic device capable of improving operation characteristics and reliability of a memory cell and a method for manufacturing the electronic device.

[0006] According to one aspect of the present disclosure, a method for manufacturing an electronic device including a semiconductor memory is provided, the method comprising: forming a stacked structure, each of the stacked structures including a storage pattern; forming a gap-filling layer, the gap-filling layer filling the space between the stacked structures; and forming nanopores distributed in the gap-filling layer by injecting an inert gas into the gap-filling layer.

[0007] According to one aspect of the present disclosure, a method for manufacturing an electronic device including a semiconductor memory is provided, the method comprising: forming a stacked structure, each of the stacked structures including a variable resistance element; forming a gap-filling layer, the gap-filling layer filling the space between the stacked structures; forming nanopores in the gap-filling layer distributed in a portion of the gap-filling layer, the portion of the gap-filling layer being located at a level corresponding to a position where the variable resistance element is located in the stacked structure.

[0008] According to one aspect of the present disclosure, there is provided an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a stacked structure, each of the stacked structures including a storage pattern; a gap-filling layer, the gap-filling layer filling the space between the stacked structures; and nanopores, the nanopores being located in the gap-filling layer and distributed in a portion of the gap-filling layer, the portion of the gap-filling layer being located at a level corresponding to a position where the storage pattern is located in each of the stacked structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and Figure 1B is a view showing a structure of an electronic device according to one embodiment of the present disclosure.

[0010] FIG. 2A to FIG. 2C is a view showing a structure of an electronic device according to one embodiment of the present disclosure.

[0011] FIG. 3A to FIG. 3C is a cross-sectional view illustrating a method for manufacturing an electronic device according to one embodiment of the present disclosure.

[0012] Figure 4 and Figure 5 is a block diagram showing a configuration of a storage system according to an embodiment of the present disclosure.

[0013] Figure 6 and Figure 7 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be sufficient and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Throughout the present disclosure, in the various figures and embodiments of the present disclosure, the same reference numerals refer to the same parts.

[0015] The drawings are not necessarily drawn to scale, and in some cases, the proportions may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0016] Figure 1A and Figure 1B is a view showing a structure of an electronic device according to one embodiment of the present disclosure. Figure 1A shows a circuit diagram of a memory cell array, and Figure 1B Shows Figure 1A A perspective view of a memory cell array.

[0017] refer to Figure 1A , the electronic device according to the present embodiment of the present disclosure may include a semiconductor memory, and the semiconductor memory may include row lines and column lines crossing the row lines. Here, the row lines may be word lines WL, and the column lines may be bit lines BL. The word lines WL and the bit lines BL are relative concepts. Therefore, in another embodiment, the row lines may be bit lines BL, and the column lines may be word lines WL. Figure 1A In FIG. 5 , it is assumed that the row lines are word lines WL1 to WL3 and the column lines are bit lines BL1 to BL3 .

[0018] The semiconductor memory may include a memory cell array 100 including memory cells MC11 to MC33 respectively arranged between column lines BL1 to BL3 and row lines WL1 to WL3. Here, the memory cells MC11 to MC33 may be arranged at intersections of the column lines BL1 to BL3 and the row lines WL1 to WL3. The memory cells MC11 to MC33 respectively include selection elements S11 to S33 and storage elements M11 to M33 connected in series with each other. The selection elements S11 to S33 may be electrically connected to the row lines WL1 to WL3, and the storage elements M11 to M33 may be electrically connected to the column lines BL1 to BL3.

[0019] Each of the storage elements M11 to M33 may include a storage pattern as a storage node for storing data. For example, each of the storage elements M11 to M33 may include a variable resistance material such as a resistance material, a magnetic tunnel junction (MTJ) or a phase change material. Each of the selection elements S11 to S33 is used to select a corresponding storage cell MC and may include a conversion material. Each of the selection elements S11 to S33 may be a diode, a PNP diode, a BJT, a metal insulator transition (MIT) element, a mixed ion electron conduction (MIEC) element, or a bidirectional threshold switch (OST) element, etc. The shape and configuration of each of the storage cells MC11 to MC33 may be variously modified according to the embodiment.

[0020] In one embodiment, the selection elements S11 to S33 may be omitted. In another embodiment, the positions of the selection elements S11 to S33 and the storage elements M11 to M33 may be reversed. That is, the selection elements S11 to S33 may be connected to the column lines BL1 to BL3, and the storage elements M11 to M33 may be connected to the row lines WL1 to WL3.

[0021] Furthermore, the semiconductor memory may further include a column circuit 110 for controlling the column lines BL1 to BL3 and a row circuit 120 for controlling the row lines WL1 to WL3 .

[0022] The row circuit 120 may be a row decoder, a word line decoder, or a word line driver, etc. For example, the row circuit 120 may select a row line WL2 among the row lines WL1 to WL3 based on the row address R_ADD. The column circuit 110 may be a column decoder, a bit line decoder, or a bit line driver, etc. For example, the column circuit 110 may select a column line BL2 among the column lines BL1 to BL3 based on the column address C_ADD. Therefore, the memory cell MC22 connected between the selected column line BL2 and the selected row line WL2 may be selected based on the row address R_ADD and the column address C_ADD.

[0023] For the sake of convenience, Figure 1A Three column lines BL1 to BL3 and three row lines WL1 to WL3 are shown. However, the embodiments of the present disclosure are not limited thereto. If necessary, the number of column lines and row lines included in the memory cell array in the embodiments of the present disclosure may be changed.

[0024] refer to Figure 1B , the memory cell array 100 may include column lines BL and row lines WL located at different levels. For example, the column lines BL may be located above the row lines WL. In addition, the row lines WL may extend parallel to each other along a first direction I, and the column lines BL may extend parallel to each other along a second direction II intersecting the first direction I.

[0025] The memory cells MC may be disposed at intersections of the column lines BL and the row lines WL and arranged in a matrix form. Moreover, each of the memory cells MC may have a stacked structure such as a memory element M and a selection element S stacked in a third direction III. The third direction III is perpendicular to the first direction I and the second direction II.

[0026] Figure 1B The memory cell array 100 having a single-layer structure is shown, but the embodiment is not limited thereto. In another embodiment, the memory cells MC may be stacked in the third direction III. For example, the memory cell array 100 may have a multi-layer structure in which the row lines WL and the column lines BL are alternately stacked in the third direction III, and the memory cells MC are disposed between the alternately stacked row lines WL and column lines BL, such as Figure 1B shown.

[0027] Meanwhile, although not shown in the figure, the insulating material may fill the space between adjacent memory cells MC, the space between adjacent row lines WL, and the space between adjacent column lines BL. In addition, nanoholes may exist in the insulating material and may be used as a heat shielding structure. For example, the nanoholes may be located between adjacent memory cells, between adjacent memory patterns, or a combination thereof.

[0028] FIG. 2A to FIG. 2C is a view showing a structure of an electronic device according to one embodiment of the present disclosure. Figure 2A It is a layout diagram. Figure 2B yes Figure 2A A cross-sectional view in a first direction I, and Figure 2C It shows the first direction I Figure 2A Cross-sectional views and graphs.

[0029] refer to Figure 2A , the nanopores NP are located in the insulating material layer disposed between adjacent memory cells MC. For example, the nanopores NP may be located between a pair of memory cells MC adjacent to each other in a first direction I. Moreover, the nanopores NP may be distributed and arranged in a region in the form of lines extending in a second direction II perpendicular to the first direction I.

[0030] refer to Figure 2B , each of the memory cells MC may include a stacked structure ST, and the stacked structure ST may be located at an intersection of a row line WL and a column line BL, which is referred to above. Figure 1B In addition, a protection layer 16 may be formed on the sidewalls of the stack structures ST, and a gap-filling layer 17 may fill the space between the stack structures ST.

[0031] Each of the stacked structures ST may include a lower electrode 11 , a conversion element 12 , an intermediate electrode 13 , a variable resistance element 14 , and an upper electrode 15 , which are sequentially stacked.

[0032] The variable resistance element 14 has a characteristic that enables it to switch between different resistance states according to an applied voltage or current, and to store data based on the set resistance state. For example, when the variable resistance element 14 has a low resistance state, data "1" can be stored therein. When the variable resistance element 14 has a high resistance state, data "0" can be stored therein. However, the embodiment is not limited thereto. In another embodiment, when the variable resistance element 14 has a low resistance state, data "0" can be stored therein. When the variable resistance element 14 has a high resistance state, data "1" can be stored therein.

[0033] When the variable resistance element 14 includes a resistance material, the variable resistance element 14 may include a transition metal oxide; a metal oxide such as a perovskite-based material; or a combination thereof. Thus, an electrical path may be generated or eliminated in the variable resistance element 14, thereby storing data in the variable resistance element 14.

[0034] When the variable resistance element 14 has an MTJ structure, the variable resistance element 14 may include a magnetization fixed layer, a magnetization free layer, and a tunnel barrier layer between the magnetization fixed layer and the magnetization free layer. For example, the magnetization fixed layer and the magnetization free layer may include a magnetic material, and the tunnel barrier layer may include a metal oxide including magnesium (Mg), aluminum (Al), zinc (Zn), or titanium (Ti). Here, the magnetization direction of the magnetization free layer may be changed by the spin torque of the electrons in the applied current. Therefore, data may be stored in the variable resistance element 14 based on the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization fixed layer.

[0035] When the variable resistance element 14 includes a phase change material, the variable resistance element 14 may include a chalcogenide-based material. The variable resistance element 14 may include silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), or selenium (Se), etc., or any combination thereof in the chalcogenide-based material. For example, the variable resistance element 14 may be Ge-Sb-Te (GST), such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, or Ge1Sb4Te7, etc. Here, the variable resistance element 14 may include a material of a specific chemical composition ratio, and the specific chemical composition ratio may be determined by considering properties such as the melting point and crystallization temperature of the material. The variable resistance element 14 may also include impurities such as carbon (C) or nitrogen (N). The phase change material has a low resistance characteristic in a crystalline state, and has a high resistance characteristic in an amorphous state or an amorphous state. Therefore, data can be stored in the variable resistance element 14 by performing a set operation, in which the resistance state of the variable resistance element 14 is converted from a high resistance amorphous state to a low resistance crystalline state; and by performing a reset operation, in which the resistance state of the variable resistance element 14 is converted from a low resistance crystalline state to a high resistance amorphous state.

[0036] The conversion element 12 may be a selection element that controls the current flowing through the conversion element 12 according to the magnitude of the applied voltage or current. For example, the conversion element 12 may substantially prevent the current from flowing therein when the magnitude of the applied voltage or current is equal to or less than a predetermined critical value, and allow the current flowing therein to increase rapidly in substantially proportion to the magnitude of the applied voltage or current when the magnitude of the applied voltage or current exceeds the predetermined critical value.

[0037] When the conversion element 12 is a metal insulator transition (MIT) element, the conversion element 12 may include any one of VO2, NbO2, TiO2, WO2, TiO2, etc. When the conversion element 12 is a mixed ion electron conduction (MIEC) element, the conversion element 12 may include ZrO2 (Y2O3), Bi2O3-BaO, (La2O3) x (CeO2) 1-x Furthermore, when the conversion element 12 is a bidirectional threshold switch (OST), the conversion element 12 may include a chalcogenide-based material such as As2Te3, As2, or As2Se3.

[0038] The lower electrode 11 may be electrically connected to the row line, the intermediate electrode 13 may be interposed between the conversion element 12 and the variable resistance element 14, and the upper electrode 15 may be electrically connected to the column line. The lower electrode 11, the intermediate electrode 13, and the upper electrode 15 may include a conductive material such as a metal or a metal oxide. For example, each of the lower electrode 11, the intermediate electrode 13, and the upper electrode 15 may include tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), etc.

[0039] Each of the lower electrode 11, the intermediate electrode 13, and the upper electrode 15 may have a single layer or a multilayer structure. Moreover, the lower electrode 11, the intermediate electrode 13, and the upper electrode 15 may have substantially the same thickness or different thicknesses. For example, the upper electrode 15 may have a smaller thickness than the lower electrode 11 and the intermediate electrode 13.

[0040] Here, the upper and lower parts of each of the stacked structures ST may have the same width or different widths. For example, each of the stacked structures ST may have a structure in which the width increases from the upper part of the structure toward the lower part of the structure. That is, the width of each of the stacked structures ST decreases in an upward direction. Therefore, the lower electrode 11 and the conversion element 12 may have a greater width than the intermediate electrode 13, the variable resistance element 14, and the upper electrode 15. Moreover, the sidewall of the stacked structure ST may have a step shape.

[0041] In other embodiments, the shape and configuration of the stacked structure ST may be variously modified. For example, at least one of the lower electrode 11, the intermediate electrode 13, and the upper electrode 15 may be omitted. Alternatively, one or more layers (not shown) for improving the characteristics of the memory cell MC and / or improving the efficiency of the manufacturing process may be additionally provided between the layers 11 to 15 included in the stacked structure ST.

[0042] The protective layer 16 is used to protect the stacked structure ST during the manufacturing process of the electronic device, and can be formed on the sidewalls of the stacked structure ST. Here, the protective layer 16 may include a non-conductive material, and may include any one of oxide, nitride, polysilicon, etc. For example, the protective layer 16 may include silicon oxide (SiO x ), silicon nitride (Si3N4), polysilicon, titanium nitride (TiN), tantalum nitride (TaN), etc. Also, the protective layer 16 may be a single layer or multiple layers (ie, a multi-layer structure).

[0043] In addition, the gap-filling layer 17 may be located between the pair of stacked structures ST adjacent to each other in the first direction I. The gap-filling layer 17 may include a material having a higher etching selectivity than the protective layer 16, and include an insulating material such as an oxide. For example, the gap-filling layer 17 may be an oxide layer such as a silicon oxide (SiO2) layer; a flowable oxide layer such as a spin-on (SOC) layer or a spin-on dielectric (SOD) layer; or a combination thereof.

[0044] The gap filling layer 17 may include nanopores NP therein. Here, the nanopore NP is an empty space with a relatively small size compared to a typical air gap. For example, the nanopore NP may be an empty space with a relatively small size, such as a diameter of a few nanometers or less, or an empty space with a relatively small size, such as a diameter of a few nanometers to tens of nanometers. For example, each of the nanopores NP may have a diameter of 1 to 100 nanometers. Therefore, the gap filling layer 17 may be a porous layer including nanometer-sized pores. In addition, the nanopore NP may include any one of air, an inert gas, and the like. The inert gas may include any one of hydrogen, helium, argon, xenon, nitrogen, and the like.

[0045] Here, the nanopores NP have a lower thermal conductivity than the insulating material of the gap filling layer 17. In addition, the nanopores NP are distributed to form a plurality of layers around the sidewalls of the memory cell MC. Therefore, the thermal insulation properties of the gap filling layer 17 can be enhanced by the nanopores NP, and the heat in the memory cell MC can be effectively prevented from being transferred to the outside or lost. In particular, the heat generated in the set operation and / or reset operation of the memory cell MC is prevented from being transferred out of the memory cell MC, so that the energy efficiency of the set operation and / or reset operation can be increased.

[0046] refer to Figure 2C , the nanopores NP may be distributed throughout the gap filling layer 17, or may be concentratedly located in a specific portion of the gap filling layer 17. For example, the nanopores NP may be distributed and arranged only in a portion of the gap filling layer 17, and the portion of the gap filling layer 17 is located at a given level corresponding to the variable resistance element 14. Therefore, the gap filling layer 17 may have a porous structure only at a given level corresponding to the variable resistance element 14, and the gap filling layer 17 may have a dense structure at a level other than the given level. The given level may be defined as a level in a third direction III perpendicular to the first direction I and the second direction II. When the nanopores NP are distributed at a given level of the gap filling layer 17 corresponding to the variable resistance element 14 with a uniform density, the gap filling layer 17 has a uniform etching rate at the given level. The distribution form of the nanopores NP can be controlled by adjusting the conditions of the ion implantation process, such as the ion beam energy, the implantation range (Rp) of the ion beam, etc.

[0047] Figure 2C The change of the concentration C of the nanopore NP with respect to the depth D in the third direction III is shown. Referring to the graph, the nanopore NP may be located in the gap filling layer 17 with a Gaussian distribution, and may be distributed at a given level corresponding to the variable resistance element 14 with the highest concentration. For example, the nanopore NP may be distributed in the middle of the variable resistance element 14 with the highest concentration in the third direction III, the concentration decreases in the direction toward the upper electrode 15, and the concentration decreases in the direction toward the middle electrode 13. Therefore, the nanopore NP is concentratedly arranged at a given level corresponding to the variable resistance element 14 (which is a storage node), so that the heat loss from the storage node can be minimized by the nanopore NP surrounding the storage node (i.e., the variable resistance element 14).

[0048] According to the above structure, the nanohole NP is located between adjacent memory cells MC. The nanohole NP forms a heat shielding structure and thus can prevent thermal crosstalk from being caused between adjacent memory cells MC. As a result, the energy efficiency of the set operation and / or reset operation of the memory cell MC can be increased.

[0049] FIG. 3A to FIG. 3C is a cross-sectional view illustrating a method of manufacturing an electronic device according to an embodiment of the present disclosure.

[0050] refer to Figure 3A, forming stacked structures ST each including a storage pattern. Each of the stacked structures ST may include a lower electrode 21, a conversion element 22, an intermediate electrode 23, a variable resistance element 24, and an upper electrode 25 stacked in sequence. Here, the variable resistance element 24 corresponds to the storage pattern and may include any one of a resistive change layer, a magnetic tunnel junction layer, a phase change layer, etc. In addition, although not shown in the figure, each of the stacked structures ST may further include a hard mask formed on the upper electrode 25.

[0051] For example, after the first conductive layer, the lower electrode layer, the conversion material layer, the intermediate electrode layer, the variable resistance material layer and the upper electrode layer for the row line are sequentially stacked, these stacked layers are patterned in the first direction. Subsequently, after forming the second conductive layer for the column line, the second conductive layer, the upper electrode layer, the variable resistance material layer, the intermediate electrode layer, the conversion material layer and the lower electrode layer for the column line are patterned in a second direction intersecting the first direction. Thus, the row line, the column line and a plurality of stacked structures ST are formed. For example, the row line has a line shape extending in the first direction, and the column line has a line shape extending in the second direction. The stacked structures ST are located in the intersection area of ​​the row line and the column line, and each has a columnar shape.

[0052] Here, the lower electrode layer, the middle electrode layer and the upper electrode layer may be formed to have substantially the same thickness or different thicknesses. For example, the upper electrode layer may be formed to have a thickness greater than that of the lower electrode layer and the middle electrode layer, and the thickness of the upper electrode layer may be reduced during a subsequent planarization process.

[0053] Subsequently, the protective layer 26 is formed along the outline of the stack structure ST. The protective layer 26 may be formed along the top surface and the sidewalls of the stack structure ST to cover the top surface and the sidewalls of the stack structure ST.

[0054] The protective layer 26 may include silicon oxide (SiO x ), silicon nitride (Si3N4), polysilicon, titanium nitride (TiN), tantalum nitride (TaN), etc. In addition, the protective layer 16 may be provided in a single layer or a multilayer.

[0055] Subsequently, a gap-filling layer 27 may be formed to fill a space between adjacent stack structures ST, and may be formed on the protective layer 26. For example, the gap-filling layer 27 may include an oxide such as silicon oxide (SiO2), a flowable oxide layer such as a spin-on (SOC) layer or a spin-on dielectric (SOD) layer, or any combination thereof.

[0056] Here, since gap filling layer 27 is formed on the resulting structure including stacked structures ST, gap filling layer 27 may be formed along the surface steps of the resulting structure. Therefore, gap filling layer 27 may have a top surface reflecting the profile of the resulting structure, and thus may have an uneven top surface corresponding to the top surface of the resulting structure. For example, the top surface of gap filling layer 27 may have a relatively high level A on the top of the stacked structures ST, and a relatively low level B on the space between the stacked structures ST.

[0057] Subsequently, an inert gas is injected into the gap filling layer 27. Here, the inert gas may include any one of hydrogen (H), helium (He), argon (Ar), xenon (Xe), nitrogen (N), and combinations thereof. For example, an ion implantation process may be used to implant the inert gas, and the energy of the ion beam used in the ion implantation process may be about 1 KeV to about 100 KeV. In addition, the inert gas may be injected at a rate of 1E15 / cm 2 To 1E17 / cm 2 Concentration injected.

[0058] The inert gas may be injected into the space between the adjacent stacked structures ST. At this time, the range (Rp) of the injected inert gas is controlled so that the inert gas may be injected to have a high concentration at a depth level corresponding to the position of the variable resistance element 24 in the stacked structure ST.

[0059] In addition, the region into which the inert gas is injected can be controlled. For example, when the nanopores NP are formed only in the space between the adjacent stacked structures ST, the inert gas is injected only into the space between the adjacent stacked structures ST. In order to inject the inert gas, a separate mask pattern may be used as an ion implantation barrier layer, or a curved top surface of the gap filling layer 27 having several different heights or depth levels may be used.

[0060] When the gap-filling layer 27 has a curved top surface, the top surface may have a relatively low level B in the space between the adjacent stacked structures ST. Therefore, Rp is determined based on the relatively low level B. In this case, since the inert gas is also injected into the portion of the gap-filling layer 27 disposed as deeply as Rp on the stacked structure ST, the injection of the inert gas into the stacked structure ST may be minimized by controlling Rp. In other embodiments, the inert gas may also be injected into the protective layer 26 or into the upper electrode 25. However, the inert gas may be prevented from being injected into the variable resistance element 24.

[0061] refer to Figure 3B, nanopores NP may be formed in the gap filling layer 27. For example, the nanopores NP may be formed by performing a heat treatment process. Here, the heat treatment process may be performed while ion implanting the inert gas, or may be performed after ion implanting the inert gas. The heat treatment process may be performed at a temperature of tens to hundreds of degrees Celsius. The heat treatment process may not be performed separately. Instead, the nanopores NP may be formed by a heat treatment process performed together with a subsequent manufacturing process.

[0062] The nanopores NP may be formed as ions of the inert gas react with each other. Therefore, the gap-filling layer 27 includes the nanopores NP distributed and arranged around the variable resistance element 24. The thermal conductivity of the gap-filling layer 27 is reduced by the nanopores NP.

[0063] Nanopore NP has several significant advantages over typical air gaps. Since typical air gaps are formed by depositing gap filling materials with poor step coverage, the air gaps have a relatively large size and are formed in a specific area. Therefore, if the air gaps are exposed in an etching process, the area where the air gaps are exposed has a high etching rate compared to the area where no air gaps exist, and thus punching may occur in the portion below the air gap due to the difference in etching rate.

[0064] On the other hand, according to the present embodiment of the present disclosure, since the nanopores NP are formed by the reaction of ions of the ion-implanted inert gas with each other, the nanopores NP have a relatively small size (e.g., a diameter of several nanometers or less or a diameter of several nanometers to several tens of nanometers), and can be distributed and arranged in the gap-filling layer 27. Therefore, the portion of the gap-filling layer 27 where the nanopores NP are arranged has a uniform etching rate, and perforation can be prevented even if the nanopores NP are exposed during etching.

[0065] For reference, when the inert gas is injected into the upper electrode 25 or the protective layer 26, the nanopores NP may also be formed in the upper electrode 25 or the protective layer 26, as shown in FIG. Figure 3B shown.

[0066] refer to Figure 3C , a planarization process such as a chemical mechanical polishing process is performed on the resulting structure including the nanopores NP. As an example, the gap-filling layer 27 is planarized until the top surface of the stacked structure ST is exposed. Therefore, the nanopores NP formed on the stacked structure ST are removed, and the portions of the gap-filling layer 27 that fill the space between the stacked structures ST are separated from each other.

[0067] In one embodiment, when nanoholes NP are also formed in the upper electrode 25, the planarization process may be performed until the nanoholes NP formed in the upper electrode 25 are removed. In other embodiments, the planarization process may be performed until the top surface of the protective layer 26 or the top surface of the upper electrode 25 is exposed.

[0068] According to the above method, when the inert gas is injected using the ion implantation process, the nanopore NP can be easily formed, and the position where the nanopore NP is formed can also be easily controlled. In addition, since the inert gas is injected using the surface profile of the gap filling layer 27, it is possible to minimize the injection of the inert gas into the stacked structure ST.

[0069] Figure 4 is a block diagram showing a configuration of a storage system 1000 according to one embodiment of the present disclosure.

[0070] refer to Figure 4 , the memory system 1000 according to the present embodiment of the present disclosure includes a memory device 1200 and a controller 1100 .

[0071] The storage device 1200 is used to store data information having various data formats (such as text, graphics, and software codes). The storage device 1200 may be a non-volatile memory. In addition, the storage device 1200 may have a reference Figures 1A to 3C The structure described in this article can be found in the reference Figures 1A to 3C The memory device 1200 is manufactured by the manufacturing method described above. In one embodiment, the memory device 1200 may include: a stacked structure, each stacked structure including a memory pattern; a gap filling layer, the gap filling layer filling the space between the stacked structures; and nanoholes located in the gap filling layer, the nanoholes being distributed only at a height or depth level corresponding to the position where the memory pattern is located in each stacked structure. The structure and manufacturing method of the memory device 1200 are the same as described above, and therefore, their detailed description will be omitted.

[0072] The controller 1100 is connected to the host and the memory device 1200 and is configured to access the memory device 1200 in response to a request from the host. For example, the controller 1100 is configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 1200.

[0073] The controller 1100 includes a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , a memory interface 1150 , and the like.

[0074] Here, the RAM 1110 may be used as an operation memory of the CPU 1120, a cache memory between the storage device 1200 and the host, and a buffer memory between the storage device 1200 and the host. For reference, the RAM 1110 may be replaced with any one of a static random access memory (SRAM), a read-only memory (ROM), and the like.

[0075] The CPU 1120 is configured to control the overall operation of the controller 1100. For example, the CPU 1120 is configured to operate firmware, such as a flash translation layer (FTL) stored in the RAM 1110.

[0076] The host interface 1130 is configured to interface with the host. For example, the controller 1100 communicates with the host using at least one of the following various interface protocols: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocol.

[0077] The ECC circuit 1140 is configured to detect and correct an error included in data read from the memory device 1200 using an error correction code (ECC).

[0078] The memory interface 1150 may be configured to interface with the memory device 1200. For example, the memory interface 1150 includes a NAND interface or a NOR interface.

[0079] For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. Here, the buffer memory may be used to temporarily store data to be transmitted to the outside through the host interface 1130 or data transmitted from the storage device 1200 through the memory interface 1150. The controller 1100 may further include a ROM for storing code data and for interfacing with the host.

[0080] As described above, the memory system 1000 according to the present embodiment of the present disclosure includes the memory device 1200 having improved integration and improved characteristics, and thus the integration and characteristics of the memory system 1000 may be improved.

[0081] Figure 51 is a block diagram showing a configuration of a storage system 1000 ′ according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with the above contents will be omitted.

[0082] refer to Figure 5 The memory system 1000' according to the present embodiment of the present disclosure includes a memory device 1200' and a controller 1100. The controller 1100 includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

[0083] The memory device 1200' may be a nonvolatile memory. Also, the memory device 1200' may have a reference Figures 1A to 3C The structure described in this article can be found in the reference Figures 1A to 3C The memory device 1200' may be manufactured by the manufacturing method described above. In one embodiment, the memory device 1200' may include: a stacked structure, each stacked structure including a memory pattern; a gap filling layer, the gap filling layer filling the space between the stacked structures; and nanoholes located in the gap filling layer, the nanoholes being distributed only at a height or depth level corresponding to the position where the memory pattern is located in each stacked structure. The structure and manufacturing method of the memory device 1200' are the same as those described above, and therefore, a detailed description thereof will be omitted.

[0084] The memory device 1200' may be a multi-chip package including a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups, and the plurality of groups are configured to communicate with the controller 1100 using the first channel to the kth channel (CH1 to CHk). In addition, the memory chips included in one group may be configured to communicate with the controller 1100 using a common channel. In one embodiment, the memory system 1000' may be modified so that one memory chip is connected to one channel.

[0085] As described above, the memory system 1000' according to the embodiment of the present disclosure includes the memory device 1200' having improved integration and improved characteristics, so that the integration and characteristics of the memory system 1000' can be improved. In particular, the memory device 1200' is configured as a multi-chip package, so that the data storage capacity of the memory system 1000' can be increased and the operation speed of the memory system 1000' can be improved.

[0086] Figure 6 2 is a block diagram showing a configuration of a computing system 2000 according to one embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with the above contents will be omitted.

[0087] refer to Figure 6The computing system 2000 according to the present embodiment of the present disclosure includes a storage device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, and the like.

[0088] The storage device 2100 stores data provided through the user interface 2400, data processed by the CPU 2200, and the like. In addition, the storage device 2100 is electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like through the system bus 2600. For example, the storage device 2100 may be connected to the system bus 2600 through a controller (not shown) or directly. When the storage device 2100 is directly connected to the system bus 2600, the function of the controller may be performed by the CPU 2200, the RAM 2300, and the like.

[0089] Here, the memory device 2100 may be a nonvolatile memory. Also, the memory device 2100 may have a reference Figures 1A to 3C The structure described in this article can be found in the reference Figures 1A to 3C The memory device 2100 is manufactured by the manufacturing method described above. In one embodiment, the memory device 2100 may include: stacked structures, each stacked structure including a memory pattern; a gap filling layer, the gap filling layer filling the space between the stacked structures; and nanoholes located in the gap filling layer, the nanoholes being distributed only at a height or depth level corresponding to the position where the memory pattern is located in each stacked structure. The structure and manufacturing method of the memory device 2100 are the same as described above, and therefore, their detailed description will be omitted.

[0090] The memory device 2100 may include a Figure 5 A multi-chip package of the plurality of memory chips.

[0091] The computing system 2000 configured as described above may be any of the following: a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device for transmitting information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, an RFID device, and the like.

[0092] As described above, the computing system 2000 according to the present embodiment of the present disclosure includes the memory device 2100 having improved integration and improved characteristics, and thus the integration and characteristics of the computing system 2000 may be improved.

[0093] Figure 7 is a block diagram illustrating a computing system 3000 according to one embodiment of the present disclosure.

[0094] refer to Figure 7 The computing system 3000 according to the present embodiment of the present disclosure includes a software layer including an operating system 3200, an application 3100, a file system 3300, and a conversion layer 3400, etc. In addition, the computing system 3000 includes a hardware layer including a storage device 3500, etc.

[0095] The operating system 3200 may manage software resources, hardware resources, etc. of the computing system 3000 and control program execution of the central processing unit. The application program 3100 is one of various application programs running on the computing system 3000 and may be a utility program executed by the operating system 3200.

[0096] The file system 3300 represents a logical structure for managing data, files, etc. in the computing system 3000, and organizes the data or files stored in the storage device 3500 according to a rule. The file system 3300 can be determined according to the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is one of Microsoft's Windows operating systems, the file system 3300 can be a file allocation table (FAT) or a new technology (NT) file system (NTFS). When the operating system 3200 is one of the Unix / Linux operating systems, the file system 3300 can be an extended file system (EXT), a Unix file system (UFS), or a journaled file system (JFS).

[0097] In the figure, the operating system 3200, the application program 3100, and the file system 3300 are shown as separate blocks. However, the application program 3100 and the file system 3300 may be included in the operating system 3200.

[0098] The translation layer 3400 converts the address into a form suitable for the storage device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 converts the logical address generated by the file system 3300 into a physical address of the storage device 3500. Here, the mapping information between the logical address and the physical address can be stored as an address translation table. For example, the translation layer 3400 can be any one of a flash translation layer (FTL), a universal flash storage link layer (ULL), etc.

[0099] The memory device 3500 may be a nonvolatile memory. Also, the memory device 3500 may have a reference Figures 1A to 3C The structure described in this article can be found in the reference Figures 1A to 3C The memory device 3500 is manufactured by the manufacturing method described above. In one embodiment, the memory device 3500 may include: a stacked structure, each stacked structure including a memory pattern; a gap filling layer, the gap filling layer filling the space between the stacked structures; nanoholes located in the gap filling layer, the nanoholes distributed only at the height or depth level corresponding to the position where the memory pattern is located in each stacked structure. The structure and manufacturing method of the memory device 3500 are the same as described above, and therefore, their detailed description will be omitted.

[0100] The computing system 3000 configured as described above may be divided into an operating system layer executed in an upper layer area and a controller layer executed in a lower layer area. Here, the application 3100, the operating system 3200, and the file system 3300 are included in the operating system layer and may be driven by an operating memory of the computing system 3000. In addition, the conversion layer 3400 may be included in the operating system layer or the controller layer.

[0101] As described above, the computing system 3000 according to the present embodiment of the present disclosure includes the memory device 3500 having improved integration and improved characteristics, and thus the integration and characteristics of the computing system 3000 may be improved.

[0102] In the electronic device and the manufacturing method thereof according to the present disclosure, the operation characteristics and reliability of the memory cell can be improved, and in particular, the characteristic degradation of the variable resistance element can be prevented.

[0103] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as would be apparent to one of ordinary skill in the art prior to filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: forming stacked structures, each of the stacked structures comprising a first electrode, a variable resistance material on the first electrode, and a second electrode on the variable resistance material; forming a protective layer of non-conductive material along the top surface and sidewalls of the first electrode, the variable resistance material, and the second electrode; forming a gap-filling layer in a first portion between the stacked structures covered by the protective layer and on a second portion, the first portion being between the stacked structures covered by the protective layer and the second portion being on the stacked structures covered by the protective layer, wherein a first height of a top surface of the gap-filling layer formed in the first portion is lower than a second height of a top surface of the gap-filling layer formed in the second portion, and the gap-filling layer comprises a material having a higher etching selectivity than that of each of the protective layers; injecting an inert gas into the gap-fill layer formed in the first portion and the second portion to form a nanopore in the first portion and the second portion, wherein the inert gas is injected into a portion of the gap-fill layer between the variable resistance materials to form the nanopore in the portion of the gap-fill layer, wherein the nanopore is not formed between the first electrodes and between the second electrodes, and A portion of the gap-fill layer formed in the second portion is removed, wherein the nanohole in the second portion is removed and the nanohole in the first portion remains.

2. The method according to claim 1, wherein: When the inert gas is ion-implanted into the gap-fill layer, the nanohole is formed between the variable resistance materials in the first portion and is formed over the stack structure in the second portion.

3. The method according to claim 1, further comprising: A heat treatment process is performed while the inert gas is being injected.

4. The method according to claim 1, further comprising: A heat treatment process is performed after the inert gas is injected.

5. The method according to claim 1, wherein: The inert gas includes any one of helium, argon, xenon and combinations thereof.

6. The method according to claim 1, wherein: The inert gas is injected into a portion of the protective layer, and a nanopore is formed in the portion of the protective layer.

7. The method according to claim 1, wherein: The inert gas is 1E15 / cm 2 To 1E17 / cm 2 concentration is implanted by ions.

8. The method according to claim 1, wherein: The ion beam used to implant the inert gas has an energy of 1 KeV to 100 KeV.

9. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: forming stacked structures, each of the stacked structures including a first electrode, a variable resistance element on the first electrode, and a second electrode on the variable resistance element; forming a protective layer of non-conductive material along top surfaces and side walls of the first electrode, the variable resistance element, and the second electrode; forming a gap-filling layer on sidewalls of the protection layer formed along sidewalls of the first electrode, the variable resistance element, and the second electrode, and on a top surface of the protection layer formed above the stacked structure, wherein the gap-filling layer comprises a material having a higher etching selectivity than that of the protection layer, and wherein an upper portion of the gap-filling layer has an undulating surface; forming a nanopore in a first portion of the gap-fill layer adjacent to the variable resistance element and in a second portion of the gap-fill layer above the stacked structure, wherein the nanopore is not formed in a portion of the gap-fill layer adjacent to the first electrode and the second electrode; and A planarization process is performed to remove the second portion of the gap-fill layer.

10. The method according to claim 9, wherein: The step of forming the nanohole includes injecting an inert gas into the first portion and the second portion of the gap-fill layer, and performing a heat treatment process for forming the nanohole while the inert gas is being injected into the gap-fill layer.

11. The method according to claim 10, wherein: The inert gas includes any one of helium, argon, xenon and combinations thereof.

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