Semiconductor device having a structure in which an insulating layer is formed under a metal interconnection

Abstract

A semiconductor device having a structure in which an insulating layer is formed under a metal interconnection is disclosed. The semiconductor device includes a via plug formed on a substrate and a metal layer for interconnection formed at one end of the via plug, wherein the insulating structure is located under the metal layer for interconnection, and the insulating structure has different layered structures according to the positional relationship with the metal layer for interconnection.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed to and the benefit of Korean Patent Application No. 10-2017-0178361, filed on December 22, 2017, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device having a structure in which an insulating layer is formed under a metal interconnection formed on a via plug structure. Background Art

[0004] A three-dimensional (3D) packaging technology is currently used in the art, in which a plurality of semiconductor chips are mounted in one package (eg, a multi-chip stack package or a system-in-package).

[0005] A through-hole plug structure that vertically passes through a substrate (eg, a die) is applied to realize high-density, low-power, and high-speed thin-film 3D packaging. Summary of the invention

[0006] Some example embodiments are directed to providing a semiconductor device having a structure in which an insulating layer is formed under an interconnection on a via plug structure, for improving electrical characteristics and reliability of the semiconductor device.

[0007] According to some example embodiments, a semiconductor device includes: a via plug on a substrate; and a metal layer at one end of the via plug, the metal layer connected to an interconnect layer. An insulating structure is located below the metal layer, and the insulating structure has different layered structures according to the positional relationship with the metal layer.

[0008] According to some example embodiments, a semiconductor device includes: a semiconductor structure; a via plug formed to at least partially penetrate the semiconductor structure; and a metal layer at one end of the via plug. A bottom surface adjacent to a side surface of the metal layer has different depths depending on the distance from the side surface.

[0009] According to some example embodiments, a semiconductor device includes: a substrate on which a photodiode is formed; an insulating layer on the substrate; a via plug passing through at least a portion of the substrate; and a metal layer formed on the via plug. An insulating structure including one or more layered structures is located below the metal layer for interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the exemplary embodiments will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view of a semiconductor device according to some example embodiments;

[0012] Figure 2 yes Figure 1 An enlarged cross-sectional view of part A;

[0013] Figures 3 to 12 , Fig.19 and Fig. 20 are cross-sectional views for describing a method of manufacturing a semiconductor device according to some example embodiments and shown according to a process sequence;

[0014] Fig.13 yes Fig.12 An enlarged cross-sectional view of part A;

[0015] Figures 14 to 18 is a semiconductor device according to some example embodiments corresponding to Fig.12 an enlarged cross-sectional view of portion A of ; and

[0016] Fig.21 and Fig. 22 is a cross-sectional view illustrating a stacked structure of a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0017] Figure 1 is a cross-sectional view for describing a semiconductor device 100 according to some example embodiments.

[0018] Reference Figure 1 , the semiconductor device 100 according to some example embodiments may include a semiconductor structure and a via plug 130. The via plug 130 may pass through the semiconductor structure completely or partially through a through hole 131 formed in the semiconductor structure. The upper end and the lower end of the via plug 130 may be connected to the connection terminals 170 and 182 through an interconnection pattern, respectively. The via plug 130 may be a through silicon via (TSV) passing through the silicon substrate 110.

[0019] The semiconductor structure according to some example embodiments may include a unit device 121 and a contact 122 on a front surface 110a of a substrate 110. A lower interlayer insulating film 120 may be on the front surface 110a of the substrate 110. An upper interlayer insulating film 150 may be located on the lower interlayer insulating film 120. A package substrate 180 and a redistribution layer 181 may be located on a rear surface 110c of the substrate 110. The front surface 110a may be an active surface, and the rear surface 110c may be an inactive surface.

[0020] The substrate 110 may include a semiconductor substrate, such as a silicon substrate. The front surface 110a of the substrate 110 on which the unit device 121 and the contact 122 are formed may be covered by a lower interlayer insulating film 120. The lower interlayer insulating film 120 may include silicon oxide (SiO2) and / or silicon nitride (SiN), and may be formed as a single layer or multiple layers.

[0021] The unit device 121 may be formed on the front surface 110a of the substrate 110 by a front end of line (FEOL) process. The unit device 121 may be a separate device and may include a metal oxide semiconductor field effect transistor (MOSFET), a system large scale integration (LSI) device, a CMOS imaging sensor (CIS), a micro electromechanical system (MEMS), an active device, a passive device, etc. The unit devices 121 may be electrically isolated from each other by a lower interlayer insulating film 120 covering the unit devices 121.

[0022] The contact 122 may vertically penetrate the lower interlayer insulating film 120 to transmit an electrical signal to upper and lower structures of the lower interlayer insulating film 120. The contact 122 may include tungsten (W), aluminum (Al), and / or copper (Cu).

[0023] Etching stop layer 141 (see Figure 3 ) may be formed on a surface (e.g., an upper surface) of the lower interlayer insulating film 120. The etch stop layer 141 may be or include a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, a silicon oxide (SiO2) film, etc. formed by a chemical vapor deposition (CVD) process. The etch stop layer 141 may form the insulating structure 140 as a single layer or together with another layer.

[0024] The through hole 131 may be a trench formed by completely or partially etching the etch stop layer 141, the lower interlayer insulating film 120, and the substrate 110. The through hole 131 may be formed by applying a photoresist (PR) film on the etch stop layer 141, exposing the PR film using a mask pattern, and then etching the through hole 131 according to the shape of the photoresist. The through hole 131 may be formed using an anisotropic etching process (e.g., a Bosch process or a laser drilling technique).

[0025] The buffer portion 132 and the conductive barrier film 133 may be sequentially formed on the inner surface of the through hole 131. The remaining space of the through hole 131 may be filled with metal by electroplating and / or other deposition methods to form a through-hole electrode 134 on the conductive barrier film 133. The through-hole electrode 134 and a portion of the upper surface of the etch stop layer 141 may be polished by a chemical mechanical polishing (CMP) process. An additional insulating layer may be formed on the polished surface to form an insulating structure 140.

[0026] An upper interlayer insulating film 150 may be formed on the insulating structure 140 , and an interconnection pattern may be formed through a back end of line (BEOL) process.

[0027] The upper interlayer insulating film 150 may include silicon oxide (SiO2) or silicon nitride (SiN), and may be formed as a single layer or multiple layers. The interconnection pattern may be formed as a plurality of interconnection structures for connecting the unit device 121 formed by the FEOL process to other interconnections on the substrate 110. For example, the interconnection structure may include a metal layer 153 for interconnection, a contact plug 154, and a metal interconnection layer 155.

[0028] Each of the metal layer 153 for interconnection, the contact plug 154, and the metal interconnection layer 155 may include at least one metal selected from tungsten (W), aluminum (Al), and copper (Cu).

[0029] The metal layer 153 for interconnection may be formed by plating the interconnection hole 151 with a metal. The interconnection hole 151 may be formed by etching the insulating structure 140, the contact 122 at the lower end of the insulating structure 140, and a portion of the via plug 130.

[0030] The upper insulating film 160 may be formed on the upper end of the upper interlayer insulating film 150. The upper insulating film 160 may be a passivation layer including silicon nitride (SiN) and / or polyimide. An upper connection terminal 170 may be on the upper insulating film 160, and the upper connection terminal 170 is connected to the front pad 156 at the uppermost end of the interconnection pattern through the connection hole 161.

[0031] The back surface 110b (refer to FIG. 1 ) of the substrate 110 may be etched from the back surface 110b of the substrate 110 using a CMP process, an etch-back process, or a combination thereof. Fig.19 ) removes a portion of the lower end of the via plug 130.

[0032] The package substrate 180 including the redistribution layer 181 may be connected to the rear surface 110c of the substrate 110, which is exposed by the CMP process. The exposed surface of the lower end of the via plug 130 may be connected to the connection terminal 182 through the redistribution layer 181. The semiconductor device 100 according to example embodiments is not limited to the above-mentioned Figure 1 Describes the configuration.

[0033] In the process of manufacturing the semiconductor device 100 according to some example embodiments, processes from after the FEOL process to a process of forming the via plug 130 will be described below.

[0034] After forming the FEOL structure on the front surface 110a of the substrate 110, the lower interlayer insulating film 120 may be on the front surface 110a of the substrate 110. The lower interlayer insulating film 120 may include silicon oxide (SiO2). An etch stop layer 141 may be formed on the surface of the lower interlayer insulating film 120. The etch stop layer 141 may be an insulating layer including silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), etc.

[0035] After forming the etch stop layer 141, the etch stop layer 141, the lower interlayer insulating film 120, and a portion of the substrate 110 may be etched to form a trench-shaped through hole 131 therethrough. A buffer portion 132 and a conductive barrier film 133 may be formed (e.g., conformally formed) inside the through hole 131. The remaining space of the through hole 131 may be filled with a metal film to form a through-hole electrode 134 on the conductive barrier film 133. A through-hole plug 130 including the through-hole electrode 134, the conductive barrier film 133, and the buffer portion 132 may be formed.

[0036] The buffer portion 132 may be used as a buffer to relieve pressure (e.g., thermal stress caused by thermal expansion of the through-hole electrode 134, etc.). The buffer portion 132 may include insulating materials such as silicon oxide (SiO2) and silicon nitride (SiN). For example, the buffer portion 132 may be formed of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The buffer portion 132 may be formed by a CVD process.

[0037] The conductive barrier film 133 can prevent the metal contained in the through-hole electrode 134 from diffusing into the substrate 110. The conductive barrier film 133 can be formed as a conductive layer including a relatively low interconnection resistance. For example, the conductive barrier film 133 may include titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), etc. The conductive barrier film 133 can be formed as a single layer or multiple layers. The conductive barrier film 133 can be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and / or an atomic layer deposition (ALD) process.

[0038] The metal film constituting the through-hole electrode 134 may be formed by electroplating a metal such as silver (Ag), gold (Au), copper (Cu), aluminum (Al), tungsten (W), indium (In), etc. For example, the metal film may be made of copper (Cu), a copper-based alloy (Cu-Sn, Cu-Mg, Cu-Ni, Cu-Zn, Cu-Pd, Cu-Au, Cu-Re, or Cu-W), tungsten (W), or a tungsten-based alloy.

[0039] Although not shown, a metal seed layer may be formed on the conductive barrier film 133. A metal film may be grown from the metal seed layer by electroplating to fill the through hole 131. The metal seed layer may be made of copper (Cu), a copper-based alloy (Cu-Co or Cu-Ru), cobalt (Co), nickel (Ni), or ruthenium (Ru).

[0040] Figure 2 yes Figure 1 An enlarged cross-sectional view of part A of FIG. Figure 2 , the insulating structure 140 may have a portion having a variable thickness or a variable number of layers around the metal layer 153. According to the shape of the metal layer 153 and / or the positional relationship with the side surface (e.g., the peripheral side surface of the metal layer 153), the insulating structure 140 may be formed to have different numbers of layers and / or different thicknesses.

[0041] Figures 3 to 18 1 is a cross-sectional view for describing a method of manufacturing a semiconductor device 100 according to some example embodiments and is shown according to a process sequence. Figures 3 to 18 A process sequence after forming the via plug 130 in the semiconductor device 100 is described.

[0042] Reference Figure 3 , the semiconductor structure on which the via plug 130 is formed may be polished by a CMP process. The upper ends of the etch stop layer 141 and the via electrode 134 may be exposed by the CMP process. As shown above, due to the material difference between the etch stop layer 141 and the via electrode 134, the upper end of the via electrode 134 after etching is completed may protrude above the upper end of the etch stop layer 141.

[0043] In the CMP process, the etch stop layer 141 can be used as an etch barrier layer and can have a relatively low etching rate, for example, lower than the etching rate of other thin films. The etch stop layer 141 can be an insulating layer made of a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, a silicon oxide (SiO2) film, etc. formed by a CVD process. Since the insulating layer used as the etch stop layer 141 can be removed later by an etch back process, the cost can be reduced by using a low-cost material for the insulating layer. For example, a silicon nitride (SiN) film including a dielectric constant (k) greater than the dielectric constant (k) of an oxide-based material can be used as the etch stop layer 141. The etch stop layer 141 and the through-hole plug 130 can be exposed in the following manner: cleaning the residue formed by the CMP process.

[0044] Figures 4 to 8 is a cross-sectional view of a process of forming an insulating structure 140 according to some example embodiments.

[0045] Reference Figure 4 , an additional insulating layer 142 may be formed on the upper surface of the exposed etch stop layer 141 and the via plug 130. The insulating layer formed on the upper surface of the exposed etch stop layer 141 is referred to as a first insulating layer 142. A second insulating layer 143 (refer to Figure 8 ). The insulating structure 140 may include an etch stop layer 141 and additional insulating layers 142 and 143 .

[0046] The first insulating layer 142 may be formed by depositing a silicon carbon nitride (SiCN) film, a silicon oxynitride (SiON) film, or the like by a CVD and / or PVD method. As shown above, even after the CMP process, the upper end of the via electrode 134 as a metal film may protrude more than the etching stop layer 141. The first insulating layer 142 may also be formed at a position higher than that above the upper interlayer insulating film 120 over the via electrode 134.

[0047] Reference Figure 5 , the protective film 190 may be on the first insulating layer 142. The protective film 190 may be a photoresist. The photoresist may be formed by applying a PR film on the upper end of the first insulating layer 142 and then performing a selective exposure process and a development process. As described above, the protective film 190 may be formed to cover the via plug 130. The protective film 190 may be formed to cover the upper end of the via plug 130 and its periphery.

[0048] Reference Figure 6 , an etch-back process may be performed on the semiconductor structure having the protective film 190 thereon. The etch-back process may be performed in a dry manner. For example, sputter etching using sputtering, reactive ion etching (RIE), vapor phase etching, etc. may be used.

[0049] The first insulating layer 142 and the etching stop layer 141 on which the protective film 190 does not exist may be removed by an etch-back process. The first insulating layer 142 and the etching stop layer 141 existing under the protective film 190 may remain without being removed. Therefore, there may be a height difference between a portion of the insulating structure 140 in which the protective film 190 does not exist and a portion of the insulating structure 140 in which the protective film 190 exists. Figure 7 After the etch-back process, the protective film 190 may be removed. When the protective film 190 is a photoresist, the photoresist may be separated from the upper surface of the semiconductor structure by an ashing (e.g., oxygen ashing) process. After the ashing process, a cleaning operation may be performed on the upper surface of the semiconductor structure (i.e., the upper surface of the remaining insulating structure 140 and the upper surfaces of the exposed lower interlayer insulating film 120 and the contact 122). Although not shown, the insulating structure 140 may be partially removed without using the protective film 190 to form a semiconductor structure such as Figure 7The shape of the insulating structure 140 is shown.

[0050] Reference Figure 8 , the second insulating layer 143 may be formed as an additional insulating layer on the upper surface of the semiconductor structure, from which the protective film 190 is removed. The second insulating layer 143 may be a silicon carbonitride (SiCN) film, a silicon oxynitride (SiON) film, etc., deposited by a CVD or PVD method. The second insulating layer 143 may be further deposited to form an insulating structure 140 including an etch stop layer 141, a first insulating layer 142, and a second insulating layer 143.

[0051] The insulating structure 140 may have different layered structures according to the positional relationship with the via plug 130. As described above, the insulating structure 140 may include a first insulating layer 142 and a second insulating layer 143 located at the upper end of the via plug 130. The insulating structure 140 may include only the second insulating layer 143 in a portion where the via plug 130 is not formed. The insulating structure 140 may include all of the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143 near the via plug 130.

[0052] For example, the insulating structure 140 at the upper end of the via plug 130 may be formed thicker than the insulating structure 140 at the upper end of the portion where the via plug 130 is not formed. In addition, the insulating structure 140 formed near the via plug 130 may be thicker than the insulating structure 140 formed at the upper end of the via plug 130. The insulating structure 140 at the upper end of the via plug 130 may be formed at a higher position than the insulating structure 140 in other portions.

[0053] Reference Fig. 9 , an upper interlayer insulating film 150 may be formed on the insulating structure 140. The upper interlayer insulating film 150 may form a BEOL structure such as an interconnection pattern. The upper interlayer insulating film 150 may be a silicon carbon nitride (SiCN) film similar to the lower interlayer insulating film 120. The upper interlayer insulating film 150 may be formed as an interlayer insulating film including a low dielectric constant (low-k) by using a silicon carbon nitride (SiCN) thin film. In this case, by combining with an interconnection pattern including copper (Cu), a delay in signal transmission speed due to interconnection resistance or parasitic capacitance may be reduced.

[0054] Reference Fig.10 , the upper interlayer insulating film 150 may be patterned to form an interconnection hole 151 exposing the upper surface of the via plug 130. When forming the interconnection hole 151, the insulating structure 140 may serve as an etching barrier. The interconnection hole 151 may have a trench shape.

[0055] The interconnection hole 151 may have different etching depths according to the thickness of the insulating structure 140. As shown above, the interconnection hole 151 may be formed on the contact 122 by patterning. Before forming the interconnection hole 151, the insulating structure 140 on the contact 122 may include only the second insulating layer 143. The interconnection hole 151 formed on the contact 122 may be formed by the second insulating layer 143 and a portion of the lower interlayer insulating film 120 etched thereon.

[0056] When the insulating structure 140 includes the first insulating layer 142 and the etch stop layer 141 in addition to the second insulating layer 143 , the interconnection hole 151 including a multi-layered structure having steps with different etching depths may be formed by an etch-back process.

[0057] Refer again Fig. 9 , the insulating structure 140 on the via plug 130 may include a first insulating layer 142 and a second insulating layer 143. Fig.10 As shown, at a position corresponding to the upper portion of the via plug 130, the interconnection hole 151 may be formed by the second insulating layer 143, the first insulating layer 142, and the upper end of the via electrode 134 etched thereon. The exposed upper end of the via electrode 134 in the interconnection hole 151 formed by etching may become the first lower surface 151a of the interconnection hole 151 (refer to Fig.13 ).

[0058] An insulating structure 140 including an etch stop layer 141, a first insulating layer 142, and a second insulating layer 143 may be formed near the upper surface of the via plug 130. In the case where the insulating structure 140 includes the etch stop layer 141, when an etch back process for forming the interconnection hole 151 is performed, a second lower surface 151b including a relatively shallow etching depth may be formed. When the etch back process for forming the interconnection hole 151 is performed, a side surface 151c may be formed. Depending on the position and / or thickness of the etch stop layer 141, the lower surfaces 151a and 151b of the interconnection hole 151 may be formed as a multilayer structure having a step (e.g., a step corresponding to the side surface 151c). The difference in etching depth between the first lower surface 151a and the second lower surface 151b may vary according to the etching selectivity of the material to be etched.

[0059] In the semiconductor structure in which the interconnection hole 151 is formed, the insulating structure 140 formed near the via plug 130 may be thicker than the insulating structure 140 formed in a portion where the via plug 130 does not exist. That is, since the etch stop layer 141 and the first insulating layer 142 remain after the etch-back process, the insulating structure 140 near the via plug 130 may be formed to be thicker than the insulating structure 140 in another portion.

[0060] Reference Fig.11, the interconnection barrier film 152 may be formed in the interconnection hole 151. The interconnection barrier film 152 may include titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), etc. The interconnection barrier film 152 may be formed by a PVD process; however, the inventive concept is not limited thereto.

[0061] Reference Fig.12 , the metal layer 153 for interconnection may be formed by electroplating a metal film in the interconnection hole 151 formed with the interconnection barrier film 152 .

[0062] The metal film may be formed by electroplating a metal such as silver (Ag), gold (Au), copper (Cu), aluminum (Al), tungsten (W), indium (In), etc. For example, the metal film may be made of copper (Cu), a copper-based alloy (Cu-Sn, Cu-Mg, Cu-Ni, Cu-Zn, Cu-Pd, Cu-Au, Cu-Re, or Cu-W), tungsten (W), or a tungsten-based alloy.

[0063] Although not shown, a metal seed layer may be formed on the interconnection barrier film 152. A metal film for forming a metal layer 153 for interconnection may be grown from the metal seed layer. The metal layer 153 for interconnection may have a first lower surface and a second lower surface corresponding to the shape of the interconnection hole 151 and including a step.

[0064] The insulating structure 140 may be located at the lower portion and the side of the second lower surface of the metal layer 153 for interconnection. As described above, the insulating structure 140 may not be below the outer peripheral surface of the metal layer 153 for interconnection formed on the contact 122. Instead, the insulating structure 140 may be located at the lower portion and the side of the outer peripheral surface. In addition, the insulating structure 140 below and around the outer peripheral surface of the via plug 130 may not have a constant thickness and may have a step.

[0065] Fig.13 yes Fig.12 An enlarged cross-sectional view of part A.

[0066] Reference Fig.13, the etching stop layer 141 and the first insulating layer 142 that remain without being removed after the etch-back process may be located on the side of the outer peripheral surface of the metal layer 153 or below the second lower surface. The etching stop layer 141 may have a higher etching resistance than the first insulating layer 142 and the second insulating layer 143. When the etching stop layer 141 has a relatively high etching resistance, the first lower surface 151a of the interconnection hole 151 may be etched deeper than the second lower surface 151b. The via plug 130 may be below the first lower surface 151a. The insulating structure 140 may be below the second lower surface 151b, and the second lower surface 151b includes an etching depth shallower than the first lower surface 151a or a portion where the via plug 130 is not formed. According to the step between the first lower surface and the second lower surface of the metal layer 153 for interconnection, the insulating structure 140 may have different thicknesses. The insulating structure 140 may be formed as one layer on the inner side of the outer peripheral side surface of the metal layer 153 for interconnection, and may be formed as three layers on the outer side of the outer peripheral surface thereof.

[0067] As shown above, the second lower surface of the metal layer 153 for interconnection may be formed by a portion of the etch stop layer 141 etched thereon. The thickness of the insulating structure 140 below the second lower surface of the metal layer 153 for interconnection may be less than the thickness of the etch stop layer 141. That is, the second lower surface of the metal layer 153 for interconnection may correspond to the position where a portion of the upper surface of the etch stop layer 141 is etched.

[0068] The insulating structure 140 including the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143 that remain without being etched may exist on the side of the metal layer 153 for interconnection. The side of the metal layer 153 for interconnection may be a position corresponding to the outer side of the outer peripheral surface of the via plug 130. The thickness of the insulating structure 140 on the side of the metal layer 153 for interconnection may be equal to the sum of the thicknesses of the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143.

[0069] Figures 14 to 18 is a semiconductor device according to some example embodiments corresponding to Fig.12 An enlarged cross-sectional view of part A.

[0070] Reference Fig.14 and Fig.15 , the interconnection hole 151 can be formed to have different depths according to the etching selectivity. Fig.14 As shown, the insulating structure 140 may be formed as two layers (such as an etching stop layer 141 and an insulating layer 142) on the inner side of the outer peripheral surface of the metal layer 153 for interconnection, and may be formed as two layers (such as an insulating layer 142 and a second insulating layer 143) on the outer side of the outer peripheral surface thereof. Fig.15As shown, the insulating structure 140 may have different numbers of layers on the inner side and the outer side of the outer peripheral surface of the metal layer 153 for interconnection. For example, inside the outer peripheral surface of the metal layer 153, the insulating structure 140 may include an etching stop layer 141, an insulating layer 142, and a second insulating layer 143. Outside the outer peripheral surface of the second metal layer 153 formed on the contact 122, the insulating structure 140 may include a second insulating layer 143. Additionally or alternatively, the insulating structure 140 on the outer side of the outer peripheral surface of the metal layer 153 for interconnection may be formed to be thicker than the insulating structure 140 on the inner side of the outer peripheral surface of the metal layer 153 for interconnection.

[0071] Reference Fig.16 , the insulating structure 140 may have a two-layered structure. For example, the insulating structure 140 may include only the etching stop layer 141 and the second insulating layer 143. As shown in the embodiment, the insulating structure 140 may be formed as one layer on the inner side of the outer peripheral surface of the metal layer 153 for interconnection, and may be formed as two layers on the outer side of the outer peripheral surface of the metal layer 153 for interconnection.

[0072] Reference Fig.17 Some example embodiments may be applied to the metal layer 153 for interconnection formed on the contact 122 in addition to the metal layer 153 for interconnection on the via plug 130 .

[0073] Reference Fig.18 , the lower end of the interconnection hole 151 may be formed as an inclined surface. For example, the lower end of the almost vertical peripheral surface may be a curved surface inclined relative to the bottom surface of the interconnection hole 151, or a curved surface including a step. Depending on the positional relationship with the edge of the bottom surface of the metal layer 153 for interconnection, the insulating structure 140 may have different layered structures and thicknesses. In the illustrated embodiment, the insulating structure 140 may be formed as a layer at a position adjacent to the edge of the bottom surface of the metal layer 153 for interconnection. The insulating structure 140 may be formed as two or more layers at a position away from the edge of the bottom surface of the metal layer 153 for interconnection. For example, the insulating structure 140 formed on the outer side of the peripheral surface of the metal layer 153 for interconnection may be formed as three layers.

[0074] Reference Fig.19, the interconnection structure can be formed by BEOL operation. The contact plug 154 including the same stack structure as the metal layer 153 for interconnection can be formed on the metal layer 153 for interconnection by a method similar to the method of forming the metal layer 153 for interconnection. The metal interconnection layer 155 can be formed on the contact plug 154 in the same manner as the metal layer 153 for interconnection, and the contact plug 154 can be formed again thereon. The metal interconnection layer 155 and the contact plug 154 can be alternately formed to form an interconnection structure in which the metal layer 153 for interconnection, a plurality of metal interconnection layers 155, and a plurality of contact plugs 154 are alternately connected.

[0075] The interconnect structure may transmit electrical signals in the horizontal direction of the upper interlayer insulating film 150. The interconnect structure may include a conductor such as doped silicon, a metal, a metal silicide, a metal alloy, and / or a metal compound. The interconnect structure may include a front pad. The front pad may include a metal such as copper (Cu), aluminum (Al), or tungsten (W).

[0076] An upper insulating film 160, which may be a passivation film, may be formed on the upper interlayer insulating film 150 surrounding the interconnect structure. The upper insulating film 160 may be made of a silicon oxide (SiO2) film, a silicon nitride (SiN) film, a polymer, or a combination thereof. A connection hole 161 exposing a front pad 156 connected to the interconnect structure may be formed on the upper insulating film 160. The front pad 156 may electrically connect a portion of the uppermost interconnect structure to the upper connection terminal 170. For example, the front pad 156 may be connected to the upper connection terminal 170 through the connection hole 161.

[0077] Reference Fig. 20 , the rear surface 110c of the substrate 110 and a portion of the lower end of the via plug 130 may be polished by a CMP process so that the lower end of the via plug 130 is exposed. The rear surface 110c of the substrate 110 shown may be a rear surface newly formed by the CMP process. The lower connection terminal 183 connected to the lower end of the via plug 130 may be formed on the rear surface 110c of the substrate 110.

[0078] The upper connection terminals 170 and the lower connection terminals 183 are not limited to the shapes shown, and may have the shapes of solder balls, solder bumps, redistribution structures, or front pads. In one embodiment, at least one of the upper connection terminals 170 and the lower connection terminals 183 may be omitted.

[0079] Fig.21 and Fig. 22 is a cross-sectional view illustrating a stacked structure of a semiconductor device 100 according to some example embodiments.

[0080] The semiconductor device 100 according to some example embodiments may be formed as a multi-chip stack package.

[0081] Reference Fig.21 , the semiconductor package may be a multi-layer device and may be formed by stacking individual semiconductor devices S1, S2, and S3 in a chip-on-wafer (COW) manner. As described above, the semiconductor package may include an upper device S1, an intermediate device S2, and a lower device S3. For example, the upper device S1 may include an image sensor, the intermediate device S2 may include a logic device such as a microprocessor, and the lower device S3 may include a memory device such as a dynamic random access memory (DRAM). The upper device S1 and the intermediate device S2, as well as the intermediate device S2 and the lower device S3 may be electrically connected through through-hole plugs 12 and 23, respectively.

[0082] The upper device S1 may include a photodiode 13, a color filter 14, a microlens 15, a via plug 12, and an I / O pad 16 formed on an upper substrate 11. The middle device S2 may include an intermediate substrate 21, an interconnect structure 22, a via plug 23, a redistribution structure 24, and an insulating structure 25. The lower device S3 may include a DRAM chip 31, a redistribution structure 32, a dummy structure 34, and / or a molding portion 35 in the form of a chip.

[0083] The upper device S1 and the middle device S2 may be electrically connected through a through-hole plug 12. The through-hole plug 12 may be a back-side through-hole stack (BVS). The electrical connection of the middle device S2 and the lower device S3 may be achieved by joining the corresponding redistribution structures 24 and 32 in a COW manner using solder bumps 33. The insulating structure 25 of some example embodiments may be applied to a metal layer for interconnection formed on the redistribution structure 24 at one end of the through-hole plug 23. In addition, the insulating structure 28 of some example embodiments may also be applied to a metal layer 27 for interconnection at a position between the interlayer insulating film of the middle device S2 and the substrate 21 on the substrate 21. In addition, although not shown, some example embodiments may also be applied to one end of the through-hole plug 12.

[0084] As shown above, in the case of stacking the individual devices S1, S2 and S3 in a COW manner, only when the structure of the stacked upper device S1 and the middle device S2 is determined to be a high-quality product can the lower device S3 in chip form be stacked, thereby improving the yield.

[0085] Reference Fig. 22, the semiconductor package may be a multi-layer device and may be formed by stacking individual devices S1', S2', and S3' in a wafer-on-wafer (WOW) manner. As described above, the semiconductor package may include an upper device S1', an intermediate device S2', and a lower device S3'. For example, the upper device S1' may include an image sensor, the intermediate device S2' may include a memory device such as a DRAM, and the lower device S3' may include a logic device such as a microprocessor. The upper device S1' and the intermediate device S2', as well as the intermediate device S2' and the lower device S3' may be electrically connected via through-hole plugs 12 and 23, respectively.

[0086] The upper device S1' may include a photodiode 13, a color filter 14, a microlens 15, a via plug 12, and an I / O pad 16 formed on an upper substrate 11. The middle device S2' may include an intermediate substrate 21, an interconnection layer 26, a via plug 23, a metal layer 29 for interconnection, and an insulating structure 25. The lower device S3' may include a lower substrate 31 and an interconnection layer 36.

[0087] The upper device S1' and the middle device S2' may be electrically connected through the via plug 12, and the middle device S2' and the lower device S3' may be electrically connected through the via plug 23. Each of the via plugs 12 and 23 may be a TSV. The insulating structure 25 of some example embodiments may be applied to the metal layer 29 for interconnection formed at the ends of the via plugs 12 and 23.

[0088] According to some example embodiments, defects of a semiconductor device may be reduced, thereby improving electrical characteristics and reliability, by providing a via plug structure and an interconnected lower structure.

[0089] Although some example embodiments have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the example embodiments and without changing their essential features. Therefore, the above embodiments should be considered only as illustrative and not for limiting purposes.

Claims

1. A semiconductor device comprising: An interlayer insulating layer located on the substrate, a via plug located on the substrate, the via plug being formed to pass through the interlayer insulating layer; an insulating structure located on the interlayer insulating layer; as well as a metal layer located at one end of the through-hole plug and the insulating structure, the metal layer being connected to the interconnection layer, wherein the insulating structure comprising one or more layered structures is located below the metal layer, and The insulating structure has different layered structures according to the positional relationship with the metal layer, The insulating structure includes fewer layers at a location spaced apart from a periphery of the metal layer than at a location adjacent to the periphery of the metal layer.

2. The semiconductor device according to claim 1, wherein The insulating structure has different thicknesses according to distances from an outer circumference of the metal layer.

3. The semiconductor device according to claim 1, wherein The insulating structure includes different numbers of layers depending on the distance from the periphery of the metal layer.

4. The semiconductor device according to claim 3, wherein: The insulating structure includes at least one of an etch stop layer and one or more insulating layers.

5. The semiconductor device according to claim 3, wherein: The insulating structure includes layers whose number increases with increasing distance from the periphery of the metal layer.

6. The semiconductor device according to claim 3, wherein: The insulating structure includes layers whose number decreases with increasing distance from the periphery of the metal layer.

7. The semiconductor device according to claim 3, wherein: The insulating structure includes an etch stop layer below the metal layer.

8. A semiconductor device comprising: Semiconductor structures; an interlayer insulating layer located on the semiconductor structure; a via plug formed to pass through the interlayer insulating layer and at least partially through the semiconductor structure; an insulating structure located on the interlayer insulating layer; as well as a metal layer located at one end of the through-hole plug and the insulating structure, wherein a bottom surface of the metal layer adjacent to the side surface has different depths depending on the distance from the side surface, and The thickness of the insulating structure at a position spaced apart from the outer periphery of the metal layer is thinner than the thickness at a position adjacent to the outer periphery of the metal layer.

9. The semiconductor device according to claim 8, wherein: The metal layer is inclined downward from the side surface of the metal layer.

10. The semiconductor device according to claim 8, wherein The metal layer is stepped downward from an inner side of the side surface of the metal layer.

11. The semiconductor device according to claim 10, wherein The metal layer comprises: a first lower surface extending inwardly from the side surface of the metal layer; and A second lower surface, wherein the second lower surface includes a step downward from the first lower surface.

12. The semiconductor device according to claim 11, wherein The insulating structure is located below the first lower surface of the metal layer.

13. The semiconductor device according to claim 12, wherein: The number of layers of the insulating structure outside the side surface of the metal layer is greater than the number of layers of the insulating structure below the first lower surface.

14. The semiconductor device according to claim 12, wherein: The number of layers of the insulating structure at a position spaced apart from the metal layer is smaller than the number of layers of the insulating structure below the first lower surface.

15. The semiconductor device according to claim 12, wherein: The number of layers of the insulating structure below the first lower surface is smaller than the number of layers of the insulating structure outside the side surface of the metal layer, and is larger than the number of layers of the insulating structure at a position spaced apart from the metal layer.

16. A semiconductor device comprising: a substrate having a photodiode formed thereon; an interlayer insulating layer located on the substrate; a via plug penetrating the interlayer insulating layer and at least a portion of the substrate; an insulating structure located on the interlayer insulating layer; as well as a metal layer formed on the via plug and the insulating structure, wherein the insulating structure comprising one or more layered structures is located below the metal layer, and The insulating structure includes fewer layers at a location spaced apart from a periphery of the metal layer than at a location adjacent to the periphery of the metal layer.

17. The semiconductor device according to claim 16, wherein: The insulating structure includes at least one of an etch stop layer and one or more insulating layers.

18. The semiconductor device according to claim 16, wherein: The insulating structure includes different numbers of layers according to distances from a side surface of the metal layer.

19. The semiconductor device according to claim 16, wherein: The metal layer comprises: a first lower surface extending inwardly from a side surface of the metal layer; and A second lower surface, wherein the second lower surface includes a step downward from the first lower surface.

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