Field effect transistor, system on chip, and method of manufacturing the same

Abstract

The present invention relates to a complementary metal oxide semiconductor system on chip, comprising a series of partially surrounding gate field effect transistors. Each partially surrounding gate field effect transistor comprises: a fin having a stack of channel regions; a source region and a drain region located on opposite sides of the fin; a dielectric separation region comprising a dielectric material between a first channel region and a second channel region; a gate stack located on the fin; and a pair of sidewall spacers located on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a corresponding sidewall spacer. The length of the portion of the dielectric separation region of one of the partially surrounding gate field effect transistors is different from the length of the portion of the dielectric separation region of another of the partially surrounding gate field effect transistors. A field effect transistor and a method for manufacturing a complementary metal oxide semiconductor system on chip are also provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 597,339, filed December 11, 2017, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to field effect transistors and methods of making the same. Background Art

[0004] Conventional circuits are often formed from non-planar "fin" field effect transistors (finFETs). Conventional fin field effect transistors generally include multiple vertical fins that act as conductive channel regions. Narrowing the width of the fin channel region improves gate control of the potential in the fin channel region. Therefore, conventional fin FETs may have narrower fin widths to reduce short channel effects and thus be able to scale to shorter gate lengths. However, as the gate length is scaled, conventional fin FETs may not provide the desired performance (e.g., I eff -I off ). In addition, conventional fin FETs are not gate-all-around (GAA) structures, and therefore the gate control is located only on one side of the fin, which limits further scaling of the gate length.

[0005] Future technologies have anticipated circuits formed by gate-all-around (GAA) nanowire (NW) FETs or GAA nanosheet (NS) FETs in order to reduce short channel effects and thereby be able to scale to shorter gate lengths. However, both GAA NW FETs and GAA NS FETs have integration issues. For example, GAA FETs require internal spacers to separate the GAA gate metal from the source / drain regions to reduce parasitic capacitance. In addition, GAA FETs generally require the GAA gate metal to be formed in a narrow vertical region between the bottom of the upper channel region and the top of the bottom channel region to reduce parasitic capacitance. However, forming the GAA gate metal in the narrow vertical region between the channel regions makes it difficult to achieve the desired threshold voltage (V t ).

[0006] In addition, future technology has anticipated that circuits formed by partial GAA NW FETs (also called partial surrounding gate field effect transistors or partial GAA FETs) will reduce short channel effects. In a conventional complementary metal oxide semiconductor (CMOS) system on chip (SoC) comprising a series of partial GAA NW FETs, all partial GAA NW FETs of the same type have the same length dielectric separation region. That is, in a conventional CMOS SoC, partial GAA NW FETs with different threshold voltage values ​​(e.g., high voltage threshold (HVT), regular voltage threshold (RVT), low voltage threshold (LVT), and super low voltage threshold (SLVT) FETs) all have the same length dielectric separation region. Therefore, these conventional CMOS SoCs comprising a series of partial GAA NW FETs are not optimized to achieve the highest performance at a compatible cost at the lowest dynamic power. Summary of the invention

[0007] Aspects of the present disclosure relate to various embodiments of a CMOS system on chip (SoC). In one embodiment, the CMOS SoC includes a series of partially surrounding gate field effect transistors, each of which includes: a fin having a stack of channel regions, the stack of channel regions including at least a first channel region and a second channel region stacked on the first channel region; a source region and a drain region located on opposite sides of the fin; a dielectric separation region including a dielectric material between the first channel region and the second channel region; a gate stack located on the fin; and a pair of sidewall spacers located on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a corresponding one of the pair of sidewall spacers. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different from the length of the portion of the dielectric separation region of another of the partial GAA FETs.

[0008] The length of the dielectrically separated portion of one of the partial GAA FETs may vary in a range of about 0 nanometers to about 10 nanometers or about 0 nanometers to about 6 nanometers.

[0009] One of the partial GAA FETs may have a high voltage threshold or a normal voltage threshold, and the capacitance of the partial GAA FET may be lower than the capacitance of the other partial GAA FET.

[0010] One of the partial GAA FETs may have a low voltage threshold or an ultra-low voltage threshold, and a resistance of the partial GAA FET may be lower than a resistance of the other GAA FET.

[0011] The length of the doped extension region of one of the partial GAA FETs may be substantially the same as the length of the doped extension region of the other partial GAA FET.

[0012] The length of the doped extension region of one partial GAA FET may be smaller than the length of the doped extension region of another partial GAA FET.

[0013] The pair of sidewall spacers of one partial GAA FET may be thinner than the pair of sidewall spacers of another partial GAA FET.

[0014] Aspects of the present disclosure also relate to various embodiments of a field effect transistor. In one embodiment, the field effect transistor includes: a fin including a stack of channel regions, the stack of channel regions having at least a first channel region and a second channel region stacked on the first channel region; a source region and a drain region located on opposite sides of the fin; a dielectric spacer region including a dielectric material between the first channel region and the second channel region; a gate stack located on the fin; and a pair of sidewall spacers located on opposite sides of the gate stack. The outer edge of the dielectric spacer region is laterally located between the inner surface and the outer surface of a corresponding one of the pair of sidewall spacers.

[0015] A portion of the dielectric separation region may have a length from an outer edge of the dielectric separation region to an inner edge of a corresponding one of the sidewall spacers. The length of the dielectric separation portion may be about 0 nanometers to about 10 nanometers, or about 0 nanometers to about 6 nanometers.

[0016] Aspects of the present disclosure also relate to various methods of manufacturing a CMOS on-chip system including a series of partial GAA FETs. In one embodiment, the method includes: forming a first partial GAA FET of the series of partial GAA FETs, and forming a second partial GAA FET of the series of partial GAA FETs. Each of the first partial GAA FET and the second partial GAA FET includes: a fin having a stack of channel regions, the stack of channel regions including at least a first channel region and a second channel region stacked on the first channel region; a source region and a drain region located on opposite sides of the fin; a dielectric separation region including a dielectric material between the first channel region and the second channel region; a gate stack located on the fin; and a pair of sidewall spacers located on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a corresponding one of the pair of sidewall spacers. The length of the portion of the dielectric separation region of the first partial GAA FET is different from the length of the portion of the dielectric separation region of the second partial GAA FET.

[0017] The length of the dielectrically separated portion of the second partial GAA FET may be less than the length of the dielectrically separated portion of the first partial GAA FET. The length of the dielectrically separated portion of the second partial GAA FET may be about 0 nm to about 10 nm, or about 0 nm to about 6 nm.

[0018] The first portion GAA FET may have a high voltage threshold or a normal voltage threshold, and a capacitance of the first portion GAA FET may be lower than a capacitance of the second portion GAA FET.

[0019] The second portion GAA FET may have a low voltage threshold or an ultra-low voltage threshold, and a resistance of the second portion GAA FET may be lower than a resistance of the first portion GAA FET.

[0020] The length of the doped extension region of the first partial GAA FET may be substantially the same as the length of the doped extension region of the second partial GAA FET.

[0021] The length of the doped extension region of the first partial GAA FET may be different from the length of the doped extension region of the second partial GAA FET.

[0022] The pair of sidewall spacers of the second partial GAA FET may be thinner than the pair of sidewall spacers of the first partial GAA FET.

[0023] Forming a first partial GAA FET or a second partial GAA FET may include: depositing a stack of alternating sacrificial layers and conductive channel layers on a silicon substrate; patterning and etching the stack to form at least one fin; forming a dummy gate stack on at least one fin; forming external sidewall spacers on opposite sides of the dummy gate stack; laterally etching opposite ends of each sacrificial layer; and forming source and drain regions.

[0024] This Summary is provided to introduce a series of features and concepts of embodiments of the present disclosure, which are further described in the following Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features can be combined with one or more other described features to provide a working device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The features and advantages of the embodiments of the present disclosure will become more apparent when considered in conjunction with the following drawings with reference to the following detailed description. In the drawings, like reference numerals are used throughout the various figures to refer to like features and components. The various figures are not necessarily drawn to scale.

[0026] Figure 1is a cross-sectional view of a CMOS system on chip (SoC) according to one embodiment of the present disclosure.

[0027] Figure 2 is a cross-sectional view of a CMOS SoC according to another embodiment of the present disclosure.

[0028] Figure 3 is a cross-sectional view of a CMOS SoC according to yet another embodiment of the present disclosure.

[0029] Figure 4 is a cross-sectional view of a CMOS SoC according to another embodiment of the present disclosure.

[0030] FIG. 5A to FIG. 5D The tasks of a method of manufacturing a CMOS SoC according to one embodiment of the present disclosure are shown.

[0031] Description of Figure Numbers

[0032] 100, 200, 300, 400, 500: complementary metal oxide semiconductor system on chip;

[0033] 101, 201, 301, 401, 501: first part of surround gate field effect transistor;

[0034] 102, 202, 302, 402, 502: second part surround gate field effect transistor;

[0035] 103, 105, 203, 205, 303, 305, 403, 405, 522, 536: source area;

[0036] 104, 106, 204, 206, 304, 306, 404, 406, 523, 537: leakage area;

[0037] 107, 108, 207, 208, 307, 308, 407, 408, 506, 507: fins;

[0038] 109, 110, 209, 210, 309, 310, 409, 410: channel region;

[0039] 111, 112, 211, 212, 311, 312, 411, 412, 552, 553: dielectric separation region;

[0040] 113, 114, 213, 214, 313, 314, 413, 414, 505: substrate;

[0041] 115, 116, 215, 216, 315, 316, 415, 416, 548, 549: gate stack;

[0042] 117, 118, 217, 218, 317, 318, 417, 418, 550: gate dielectric layer;

[0043] 119, 120, 219, 220, 319, 320, 419, 420, 551: metal layer;

[0044] 121, 122, 123, 124, 221, 222, 223, 224, 321, 322, 323, 324, 421, 422, 423, 424, 510, 511, 512, 513: sidewall spacers;

[0045] 125, 126, 127, 128, 225, 226, 227, 228, 325, 326, 327, 328, 425, 426, 427, 428, 514, 515, 534, 535: outer surface;

[0046] 129, 130, 131, 132, 229, 230, 231, 232, 329, 330, 331, 332, 429, 430, 431, 432, 520, 521, 556, 557: inner surface;

[0047] 133, 134, 135, 136, 233, 234, 235, 236, 333, 334, 335, 336, 433, 434, 435, 436, 518, 519, 530, 531, 554, 555, 558, 559: outer edge;

[0048] 237, 238, 239, 240, 337, 338, 339, 340, 437, 438, 439, 440: doped extension region;

[0049] 241, 242, 243, 244, 341, 342, 343, 344, 441, 442, 443, 444: inner edge;

[0050] 503: Sacrificial layer;

[0051] 504: channel layer;

[0052] 508, 509: dummy gate stack;

[0053] 516, 517: recessed parts;

[0054] 524, 538: source buffer layer;

[0055] 525, 539: drain buffer layer;

[0056] 526, 527, 540, 541, 542, 543: vertical side walls;

[0057] 528, 529, 544, 545: exposure part;

[0058] 532, 546: doped source region;

[0059] 533, 547: doped drain region;

[0060] D.D 2 :distance;

[0061] D 1 :depth;

[0062] L 1 , L 2 :length;

[0063] W 1 , W 2 :width. DETAILED DESCRIPTION

[0064] The present disclosure relates to various embodiments of a low-power, high-performance CMOS system-on-chip (SoC) that includes a series of partial-all-around gate (partial GAA) nFETs and partial GAA pFETs. According to one or more embodiments of the CMOS SoC, dielectric separation regions of the partial GAA nFETs and partial GAA pFETs do not have the same length for all partial GAA nFETs and partial GAA pFETs (e.g., the length of the dielectric separation region of one of the partial GAA pFETs or partial GAA nFETs is different from the length of the dielectric separation region of at least one other partial GAA pFET or partial GAA nFET of the CMOS SoC). Compared to a prior art CMOS SoC in which the length of the dielectric separation region is the same for each of the partial GAA pFETs and partial GAA nFETs, the difference between the lengths of the dielectric separation regions of the partial GAA nFETs and partial GAA pFETs is configured to achieve the highest performance at the lowest dynamic power of the CMOS SoC (e.g., the difference between the lengths of the dielectric separation regions of the partial GAA nFETs and partial GAA pFETs can achieve the highest performance at a compatible cost at the lowest dynamic power of the CMOS SoC).

[0065] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which similar reference numerals refer to similar elements throughout the text. However, the present invention can be embodied in various different forms and should not be construed as being limited to the embodiments shown only herein. On the contrary, these embodiments are provided as examples so that the present invention will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements, and technologies that are not necessary for a complete understanding of the aspects and features of the present invention by those of ordinary skill in the art may not be described. Unless otherwise noted, similar reference numerals represent similar elements throughout the drawings and written descriptions, and therefore their descriptions will not be repeated.

[0066] In the accompanying drawings, the relative sizes of elements, layers, and regions may be exaggerated and / or simplified for clarity. For ease of explanation, spatially relative terms such as "beneath," "below," "lower," "under," "above," "upper," and the like may be used herein to describe the relationship between an element or feature and another element or feature as shown in the figure. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figure. For example, if the device in the figure is turned upside down, the element described as "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the example terms "below" and "below" may encompass orientations above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0067] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the first element, first component, first region, first layer or first section described below may be referred to as the second element, second component, second region, second layer or second section without departing from the spirit and scope of the present invention.

[0068] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0069] The terms used herein are only for the purpose of describing a specific embodiment, and are not intended to limit the present invention. As used herein, unless the context makes clear indications otherwise, the singular form "a / an" is also intended to include the plural form. It will be further understood that when used in this specification, the terms "comprises / comprising", "includes / including" limit the existence of stated features, integral bodies, steps, operations, elements and / or components, but do not exclude the existence or supplementation of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When before a list of elements, the expression of, for example, "at least one of" modifies the entire list of elements and does not modify the individual elements in the list.

[0070] As used herein, the terms "substantially," "about," and the like are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations of measurements or calculations that would be recognized by one of ordinary skill in the art. Additionally, when describing embodiments of the present invention, the use of "may" refers to "one or more embodiments of the present invention." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Furthermore, the term "exemplary" is intended to refer to an example or illustration.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0072] Reference now Figure 1, a CMOS system-on-chip (SoC) 100 according to one embodiment of the present disclosure includes a first partial gate-all-around (GAA) field-effect transistor (FET) 101 and a second partial GAA FET 102. In the illustrated embodiment, each of the first partial GAA FET 101 and the second partial GAA FET 102 includes a source region 103 and a drain region 104, a source region 105 and a drain region 106, respectively, and at least one fin 107, a fin 108 extending between the source region 103 and the drain region 104, and between the source region 105 and the drain region 106, respectively. In the illustrated embodiment, the fin 107, a fin 108 of each of the first partial GAA FET 101 and the second partial GAA FET 102 includes a series of stacked channel regions 109, a stacked channel region 110, respectively. In addition, in the illustrated embodiment, each of the partial GAA FET 101 and the partial GAA FET 102 includes a series of dielectric partitions 111 and 112 located between adjacent channel regions 109 and adjacent channel regions 110 and between the lowermost channel regions 109 and the lowermost channel regions 110 and the substrates 113 and 114, respectively, and the fins 107 and 108 are formed on the substrates 113 and 114. In the illustrated embodiment, each of the partial GAA FET 101 and the partial GAA FET 102 further includes a gate stack 115 and a gate stack 116 on the fins 107 and 108, respectively. Each of the gate stacks 115 and 116 includes a gate dielectric layer 117 and a gate dielectric layer 118 and a metal layer 119 and a metal layer 120 on the gate dielectric layer 117 and the gate dielectric layer 118, respectively. In the illustrated embodiment, each of the partial GAA FET 101 and the partial GAA FET 102 further includes a pair of sidewall spacers 121 and 122 and a pair of sidewall spacers 123 and 124 on opposite sides of the gate stack 115 and the gate stack 116, respectively. Each of the sidewall spacers 121, 122, 123 and 124 includes an outer surface 125, 126, 127 and 128 facing outward away from the corresponding gate stack 115 and the corresponding gate stack 116, and an inner surface 129, 130, 131 and 132 facing inward toward the corresponding gate stack 115 and the corresponding gate stack 116 and opposite to the corresponding outer surface 125, 126, 127 and 128.

[0073] Continue to refer Figure 1In the embodiment shown in FIG. 1 , the portion of each dielectric partition region 111 of the first partial GAA FET 101 has a length L defined from the outer edge 133, the outer edge 134 of the dielectric partition region 111 to the inner surface 129, the inner surface 130 of the corresponding sidewall spacer 121, the corresponding sidewall spacer 122 (e.g., the inner surface 129, the inner surface 130 of the upper sidewall spacer 121, the upper sidewall spacer 122) 1 In addition, in the illustrated embodiment, the portion of each dielectric partition region 112 of the second partial GAA FET 102 has a length L defined from the outer edge 135, the outer edge 136 of the dielectric partition region 112 to the inner surface 131, the inner surface 132 of the corresponding sidewall spacer 123, the corresponding sidewall spacer 124 (e.g., the inner surface 131, the inner surface 132 of the upper sidewall spacer 123, the upper sidewall spacer 124). 2 In addition, in the illustrated embodiment, the length L of the portion of the dielectric separation region 111 of the first partial GAA FET 101 is 1 The length L of the portion of the dielectric separation region 112 greater than the second portion of the GAA FET 102 2 In the illustrated embodiment, the outer edges 133, 134 of the dielectric separation region 111 of the first partial GAA FET 101 are aligned or substantially aligned with the outer surfaces 125, 126 of the upper sidewall spacers 121, 122, respectively, and the outer edges 135, 136 of the dielectric separation region 112 of the second partial GAA FET 102 are located between the inner surfaces 131, 132 and the outer surfaces 127, 128 of the upper sidewall spacers 123, 124, respectively. Therefore, in the illustrated embodiment, the dielectric separation region 111 of the first partial GAA FET 101 is longer than the dielectric separation region 112 of the second partial GAA FET 102.

[0074] In one or more embodiments, different lengths L 1 Length L 2 The first part GAAFET 101 and the second part GAAFET 102 of the dielectric separation region have different threshold voltages V t or the same threshold voltage V t In one or more embodiments, the CMOS SoC 100 may include a series of partial GAA FETs with different threshold voltages, and may have different threshold voltages V t The first partial GAA FET 101 and the second partial GAA FET 102 are at least a subset of partial GAA FETs having different threshold voltages of the CMOS SoC 100. In one or more embodiments, the GAA FETs having different lengths L1 Length L 2 The dielectric separation region 111, the first partial GAA FET 101 of the dielectric separation region 112, and the second partial GAA FET 102 may be disposed at different portions of the CMOS SoC 100. In one or more embodiments, the first partial GAA FET 101 having a longer length of the dielectric separation region 111 than the second partial GAA FET 102 has or may have a high voltage threshold V t (HVT) or conventional voltage threshold V t (RVT), while the second partial GAA FET 102 having a shorter length of the dielectric separation region 112 than the dielectric separation region in the first partial GAA FET 101 has or may have a low voltage threshold V t (LVT) or Very Low Voltage Threshold V t (SLVT). In one or more embodiments, the length of the dielectric separation region of the HVT portion GAA FET is longer than the length of the dielectric separation region of the RVT portion GAA FET. In addition, the length of the dielectric separation region of the RVT portion GAA FET is longer than the length of the dielectric separation region of the LVT portion GAA FET, and the length of the dielectric separation region of the LVT portion GAA FET is longer than the length of the dielectric separation region of the SLVT portion GAA FET. In one or more embodiments, the threshold voltage difference between the HVT portion GAA FET and the RVT portion GAA FET, between the RVT portion GAA FET and the LVT portion GAA FET, and between the LVT portion GAA FET and the SLVT portion GAA FET is about 20 millivolts to about 50 millivolts. In one or more embodiments, the first portion GAA FET 101 having a relatively longer dielectric separation region 111 may be provided in a portion of the CMOS SoC 100 to minimize or at least reduce the parasitic gate-drain capacitance (Cgd) of the portion to reduce the dynamic power associated with the portion of the CMOS SoC 100. In addition, in one or more embodiments, this portion of the CMOS SoC 100 may include at least a subset of GPU cores. In one or more embodiments, this portion of the CMOS SoC 100 where the first portion GAA FET 101 is located may include at least a subset of GPU cores and / or at least a subset of GPU cores and CPU cores that do not include a critical speed path. In one or more embodiments, the second portion GAA FET 102 having a relatively shorter dielectric separation region 112 may be disposed in a portion of the CMOS SoC 100 that includes, for example, a critical speed path, and the parasitic spreading resistance (R ext) is minimized or at least reduced to increase the effective drive current (I ) associated with this portion of the CMOS SoC 100 eff ).

[0075] In one or more embodiments where the second portion GAA FET 102 is an LVT portion GAA FET, the length L of the portion of the dielectric separation region 112 is 2 The length L of the portion of the dielectric separation region 112 may be from about 0 nanometers (e.g., the outer edge 135, 136 of the dielectric separation region 112 may be aligned or substantially aligned with the inner surface 131, 132 of the corresponding sidewall spacer 123, 124) to about 6 nanometers. In one or more embodiments, the length L of the portion of the dielectric separation region 112 may be from about 0 nanometers (e.g., the outer edge 135, 136 of the dielectric separation region 112 may be aligned or substantially aligned with the inner surface 131, 132 of the corresponding sidewall spacer 123, 124). 2 In one or more embodiments where the first partial GAA FET 101 is disposed in a portion of the CMOS SoC 100 to minimize or at least reduce the Cgd of the portion, the length L of the portion of the dielectric separation region 111 in the first partial GAA FET 101 is 1 The length L of the portion of the dielectric separation region 111 in the first partial GAA FET 101 may be greater than 0 nanometers (eg, about 3 nanometers to about 10 nanometers). 1 The width may be equal to or substantially equal to the width of the sidewall spacers 123 and 124 so that the outer edges 133 and 134 of the dielectric separation region 111 are aligned or substantially aligned with the outer surfaces 125 and 126 of the corresponding sidewall spacers 121 and 122 .

[0076] Reference now Figure 2, a CMOS SOC 200 according to another embodiment of the present disclosure includes a first partial GAA FET 201 and a second partial GAA FET 202. In the illustrated embodiment, each of the first partial GAA FET 201 and the second partial GAA FET 202 includes a source region 203 and a drain region 204, a source region 205 and a drain region 206, and at least one fin 207, a fin 208 extending between the source region 203 and the drain region 204, and between the source region 205 and the drain region 206, respectively. In the illustrated embodiment, the fin 207, the fin 208 of each of the first partial GAA FET 201 and the second partial GAA FET 202 includes a series of stacked channel regions 209, a stacked channel region 210, respectively. In addition, in the illustrated embodiment, each of the partial GAA FET 201 and the partial GAA FET 202 includes a series of dielectric partitions 211 and 212 located between adjacent channel regions 209 and adjacent channel regions 210 and between the lowermost channel regions 209 and the lowermost channel regions 210 and the substrates 213 and 214, respectively, and the fins 207 and 208 are formed on the substrates 213 and 214. In the illustrated embodiment, each of the partial GAA FET 201 and the partial GAA FET 202 also includes a gate stack 215 and a gate stack 216 on the fins 207 and 208, respectively. Each of the gate stacks 215 and 216 includes a gate dielectric layer 217 and a gate dielectric layer 218 and a metal layer 219 and a metal layer 220 on the gate dielectric layer 217 and the gate dielectric layer 218, respectively. In the illustrated embodiment, each of the partial GAA FET 201 and the partial GAA FET 202 further includes a pair of sidewall spacers 221 and 222 and a pair of sidewall spacers 223 and 224 on opposite sides of the gate stack 215 and the gate stack 216, respectively. Each of the sidewall spacers 221, 222, 223 and 224 includes an outer surface 225, an outer surface 226, an outer surface 227 and an outer surface 228 facing outward away from the corresponding gate stack 215 and the corresponding gate stack 216, and an inner surface 229, an inner surface 230, an inner surface 231 and an inner surface 232 facing inward toward the corresponding gate stack 215 and the corresponding gate stack 216 and opposite to the corresponding outer surface 225, the outer surface 226, the outer surface 227 and the outer surface 228.

[0077] exist Figure 2In the embodiment shown in FIG. 1 , the portion of each dielectric partition region 211 of the first partial GAA FET 201 has a length L defined from the outer edge 233, the outer edge 234 of the dielectric partition region 211 to the inner surface 229, the inner surface 230 of the corresponding sidewall spacer 221, the corresponding sidewall spacer 222 (e.g., the inner surface 229, the inner surface 230 of the upper sidewall spacer 221, the upper sidewall spacer 222) 1 In addition, in the illustrated embodiment, the portion of each dielectric partition region 212 of the second partial GAA FET 202 has a length L defined from the outer edge 235, outer edge 236 of the dielectric partition region 212 to the inner surface 231, inner surface 232 of the corresponding sidewall spacer 223, corresponding sidewall spacer 224 (e.g., the inner surface 231, inner surface 232 of the upper sidewall spacer 223, upper sidewall spacer 224). 2 In addition, in the illustrated embodiment, the length L of the portion of the dielectric separation region 211 of the first partial GAA FET 201 is 1 The length L of the portion of the dielectric separation region 212 greater than the second portion of the GAA FET 202 2 Therefore, in the illustrated embodiment, the dielectric separation region 211 of the first partial GAA FET 201 is longer than the dielectric separation region 212 of the second partial GAA FET 202. The length L of the dielectric separation region 211 and the dielectric separation region 212 is 1 Length L 2 Can refer to the above Figure 1 The lengths described in the embodiments shown in are the same or similar. Figure 1 As described in the embodiment shown in FIG. 1 , the first partial GAA FET 201 having a longer length of the dielectric separation region 211 than the second partial GAA FET 202 has or may have a high voltage threshold V t (HVT) or conventional voltage threshold V t (RVT), while the second partial GAA FET 202 having a shorter dielectric separation region 212 than the first partial GAA FET 201 has or may have a low voltage threshold V t (LVT) or Very Low Voltage Threshold V t (SLVT).

[0078] In addition, unlike Figure 1 The embodiment of the CMOS SoC 100 shown in FIG. Figure 2In the embodiment of the CMOS SOC 200 shown in the figure, the extension under the gate stack 215 of the doped extension region 237 and the doped extension region 238 of the source region 203 and the drain region 204 in the first part GAA FET 201 is different from the extension under the gate stack 216 of the doped extension region 239 and the doped extension region 240 of the source region 205 and the drain region 206 in the second part GAA FET 202. In the illustrated embodiment, the inner edges 241, 242 of the doped extension regions 237, 238 in the first partial GAA FET 201 are aligned or substantially aligned with the inner surfaces 229, 230 of the sidewall spacers 221, 222, and the inner edges 243, 244 of the doped extension regions 239, 240 in the second partial GAA FET 202 are spaced inwardly from the inner surfaces 231, 232 of the corresponding sidewall spacers 223, 224 (for example, the doped extension regions 239, 240 of the second partial GAA FET 202 extend farther under the gate stack 216 than the doped extension regions 237, 238 under the gate stack 215 of the first partial GAA FET 201). In one or more embodiments, the distance D between the doped extension region 239, the inner edge 243, and the inner edge 244 of the doped extension region 240 of the second partial GAA FET 202 and the inner surface 231, and the inner surface 232 of the sidewall spacer 223, the sidewall spacer 224, respectively, is in the range of about 0 nanometers to about 10 nanometers (for example, in the range of about 0 nanometers to about 5 nanometers).

[0079] In one or more embodiments, a first partial GAA FET 201 having a relatively longer dielectric separation region 211 may be disposed in a portion of a CMOS SoC 200, minimizing or at least reducing a parasitic gate-drain capacitance (Cgd) of the portion to reduce dynamic power associated with the portion of the CMOS SoC 200. In one or more embodiments, a second partial GAA FET 202 having a relatively shorter dielectric separation region 212 may be disposed in a portion of the CMOS SoC 200 including, for example, a critical speed path, and minimizing a parasitic spreading resistance (R ext ) is minimized or at least reduced to increase the effective drive current (I ) associated with this portion of the CMOS SoC 200 eff ).

[0080] Reference now Figure 3, a CMOS SOC 300 according to another embodiment of the present disclosure includes a first partial GAA FET 301 and a second partial GAA FET 302. In the illustrated embodiment, each of the first partial GAA FET 301 and the second partial GAA FET 302 includes a source region 303 and a drain region 304, a source region 305 and a drain region 306, respectively, and at least one fin 307, a fin 308 extending between the source region 303 and the drain region 304, and between the source region 305 and the drain region 306, respectively. In the illustrated embodiment, the fin 307, the fin 308 of each of the first partial GAA FET 301 and the second partial GAA FET 302 includes a series of stacked channel regions 309, a stacked channel region 310, respectively. In addition, in the illustrated embodiment, each of the partial GAA FET 301 and the partial GAA FET 302 includes a series of dielectric partitions 311 and 312 located between adjacent channel regions 309 and adjacent channel regions 310 and between the lowermost channel regions 309 and the lowermost channel regions 310 and the substrates 313 and 314, respectively, and the fins 307 and 308 are formed on the substrates 313 and 314. In the illustrated embodiment, each of the partial GAA FET 301 and the partial GAA FET 302 also includes a gate stack 315 and a gate stack 316 on the fins 307 and 308, respectively. Each of the gate stacks 315 and 316 includes a gate dielectric layer 317 and a gate dielectric layer 318 and a metal layer 319 and a metal layer 320 on the gate dielectric layer 317 and the gate dielectric layer 318, respectively. In the illustrated embodiment, each of the partial GAA FET 301 and the partial GAA FET 302 further includes a pair of sidewall spacers 321 and 322 and a pair of sidewall spacers 323 and 324 on opposite sides of the gate stack 315 and the gate stack 316, respectively. Each of the sidewall spacers 321, 322, 323 and 324 includes an outer surface 325, 326, 327 and 328 facing outward away from the corresponding gate stack 315 and the corresponding gate stack 316, and an inner surface 329, 330, 331 and 332 facing inward toward the corresponding gate stack 315 and the corresponding gate stack 316 opposite to the outer surface 325, 326, 327 and 328.

[0081] Additionally, in the illustrated embodiment, the sidewall spacers 321, 322 of the first partial GAA FET 301 have a width W defined from the inner surface 329, 330 to the respective outer surface 325, 326. 1, and the sidewall spacers 323 and 324 of the second partial GAA FET 302 have a width W defined from the inner surface 331 and the inner surface 332 to the corresponding outer surface 327 and the corresponding outer surface 328 2 In the illustrated embodiment, the width W of the sidewall spacers 323 and 324 of the second partial GAA FET 302 is 2 Smaller than the width W of the sidewall spacers 321 and 322 of the first portion GAA FET 301 1 (For example, the sidewall spacers 323 and 324 of the second partial GAA FET 302 are relatively narrower than the sidewall spacers 321 and 322 of the first partial GAA FET 301).

[0082] exist Figure 3 In the embodiment shown in FIG. 1 , the portion of each dielectric partition region 311 of the first partial GAA FET 301 has a length L defined from the outer edge 333, the outer edge 334 of the dielectric partition region 311 to the inner surface 329, the inner surface 330 of the corresponding sidewall spacer 321, the corresponding sidewall spacer 322 (e.g., the inner surface 329, the inner surface 330 of the upper sidewall spacer 321, the upper sidewall spacer 322). 1 In addition, in the illustrated embodiment, the portion of each dielectric partition region 312 of the second partial GAA FET 302 has a length L defined from the outer edge 335, the outer edge 336 of the dielectric partition region 312 to the inner surface 331, the inner surface 332 of the corresponding sidewall spacer 323, the corresponding sidewall spacer 324 (e.g., the inner surface 331, the inner surface 332 of the upper sidewall spacer 323, the upper sidewall spacer 324). 2 In addition, in the illustrated embodiment, the length L of the portion of the dielectric separation region 311 of the first partial GAA FET 301 is 1 greater than the length L of the portion of the dielectric separation region 312 of the second portion GAA FET 302 2 Therefore, in the illustrated embodiment, the dielectric separation region 311 of the first partial GAA FET 301 is longer than the dielectric separation region 312 of the second partial GAA FET 302. The length L of the dielectric separation region 311 and the dielectric separation region 312 is 1 Length L 2 Can refer to the above Figure 1 The lengths described in the embodiments shown in are the same or similar. Figure 1 As described in the embodiment shown in FIG. 1 , the first partial GAA FET 301 having a longer dielectric separation region 311 than the second partial GAA FET 302 has or may have a high voltage threshold V t(HVT) or conventional voltage threshold V t (RVT), while the second partial GAA FET 302 having a shorter length of dielectric separation region 312 than in the first partial GAA FET 301 has or may have a low voltage threshold V t (LVT) or Very Low Voltage Threshold V t (SLVT).

[0083] Continue to refer Figure 3 In the embodiment shown in the figure, the extension under the gate stack 315 of the doped extension region 337 and the doped extension region 338 of the source region 303 and the drain region 304 in the first part GAA FET 301 is different from the extension under the gate stack 316 of the doped extension region 339 and the doped extension region 340 of the source region 305 and the drain region 306 in the second part GAA FET 302. In the illustrated embodiment, the inner edges 341, 342 of the doped extension regions 337, 338 in the first partial GAA FET 301 are aligned or substantially aligned with the inner surfaces 329, 330 of the sidewall spacers 321, 322, and the inner edges 343, 344 of the doped extension regions 339, 340 in the second partial GAA FET 302 are spaced inwardly by a distance D from the inner surfaces 331, 332 of the corresponding sidewall spacers 323, 324 (for example, the doped extension regions 339, 340 of the second partial GAA FET 302 extend farther below the gate stack than the doped extension regions 337, 338 of the first partial GAA FET 301). In one or more embodiments, the distance D between the doped extension region 339, the inner edge 343, and the inner edge 344 of the doped extension region 340 of the second partial GAA FET 302 and the inner surface 331 and the inner surface 332 of the sidewall spacer 323, the sidewall spacer 324, respectively, is in the range of about 0 nanometers to about 10 nanometers (for example, in the range of about 0 nanometers to about 5 nanometers).

[0084] In one or more embodiments, the first partial GAA FET 301 having a relatively longer dielectric separation region 311 and relatively wider sidewall spacers 321 and 322 may be disposed in a portion of the CMOS SOC 300, minimizing or at least reducing the parasitic gate-drain capacitance (Cgd) of the portion to reduce the dynamic power associated with the portion of the CMOS SOC 300. In one or more embodiments, the second partial GAA FET 302 having a relatively shorter dielectric separation region 312 and relatively narrower sidewall spacers 323 and 324 may be disposed in a portion of the CMOS SOC 300 including, for example, a critical speed path, and minimizing or at least reducing the parasitic gate-drain capacitance (Cgd) of the portion to reduce the dynamic power associated with the portion of the CMOS SOC 300. ext ) is minimized or at least reduced to increase the effective drive current (I eff ).

[0085] Reference now Figure 4, a CMOS SOC 400 according to another embodiment of the present disclosure includes a first partial GAA FET 401 and a second partial GAA FET 402. In the illustrated embodiment, each of the first partial GAA FET 401 and the second partial GAA FET 402 includes a source region 403 and a drain region 404, a source region 405 and a drain region 406, respectively, and at least one fin 407, a fin 408 extending between the source region 403 and the drain region 404, and between the source region 405 and the drain region 406, respectively. In the illustrated embodiment, the fin 407, the fin 408 of each of the first partial GAA FET 401 and the second partial GAA FET 402 includes a series of stacked channel regions 409, a stacked channel region 410, respectively. In addition, in the illustrated embodiment, each of the partial GAA FET 401 and the partial GAA FET 402 includes a series of dielectric partitions 411 and 412 located between adjacent channel regions 409 and 410 and between the lowermost channel regions 409 and 410 and substrates 413 and 414, respectively, and the fins 407 and 408 are formed on the substrates 413 and 414. In the illustrated embodiment, each of the partial GAA FET 401 and the partial GAA FET 402 further includes a gate stack 415 and a gate stack 416 on the fins 407 and 408, respectively. Each of the gate stacks 415 and 416 includes a gate dielectric layer 417 and a gate dielectric layer 418 and a metal layer 419 and a metal layer 420 on the gate dielectric layer 417 and the gate dielectric layer 418, respectively. In the illustrated embodiment, each of the partial GAA FET 401 and the partial GAA FET 402 further includes a pair of sidewall spacers 421 and 422 and a pair of sidewall spacers 423 and 424 on opposite sides of the gate stack 415 and the gate stack 416, respectively. Each of the sidewall spacers 421, 422, 423 and 424 includes an outer surface 425, an outer surface 426, an outer surface 427 and an outer surface 428 facing outward away from the corresponding gate stack 415 and the corresponding gate stack 416, and an inner surface 429, an inner surface 430, an inner surface 431 and an inner surface 432 facing inward toward the corresponding gate stack 415 and the corresponding gate stack 416 and opposite to the corresponding outer surface 425, the outer surface 426, the outer surface 427 and the outer surface 428.

[0086] exist Figure 4In the embodiment shown in FIG. 1 , the portion of each dielectric partition region 411 of the first partial GAA FET 401 has a length L defined from the outer edge 433, the outer edge 434 of the dielectric partition region 411 to the inner surface 429, the inner surface 430 of the corresponding sidewall spacer 421, the corresponding sidewall spacer 422 (e.g., the inner surface 429, the inner surface 430 of the upper sidewall spacer 421, the upper sidewall spacer 422) 1 In addition, in the illustrated embodiment, the portion of each dielectric partition region 412 of the second partial GAA FET 402 has a length L defined from the outer edge 435, the outer edge 436 of the dielectric partition region 412 to the inner surface 431, the inner surface 432 of the corresponding sidewall spacer 423, the corresponding sidewall spacer 424 (e.g., the inner surface 431, the inner surface 432 of the upper sidewall spacer 423, the upper sidewall spacer 424). 2 In addition, in the illustrated embodiment, the length L of the portion of the dielectric separation region 411 of the first partial GAA FET 401 is 1 greater than the length L of the portion of the dielectric separation region 412 of the second portion GAA FET 402 2 Therefore, in the illustrated embodiment, the dielectric separation region 411 of the first partial GAA FET 401 is longer than the dielectric separation region 412 of the second partial GAA FET 402. The length L of the dielectric separation region 411 and the dielectric separation region 412 is 1 Length L 2 Can refer to the above Figure 1 In one or more embodiments, the length L of the dielectric separation region 412 of the second partial GAA FET 402 is the same or similar to the length L of the dielectric separation region 412 of the second partial GAA FET 402. 2 may be zero or substantially zero so that the outer edge 435, outer edge 436 of the dielectric separation region 412 of the second partial GAA FET 402 is aligned or substantially aligned with the inner surface 431, inner surface 432 of the sidewall spacer 423, sidewall spacer 424, respectively. Figure 1 As described in the embodiment shown in FIG. 1 , the first partial GAA FET 401 having a longer dielectric separation region 411 than the second partial GAA FET 402 has or may have a high voltage threshold V t (HVT) or conventional voltage threshold V t (RVT), while the second partial GAA FET 402 having a shorter length of dielectric separation region 412 than in the first partial GAA FET 401 has or may have a low voltage threshold V t (LVT) or Very Low Voltage Threshold V t (SLVT).

[0087] In addition, Figure 4 In the embodiment of the CMOS SoC 400 shown in the figure, the extension under the gate stack 415 of the doped extension region 437 and the doped extension region 438 of the source region 403 and the drain region 404 in the first part GAA FET 401 is different from the extension under the gate stack 416 of the doped extension region 439 and the doped extension region 440 of the source region 405 and the drain region 406 in the second part GAA FET 402. In the illustrated embodiment, the inner edges 441, 442 of the doped extension regions 437, 438 in the first partial GAA FET 401 are aligned or substantially aligned with the inner surfaces 429, 430 of the sidewall spacers 421, 422, and the inner edges 443, 444 of the doped extension regions 439, 440 in the second partial GAA FET 402 are spaced inwardly at a distance D from the inner surfaces 431, 432 of the corresponding sidewall spacers 423, 424 (for example, the doped extension regions 439, 440 of the second partial GAA FET 402 extend farther below the gate stack than the doped extension regions 437, 438 of the first partial GAA FET 401). In one or more embodiments, the distance D between the doped extension region 439, the inner edge 443, and the inner edge 444 of the doped extension region 440 of the second partial GAA FET 402 and the inner surface 431 and the inner surface 432 of the sidewall spacer 423, the sidewall spacer 424, respectively, is in the range of about 0 nanometers to about 10 nanometers (for example, in the range of about 0 nanometers to about 5 nanometers).

[0088] In one or more embodiments, a first partial GAA FET 401 having a relatively longer dielectric separation region 411 may be disposed in a portion of a CMOS SoC 400, minimizing or at least reducing a parasitic gate-drain capacitance (Cgd) of the portion to reduce dynamic power associated with the portion of the CMOS SoC 400. In one or more embodiments, a second partial GAA FET 402 having a relatively shorter dielectric separation region 412 may be disposed in a portion of the CMOS SoC 400 including, for example, a critical speed path, and minimizing a parasitic spreading resistance (R ext ) is minimized or at least reduced to increase the effective drive current (I ) associated with this portion of the CMOS SoC 400 eff ).

[0089] The CMOS SoC according to one or more embodiments of the present disclosure may have the above reference Figures 1 to 4Any suitable combination of features of two or more of the described embodiments of CMOS SoC 100 , CMOS SoC 200 , CMOS SoC 300 , and CMOS SoC 400 .

[0090] FIG. 5A to FIG. 5D Depicts fabrication of a first partially all-around gate (GAA) FET 501 and a second partially all-around gate FET 502 (see FIG. Figure 5D ) is a method for a CMOS system on chip (SoC) 500. The first partial GAA FET 501 and the second partial GAA FET 502 may be partial GAA nFETs, partial GAA pFETs, or a combination of partial GAA nFETs and partial GAA pFETs. The first partial GAA FET 501 may be formed in a portion of the CMOS SoC 500, minimizing or at least reducing the parasitic gate-drain capacitance (Cgd) of the portion to reduce dynamic power associated with the portion of the CMOS SoC 500. The second partial GAA FET 502 may be formed in a portion of the CMOS SoC 500 that includes, for example, a critical speed path, and minimizing the parasitic spreading resistance (R ext ) is minimized or at least reduced to increase the effective drive current (I eff ). In one or more embodiments, the first portion GAA FET 501 has or may have a high voltage threshold V t (HVT) or conventional voltage threshold V t (RVT), and the second portion GAA FET 502 has or may have a low voltage threshold V t (LVT) or Very Low Voltage Threshold V t (SLVT).

[0091] like Figure 5AAs shown in , the method includes the following tasks: depositing a stack of alternating sacrificial layers 503 and conductive channel layers 504 layer by layer on a silicon substrate 505 so that the lowermost sacrificial layer 503 is directly located on the silicon substrate 505 and each remaining sacrificial layer 503 is disposed between the bottom channel layer 504 and the upper channel layer 504. In one or more embodiments, the sacrificial layer 503 is formed of silicon germanium (SiGe) and the conductive channel layer 504 is formed of Si. In one or more embodiments, the SiGe material of the sacrificial layer 503 may contain Ge in the range of about 15% to about 35%. In one or more embodiments, the sacrificial layer 503 has a thickness of about 2 nanometers to about 6 nanometers and the conductive channel layer 504 has a thickness of about 2 nanometers to about 12 nanometers. The silicon substrate 505 may include a (100) or (110) silicon substrate. Although in the illustrated embodiment, the task includes depositing four conductive channel layers 504 and four sacrificial layers 503, in one or more embodiments, the task may include depositing any other suitable number of conductive channel layers 504 and sacrificial layers 503 depending on the desired size of the first partial GAA FET 501 and the second partial GAA FET 502 (for example, the task may include depositing one or more conductive channel layers 504 and one or more sacrificial layers 503).

[0092] In one or more embodiments, the conductive channel layer 504 and the sacrificial layer 503 may not be formed of Si and SiGe, respectively. In one or more embodiments, the conductive channel layer 504 and the sacrificial layer 503 may be any other suitable material, whereby the sacrificial layer 503 may be selectively etched relative to the conductive channel layer 504 for use in n-type FETs, p-type FETs, or both n-type FETs and p-type FETs. In one or more embodiments where the FET is an n-type FET, the material of the conductive channel layer 504 and the sacrificial layer 503 may be a III-V group material, such as indium gallium arsenide (InGaAs) and indium phosphide (InP), respectively. In one or more embodiments, the material of the conductive channel layer 504 and the sacrificial layer 503 may be a IV group material for an n-type FET or a p-type FET, such as Ge and SiGe, respectively. In one or more embodiments where the FET is a p-type FET, the material of the conductive channel layer 504 and the sacrificial layer 503 may be a IV group material, such as SiGe and Si, respectively.

[0093] Continue to refer Figure 5AIn the embodiment shown in , the method further includes the following tasks: patterning and etching the stack of conductive channel layers 504 and sacrificial layers 503 to form at least one fin 506, 507 having the desired width of the first partial GAA FET 501 and the second partial GAA FET 502, respectively. The task of patterning and etching the stack of alternating conductive channel layers 504 and sacrificial layers 503 can be performed by any suitable process or technique, such as photolithography or etching (e.g., dry etching). In one or more embodiments, the task of forming the fins 506, 507 may include a single mask step and etching step or multiple mask steps and etching steps. In one or more embodiments, the task may include non-selective etching (e.g., dry etching) of the material of the channel layer 504 or the material of the sacrificial layer 503. Although in the embodiment shown, each partial GAA FET includes only a single fin 506, 507, in one or more embodiments, the method may include forming two or more fins for one or more of the partial GAA FETs. In one or more embodiments where the method includes forming two or more fins for one or more of the partial GAA FETs, the tasks of patterning and etching the stack of conductive channel layer 504 and sacrificial layer 503 include forming fins with a desired horizontal separation distance between adjacent fins.

[0094] Continue to refer Figure 5A In the embodiment shown in , the method further includes the following tasks: forming a dummy gate stack 508 and a dummy gate stack 509 (for example, a dummy gate stack 508 and a dummy gate stack 509 formed of oxide / poly-Si / nitride) on the fin 506 and the fin 507, respectively, by any process known in the art (for example, nitride deposition), and forming an external sidewall spacer 510, an external sidewall spacer 511 and an external sidewall spacer 512, an external sidewall spacer 513 on opposite sides of the dummy gate stack 508 and the dummy gate stack 509, respectively.

[0095] exist Figure 5A In the embodiment shown in , the method further includes the following tasks: masking the area of ​​the first partial GAA FET and etching the area of ​​the one or more fins 507 of the second partial GAA FET that are not protected by the dummy gate 509 and the external sidewall spacers 512, 513. In one or more embodiments, the etching of the one or more fins 507 of the second partial GAA FET is carried out all the way down to or into the silicon substrate 505. In one or more embodiments, the etching of the one or more fins 507 of the second partial GAA FET is a vertical or substantially vertical recessed etch, and the recessed etch is aligned or substantially aligned with the outer surface 514, 515 of the outer sidewall spacers 512, 513, respectively.

[0096] Continue to refer Figure 5A In the embodiment shown in , the method further includes the following task: laterally etching the opposite ends of each sacrificial layer 503 (for example, a sacrificial layer 503 formed of SiGe) of the fin 507 of the second partial GAAFET. The lateral recessed etching can be a wet etch or a dry etch as known in the art. During the task of laterally etching the sacrificial layer 503, the opposite ends of the sacrificial layer 503 are laterally removed, but the channel layer 504 remains substantially intact. Therefore, after the task of laterally etching the opposite ends of the sacrificial layer 503, the channel layer 504 extends beyond (for example, protrudes) the sacrificial layer 503, and the recessed portions 516 and 517 are formed between the outer edge 518 and the outer edge 519 of the recessed sacrificial layer 503 and the protruding portion of the channel layer 504, respectively. Depending on the selectivity of the material of the sacrificial layer 503 to the lateral etching of the material of the channel layer 504, the recessed portions 516 and 517 may have any shape (for example, a rectangular cross-sectional shape or a trapezoidal cross-sectional shape).

[0097] The sacrificial layer 503 of the fin 507 of the second portion GAA FET may be laterally recessed to any suitable depth D depending on the desired length of the dielectric separation region of the second portion GAA FET 502. 1 , the second portion GAAFET 502 is formed during a subsequent task of the method described below. In one or more embodiments, the lateral recess etching of the sacrificial layer 503 may be performed to a depth D 1 , so that the outer edge 518, the outer edge 519 of the side-etched sacrificial layer 503 is separated from the inner surface 520, the inner surface 521 of the corresponding sidewall spacer 512, the corresponding sidewall spacer 513 by a distance D 2 Laterally spaced apart (eg, each of the outer edges 518 and 519 of the laterally etched sacrificial layer 503 is spaced apart from the inner surfaces 520 and 521 of the upper sidewall spacers 512 and 513 by a distance D 2 In one or more embodiments, the distance D 2 The distance D may be about 0 nanometers (e.g., the outer edge 518, 519 of the laterally etched sacrificial layer 503 is aligned or substantially aligned with the inner surface 520, 521 of the corresponding sidewall spacer 512, 513) to about 10 nanometers. In one or more embodiments, the distance D 2 It may be about 0 nanometers to about 6 nanometers. In one or more embodiments, the distance D 2 It can be about 0 nanometers to about 3 nanometers. 2In one or more embodiments of the invention, the distance D is measured from the inner surface 520, inner surface 521 of the corresponding sidewall spacer 512, corresponding sidewall spacer 513 in the direction toward the outer surface 514, outer surface 515 of the corresponding sidewall spacer 512, corresponding sidewall spacer 513. 2 (For example, in one or more embodiments, outer edges 518, 519 of the laterally etched sacrificial layer 503 are laterally located between inner surfaces 520 and outer surfaces 514, and inner surfaces 521 and outer surfaces 515 of respective sidewall spacers 512, 513.) In the embodiment shown, the sacrificial layer 503 of the fin 506 of the first partial GAA FET is not laterally etched or is laterally etched to a lesser extent than the sacrificial layer 503 of the fin 507 of the second partial GAA FET.

[0098] Reference now Figure 5B , the method further includes the following task: forming a source region 522 and a drain region 523 (e.g., an nFET source region and a drain region or a pFET source region and a drain region) of a second partial GAA FET by, for example, epitaxial deposition. In the illustrated embodiment, the task of forming the source region 522 and the drain region 523 of the second partial GAA FET includes forming a source buffer layer 524 and a drain buffer layer 525 of undoped silicon, respectively. In one or more embodiments, the source buffer layer 524 and the drain buffer layer 525 of undoped silicon have a thickness of about 0 nanometers to about 4 nanometers (e.g., a thickness of about 1 nanometer to about 3 nanometers). In the illustrated embodiment, the source buffer layer 524 and the drain buffer layer 525 of undoped silicon are filled or substantially filled by the above reference Figure 5A The recessed portions 516 and 517 are formed by the described task of laterally etching the sacrificial layer 503. In addition, in the illustrated embodiment, the source buffer layer 524 and the drain buffer layer 525 are respectively formed along the vertical sidewalls 526 and 527 of the channel layer 504 and respectively along the exposed portions 528 and 529 of the substrate 505. In addition, in the illustrated embodiment, the outer edges 530 and 531 of the source buffer layer 524 and the drain buffer layer 525 are respectively vertical or substantially vertical along the fin 507.

[0099] In the illustrated embodiment, the task of forming the source region 522 and the drain region 523 further includes the task of forming a doped source region 532 and a doped drain region 533 adjacent to the source buffer layer 524 and the drain buffer layer 525, respectively. In one or more embodiments where the second portion GAA FET is an nFET, the doped source region 532 and the doped drain region 533 may include silicon phosphide (SiP), silicon carbon phosphide (SiCP), or any other suitable material known in the art. In one or more embodiments where the second portion GAA FET is a pFET, the doped source region 532 and the doped drain region 533 may include silicon germanium boron (SiGeB), silicon boron (SiB), silicon germanium tin boron (SiGeSnB), or any other suitable material known in the art.

[0100] Continue to refer FIG. 5A to FIG. 5B , the method further includes the task of removing the mask from the region of the first partial GAA FET and masking the region of the second partial GAA FET. The method further includes the task of etching the region of the one or more fins 506 of the first partial GAA FET that is not protected by the dummy gate 508 and the external sidewall spacers 510, 511. In one or more embodiments, the etching of the one or more fins 506 of the first partial GAA FET proceeds all the way down to or into the silicon substrate 505. In one or more embodiments, the etching of the one or more fins 506 of the first partial GAA FET is a vertical or substantially vertical recessed etch, and the recessed etch is aligned or substantially aligned with the outer surface 534, 535 of the outer sidewall spacers 510, 511, respectively.

[0101] In the illustrated embodiment, the method further includes the following tasks: forming a source region 536 and a drain region 537 (e.g., an nFET source region and a drain region or a pFET source region and a drain region) of the first partial GAA FET by, for example, epitaxial deposition. In the illustrated embodiment, the task of forming the source region 536 and the drain region 537 of the first partial GAA FET includes forming a source buffer layer 538 and a drain buffer layer 539 of undoped silicon, respectively. In one or more embodiments, the source buffer layer 538 and the drain buffer layer 539 of undoped silicon have a thickness of about 0 nanometers to about 4 nanometers (e.g., a thickness of about 1 nanometer to about 3 nanometers). In the illustrated embodiment, the source buffer layer 538 and the drain buffer layer 539 are formed along the vertical sidewalls 540 and 541 of the channel layer 504, respectively, along the vertical sidewalls 542 and 543 of the sacrificial layer 503, respectively, and along the exposed portions 544 and 545 of the substrate 505, respectively.

[0102] In the illustrated embodiment, the task of forming the source region 536 and the drain region 537 further includes the task of forming a doped source region 546 and a doped drain region 547 adjacent to the source buffer layer 538 and the drain buffer layer 539, respectively. In one or more embodiments where the first portion GAA FET is an nFET, the doped source region 546 and the doped drain region 547 may include SiP, SiCP, or any other suitable material known in the art. In one or more embodiments where the first portion GAA FET is a pFET, the doped source region 546 and the doped drain region 547 may include SiGeB, SiB, SiGeSnB, or any other suitable material known in the art.

[0103] Reference now Figure 5C , the method according to an embodiment of the present disclosure further includes the following task: annealing the source region 536 and the drain region 537 and the source region 522 and the drain region 523 of the first partial GAA FET and the second partial GAA FET, respectively, so that the source buffer layer 538 and the drain buffer layer 539 and the source buffer layer 524 and the drain buffer layer 525 are doped due to dopant diffusion.

[0104] Reference now Figure 5D , the method according to an embodiment of the present disclosure further includes the following tasks: depositing an interlayer dielectric (ILD) on each of the dummy gate stacks 508 and 509, performing chemical mechanical planarization (CMP) on the top of the dummy gate stacks 508 and 509, and then removing (e.g., by etching) the dummy gate stacks 508 and 509 to expose one or more fins 506 and 507 of each of the first partial GAA FET 501 and the second partial GAA FET 502. Continue to refer to Figure 5D The method further includes the following task: removing the sacrificial layer 503 (e.g., SiGe sacrificial layer 503) by wet or dry etching that is selective to the channel layer 504 (e.g., selective to the Si channel layer 504). In one or more embodiments, because the source region 522 and the drain region 523 and the source region 536 and the drain region 537 include Si material adjacent to the sacrificial layer 503, the selective etching of the sacrificial layer 503 will not etch into the source region 522 and the drain region 523 and the source region 536 and the drain region 537.

[0105] Continue to refer Figure 5DThe method further includes forming a gate dielectric layer 550 and then forming a metal layer 551 on the gate dielectric layer 550 by any one or more processes known in the art (e.g., atomic-layer deposition (ALD)) to form gate stacks 548 and 549 on the fins 506 and 507 of the first partial GAA FET 501 and the second partial GAA FET 502, respectively. During the task of forming the gate stacks 548 and 549, the gate dielectric layer 550 or a portion of the gate dielectric layer 550 fills the area where the sacrificial layer 503 is removed and forms dielectric separation regions 552 and dielectric separation regions 553 (e.g., the gate dielectric layer 550 or a portion of the gate dielectric layer 550 fills the area previously occupied by the sacrificial layer 503 and forms dielectric separation regions 552 and dielectric separation regions 553). A gate dielectric layer 550 is also formed above each of the one or more fins 506, 507 (e.g., the gate dielectric layer 550 is formed along the upper surface of the uppermost channel layer 504 in each of the fins 506, 507). In the illustrated embodiment, the gate dielectric layer 550 is formed uniformly or substantially uniformly on all exposed surfaces. Since the gate dielectric layer 550 or a portion of the gate dielectric layer 550 fills the area where the sacrificial layer 503 is removed, the metal layer 551 of the gate stack 548, 549 is not deposited into the area where the sacrificial layer 503 is removed. Therefore, after the task of forming the gate stack 548, 549, each of the fins 506, 507 includes a stack of two or more channel layers 504 (e.g., four channel layers 504) separated by dielectric separation regions 552, 553 (e.g., four dielectric separation regions 552, 553).

[0106] like Figure 5D As shown in FIG. 1 , after forming the gate stacks 548 and 549 of the first and second partial GAA FETs 501 and 502, the dielectric separation region 553 of the second partial GAA FET 502 has a shorter length than the dielectric separation region 552 of the first partial GAA FET 501. In the embodiment shown, the length L 1The outer edges 554 and 555 of each dielectric partition 552 of the first partial GAAFET 501 are defined to the inner surfaces 556 and 557 of the corresponding sidewall spacers 510 and 511 (e.g., the inner surfaces 556 and 557 of the upper sidewall spacers 510 and 511). In the illustrated embodiment, the outer edges 554 and 555 of each dielectric partition 552 are aligned or substantially aligned with the outer surfaces 534 and 535 of the corresponding sidewall spacers 510 and 511, so that the length L of each dielectric partition 552 is 1 / 4 of the dielectric partition 552. 1 is equal to or substantially equal to the width of the sidewall spacers 510 and 511. In addition, in the embodiment shown, the length L 2 The length L of the dielectric isolation region 553 of the second partial GAA FET 502 is defined from the outer edge 558, the outer edge 559 of each dielectric isolation region 553 to the inner surface 520, the inner surface 521 of the corresponding sidewall spacer 512, the corresponding sidewall spacer 513 (e.g., the inner surface 520, the inner surface 521 of the upper sidewall spacer 512, the upper sidewall spacer 513). 2 Depends on Figure 5A During the task shown in FIG. 5 , the sacrificial layer 503 is laterally etched to a depth D 1 In the illustrated embodiment, the length L of the dielectric separation region 552 of the first partial GAA FET 501 is 1 is greater than the length L of the dielectric separation region 553 of the second partial GAA FET 502 2 In one or more embodiments, the length L of the dielectric separation region 553 of the second portion GAAFET 502 is 2 It can be approximately 0 nanometers (e.g., outer edge 558, outer edge 559 of dielectric separation region 553 is aligned or substantially aligned with inner surface 520, inner surface 521 of corresponding sidewall spacer 512, corresponding sidewall spacer 513) to approximately 6 nanometers (e.g., approximately 0 nanometers to approximately 3 nanometers).

[0107] The method also includes completing the formation of a first partial GAA FET 501 and a second partial GAA FET 502 and a CMOS SoC 500 including the partial GAA FET 501 and the partial GAA FET 502 through tasks known in the art, including a CMP task of enabling gate metal only in the removed dummy gate area, followed by a task of contact formation, and a task of back-end-of-line (BEOL) formation.

[0108] In one or more embodiments, the method may include one or more tasks to implement the above reference Figures 1 to 4 For example, in one or more embodiments, the method may include the following tasks: laterally etching both the sacrificial layer 503 and the conductive channel layer 504 of the second portion GAA FET 502 (e.g., as shown in FIG. Figure 2 ). In one or more embodiments, the method may include the following tasks: forming sidewall spacers 510, sidewall spacers 511, and sidewall spacers 512 and sidewall spacers 513 having different widths for the first partial GAA FET 501 and the second partial GAA FET 502. In one or more embodiments, the method may include the following tasks: forming the sidewall spacers 510, sidewall spacers 511, and sidewall spacers 512 and sidewall spacers 513 so that the sidewall spacers 512 and sidewall spacers 513 of the second partial GAA FET 502 are relatively narrower than the sidewall spacers 510 and sidewall spacers 511 of the first partial GAA FET 501 (for example, as shown in FIG. 1 ). Figure 3 ). In one or more embodiments, the task of forming sidewall spacers 510, 511, and sidewall spacers 512, 513 having different widths may include forming sidewall spacers 510, 511, and sidewall spacers 512, 513 from materials suitable for subsequent thinning, such as (for example) nitride 1 deposition, followed by oxide deposition, followed by nitride 2 deposition, as is known in the art.

Claims

1. A complementary metal oxide semiconductor system on chip, comprising: A plurality of partially-all-around-gate field effect transistors, each of the plurality of partially-all-around-gate field effect transistors comprising: A fin comprising a stack of channel regions, the stack comprising at least a first channel region and a second channel region stacked on the first channel region; a source region and a drain region located on opposite sides of the fin; a dielectric separation region comprising a dielectric material between the first channel region and the second channel region; a gate stack located on the fin; and a pair of sidewall spacers on opposite sides of the gate stack, wherein a portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a corresponding one of the pair of sidewall spacers, and wherein the length of the portion of the dielectric separation region of one of the partially surrounding gate field effect transistors is different from the length of the portion of the dielectric separation region of another of the partially surrounding gate field effect transistors.

2. The complementary metal oxide semiconductor system on chip of claim 1 , wherein the length of the portion of the dielectric separation region of the one of the partially surrounding gate field effect transistors is less than the length of the portion of the dielectric separation region of the other of the partially surrounding gate field effect transistors. 3 . The complementary metal oxide semiconductor system on chip of claim 2 , wherein the length of the portion of the dielectric separation region of the one of the partial surround gate field effect transistors is 0 nanometers to 10 nanometers.

4. The complementary metal oxide semiconductor system on chip of claim 2, wherein the length of the portion of the dielectric separation region of the one of the partial surround gate field effect transistors is 0 nanometers to 6 nanometers.

5. The complementary metal oxide semiconductor system on chip of claim 2 , wherein the other of the partial surrounding gate field effect transistors has a high voltage threshold or a normal voltage threshold, and wherein a capacitance of the other of the partial surrounding gate field effect transistors is lower than a capacitance of the one of the partial surrounding gate field effect transistors.

6. The complementary metal oxide semiconductor system on chip of claim 2 , wherein the one of the partial surrounding gate field effect transistors has a low voltage threshold or an ultra-low voltage threshold, and wherein a resistance of the one of the partial surrounding gate field effect transistors is lower than a resistance of the other of the partial surrounding gate field effect transistors.

7. The complementary metal oxide semiconductor system on chip of claim 1, wherein the pair of sidewall spacers of the one of the partial all-around gate field effect transistors is thinner than the pair of sidewall spacers of the other of the partial all-around gate field effect transistors.

8. A field effect transistor comprising: A fin comprising a stack of channel regions, the stack comprising at least a first channel region and a second channel region stacked on the first channel region; a source region and a drain region located on opposite sides of the fin; a dielectric separation region comprising a dielectric material between the first channel region and the second channel region; a gate stack located on the fin; as well as a pair of sidewall spacers located on opposite sides of the gate stack, wherein an outer edge of the dielectric separation region is laterally located between an inner surface and an outer surface of a corresponding one of the pair of sidewall spacers, The gate stack includes a metal layer and a gate dielectric layer, and The level of the lower surface of the metal layer is higher than the level of the lower surface of the sidewall spacer. 9 . The field effect transistor of claim 8 , wherein a portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a corresponding one of the pair of sidewall spacers. 10 . The field effect transistor of claim 9 , wherein the length of the portion of the dielectric separation region is 0 nanometers to 10 nanometers.

11. The field effect transistor of claim 9, wherein the length of the portion of the dielectric separation region is 0 nanometers to 6 nanometers.

12. A method of manufacturing a complementary metal oxide semiconductor system on chip including a plurality of partial all-around gate field effect transistors, the method comprising: forming a first partial all-around gate field effect transistor of the plurality of partial all-around gate field effect transistors; as well as forming a second partial-all-around-gate field effect transistor of the plurality of partial-all-around-gate field effect transistors, Each of the first partial surround gate field effect transistor and the second partial surround gate field effect transistor comprises: A fin comprising a stack of channel regions, the stack comprising at least a first channel region and a second channel region stacked on the first channel region; a source region and a drain region located on opposite sides of the fin; a dielectric separation region comprising a dielectric material between the first channel region and the second channel region; a gate stack located on the fin; and a pair of sidewall spacers on opposite sides of the gate stack, wherein a portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a corresponding one of the pair of sidewall spacers, and wherein the length of the portion of the dielectric separation region of the first partially surround-gate field effect transistor is different from the length of the portion of the dielectric separation region of the second partially surround-gate field effect transistor.

13. The method of claim 12, wherein the length of the portion of the dielectric separation region of the second partially surrounding gate field effect transistor is less than the length of the portion of the dielectric separation region of the first partially surrounding gate field effect transistor.

14. The method of claim 13, wherein the first partial surrounding gate field effect transistor has a high voltage threshold or a normal voltage threshold, and a capacitance of the first partial surrounding gate field effect transistor is lower than a capacitance of the second partial surrounding gate field effect transistor.

15. The method of claim 13, wherein the second partial surrounding gate field effect transistor has a low voltage threshold or an ultra-low voltage threshold, and wherein a resistance of the second partial surrounding gate field effect transistor is lower than a resistance of the first partial surrounding gate field effect transistor.

16. The method of claim 13, wherein the length of the portion of the dielectric separation region of the second partial surround gate field effect transistor is 0 nanometers to 10 nanometers.

17. The method of claim 13, wherein the length of the portion of the dielectric separation region of the second partial surround gate field effect transistor is 0 nanometers to 6 nanometers.

18. The method of claim 12, wherein a length of the doped extension region of the first partial all-around-gate field effect transistor is the same as a length of the doped extension region of the second partial all-around-gate field effect transistor.

19. The method of claim 12, wherein the pair of sidewall spacers of the second partial surround-gate field effect transistor are thinner than the pair of sidewall spacers of the first partial surround-gate field effect transistor.

20. The method of claim 12, wherein forming the second partial all-around gate field effect transistor comprises: depositing a stack of alternating sacrificial layers and conductive channel layers on a silicon substrate; patterning and etching the stack to form at least one fin; forming a dummy gate stack on the at least one fin; forming outer sidewall spacers on opposite sides of the dummy gate stack; laterally etching opposite ends of each of the sacrificial layers; as well as A source region and a drain region are formed.

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