Computational optimization mechanisms for deep neural networks

Abstract

A device for facilitating computational optimization is disclosed. The device includes at least one processor for performing operations to implement a neural network, and computational logic for accelerating neural network computations.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes the development of systems and methods for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, some graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of the software and hardware of a SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order that the above-described features of the present embodiment can be understood in detail, the embodiments briefly summarized above may be described in more detail by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments and, therefore, should not be considered as limiting the scope thereof.

[0005] Figure 1 is a block diagram of a processing system according to an embodiment.

[0006] Figure 2 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0007] Figure 3 is a block diagram of a graphics processor, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores.

[0008] Figure 4 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments.

[0009] Figure 5 is a block diagram of the hardware logic of a graphics processor core, according to some embodiments.

[0010] Figures 6A-6B Thread execution logic including an array of processing elements employed in a graphics processor core is shown, according to some embodiments.

[0011] Figure 7 is a block diagram illustrating a graphics processor instruction format according to some embodiments.

[0012] Figure 8 is a block diagram of another embodiment of a graphics processor.

[0013] Figure 9A is a block diagram illustrating a graphics processor command format according to an embodiment.

[0014] Figure 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment.

[0015] Figure 10 An exemplary graphics software architecture for a data processing system is shown in accordance with some embodiments.

[0016] Figure 11A is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment.

[0017] Figure 11B A cross-sectional side view of an integrated circuit package assembly is shown in accordance with some embodiments.

[0018] Figure 12 is a block diagram illustrating an exemplary system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment.

[0019] Figures 13A-13B is a block diagram illustrating an exemplary graphics processor for use within a system on a chip (SoC) according to embodiments described herein.

[0020] Figures 14A-14B Additional exemplary graphics processor logic is shown according to embodiments described herein.

[0021] Figure 15 A machine learning software stack is shown, according to an embodiment.

[0022] Figures 16A-16B The layers of an exemplary deep neural network are shown.

[0023] Figure 17 An exemplary recurrent neural network is shown.

[0024] Figure 18Demonstrates the training and deployment of a deep neural network.

[0025] Figure 19 is a block diagram illustrating distributed learning.

[0026] Figure 20 A computing device employing a computing mechanism according to an embodiment is shown.

[0027] Figure 21 One embodiment of a graphics processing unit is shown.

[0028] Figure 22A and 22B A flow diagram of an embodiment for requesting a shader is shown.

[0029] Figure 23 One embodiment of quantization error is shown.

[0030] Figure 24 A flow chart illustrating one embodiment of a quantization process is shown.

[0031] Figure 25 Another embodiment of quantization error is shown.

[0032] Figure 26A An exemplary recurrent neural network is shown.

[0033] Figure 26B An exemplary long short-term memory network is shown.

[0034] Figure 27A An embodiment of an activation function is shown.

[0035] Figure 27B and 27F An embodiment of a computing architecture for enabling deep learning capabilities is shown.

[0036] Figure 28 A conventional method for processing high-resolution images is shown.

[0037] Figure 29 An embodiment for processing high-resolution images is shown.

[0038] Figure 30 Another embodiment for processing high-resolution images is shown.

[0039] Figure 31 is a flow chart illustrating one embodiment for processing high-resolution images.

[0040] Figure 32 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0041] Figures 33A-33D A parallel processor component according to an embodiment is shown.

[0042] Figures 34A-34B is a block diagram of a graphics multiprocessor according to an embodiment.

[0043] Figures 35A-35G An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors.

[0044] Figure 36 A graphics processing pipeline is shown according to an embodiment. DETAILED DESCRIPTION

[0045] Various embodiments are disclosed for optimizing computations at a graphics processor.

[0046] In the following description, numerous specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiments.

[0047] System Overview

[0048] Figure 1 1 is a block diagram of a processing system 100 according to an embodiment. In various embodiments, system 100 includes one or more processors 102 and one or more graphics processors 108, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0049] In one embodiment, system 100 may include or be incorporated into a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 100 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Processing system 100 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), be coupled to the wearable device, or be integrated into the wearable device. In some embodiments, processing system 100 is a television or set-top box device having one or more processors 102 and a graphical interface generated by one or more graphics processors 108.

[0050] In some embodiments, one or more processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform operations of the system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, the instruction set 109 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 107 can each process a different instruction set 109, which may include instructions for facilitating emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as a digital signal processor (DSP).

[0051] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among the components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherence techniques. Additionally, a register file 106 is included in the processor 102, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0052] In some embodiments, one or more processors 102 are coupled to one or more interface buses 110 that are used to transmit communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor(s) 102 include an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connections to I / O devices via a local I / O bus.

[0053] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, the memory device 120 may operate as system memory for the system 100, storing data 122 and instructions 121 for use when the one or more processors 102 execute applications or processes. The memory controller 116 is also coupled to an optional external graphics processor 112, which may communicate with the one or more graphics processors 108 in the processor 102 to perform graphics and media operations. In some embodiments, a display device 111 may be connected to the processor(s) 102. The display device 111 may be one or more of: an internal display device, such as in a mobile electronic device or laptop; or an external display device attached via a display interface (e.g., a display port, etc.). In one embodiment, the display device 111 may be a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0054] In some embodiments, the platform controller hub 130 enables peripheral devices to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., a hard drive, flash memory, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). The network controller 134 can enable network connectivity to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus 110. In one embodiment, the audio controller 146 is a multi-channel high-definition audio controller. In one embodiment, the system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. The platform controller hub 130 can also be connected to one or more Universal Serial Bus (USB) controllers 142 to connect input devices, such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

[0055] It will be appreciated that the illustrated system 100 is exemplary and non-limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 116 and the platform controller hub 130 may be integrated into a discrete external graphics processor, such as the external graphics processor 112. In one embodiment, the platform controller hub 130 and / or the memory controller 160 may be external to the one or more processors 102. For example, the system 100 may include the external memory controller 116 and the platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 102.

[0056] Figure 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A- 202N, an integrated memory controller 214 , and an integrated graphics processor 208 . Figure 2 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 200 may include additional cores up to and including additional core 202N represented by a dashed box. Processor cores 202A through 202N each include one or more internal cache units 204A through 204N. In some embodiments, each processor core may also have access to one or more shared cache units 206.

[0057] Internal cache units 204A to 204N and shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 206 and 204A to 204N.

[0058] In some embodiments, the processor 200 may further include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, the system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0059] In some embodiments, one or more of the processor cores 202A through 202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A through 202N during multithreaded processing. Additionally, the system agent core 210 may include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 202A through 202N and the graphics processor 208.

[0060] In some embodiments, processor 200 also includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 is coupled to a shared cache unit 206 and a system agent core 210, which includes one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 208.

[0061] In some embodiments, a ring-based interconnect 212 is used to couple the internal components of the processor 200. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 208 is coupled to the ring interconnect 212 via an I / O link 213.

[0062] Exemplary I / O link 213 represents at least one of a variety of I / O interconnects, including package I / O interconnects, that facilitate communication between various processor components and high-performance embedded memory modules 218 (e.g., eDRAM modules). In some embodiments, each of processor cores 202A through 202N and graphics processor 208 utilize embedded memory modules 218 as a shared last-level cache.

[0063] In some embodiments, the processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 200 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0064] Figure 3 is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0065] In some embodiments, the graphics processor 300 also includes a display controller 302, which is used to drive display output data to a display device 320. The display controller 302 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. The display device 320 can be an internal or external display device. In one embodiment, the display device 320 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding, decoding, or converting media codes to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) format (such as MPEG-2), Advanced Video Coding (AVC) format (such as H.264 / MPEG-4AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) format (such as JPEG, and Motion JPEG (MJPEG) format).

[0066] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0067] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed functional elements that perform various tasks within components and / or spawned execution threads to 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0068] In some embodiments, the media pipeline 316 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 306. In some embodiments, the media pipeline 316 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 315. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0069] In some embodiments, the 3D / media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and to store output data.

[0070] Graphics processing engine

[0071] Figure 4is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is Figure 3 One version of the GPE 310 is shown. Figure 4 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 3 4. The 3D pipeline 312 and the media pipeline 316 of the GPE 410 are shown in FIG. 4. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, and in at least one embodiment, separate media and / or graphics processors are coupled to the GPE 410.

[0072] In some embodiments, GPE 410 is coupled to or includes a command streamer 403, which provides a command stream to 3D pipeline 312 and / or media pipeline 316. In some embodiments, command streamer 403 is coupled to a memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 403 receives commands from memory and sends these commands to 3D pipeline 312 and / or media pipeline 316. The commands are instructions retrieved from a circular buffer storing commands for 3D pipeline 312 and media pipeline 316. In one embodiment, the circular buffer may further include a batch command buffer that stores multiple batches of commands. Commands for 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for 3D pipeline 312 and / or image data and memory objects for media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process the commands and data by executing operations through logic within their respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more graphics core blocks (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources, including general-purpose execution logic and graphics-specific execution logic for executing graphics and compute operations, as well as fixed-function texture processing logic and / or machine learning and artificial intelligence acceleration logic.

[0073] In various embodiments, the 3D pipeline 312 includes fixed-function logic and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. The multi-purpose execution logic (e.g., execution units) within the graphics core(s) 415A-414B of the graphics core array 414 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0074] In some embodiments, the graphics core array 414 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations. The general logic can be used with Figure 1 (multiple) processor cores 107 or Figure 2 The general logic within cores 202A to 202N in the FPGA performs processing operations in parallel or in combination.

[0075] Output data generated by threads executing on graphics core array 414 can be output to memory in unified return buffer (URB) 418. URB 418 can store data for multiple threads. In some embodiments, URB 418 can be used to send data between different threads executing on graphics core array 414. In some embodiments, URB 418 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared function logic 420.

[0076] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0077] Graphics core array 414 is coupled to shared function logic 420, which includes a number of resources shared between the graphics cores in the graphics core array. Shared functions within shared function logic 420 are hardware logic units that provide specialized, supplemental functionality to graphics core array 414. In various embodiments, shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 within shared function logic 420.

[0078] Shared functionality is implemented when demand for a given specialized functionality is insufficient to include it within graphics core array 414. Instead, a single instance of the specialized functionality is implemented as a separate entity within shared functionality logic 420 and shared among execution resources within graphics core array 414. The exact set of functionality shared between and included within graphics core array 414 varies between various embodiments. In some embodiments, specific shared functionality within shared functionality logic 420 that is widely used by graphics core array 414 may be included within shared functionality logic 416 within graphics core array 414. In various embodiments, shared functionality logic 416 within graphics core array 414 may include some or all of the logic within shared functionality logic 420. In one embodiment, all logic elements within shared functionality logic 420 may be duplicated within shared functionality logic 416 within graphics core array 414. In one embodiment, shared functionality logic 420 is implemented to support shared functionality logic 416 within graphics core array 414.

[0079] Figure 5 is a block diagram of the hardware logic of graphics processor core 500 according to some embodiments described herein. Figure 5 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. In some embodiments, the graphics processor core 500 shown includes Figure 4 4. A graphics processor core 500, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. An example of a graphics processor core 500 is one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics core 500 may include fixed function blocks 530 coupled to multiple sub-cores 501A to 501F (also referred to as sub-slices) including modular general purpose logic blocks and fixed function logic blocks.

[0080] In some embodiments, fixed function block 530 includes a geometry / fixed function pipeline 536, which may be shared by all sub-cores in graphics processor 500, for example, in low-performance and / or low-power graphics processor implementations. In various embodiments, geometry / fixed function pipeline 536 includes a 3D fixed function pipeline (e.g., as in Figure 3 and Figure 4 3D pipeline 312 in the video front end unit, thread spawner and thread dispatcher, and management such as Figure 4 The unified return buffer 418 and other unified return buffers are managed by a unified return buffer manager.

[0081] In one embodiment, the fixed function block 530 also includes a graphics SoC interface 537, a graphics microcontroller 538, and a media pipeline 539. The graphics SoC interface 537 provides an interface between the graphics core 500 and other processor cores within the system-on-chip integrated circuit. The graphics microcontroller 538 is a programmable subprocessor that can be configured to manage various functions of the graphics processor 500, including thread dispatching, scheduling, and pre-emption. The media pipeline 539 (e.g., Figure 3 and Figure 4 The media pipeline 316 includes logic for facilitating decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image data and video data. The media pipeline 539 implements media operations via requests to computational or sampling logic within the sub-cores 501 to 501F.

[0082] In one embodiment, the SoC interface 537 enables the graphics core 500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 537 may also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 500 and the CPU within the SoC. The SoC interface 537 may also implement power management controls for the graphics core 500 and enable interfaces between the clock domain of the graphics core 500 and other clock domains within the SoC. In one embodiment, the SoC interface 537 enables receiving command buffers from a command stream converter and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. These commands and instructions may be dispatched to the media pipeline 539 when media operations are to be performed, or to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipeline 536, geometry and fixed-function pipeline 514) when graphics processing operations are to be performed.

[0083] The graphics microcontroller 538 can be configured to perform various scheduling and management tasks for the graphics core 500. In one embodiment, the graphics microcontroller 538 can perform graphics and / or compute workload scheduling for the various graphics parallel engines within the execution unit (EU) arrays 502A to 502F, 504A to 504F within the sub-cores 501A to 501F. In this scheduling model, host software executing on the CPU core of the SoC including the graphics core 500 can submit a workload via one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, the graphics microcontroller 538 may also facilitate a low-power or idle state for the graphics core 500, thereby providing the graphics core 500 with the ability to save and restore registers within the graphics core 500 independently of transitioning across low-power states by the operating system and / or graphics driver software on the system.

[0084] The graphics core 500 may have more or fewer sub-cores 501A to 501F than shown, up to N modular sub-cores. For each set of N sub-cores, the graphics core 500 may also include shared function logic 510, shared memory and / or cache memory 512, geometry / fixed function pipelines 514, and additional fixed function logic 516 for accelerating various graphics and compute processing operations. The shared function logic 510 may include logic that can be shared by each of the N sub-cores within the graphics core 500. Figure 4 Logic units associated with the shared function logic 420 (e.g., sampler logic, math logic, and / or inter-thread communication logic). Shared memory and / or cache memory 512 can be a last-level cache for the set of N sub-cores 501A to 501F within the graphics core 500 and can also serve as shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 514 can be included within fixed function block 530 in place of geometry / fixed function pipeline 536 and can include the same or similar logic units.

[0085] In one embodiment, the graphics core 500 includes additional fixed-function logic 516, which may include various fixed-function acceleration logic for use by the graphics core 500. In one embodiment, the additional fixed-function logic 516 includes an additional geometry pipeline for use in positional-only shading. In positional-only shading, there are two geometry pipelines: a full geometry pipeline within the geometry / fixed-function pipelines 516, 536; and a picking pipeline, which is an additional geometry pipeline that may be included within the additional fixed-function logic 516. In one embodiment, the picking pipeline is a streamlined version of the full geometry pipeline. The full pipeline and the picking pipeline can execute different instances of the same application, each with a separate context. Positional-only shading can hide long picking runs for discarded triangles, thereby enabling shading to complete earlier in some instances. For example, and in one embodiment, the picking pipeline logic within the attachment fixed function logic 516 can execute position shaders in parallel with the main application and generally generate key results faster than the full pipeline because the full pipeline only fetches and shades the position attributes of the vertices without performing rasterization and rendering of pixels to the frame buffer. The picking pipeline can use the generated key results to calculate visibility information for all triangles, regardless of whether those triangles are picked. The full pipeline (which in this example may be referred to as a replay pipeline) can consume visibility information in order to skip picked triangles and thus only shade visible triangles that are ultimately passed to the rasterization stage.

[0086] In one embodiment, additional fixed-function logic 516 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementations including those for machine learning training or inference.

[0087] Each graphics sub-core 501A to 501F includes a set of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. Graphics sub-cores 501A to 501F include: multiple EU arrays 502A to 502F, 504A to 504F; thread dispatch and inter-thread communication (TD / IC) logic 503A to 503F; 3D (e.g., texture) samplers 505A to 505F; media samplers 506A to 506F; shader processors 507A to 507F; and shared local memory (SLM) 508A to 508F. Each of EU arrays 502A to 502F and 504A to 504F includes multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to service graphics, media, or compute operations, including graphics programs, media programs, or compute shader programs. TD / IC logic 503A to 503F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitates communication between threads executing on the execution units of the sub-core. 3D samplers 505A to 505F can read textures or other 3D graphics-related data into memory. 3D samplers can read texture data in different ways based on the configured sample state and the texture format associated with a given texture. Media samplers 506A to 506F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 501A to 501F can alternately include unified 3D and media samplers. Threads executing on execution units within each of sub-cores 501A- 501F may utilize shared local memory 508A- 508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0088] Execution Unit

[0089] Figures 6A to 6B Thread execution logic 600 is shown including an array of processing elements employed in a graphics processor core according to embodiments described herein. Figures 6A to 6B Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 6A An overview of thread execution logic 600 is shown, which may include a Figure 5 A variation of the hardware logic of each sub-core 501A to 501F. Figure 6B Exemplary internal details of an execution unit are shown.

[0090] like Figure 6A As shown in , in some embodiments, thread execution logic 600 includes a shader processor 602, a thread dispatcher 604, an instruction cache 606, a scalable execution unit array including a plurality of execution units 608A to 608N, a sampler 610, a data cache 612, and a data port 614. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 608A, 608B, 608C, 608D, up to any one of 608N-1 and 608N) based on the computational needs of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 600 includes one or more connections to a memory (such as system memory or cache memory) through the instruction cache 606, the data port 614, the sampler 610, and one or more of the execution unit arrays 608A to 608N. In some embodiments, each execution unit (e.g., 608A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A to 608N is scalable to include any number of individual execution units.

[0091] In some embodiments, execution units 608A to 608N are primarily used to execute shader programs. Shader processor 602 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 604. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units 608A to 608N. For example, the geometry pipeline can dispatch vertex processing, tessellation, or geometry processing threads to thread execution logic for processing. In some embodiments, thread dispatcher 604 can also handle runtime thread generation requests from executing shader programs.

[0092] In some embodiments, execution units 608A through 608N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of execution units 608A through 608N is capable of multi-issue single instruction, multiple data (SIMD), and multi-threaded operation enables an efficient execution environment in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock for pipelines with integer, single-precision floating-point, and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations. When waiting for data from memory or one of the shared functions, dependency logic within execution units 608A through 608N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program that includes a different vertex shader.

[0093] Each execution unit in execution units 608A-608N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes of an instruction. An execution lane is a logical unit that performs data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 608A-608N support integer and floating point data types.

[0094] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compressed data elements (data elements of double word length (DW) size), sixteen separate 16-bit compressed data elements (data elements of word length (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0095] In one embodiment, one or more execution units can be combined into fused execution units 609A to 609N, which have thread control logic (607A to 607N) common to the fused EUs. Multiple EUs can be fused into a single EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group can vary depending on the embodiment. In addition, different SIMD widths can be executed per EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 609A to 609N includes at least two execution units. For example, the fused execution unit 609A includes a first EU 608A, a second EU 608B, and thread control logic 607A common to the first EU 608A and the second EU 608B. The thread control logic 607A controls the threads executed on the fused graphics execution unit 609A, thereby allowing each EU within the fused execution unit 609A to 609N to execute using a common instruction pointer register.

[0096] One or more internal instruction caches (e.g., 606) are included in the thread execution circuitry 600 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 612) are included to cache thread data during thread execution. In some embodiments, a sampler 610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 610 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0097] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 600 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 602 is called to further calculate output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 602 then executes the pixel or fragment shader program provided by the application programming interface (API). To execute the shader program, the shader processor 602 dispatches a thread to an execution unit (e.g., 608A) via the thread dispatcher 604. In some embodiments, the shader processor 602 uses the texture sampling logic in the sampler 610 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0098] In some embodiments, the data port 614 provides a memory access mechanism for the thread execution logic 600 to output processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, the data port 614 includes or is coupled to one or more cache memories (e.g., data cache 612) to cache data via the data port for memory access.

[0099] like Figure 6B As shown in FIG, the graphics execution unit 608 may include an instruction fetch unit 637, a general register file array (GRF) 624, an architectural register file array (ARF) 626, a thread arbiter 622, an issue unit 630, a branch unit 632, a set of SIMD floating point units (FPUs) 634, and, in one embodiment, a set of dedicated integer SIMD ALUs 635. The GRF 624 and ARF 626 include the set of general register files and architectural register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 608. In one embodiment, per-thread architectural state is maintained in the ARF 626, while data used during thread execution is stored in the GRF 624. The execution state of each thread, including the instruction pointer of each thread, may be maintained in thread-specific registers in the ARF 626.

[0100] In one embodiment, graphics execution unit 608 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the target number of registers per execution unit, in which execution unit resources are divided across the logic used to execute multiple simultaneous threads.

[0101] In one embodiment, the graphics execution unit 608 can collectively issue multiple instructions, each of which can be a different instruction. The thread arbiter 622 of the graphics execution unit thread 608 can dispatch the instruction to one of the following for execution: the issue unit 630, the branch unit 642, or the SIMD FPU(s) 634. Each execution thread can access 128 general purpose registers within the GRF 624, each of which can store 32 bytes accessible as a SIMD 8-element vector with 32-bit data elements. In one embodiment, each execution unit thread accesses 4 kilobytes within the GRF 624, but embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In one embodiment, up to seven threads can execute simultaneously, but the number of threads per execution unit can vary depending on the embodiment. In an embodiment where seven threads can access 4 kilobytes, the GRF 624 can store a total of 28 kilobytes. Flexible addressing modes can allow multiple registers to be addressed together, efficiently creating wider registers or representing strided rectangular block data structures.

[0102] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by message passing send unit 630. In one embodiment, branch instructions are dispatched to a dedicated branch unit 632 to facilitate SIMD divergence and eventual convergence.

[0103] In one embodiment, graphics execution unit 608 includes one or more SIMD floating point units (FPUs) 634 for performing floating point operations. In one embodiment, FPU(s) 634 also support integer computations. In one embodiment, FPU(s) 634 can SIMD execute up to M 32-bit floating point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPU(s) provides extended math capabilities that support high-throughput transcendental math functions and double-precision 64-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 635 are also represented and may also be specifically optimized to perform operations associated with machine learning computations.

[0104] In one embodiment, an array of multiple instances of graphics execution unit 608 can be instantiated when graphics sub-cores are grouped (e.g., sub-slices). For scalability, the product architecture can choose the exact number of execution units per sub-core grouping. In one embodiment, execution unit 608 can execute instructions across multiple execution lanes. In further embodiments, each thread executed on graphics execution unit 608 executes on a different lane.

[0105] Figure 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are included only in a subset of instructions. In some embodiments, the instruction format 700 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0106] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 710. A 64-bit compact instruction format 730 may be used for some instructions based on the selected instruction, a number of instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 710.

[0107] For each format, the instruction opcode 712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, where the color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 714 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., blending). For instructions using the 128-bit instruction format 710, the execution size field 716 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 716 is not available for the 64-bit compact instruction format 730.

[0108] Some execution unit instructions have up to three operands, including two source operands (src0 720, src1 722) and a destination 718. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 724), where the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0109] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0110] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0111] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0112] In some embodiments, instructions are grouped based on the opcode 712 bit field to simplify opcode decoding 740. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares the five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, while the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 744 (e.g., call (call), jump (jmp)) includes instructions using the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 746 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) using the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel across data lanes. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot products.

[0113] Graphics pipeline

[0114] Figure 8 is a block diagram of another embodiment of a graphics processor 800 . Figure 8 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0115] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 800 via ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by command stream converter 803, which supplies instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0116] In some embodiments, command stream converter 803 directs the operation of vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 803. In some embodiments, vertex fetcher 805 provides vertex data to vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A and 852B via thread dispatcher 831.

[0117] In some embodiments, execution units 852A-852B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851, which is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0118] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 813 operates under the direction of the hull shader 811 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., hull shader 811, tessellator 813, domain shader 817) can be bypassed if tessellation is not used.

[0119] In some embodiments, the complete geometric object may be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A-852B, or may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0120] Before rasterization, the clipper 829 processes the vertex data. The clipper 829 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 873 in the render output pipeline 870 dispatches a pixel shader to convert the geometric objects into a per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth test component 873 and access the unrasterized vertex data via the outflow unit 823.

[0121] The graphics processor 800 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the graphics processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data port 856 to perform memory access and communicate with the processor's rendering output pipeline components. In some embodiments, sampler 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path. In one embodiment, texture cache 858 can also be configured as a sampler cache.

[0122] In some embodiments, the render output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated render cache 878 and depth cache 879 are also available in some embodiments. A pixel operation component 877 performs pixel-based operations on data, however, in some instances, pixel operations associated with 2D operations (e.g., using mixed bit-block image transfer) are performed by the 2D engine 841 or replaced at display time by the display controller 843 using overlapping display planes. In some embodiments, a shared L3 cache 875 can be used for all graphics components, allowing data to be shared without using main system memory.

[0123] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command stream converter 803. In some embodiments, the media pipeline 830 includes a separate command stream converter. In some embodiments, the video front end 834 processes the media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function for generating threads for dispatching to the thread execution logic 850 via the thread dispatcher 831.

[0124] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled to the graphics processor via the ring interconnect 802, or some other interconnect bus or mechanism. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0125] In certain embodiments, geometry pipeline 820 and media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any application programming interface (API). In certain embodiments, the driver software of the graphics processor converts the API dispatch dedicated to specific graphics or media library into a command that can be processed by the graphics processor. In certain embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group. In certain embodiments, support can also be provided for Microsoft's Direct3D library. In certain embodiments, the combination of these libraries can be supported. Support can also be provided for open source computer vision library (OpenCV). If the mapping from the pipeline of future API to the pipeline of graphics processor can be made, the future API with compatible 3D pipeline will also be supported.

[0126] Graphics pipeline programming

[0127] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. Figure 9ASolid-line boxes in show components that are typically included in a graphics command, while dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 9A The exemplary graphics processor command format 900 includes a data field for identifying the client 902, a command operation code (opcode) 904, and data for the command 906. Some commands also include a sub-opcode 905 and a command size 908.

[0128] In some embodiments, client 902 specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once the command is received by the client unit, the client unit reads the opcode 904 and the sub-opcode 905 (if any) to determine the operation to be performed. The client unit uses the information in the data field 906 to execute the command. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of the double word length.

[0129] Figure 9B The flowchart in FIG. 9 illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses versions of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these specific commands or command sequences. Furthermore, the commands may be issued as a batch of commands in a command sequence such that the graphics processor processes the command sequence at least partially simultaneously.

[0130] In some embodiments, graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, 3D pipeline 922 and media pipeline 924 are not operating simultaneously. A pipeline flush is performed to allow the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will halt command processing until the active rendering engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0131] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 913 is used. In some embodiments, a pipeline select command 913 is only required once in an execution context before issuing pipeline commands, unless the context is issuing commands for two pipelines. In some embodiments, a pipeline flush command 912 is required immediately before a pipeline switch via a pipeline select command 913.

[0132] In some embodiments, pipeline control commands 914 configure the graphics pipeline for operation and are used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0133] In some embodiments, return buffer status commands 916 are used to configure a set of return buffers for the corresponding pipeline to write data to. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer status 916 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0134] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 920 , the command sequence is tailored for either the 3D pipeline 922 starting at 3D pipeline state 930 or the media pipeline 924 starting at media pipeline state 940 .

[0135] The commands used to configure the 3D pipeline state 930 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0136] In some embodiments, the 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 932 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches the shader execution thread to the graphics processor execution unit.

[0137] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution in order to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on the 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. These operations may also include additional commands for controlling pixel shading and pixel backend operations.

[0138] In some embodiments, when performing media operations, the graphics processor command sequence 910 follows the media pipeline 924 path. Generally, the specific purpose and manner of programming the media pipeline 924 depends on the media or computational operation to be performed. During the media decoding process, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0139] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands for configuring the media pipeline state 940 is dispatched or placed into the command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0140] In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 942. Once the pipeline state is configured and media object commands 942 are queued, the media pipeline 924 is triggered via an execute 944 command or an equivalent execution event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0141] Graphics software architecture

[0142] Figure 10 An exemplary graphics software architecture for data processing system 1000 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. Graphics application 1010 and operating system 1020 each execute in system memory 1050 of the data processing system.

[0143] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0144] In some embodiments, operating system 1020 is from Microsoft Corporation The operating system 1020 may be a graphics API 1022, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation, or the application may precompile the shader. In some embodiments, during the compilation of the 3D graphics application 1010, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0145] In some embodiments, user-mode graphics driver 1026 includes a back-end shader compiler 1027 that converts shader instructions 1012 into a hardware-specific representation. When using the OpenGL API, shader instructions 1012 in the GLSL high-level language are passed to user-mode graphics driver 1026 for compilation. In some embodiments, user-mode graphics driver 1026 uses operating system kernel-mode functionality 1028 to communicate with kernel-mode graphics driver 1029. In some embodiments, kernel-mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions.

[0146] IP core implementation

[0147] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions representing the various logic within the processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0148] Figure 11A 1 is a block diagram illustrating an IP core development system 1100 that can be used to manufacture integrated circuits to perform operations according to an embodiment. The IP core development system 1100 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SoC integrated circuits). A design facility 1130 can generate a software simulation 1110 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 1115, lower-level designs at the logic or transistor levels can also be created, designed, or synthesized. Consequently, the specific details of the initial design and simulation can vary.

[0149] The RTL design 1115 or an equivalent solution can be further synthesized by the design facility into a hardware model 1120, which can be in hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 1150 or a wireless connection 1160. The manufacturing facility 1165 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0150] Figure 11BA cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein is shown. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes a plurality of hardware logic units 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least in part in configurable logic or fixed-function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each logic unit 1172, 1174 may be implemented within a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structure 1173 can be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the package substrate 1180 may include other suitable types of substrates. The package assembly 1170 can be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 can be coupled to the surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0151] In some embodiments, logic units 1172 and 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between logic units 1172 and 1174. Bridge 1182 may be a dense interconnect structure that provides routing for electrical signals. Bridge 1182 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuitry features may be formed on the bridge substrate to provide chip-to-chip connectivity between logic units 1172 and 1174.

[0152] Although two logic units 1172, 1174 and bridge 1182 are shown, the embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 1182 may be excluded when logic is included on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

[0153] Exemplary System-on-Chip Integrated Circuit

[0154] Figure 12 to Figure 1 FIG4 shows an exemplary integrated circuit and related graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0155] Figure 12 1 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may also include an image processor 1215 and / or a video processor 1220, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic, including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller. 2 S / I 2 The integrated circuit may also include a display device 1245 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 1265 to access SDRAM or SRAM memory devices. Some integrated circuits may also include an embedded security engine 1270.

[0156] 13A to 13B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 13A An exemplary graphics processor 1310 of a system-on-chip integrated circuit is shown that may be fabricated using one or more IP cores in accordance with an embodiment. Figure 13B An additional exemplary graphics processor 1340 is shown that may be fabricated using one or more IP cores for a system-on-chip integrated circuit according to an embodiment. Figure 13A Graphics processor 1310 is an example of a low-power graphics processor core. Figure 13B The graphics processor 1340 is an example of a higher performance graphics processor core. Each of the graphics processors 1310, 1340 may be Figure 12 A variant of the graphics processor 1210.

[0157] like Figure 13AAs shown in FIG, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A to 1315N (e.g., 1315A, 1315B, 1315C, 1315D, up to 1315N-1 and 1315N). The graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to perform the operations of the vertex shader program, while the one or more fragment processors 1315A to 1315N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 1315A to 1315N use the primitives and vertex data generated by the vertex processor 1305 to generate a frame buffer for display on the display device. In one embodiment, the fragment processor(s) 1315A through 1315N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0158] In addition, the graphics processor 1310 also includes one or more memory management units (MMUs) 1320A-1320B, one or more caches 1325A-1325B, and one or more circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mappings for the graphics processor 1310, including for the vertex processor 1305 and / or (multiple) fragment processors 1315A-1315N, and the virtual-to-physical address mappings can also reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B can communicate with the system, including those within the system. Figure 12 The graphics processor 1310 may be synchronized with other MMUs, including one or more MMUs associated with the one or more application processors 1205, the image processor 1215, and / or the video processor 1220, so that each processor 1205 to 1220 may participate in a shared or unified virtual memory system. In accordance with an embodiment, the one or more circuit interconnects 1330A to 1330B enable the graphics processor 1310 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0159] like Figure 13B As shown in FIG, the graphics processor 1340 includes Figure 13AThe one or more MMUs 1320A to 1320B, caches 1325A to 1325B, and circuit interconnects 1330A to 1330B of the graphics processor 1310. The graphics processor 1340 includes one or more shader cores 1355A to 1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F, all the way to 1355N-1 and 1355N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. In addition, the graphics processor 1340 includes an inter-core task manager 1345, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A to 1355N and a tiling unit 1358 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0160] FIG. 14A to FIG. 14B Additional exemplary graphics processor logic is shown according to embodiments described herein. Figure 14A A graphics core 1400 is shown, which may include Figure 12 The graphics processor 1210 may be Figure 13B Unified shader cores 1355A to 1355N in. Figure 14B A highly parallel general purpose graphics processing unit 1430 suitable for deployment on a multi-chip module is shown.

[0161] like Figure 14A, graphics core 1400 includes a shared instruction cache 1402, texture units 1418, and cache memory / shared memory 1420 that are common to execution resources within graphics core 1400. Graphics core 1400 may include multiple slices 1401A through 1401N or partitions for each core, and a graphics processor may include multiple instances of graphics core 1400. Slices 1401A through 1401N may include support logic including local instruction caches 1404A through 1404N, thread schedulers 1406A through 1406N, thread dispatchers 1408A through 1408N, and a set of registers 1410A. To perform logical operations, slices 1401A to 1401N may include a set of additional function units (AFUs 1412A to 1412N), floating point units (FPUs 1414A to 1414N), integer arithmetic logic units (ALUs 1416 to 1416N), addressing computation units (ACUs 1413A to 1413N), double-precision floating point units (DPFPUs 1415A to 1415N), and matrix processing units (MPUs 1417A to 1417N).

[0162] Some of these computing units operate with specific precision. For example, FPUs 1414A to 1414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1415A to 1415N perform double-precision (64-bit) floating-point operations. ALUs 1416A to 1416N can perform variable-precision integer operations with 8-bit precision, 16-bit precision, and 32-bit precision, and can be configured for mixed-precision operations. MPUs 1417A to 1417N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. MPUs 1417 to 1417N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling general matrix-to-matrix multiplication (GEMM) that supports acceleration. AFUs 1412A to 1412N can perform additional logical operations that are not supported by floating-point units or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0163] like Figure 14BAs shown in , a general purpose processing unit (GPGPU) 1430 can be configured to enable highly parallel computing operations to be performed by an array of graphics processing units. In addition, GPGPU 1430 can be directly linked to other instances of GPGPU to create a multi-GPU cluster, thereby increasing the training speed of deep neural networks in particular. GPGPU 1430 includes a host interface 1432 for implementing a connection with a host processor. In one embodiment, host interface 1432 is a PCI Express interface. However, the host interface can also be a supplier-specific communication interface or communication structure. GPGPU 1430 receives commands from the host processor and uses a global scheduler 1434 to distribute the execution threads associated with those commands to a group of computing clusters 1436A to 1436H. Computing clusters 1436A to 1436H share cache memory 1438. Cache memory 1438 can act as a higher-level cache of the cache memory within computing clusters 1436A to 1436H.

[0164] GPGPU 1430 includes memory 1434A-1434B coupled to compute clusters 1436A-1436H via a set of memory controllers 1442A-1442B. In various embodiments, memory 1434A-1434B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0165] In one embodiment, computing clusters 1436A through 1436H each include a set of graphics cores, such as Figure 14A The graphics core 1400 may include multiple types of integer logic units and floating-point logic units that can perform computational operations within a range of precision, including those suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating-point units in each of the compute clusters 1436A through 1436H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0166] Multiple instances of GPGPU 1430 can be configured to operate as a compute cluster. The computing mechanisms used by the compute cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 1430 communicate via a host interface 1432. In one embodiment, GPGPU 1430 includes an I / O hub 1439 that couples GPGPU 1430 to a GPU link 1440 that enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1430. In one embodiment, GPU link 1440 is coupled to a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1430 are located in separate data processing systems and communicate via a network device accessible via host interface 1432. In one embodiment, GPU link 1440 can be configured to enable connections to a host processor in addition to or as an alternative to host interface 1432.

[0167] While the illustrated configuration of GPGPU 1430 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 1430 that can be configured to be deployed within a high-performance or low-power inference platform. In the inference configuration, GPGPU 1430 includes fewer of compute clusters 1436A-1436H than in the training configuration. Additionally, the memory technology associated with memories 1434A-1434B can differ between the inference configuration and the training configuration, with higher-bandwidth memory technology being dedicated to the training configuration. In one embodiment, the inference configuration of GPGPU 1430 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations of a deployed neural network.

[0168] Machine Learning Overview

[0169] Machine learning algorithms are algorithms that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0170] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights"), which are respectively associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0171] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for the instance; an error signal representing the difference between the output and the labeled output is calculated; and as the error signal is propagated back through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0172] The accuracy of a machine learning algorithm can be greatly affected by the quality of the dataset used to train it. The training process can be computationally intensive and can require a significant amount of time on conventional general-purpose processors. Consequently, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0173] Figure 151500 is a generalized diagram of a machine learning software stack. Machine learning applications 1502 can be configured to train a neural network using a training dataset or to use a trained deep neural network to implement machine intelligence. Machine learning applications 1502 can include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. Machine learning applications 1502 can implement any type of machine intelligence, including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0174] Hardware acceleration for machine learning applications 1502 can be implemented via a machine learning framework 1504. The machine learning framework 1504 can provide a library of machine learning primitives. Machine learning primitives are basic operations that machine learning algorithms typically perform. Without the machine learning framework 1504, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning framework 1504 to perform the necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 1504 can also provide primitives for implementing basic linear algebra subroutines, such as matrix and vector operations, that are performed by many machine learning algorithms.

[0175] The machine learning framework 1504 can process input data received from the machine learning application 1502 and generate appropriate input to the computation framework 1506. The computation framework 1506 can abstract the underlying instructions provided to the GPGPU driver 1508 to enable the machine learning framework 1504 to take advantage of hardware acceleration via the GPGPU hardware 1510 without requiring the machine learning framework 1504 to be intimately familiar with the architecture of the GPGPU hardware 1510. In addition, the computation framework 1506 can implement hardware acceleration for the machine learning framework 1504 across multiple types and generations of GPGPU hardware 1510.

[0176] Machine Learning Neural Network Implementation

[0177] The computing architecture provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly well-suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0178] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network used to process data with a known, grid-like topology (e.g., image data). CNNs are therefore commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The calculations used in a CNN involve applying a mathematical operation called convolution to each filter to produce the output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function involved in the convolution can be called the input, while the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted through a training process for the neural network.

[0179] Recurrent neural networks (RNNs) are a type of feedforward neural network that includes feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of the neural network. The architecture of RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at future times, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data, which can be composed.

[0180] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiment described herein, and that the concepts presented can generally be applied to deep neural networks and machine learning techniques in general.

[0181] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0182] The deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0183] Once a neural network is structured, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of error is a common method for training neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as stochastic gradient descent) to update the weights of the neural network.

[0184] Figures 16A-16B Shows an example convolutional neural network. Figure 16A Show the various layers in CNN. Figure 16A As shown in , an exemplary CNN for modeling image processing can receive an input 1602 that describes the red, green, and blue (RGB) components of an input image. The input 1602 can be processed by multiple convolutional layers (e.g., a first convolutional layer 1604, a second convolutional layer 1606). Optionally, the outputs from the multiple convolutional layers can be processed by a set of fully connected layers 1608. The neurons in the fully connected layer have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The outputs from the fully connected layer 1608 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activation function within the fully connected layer 1608. Not all CNN implementations use the fully connected layer 1608. For example, in some implementations, the second convolutional layer 1606 can generate the output of the CNN.

[0185] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1608. Traditional neural network layers are fully connected so that every output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0186] Figure 16B Exemplary computational stages within a convolutional layer of a CNN are shown. Input 1612 to a convolutional layer of the CNN can be processed in three stages within a convolutional layer 1614. These three stages can include a convolution stage 1616, a detector stage 1618, and a pooling stage 1620. Convolutional layer 1614 can then output data to a subsequent convolutional layer. The last convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN.

[0187] Several convolutions are performed in parallel in the convolution stage 1616 to produce a set of linear activation functions. The convolution stage 1616 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function connected to a specific region in the input (e.g., a neuron), which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the neuron's weight and the region in the local input (to which the neuron is connected). The output from the convolution stage 1616 defines a set of linear activation functions that are processed by successive stages of the convolution layer 1614.

[0188] The linear activation function may be processed by the detector stage 1618. In the detector stage 1618, each linear activation function is processed by a nonlinear activation function. Nonlinear activation functions increase the nonlinear nature of the overall network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions may be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x), such that the activation function is thresholded to zero.

[0189] The pooling stage 1620 uses a pooling function that replaces the output of the second convolutional layer 1606 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a slight translation to the input does not change the pooled output. The invariance of local translation can be useful when the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 1620, including maximum pooling, average pooling, and L2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolution stage with an increased stride relative to the previous convolution stage.

[0190] The output from the convolutional layer 1614 may then be processed by the next layer 1622. The next layer 1622 may be an additional convolutional layer or one of the fully connected layers 1608. For example, Figure 16A The first convolutional layer 1604 can output to the second convolutional layer 1606, and the second convolutional layer can output to the first layer in the fully connected layer 1608.

[0191] Figure 17 An exemplary recurrent neural network is shown. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The shown RNN 1700 can be described as having the following: an input layer 1702, which receives an input vector; a hidden layer 1704, which implements a recursive function; a feedback mechanism 1705, which implements a 'memory' of previous states; and an output layer 1706, which outputs a result. RNN 1700 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1705. For a given time step, the state of the hidden layer 1704 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1704. The second input (x2) can be processed by the hidden layer 1704 using the state information determined during the processing of the initial input (x1). The given state can be calculated as s t =f(Ux t +Ws t-1), where U and W are parameter matrices. Function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x) = max(0, x). However, the specific mathematical function used in hidden layer 1704 may vary depending on the specific implementation details of RNN 1700.

[0192] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary to process longer language sequences. A variant of CNN is the convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0193] Figure 18 Demonstrates the training and deployment of a deep neural network. Once a given network has been structured for a task, the neural network is trained using a training dataset 1802. Various training frameworks have been developed to enable hardware acceleration of the training process. For example, Figure 15 The machine learning framework 1504 can be configured as a training framework 1804. The training framework 1804 can be linked to an untrained neural network 1806 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1808. To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. The training cycle is then executed in a supervised or unsupervised manner.

[0194] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training dataset 1802 includes inputs paired with expected outputs for those inputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then backpropagated through the system. The training framework 1804 can be adjusted to adjust the weights of the untrained neural network 1806. The training framework 1804 can provide tools for monitoring the extent to which the untrained neural network 1806 is converging to a model suitable for generating the correct answer based on the known input data. The training process occurs iteratively as the network's weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1808. The trained neural network 1808 can then be deployed to implement any number of machine learning operations.

[0195] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training data set 1802 will include input data without any associated output data. The untrained neural network 1806 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1807 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input data set that deviate from the normal pattern of the data.

[0196] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1802 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1808 to adapt to new data 1812 without forgetting the knowledge embedded in the network during initial training.

[0197] The training process for particularly deep neural networks, whether supervised or unsupervised, can be too computationally intensive for a single compute node. The training process can be accelerated by using a distributed network of compute nodes rather than a single compute node.

[0198] Figure 19is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more general-purpose processing nodes. As shown, distributed learning can perform model parallelism 1902, data parallelism 1904, or a combination of model and data parallelism 1904.

[0199] In model parallelization 1902, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelization include the ability to scale to extremely large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks, where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelization can be particularly useful in performing unsupervised training of large neural networks.

[0200] In data parallelization 1904, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different methods for data parallelization are possible, data parallel training methods all require a technique for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are passed instead of passing parameters from the nodes to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and passed between nodes.

[0201] For example, combined model and data parallelism 1906 can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0202] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0203] Example Machine Learning Applications

[0204] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than were previously feasible to train computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0205] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0206] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has replaced the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0207] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0208] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training, while deployed machine learning (e.g., inference) platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0209] Figure 20An embodiment of a computing device 2000 employing a computing optimization (computing) mechanism is shown. The computing device 2000 (e.g., a smart wearable device, a virtual reality (VR) device, a head-mounted display (HMD), a mobile computer, an Internet of Things (IoT) device, a laptop computer, a desktop computer, a server computer, etc.) can be connected to Figure 1 The data processing system 100 is the same as that of FIG. 1 , and therefore for the sake of brevity, clarity, and ease of understanding, the above references Figure 1-19 Many of the details set forth are not discussed further or repeated below. As shown, in one embodiment, computing device 2000 is shown as a host computing mechanism 2010 .

[0210] As shown, in one embodiment, the computing mechanism 2010 may be hosted by the graphics driver 2016. However, in other embodiments, the computing mechanism 2014 may be hosted solely in the GPU 2010. In still other embodiments, the computing mechanism 2010 may be hosted by or part of the firmware of the central processing unit ("GPU" or "application processor") 2012. For the sake of brevity, clarity, and ease of understanding, throughout the remainder of this document, the computing mechanism 2010 may be discussed as part of the graphics driver 616; however, embodiments are not limited in this regard.

[0211] In yet another embodiment, the computer mechanism 2010 may be hosted as software or firmware logic by the operating system 2006. In yet further embodiments, the computer mechanism 2010 may be partially and simultaneously hosted by multiple components of the computing device 2000, such as one or more of the graphics driver 2016, GPU 2014, GPU firmware, CPU 2012, CPU firmware, operating system 2006, etc. It is contemplated that the computer mechanism 2010 or one or more of its components may be implemented as hardware, software, and / or firmware.

[0212] Throughout this document, the term "user" may be referred to interchangeably as "viewer," "observer," "person," "individual," "end-user," etc. It should be noted that throughout this document, terms such as "graphics domain" may be referred to interchangeably with "graphics processing unit," "graphics processor," or simply "GPU," and similarly, "CPU domain" or "host domain" may be referred to interchangeably with "computer processing unit," "application processor," or simply "CPU."

[0213] The computing device 2000 may include any number and type of communication devices, such as large computing systems such as server computers, desktop computers, etc., and may further include set-top boxes (e.g., Internet-based cable TV set-top boxes, etc.), devices based on the Global Positioning System (GPS), etc. The computing device 2000 may include mobile computing devices used as communication devices, such as cellular phones including smartphones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart TVs, TV platforms, wearable devices (e.g., glasses, watches, bracelets, smart cards, jewelry, clothing, etc.), media players, etc. For example, in one embodiment, the computing device 2000 may include a mobile computing device that employs a computer platform that hosts an integrated circuit ("IC") such as a system on a chip ("SoC" or "SOC") that integrates various hardware and / or software components of the computing device 2000 on a single chip.

[0214] As shown, in one embodiment, the computing device 2000 may include any number and types of hardware and / or software components, such as (but not limited to) a GPU 2014, a graphics driver (also referred to as a "GPU driver," "graphics driver logic," "driver logic," user-mode driver (UMD), UMD, user-mode driver framework (UMDF), UMDF, or simply "driver") 616, a CPU 2012, memory 2008, network devices, drivers, etc., and input / output (I / O) sources 2004 such as a touch screen, touch panel, touchpad, a virtual or conventional keyboard, a virtual or conventional mouse, ports, connectors, etc.

[0215] The computing device 2000 may include an operating system (OS) 2006 that serves as an interface between the hardware and / or physical resources of the computing device 2000 and a user. It is contemplated that the CPU 2012 may include one or more processors, such as Figure 1 (multiple) processors 102, and GPU 2014 may include one or more graphics processors (or multiple processors).

[0216] It should be noted that throughout this document, terms such as "node," "computing node," "server," "server device," "cloud computer," "cloud server," "cloud server computer," "machine," "host," "device," "computing device," "computer," "computing system," etc., may be used interchangeably. It should be further noted that throughout this document, terms such as "application," "software application," "program," "software program," "package," "software software package," etc., may be used interchangeably. Also, throughout this document, terms such as "job," "input," "request," "message," etc., may be used interchangeably.

[0217] It is foreseeable and as reference Figure 1-1 As further described, some of the processes in the graphics pipeline described above are implemented in software, while others are implemented in hardware. The graphics pipeline can be implemented in a graphics coprocessor design, wherein CPU 2012 is designed to work with GPU 2014, which can be included in or co-located with CPU 2012. In one embodiment, GPU 2014 can employ any number and type of conventional software and hardware logic for performing conventional functions related to graphics rendering, as well as novel software and hardware logic for executing any number and type of instructions.

[0218] As described above, the memory 2008 may include random access memory (RAM) including an application database with object information. Figure 1 The memory hub 105 of the CPU 2012 can access data in the RAM and forward it to the GPU 2014 for graphics pipeline processing. The RAM may include double data rate RAM (DDR RAM), extended data output RAM (EDO RAM), etc. The CPU 2012 interacts with the hardware graphics pipeline to share graphics pipeline functions.

[0219] The processed data is stored in a buffer of the hardware graphics pipeline, and state information is stored in memory 2008. The resulting image is then passed to an I / O source 2004, such as a display component for displaying the image. It is contemplated that the display device may be any type of display device for displaying information to a user, such as a cathode ray tube (CRT), a thin film transistor (TFT), a liquid crystal display (LCD), an organic light emitting diode (OLED) array, and the like.

[0220] The memory 2008 may include a pre-allocated area of ​​a buffer (e.g., a frame buffer); however, it will be understood by those skilled in the art that embodiments are not limited thereto and any memory accessible to the lower level graphics pipeline may be used. The computing device 2000 may further include a pre-allocated area of ​​a buffer (e.g., a frame buffer); however, it will be understood by those skilled in the art that embodiments are not limited thereto and any memory accessible to the lower level graphics pipeline may be used. Figure 1 The input / output (I / O) control hub (ICH) 107 referenced in the specification serves as one or more I / O sources 2004, etc.

[0221] CPU 2012 may include one or more processors for executing instructions to perform any software routines implemented by the computing system. Instructions often involve some operation performed on data. Both data and instructions may be stored in system memory 2008 and any associated caches. Caches are typically designed to have lower latency than system memory 2008; for example, caches may be integrated onto the same silicon chip(s) as the processor(s) and / or constructed with faster static RAM (SRAM) cells, while system memory 2008 may be constructed with slower dynamic RAM (DRAM) cells. By tending to store more frequently used instructions and data in caches as opposed to system memory 2008, the overall performance efficiency of computing device 2000 is improved. It is contemplated that in some embodiments, GPU 2014 may exist as part of CPU 2012 (such as part of a physical CPU package), in which case memory 2008 may be shared by CPU 2012 and GPU 2014 or kept separate.

[0222] The system memory 2008 may be available to other components within the computing device 2000. For example, any data (e.g., input graphics data) received from various interfaces to the computing device 2000 (e.g., keyboard and mouse, printer port, local area network (LAN) port, modem port, etc.) or any data retrieved from the internal storage elements of the computing device 2000 (e.g., hard drive) is often temporarily queued into the system memory 2008 before being processed by one or more processors in the execution of software programs. Similarly, data that the software programs determine should be sent from the computing device 2000 to an external entity or stored in an internal storage element through one of the computing system interfaces is often temporarily queued in the system memory 2008 before it is transmitted or stored.

[0223] Further, for example, the ICH may be used to ensure that such data is properly transferred between system memory 2008 and its appropriate corresponding computing system interface (and internal storage devices, if the computing system is so designed) and may have bidirectional point-to-point links between itself and the illustrated I / O sources / devices 2004. Similarly, the MCH may be used to manage multiple competing requests for access to system memory 2008 between the CPU 2012 and GPU 2014, interfaces, and internal storage elements, which may occur close in time with each other.

[0224] The I / O sources 2004 may include one or more I / O devices implemented to transmit data to and / or from the computing device 2000 (e.g., a network adapter); or for large-scale non-volatile storage within the computing device 2000 (e.g., a hard drive). User input devices including alphanumeric and other keys may be used to communicate information and command selections to the GPU 2014. Another type of user input device is a cursor control, such as a mouse, trackball, touch screen, touchpad, or cursor direction keys, for communicating direction information and command selections to the GPU 2014 and controlling cursor movement on a display device. The camera and microphone array of the computing device 2000 may be used to observe gestures, record audio and video, and receive and transmit visual and audio commands.

[0225] The computing device 2000 may further include (multiple) network interfaces to provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., 3rd generation (3G), 4th generation (4G), etc.), an intranet, the Internet, etc. The (multiple) network interfaces may include, for example, a wireless network interface having an antenna, which may represent one or more antennas. The (multiple) network interfaces may also include, for example, a wired network interface for communicating with a remote device via a network cable, such as an Ethernet cable, a coaxial cable, an optical cable, a serial cable, or a parallel cable.

[0226] The network interface(s) may provide access to a LAN, for example, by conforming to the IEEE 802.11b and / or IEEE 802.11g standards, and / or the wireless network interface may provide access to a personal area network, for example, by conforming to the Bluetooth standard. Other wireless network interfaces and / or protocols (including previous and subsequent versions of the standards) may also be supported. In addition to or in lieu of communication via the wireless LAN standard, the network interface(s) may provide wireless communication using, for example, a Time Division Multiple Access (TDMA) protocol, a Global System for Mobile Communications (GSM) protocol, a Code Division Multiple Access (CDMA) protocol, and / or any other type of wireless communication protocol.

[0227] The network interface(s) may include one or more communication interfaces, such as a modem, a network interface card, or other well-known interface devices, such as those used to couple to Ethernet, token ring, or other types of physical wired or wireless attachments in order to provide a communication link to support, for example, a LAN or WAN. In this way, the computer system may also be coupled to a number of peripheral devices, clients, control surfaces, consoles, or servers via conventional network infrastructure (e.g., including an intranet or the Internet).

[0228] Should be understood that, for some embodiments, it can be preferred to have less or more systems equipped with than the example described above.Therefore, depending on numerous factors, such as price constraints, performance requirements, technological improvements or other situations, the configuration of computing device 2000 can change along with embodiment.The example of electronic equipment or computer system 2000 can include, but is not limited to: mobile device, personal digital assistant, mobile computing device, smart phone, cellular phone, handheld device, one-way pager, two-way pager, message transceiver, computer, personal computer (PC), desktop computer, laptop computer, notebook computer, handheld computer, tablet computer, server, server array or server farm, web server, network server, internet server, workstation, minicomputer, mainframe computer, supercomputer, network device, web device, distributed computing system, multiprocessor system, system based on processor, consumer electronic product, programmable consumer electronic product, TV, digital television, set-top box, wireless access point, base station, user station, mobile user center, radio network controller, router, hub, gateway, bridge, switch, machine or the combination of above-mentioned.

[0229] Embodiments may be implemented as any one or a combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and / or a field programmable gate array (FPGA). Throughout this document, the terms "logic," "module," "component," "engine," "mechanism," "tool," "circuit," and "circuitry" are referenced interchangeably and may include, by way of example, software, hardware, firmware, or any combination thereof.

[0230] Embodiments may be provided, for example, as a computer program product, which may include one or more machine-readable media having machine-executable instructions stored thereon, which, when executed by one or more machines (such as computers, computer networks, or other electronic devices), may cause the one or more machines to perform operations according to the embodiments described herein. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disk read-only memory) and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable programmable read-only memory), magnetic or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0231] Furthermore, embodiments may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communications link (e.g., a modem and / or a network connection) by means of one or more data signals embodied in and / or modulated by a carrier wave or other propagation medium.

[0232] According to one embodiment, the computing mechanism 2010 may be implemented to perform hardware acceleration of common graph-based algorithms, such as for neural networks, and register allocation for the GPU 2014. In such an embodiment, acceleration is achieved by compilation at the GPU 2014 without synchronization with the CPU 2012. Figure 21 One embodiment of a graphics processing unit 2014 is shown that includes a computing mechanism 2010 that includes a compilation unit (CU) 2101 and a graphics processing unit (GrPU) 2102 .

[0233] In one embodiment, GrPU 2102 is implemented to accelerate general graph-based algorithms and works with CU2101 to compile shader kernels at GPU 2014. In such an embodiment, GrPU 2102 includes local memory for storing one or more graph representations and supports both adjacency list and matrix representations. In a further embodiment, the local memory can be reconfigured to optimize the current representation type. In another embodiment, in order to speed up graph traversal, GrPU2102 can support multiple function pointers / threads to enable traversal of multiple graphs at the same time. For example, when providing a memory request for the next node of graph A, GrPU 2102 can switch to performing calculations for graph B. In addition, SIMD support is also included to perform similar operations on multiple nodes within the same graph at the same time.

[0234] According to one embodiment, the CU 2101 interacts with the GrPU 2102 to obtain compiled portions of the utilization graph (e.g., graph shading for register allocation). In further embodiments, shader requests may be received at the CU 2101 from the CPU 2012 (e.g., a driver or application) or from other components of the GPU 2014. In further embodiments, in addition to servicing the CU 2101, the GrPU 2102 may also be accessed from another subunit within the GPU 2014 or from the CPU 2012. Thus, shaders may be optimized for specific runtime scenarios, such as performing scene graph analysis and processing neural networks.

[0235] In one embodiment, the CU 2101 and the GrPU 2102 can be implemented as a feedback loop. For example, the driver can send a request for scene graph analysis to the GrPU 2102. The GrPU 2102 can detect during analysis that the shader of drawing B can be optimized when a certain condition is met in drawing A. If the condition is met, the GrPU 2102 can send a compilation request to the CU 2101, which in turn calls back to the GrPU 2102 to assist with compilation.

[0236] When used for shader compilation, optimized shaders can be requested using one of two methods. The first method involves a direct request from the CPU. Figure 22A 2 is a flow chart illustrating one embodiment of a direct shader request. At processing block 2203, the CPU sends a command to the GPU to execute the shader operation. At processing block 2204, the CPU detects one or more conditions indicating the possibility of a target rendering optimization. For example, one such condition may indicate a situation where a shader can be simplified using a particular blend state. In one embodiment, the condition may alternatively be programmed directly by the CPU (e.g., via a graphics driver or application).

[0237] At processing block 2205, the original shader request is sent to the GPU. At processing block 2206, the optimized shader request is transmitted to CU 2101. At processing block 2207, CU 2101 compiles the shader. Subsequently, the GPU begins target drawing (processing block 2208). At decision block 2209, a determination is made as to whether the optimized shader is ready. If so, the optimized shader is used (processing block 2210). Otherwise, the original shader is used. Therefore, if compilation is completed before the relevant drawing, the optimized shader is used.

[0238] A second approach may include indirect requests, where compilation is automatically generated from the GPU. Figure 22B 22 is a flow chart illustrating an embodiment of an indirect shader request. At processing block 2203, the CPU sends a command to the GPU to perform the shader operation. At processing block 2212, the CPU specifies a condition indicating the possibility of target drawing optimization. At processing block 2213, the GPU receives the conditional requirement. At processing block 2214, the GPU detects that the condition has been met and sends a shader request for an optimized shader without CPU intervention. At processing block 2215, the CU 2101 receives the request and compiles the shader (processing block 2216). In this embodiment, the condition may include that the GPU detects that all writes to a surface are zero and that subsequent drawing will be sampled from that surface. Therefore, the GPU issues a request to the CU 2101 to create an optimized shader that replaces texture reads with constant zeros. Subsequently, as described above with respect to Figure 22A Blocks 2208-2211 are processed in the manner discussed above. In this embodiment, creating optimized shaders without the CU 701 would require sending information back to the CPU, compiling on the CPU, and uploading the optimized shaders back to the GPU. This overhead would likely make optimization impractical.

[0239] In another embodiment, a computing mechanism 2010 can be implemented to perform quantization of a deep neural network. Quantization is implemented to reduce file size by storing the minimum and maximum values ​​of each network layer, and then compressing each floating-point value into an integer representing the closest real number in a linear set within the range. Quantization also reduces the computing resources required to perform inference calculations. Most deep neural networks are trained using 32-bit floating-point (FP32) numbers, which have 232 discrete values ​​that can represent numbers approximately in the range [-2128, +2128]. However, this representation does not uniformly distribute precision within this range. For example, numbers closer to zero have higher precision (lower quantization error), while numbers farther from zero have lower precision (higher quantization error).

[0240] Another option is to use a 32-bit fixed-point representation, which uses 232 discrete values ​​to represent numbers in the approximate range [-231, +231]. However, this representation has the same quantization error over the entire range. Small absolute value numbers (e.g., numbers close to zero) may have a relatively small impact on overall network training / inference. Quantizing these small numbers with floating point or fixed point may not be optimal because unnecessary precision is given to relatively unimportant numbers. For example, assuming a 32-bit representation of the number, there are 232 discrete points to perform quantization.

[0241] Figure 23 Figure 1 shows how quantization error is generally distributed over the range of numbers that can be represented by fixed-point and floating-point numbers. For the floating-point format, numbers close to zero have lower quantization error, while numbers farther from zero have larger quantization error. For the fixed-point format, the quantization error is constant over the entire range, where the entire range may be smaller. Both types of quantization may not be optimal for neural network training. Smaller numbers may not be as important in training and can be quantized more coarsely (higher quantization error). Conversely, lower quantization error may be desired for numbers farther from zero. Lower quantization error may also be desirable for moderately large numbers, but not for very small and very large numbers.

[0242] According to one embodiment, quantization is performed non-uniformly to provide higher resolution to weight values ​​that have a more significant impact on the accuracy of the neural network than to those weight values ​​that have a lower impact. In such an embodiment, the discrete points are selected to have higher precision (e.g., lower error percentage) in numbers with larger absolute values ​​and lower precision (e.g., higher error percentage) for numbers with smaller absolute values. In addition, the precision can be distributed according to any suitable manner to maximize the benefits of network training / inference (e.g., lower quantization error for numbers with medium absolute values ​​and higher quantization error for numbers with small and large absolute values). In a further embodiment, many small weights that are truncated to zero may indicate that the vector / matrix / tensor may be sparse, which can allow hardware implementations that exploit this sparsity.

[0243] Figure 24 23 is a flow chart illustrating one embodiment of a quantization process. At processing block 2351, a discrete value range for a neural network is determined. At processing block 2352, discrete points representing significant accuracy impact on training / inference are determined. At processing block 2353, resolution is assigned to each discrete point based on accuracy importance. As discussed above, discrete points can be selected to have more precise accuracy for larger absolute values ​​and less precise accuracy for smaller absolute values.

[0244] Figure 25 An embodiment of the quantization error of non-uniform quantization is shown. Figure 25 As shown in , the points are assigned such that the quantization error is small for large floating-point numbers and high for small floating-point numbers. Furthermore, the points are assigned with low quantization error for moderately large fixed numbers, but not for very small or very large fixed numbers. The mechanism described above can help neural networks converge faster or result in fewer bits required to store network weights, activations, and gradients; ultimately leading to lower power consumption and smaller and / or faster hardware designs.

[0245] In yet another embodiment, the computational mechanism can also be implemented to accelerate workloads. Recurrent neural networks (RNNs) and long short-term memory networks (LTSMs) are rapidly becoming the most important building blocks for data center workloads. These neural network topologies differ from convolutional neural networks (CNNs) in that they have memory and can be trained on data sequences (rather than single images). Therefore, LSTMs and RNNs are capable of handling complex tasks such as language understanding, document translation, anomaly detection in time series data, and activity recognition in videos.

[0246] RNNs add feedback loops to standard feedforward neural networks. Figure 26A An exemplary RNN is shown. Figure 26AAs shown in , RNN can be extended to a neural network that grows over time, thereby introducing memory into the architecture. LSTM is similar to RNN, but each cell has a more complex structure. Figure 26B An exemplary LSTM is shown. Figure 26B As shown in , an LSTM may include three gates that enable the network to decide which information to retain and which to filter out (e.g., forget gate, input gate, output gate).

[0247] According to one embodiment, the Open Computing Language (OpenCL) is implemented to accelerate workloads on LSTMs and RNNs. OpenCL is a framework for writing programs that execute across heterogeneous platforms consisting of central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and other processors or hardware accelerators. OpenCL specifies a programming language for programming devices and an application programming interface (API) to control the platform and execute programs on the computing devices. OpenCL provides a standard interface for parallel computing using task- and data-based parallelism.

[0248] In one embodiment, the OpenCL implementation supports built-in memory features for both LSTM and RNN, so that each layer is affected by the previous input as well as the current input. Further, the OpenCL implementation shares weights across all hidden LSTM and RNN layers and handles large layer sizes (e.g., translating a story requires large input sizes = many words). In such an embodiment, OpenCL provides a four-level memory hierarchy that can be used for large memory (global) and efficient weight sharing (local). In a further embodiment, OpenCL includes a sparse expansion mechanism for computing large sparse matrices. For activations / gates, OpenCL supports which operator performs hyperbolic tangent (tanh).

[0249] In another embodiment, the computing mechanism 2010 includes an activation architecture for performing deep learning functions. Deep learning applications typically include traditional activation functions (e.g., Sigmoid, Tanh, Relu, etc.), as well as emerging functions (e.g., ELU, Selu). According to one embodiment, an integrated architecture is provided to support current deep learning activation functions, as well as emerging activation functions. For example, Figure 27A One embodiment of activation functions supported by the architecture is shown.

[0250] Figures 27B-27F An embodiment of a computing architecture 2530 for enabling deep learning capabilities is shown. Figure 27BOne embodiment of architecture 2530 is shown, including fetch stage 2532, execute stage 2534, and writeback stage 2536. Fetch stage 2532 prepares input prior to execution. In one embodiment, fetch stage 2532 analyzes and identifies values ​​that can be computed quickly (e.g., x>0 in elu, selu; zero value) relative to those requiring complex operations (e.g., exp). Further, fetch stage 2532 schedules values ​​to be sent to the appropriate execution channel(s) (e.g., one subset to a simple / fast execution channel and another subset to a complex / slower execution channel).

[0251] The execute stage 2534 performs the computation. In one embodiment, the execute stage features simple channels that handle fast operations (e.g., y=0, y=x, y=scale.x) and complex channels that handle slower complex operations (e.g., exp). The writeback stage 2536 packages and prepares the results for output. In one embodiment, the writeback stage 2536 receives the results of the simple and complex channels from the execute stage 2534 and places the results in the appropriate layout format for the tensor output.

[0252] According to one embodiment, the condition of a simple operation relative to (vs) a complex operation can be based on the selected tan activation function and the desired execution. Examples of simple cases include: x=0 can produce y=0 (e.g., in this case skip the calculation (do not send it for execution)); x=negative, which produces 0 in Relu, as described above, skip the calculation; x>0 (e.g., the case of y=x, which is passed, such as in all variants of relu, and y=scale*x, which is used in selu; and x meets the threshold N in ReluN, in which case y=N. Examples of complex cases include: exponential calculation (in sigmoid, elu, selu, softplus); Tanh, log, div (in sigmoid, softplus, softsign); and an internal complex execution channel that can utilize existing methods to implement these complex operations.

[0253] Figure 27CAn embodiment of the extraction stage 2532 is shown. This embodiment shows a 4-width input tensor with 4 elements x0 to x3 (whose values ​​are 0, positive, negative, and positive, respectively). The Analyze Vals component identifies whether each element belongs to a simple case or a complex case based on the target activation function. In one embodiment, this process involves checking the sign bit and whether the value is zero. In this embodiment, when selu is used as the target, x0 is identified as 0, and x1 and x3 are identified as positive, and x2 is identified as negative. The Schedule Exe component utilizes value analysis and decides what to send for execution and which channel(s) to send it for. In this embodiment, knowing that x0 is 0 will produce an output of 0 in selu, this does not schedule x0 for execution. Further, because x1 and x3 are positive, they are sent to the simple channel, while x2 goes to the complex channel.

[0254] Figure 27D An embodiment of the execution stage 2534 is shown. In this embodiment, execution is divided into simple calculation paths and complex calculation paths. The calculation implementation method can be selected based on the target design goals (e.g., hardware area / frequency / power, accuracy of the results). Figure 27E Another embodiment of the execution stage 2534 is shown in which a complex pass is implemented using a lookup table (LT). In this case, the LT can be dynamically loaded (e.g., via GPU instructions) with the parameters needed to approximate the complex function. In other embodiments, the LT can be used in simple passes, and / or in both simple and complex passes. In still other embodiments, the approximation can be implemented using piecewise linear or nonlinear approximations, or a combination of these approximations and lookup table(s).

[0255] Figure 27F One embodiment of a write-back stage 2536 is shown. As discussed above, results from execution are packaged to produce tensor outputs at the write-back stage 2536. In this embodiment, simple channels produce results y1 and y3 in the execute stage 2534, and complex channels produce y2. Note that the rate at which simple and complex channels produce results may be different. In one embodiment, appropriate parameters such as how many simple / complex channels there are, the width of such channels, etc., can be selected based on design goals. Thus, the write-back stage 2536 is designed to match the rate at which results are produced by the execute stage 2534.

[0256] For this embodiment, two elements are produced by the simple channel, while one element is produced by the complex channel. In addition, the extract stage 2532 also propagates information about the skipped inputs (e.g., zero in this case). Based on these inputs, the writeback stage 2536 places the results in the appropriate positions of the tensor output (e.g., y1, y2, y3 are spatially sorted). Similarly, y0 is simply set to 0.

[0257] According to one embodiment, the compute architecture 2530 may implement one or more new instructions to initialize or configure (e.g., configure alpha, scale, N parameters and load lookup tables if used) and execute activation functions (e.g., indicate the function to be executed, the input tensors (as values ​​or pointers to tensors), and the write-back targets for the output tensors). Warp-level type instructions (e.g., the type used by tensor cores) or lane-level type instructions may also be implemented depending on the integration options used.

[0258] In another embodiment, the computing mechanism 2010 can process high-resolution input images through a CNN on a distributed architecture. Traditionally, CNN data layers use resizing operations to resize high-resolution inputs to meet CNN requirements so that images can be processed in a linear manner, where computationally intensive layers are delegated to accelerators and GPUs. Figure 28 A traditional linear approach for processing high-resolution images is shown. Resizing to lower dimensions and different aspect ratios degrades detection accuracy. Therefore, the higher the resolution of the original image, the more severe the impact of the resizing operation. Other disadvantages of the traditional approach include: the continuous transfer of intermediate outputs from the CPU to the GPU / accelerator (and vice versa), which significantly impacts detection latency; it does not exploit the parallelization properties of the distributed architecture, as computational units are idle multiple times; and the batch size is set to 1 (an efficient combination for CNNs on GPUs) for real-time processing.

[0259] In one embodiment, the distributed architecture includes one or more CPUs, one or more GPUs, and one or more accelerators. According to one embodiment, the distributed architecture provides a method for processing an input image into image batches ( Figure 29 ) and simultaneously process all available computing units (such as one or more CPUs 2712, one or more GPUs 2714, and one or more accelerators 2716 ( Figure 30 )) to process high-resolution input images through CNN in batches.

[0260] According to one embodiment, the input image is cropped into the small plane segments required by the CNN. In such an embodiment, the cropping factors can overlap to increase the accuracy of the detection as well as the computation time. In further embodiments, the optimal overlap ratio can be determined based on the use case. Once available, the crops are aggregated into static batches for each computing unit (e.g., CPU 2712, GPU 2714, and accelerator 2716) with dedicated memory to avoid latency associated with memory copies. In one embodiment, the generated results include information about the position of each cropped piece, which can be traced back to the original image via an offset associated with each cropped segment.

[0261] In other embodiments, profiles of compute units can be saved as an alternative to using static batch sizes. Thus, an optimal batch size can be assigned to each compute type based on current usage. This embodiment features housekeeping and resource monitoring, which can provide significant performance improvements when a resource is running several use cases. Figure 31 is a flow chart illustrating one embodiment for processing high-resolution images. At processing block 2901, high-resolution input is received. At processing block 2902, overlap processing is performed based on a user-defined overlap threshold. At processing block 2903, the clippings are packed for plane conversion. At processing block 2904, batches are created. At processing block 2905, the batches are dispatched to compute nodes. In one embodiment, the compute nodes may provide feedback on the traffic to be achieved to determine the batch size. At processing block 2906, detection position information is collected. At processing block 2907, frames are drawn based on an overlap variable based on the user-defined overlap threshold.

[0262] The mechanism described above is characterized by not resizing or distorting the original input image, thereby improving the detection accuracy of the client NN. Furthermore, batch processing during the forward pass ensures efficient utilization of computational units, improving latency compared to high-resolution input processing. Furthermore, each computational unit is tasked with end-to-end processing of the input image segment, so no memory copying from one computational unit to another occurs, resulting in improved latency. Furthermore, all computational units are busy processing the corresponding image segment with minimal impact on latency, as the cropping operation is merged with the image transformation at the data level.

[0263] Figure 323 is a block diagram illustrating a computer system 3200 configured to implement one or more aspects of the embodiments described herein. The computing system 3200 includes a processing subsystem 3201 having one or more processors 3202 and a system memory 3204, the one or more processors and the system memory communicating via an interconnect path, which may include a memory hub 3205. The memory hub 3205 may be a separate component within a chipset assembly or integrated within the one or more processors 3202. The memory hub 3205 is coupled to an I / O subsystem 3211 via a communication link 3206. The I / O subsystem 3211 includes an I / O hub 3207, which enables the computing system 3200 to receive input from one or more input devices 3208. Additionally, the I / O hub 3207 enables a display controller (which may be included in the one or more processors 3202) to provide output to one or more display devices 3210A. In one embodiment, the one or more display devices 3210A coupled to the I / O hub 3207 may include a local display device, an internal display device, or an embedded display device.

[0264] In one embodiment, the processing subsystem 3201 includes one or more parallel processors 3212, which are coupled to the memory hub 3205 via a bus or other communication link 3213. The communication link 3213 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 3212 form a compute-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 3212 form a graphics processing subsystem that can output pixels to one of one or more display devices 3210A coupled via the I / O hub 3207. The one or more parallel processors 3212 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 3210B.

[0265] Within the I / O subsystem 3211, a system storage unit 3214 can be connected to the I / O hub 3207 to provide a storage mechanism for the computing system 3200. The I / O switch 3216 can be used to provide an interface mechanism to enable connection between the I / O hub 3207 and other components that can be integrated into the platform, such as a network adapter 3218 and / or a wireless network adapter 3219, as well as various other devices that can be added via one or more plug-in devices 3220. The network adapter 3218 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 3219 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0266] Computing system 3200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 3207. Figure 32 The communication paths interconnecting the various components can be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or (multiple) any other bus or point-to-point communication interface and / or protocol such as the NV-Link high-speed interconnect or interconnect protocols known in the art.

[0267] In one embodiment, one or more parallel processors 3212 are incorporated with circuits optimized for graphics and video processing, including, for example, video output circuits, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 3212 are incorporated with circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 3200 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 3212, a memory hub 3205, (multiple) processors 3202, and an I / O hub 3207 can be integrated into a system on a chip (SoC) integrated circuit. Alternatively, the components of the computing system 3200 can be integrated into a single package to form a system in package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 3200 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0268] It should be understood that the computing system 3200 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 3202, and the number of parallel processor(s) 3212, can be modified as needed. For example, in some embodiments, the system memory 3204 is connected directly to the processor(s) 3202 rather than through a bridge, while other devices communicate with the system memory 3204 via the memory hub 3205 and the processor(s) 3202. In other alternative topologies, the parallel processor(s) 3212 are connected to the I / O hub 3207 or directly to one of the one or more processors 3202 rather than to the memory hub 3205. In other embodiments, the I / O hub 3207 and the memory hub 3205 can be integrated into a single chip. Some embodiments may include two or more groups of processor(s) 3202 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 3212.

[0269] Some specific components shown herein are optional and may not be included in all implementations of the computing system 3200. For example, any number of plug-in cards or peripherals may be supported, or some components may be omitted. In addition, some architectures may use different terminology to describe components related to the computing system 3200. Figure 32 For example, in some architectures, memory hub 3205 may be referred to as a north bridge, while I / O hub 3207 may be referred to as a south bridge.

[0270] Figure 33A The parallel processor 3300 according to an embodiment is shown. The various components of the parallel processor 3300 can be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 3300 shown is Figure 32 A variation of one or more parallel processors 3212 is shown.

[0271] In one embodiment, parallel processor 3300 includes a parallel processing unit (PPU) 3302. The PPU includes an I / O unit (I / O unit) 3304 that enables communication with other devices, including other instances of PPU 3302. I / O unit 3304 can be directly connected to other devices. In one embodiment, I / O unit 3304 connects to other devices via the use of a hub or switch interface, such as a memory hub 3205. The connection between memory hub 3205 and I / O unit 3304 forms a communication link 3213. Within PPU 3302, I / O unit 3304 is connected to a host interface 3306 that receives commands related to performing processing operations and a memory crossbar switch 3316 that receives commands related to performing memory operations.

[0272] When host interface 3306 receives command buffers via I / O unit 3304, host interface 3306 can direct work operations for executing those commands to front end 3308. In one embodiment, front end 3308 is coupled to scheduler 3310, which is configured to distribute commands or other work items to processing cluster array 3312. In one embodiment, scheduler 3310 ensures that processing cluster array 3312 is properly configured and in a valid state before assigning tasks to processing clusters within processing cluster array 3312. In one embodiment, scheduler 3310 is implemented via firmware logic executed on a microcontroller. A microcontroller-implemented scheduler 3310 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 3312. In one embodiment, host software can validate workloads for scheduling on processing array 3312 via one of multiple graphics processing doorbell mechanisms. These workloads may then be automatically distributed throughout the processing array 3310 by the scheduler 3312 logic within the scheduler microcontroller.

[0273] Processing cluster array 3312 may include up to "N" processing clusters (e.g., cluster 3314A, cluster 3314B, all the way to cluster 3314N). Each cluster 3314A to 3314N of processing cluster array 3312 can execute a large number of concurrent threads. Scheduler 3310 can use various scheduling and / or work distribution algorithms to allocate work to clusters 3314A to 3314N of processing cluster array 3312, and these algorithms can vary depending on the workload caused by each type of program or calculation. Scheduling can be handled dynamically by scheduler 3310, or can be partially assisted by compiler logic during the process of compiling program logic configured to be executed by processing cluster array 3312. In one embodiment, different clusters 3314A to 3314N of processing cluster array 3312 can be assigned to process different types of programs or to perform different types of calculations.

[0274] Processing cluster array 3312 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 3312 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 3312 can include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0275] In one embodiment, processing cluster array 3312 is configured to perform parallel graphics processing operations. In embodiments where parallel processors 3300 are configured to perform graphics processing operations, processing cluster array 3312 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 3312 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing units 3302 may transfer data from system memory via I / O units 3304 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 3322) during processing and then written back to system memory.

[0276] In one embodiment, when parallel processing unit 3302 is used to perform graphics processing, scheduler 3310 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 3314A to 3314N of processing cluster array 3312. In some embodiments, different portions of processing cluster array 3312 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform surface tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 3314A to 3314N can be stored in a buffer to allow the intermediate data to be transferred between clusters 3314A to 3314N for further processing.

[0277] During operation, the processing cluster array 3312 may receive processing tasks to be executed via the scheduler 3310, which receives commands defining the processing tasks from the front end 3308. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and an index of commands (e.g., which program to execute) that define how the data is to be processed. The scheduler 3310 may be configured to obtain an index corresponding to a task or may receive an index from the front end 3308. The front end 3308 may be configured to ensure that the processing cluster array 3312 is configured to be in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0278] Each of the one or more instances of parallel processing unit 3302 can be coupled to parallel processor memory 3322. Parallel processor memory 3322 can be accessed via memory crossbar switch 3316, which can receive memory requests from processing cluster array 3312 and I / O unit 3304. Memory crossbar switch 3316 can access parallel processor memory 3322 via memory interface 3318. Memory interface 3318 can include multiple partition units (e.g., partition unit 3320A, partition unit 3320B, through partition unit 3320N), each of which can be coupled to a portion (e.g., memory cells) of parallel processor memory 3322. In one implementation, the number of partition units 3320A through 3320N is configured to be equal to the number of memory cells, such that the first partition unit 3320A has a corresponding first memory cell 3324A, the second partition unit 3320B has a corresponding memory cell 3324B, and the Nth partition unit 3320N has a corresponding Nth memory cell 3324N. In other embodiments, the number of partition units 3320A to 3320N may not be equal to the number of memory devices.

[0279] In various embodiments, memory units 3324A through 3324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 3324A through 3324N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 3324A through 3324N may vary and may be selected from a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored on memory units 3324A through 3324N, allowing partition units 3320A through 3320N to write to portions of each render target in parallel, efficiently utilizing the available bandwidth of parallel processor memory 3322. In some embodiments, to support a unified memory design that utilizes system memory along with local cache memory, the local instance of parallel processor memory 3322 may be excluded.

[0280] In one embodiment, any of the clusters 3314A to 3314N of the processing cluster array 3312 can process data to be written to any of the memory units 3324A to 3324N within the parallel processor memory 3322. The memory crossbar 3316 can be configured to pass the output of each cluster 3314A to 3314N to any partition unit 3320A to 3320N or another cluster 3314A to 3314N, which can perform additional processing operations on the output. Each cluster 3314A to 3314N can communicate with the memory interface 3318 via the memory crossbar 3316 to perform read or write operations on various external memory devices. In one embodiment, memory crossbar switch 3316 may be connected to memory interface 3318 for communicating with I / O unit 3304 and to local instances of parallel processor memory 3322, thereby enabling processing units within different processing clusters 3314A through 3314N to communicate with system memory or other memory that is not local to parallel processing unit 3302. In one embodiment, memory crossbar switch 3316 may use virtual channels to separate traffic flows between clusters 3314A through 3314N and partition units 3320A through 3320N.

[0281] Although a single instance of parallel processing unit 3302 is shown within parallel processor 3300, any number of instances of parallel processing unit 3302 may also be included. For example, multiple instances of parallel processing unit 3302 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 3302 may be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor storage, and / or other configuration differences. For example, in one embodiment, some instances of parallel processing unit 3302 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 3302 or parallel processor 3300 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0282] Figure 33B is a block diagram of a partitioning system 3320 according to an embodiment. In one embodiment, the partitioning system 3320 is Figure 33A33. As shown in the figure, partition unit 3320 includes L2 cache 3321, frame buffer interface 3325 and ROP 3326 (raster operation unit). L2 cache 3321 is a read / write cache configured to perform load and store operations received from memory crossbar switch 3316 and ROP 3326. Read misses and urgent write-back requests are output by L2 cache 3321 to frame buffer interface 3325 for processing. Updates can also be sent to the frame buffer via frame buffer interface 3325 for processing. In one embodiment, frame buffer interface 3325 interacts with one of the memory units in parallel processor memory, such as memory units 3324A to 3324N in FIG. 33 (e.g., within parallel processor memory 3322).

[0283] In graphics applications, ROP 3326 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 3326 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 3326 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 3326 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0284] In some embodiments, ROP 3326 is included within each processing cluster (e.g., clusters 3314A through 3314N of FIG. 33 ) rather than within partition unit 3320. In this embodiment, read and write requests for pixel data are transmitted through memory crossbar 3316 rather than pixel fragment data. The processed graphics data may be displayed on a display device such as a Figure 32 , routed by processor(s) 3202 for further processing, or by Figure 33A One of the processing entities within parallel processor 3300 is routed for further processing.

[0285] Figure 33C33. It is a block diagram of a processing cluster 3314 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 3314A to 3314N of Figure 33. The processing cluster 3314 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) technology is used to use a public instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters to support the parallel execution of a large number of roughly synchronized threads. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. It will be understood by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0286] The operation of processing cluster 3314 can be controlled via pipeline manager 3332, which distributes processing tasks to SIMT parallel processors. Pipeline manager 3332 receives instructions from scheduler 3310 in FIG. 33 and manages the execution of those instructions via graphics multiprocessor 3334 and / or texture unit 3336. The illustrated graphics multiprocessor 3334 is an illustrative example of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included in processing cluster 3314. One or more instances of graphics multiprocessor 3334 can be included in processing cluster 3314. Graphics multiprocessor 3334 can process data, and data crossbar 3340 can be used to distribute processed data to one of multiple possible destinations, including other shading units. Pipeline manager 3332 can facilitate the distribution of processed data by specifying a destination for data to be distributed via data crossbar 3340.

[0287] Each graphics multiprocessor 3334 within a processing cluster 3314 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before the previous instruction is completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0288] Instructions transmitted to processing cluster 3314 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 3334. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 3334. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 3334. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 3334, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 3334.

[0289] In one embodiment, the graphics multiprocessor 3334 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 3334 can abandon the internal cache and instead use cache memory (e.g., L1 cache 3348) within the processing cluster 3314. Each graphics multiprocessor 3334 can also access the L2 cache within the partition unit (e.g., partition units 3320A to 3320N in Figure 33) shared between all processing clusters 3314, and can be used to pass data between threads. The graphics multiprocessor 3334 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 3302 can be used as global memory. In embodiments where the processing cluster 3314 includes multiple instances of the graphics multiprocessor 3334, common instructions and data that can be stored in the L1 cache 3348 can be shared.

[0290] Each processing cluster 3314 may include an MMU 3345 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 3345 may reside within the memory interface 3318 of FIG. 33 . The MMU 3345 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and, optionally, cache line indexes. The MMU 3345 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 3334 or L1 cache or processing cluster 3314. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0291] In graphics and compute applications, processing clusters 3314 can be configured such that each graphics multiprocessor 3334 is coupled to a texture unit 3336 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 3334 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 3334 outputs processed tasks to a data crossbar 3340 to provide the processed tasks to another processing cluster 3314 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 3316. A preROP 3342 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 3334 and direct the data to ROP units, which can be located using partition units (e.g., partition units 3320A through 3320N of FIG. 33 ) as described herein. The preROP 3342 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0292] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. For example, any number of processing units, such as graphics multiprocessor 3334, texture unit 3336, preROP 3342, etc., may be included in processing cluster 3314. Furthermore, while only one processing cluster 3314 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 3314. In one embodiment, each processing cluster 3314 may be configured to operate independently of other processing clusters 3314 using separate and distinct processing units, L1 cache, etc.

[0293] Figure 33D A graphics multiprocessor 3334 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 3334 is coupled to a pipeline manager 3332 of the processing cluster 3314. The graphics multiprocessor 3334 has an execution pipeline that includes, but is not limited to, an instruction cache 3352, an instruction unit 3354, an address mapping unit 3356, a register file 3358, one or more general purpose graphics processing unit (GPGPU) cores 3362, and one or more load / store units 3366. The GPGPU cores 3362 and the load / store units 3366 are coupled to a cache memory 3372 and a shared memory 3370 via a memory and cache interconnect 3368.

[0294] In one embodiment, the instruction cache 3352 receives a stream of instructions to be executed from the pipeline manager 3332. These instructions are cached in the instruction cache 3352 and dispatched for execution by the instruction unit 3354. The instruction unit 3354 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 3362. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 3356 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 3366.

[0295] The register file 3358 provides a set of registers for the functional units of the graphics multiprocessor 3324. The register file 3358 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 3362, load / store unit 3366) connected to the graphics multiprocessor 3324. In one embodiment, the register file 3358 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 3358. In one embodiment, the register file 3358 is divided between the different warps being executed by the graphics multiprocessor 3324.

[0296] The GPGPU cores 3362 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 3324. Depending on the embodiment, the architecture of the GPGPU cores 3362 may be similar or different. For example, in one embodiment, the first portion of the GPGPU core 3362 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 3324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0297] In one embodiment, the GPGPU core 3362 includes SIMD logic capable of executing a single instruction to multiple sets of data. In one embodiment, the GPGPU core 3362 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for the GPGPU core can be generated by the shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads can be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0298] The memory and cache interconnect 3368 is an interconnect network that connects each of the functional units of the graphics multiprocessor 3324 to the register file 3358 and shared memory 3370. In one embodiment, the memory and cache interconnect 3368 is a crossbar interconnect that allows the load / store unit 3366 to perform load and store operations between the shared memory 3370 and the register file 3358. The register file 3358 can operate at the same frequency as the GPGPU core 3362, so data transfer between the GPGPU core 3362 and the register file 3358 has very low latency. Shared memory 3370 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 3334. For example, cache memory 3372 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 3336. Shared memory 3370 can also be used as a cached managed program. In addition to the automatically cached data stored in cache memory 3372, threads executing on GPGPU core 3362 can also programmatically store data in shared memory.

[0299] Figures 34A to 34B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 3425, 3450 shown are Figure 33C The illustrated graphics multiprocessors 3425, 3450 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0300] Figure 34A A graphics multiprocessor 3425 is shown according to an additional embodiment. The graphics multiprocessor 3425 includes Figure 33DThe graphics multiprocessor 3425 may include multiple additional instances of execution resource units of the graphics multiprocessor 3334. For example, the graphics multiprocessor 3425 may include multiple instances of instruction units 3432A-3432B, register files 3434A-3434B, and texture unit(s) 3444A-3444B. The graphics multiprocessor 3425 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 3436A-3436B, GPGPU cores 3437A-3437B, GPGPU cores 3438A-3438B) and multiple sets of load / store units 3440A-3440B. In one embodiment, the execution resource units have a common instruction cache 3430, texture and / or data cache memory 3442, and shared memory 3446.

[0301] Various components can communicate via an interconnect fabric 3427. In one embodiment, the interconnect fabric 3427 includes one or more crossbar switches to facilitate communication between the various components of the graphics multiprocessor 3425. In one embodiment, the interconnect fabric 3427 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 3425 is stacked. Components of the graphics multiprocessor 3425 communicate with remote components via the interconnect fabric 3427. For example, the GPGPU cores 3436A-3436B, 3437A-3437B, and 34378A-3437B can each communicate with the shared memory 3446 via the interconnect fabric 3427. The interconnect fabric 3427 can arbitrate communications within the graphics multiprocessor 3425 to ensure fair bandwidth distribution between components.

[0302] Figure 34B A graphics multiprocessor 3450 is shown according to an additional embodiment. Figure 33D and Figure 34A As shown, the graphics processor includes multiple sets of execution resources 3456A to 3456D, each of which includes multiple instruction units, register files, GPGPU cores, and load-store units. The execution resources 3456A to 3456D can work with (multiple) texture units 3460A to 3460D to perform texture operations while sharing an instruction cache 3454 and a shared memory 3462. In one embodiment, the execution resources 3456A to 3456D can share multiple instances of the instruction cache 3454 and the shared memory 3462 as well as texture and / or data cache memories 3458A to 3458B. Various components can be connected to the graphics processor via the CPU. Figure 34A The interconnect structure 3427 communicates with a similar interconnect structure 3452.

[0303] Those skilled in the art will understand that Figure 32 、 Figures 33A to 33Dand Figures 34A to 34B The architecture described in is illustrative and does not limit the scope of the embodiments of the present invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as parallel processing unit 3302 of Figure 33; and one or more graphics processors or special purpose processing units, without departing from the scope of the embodiments described herein.

[0304] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0305] Technologies for GPU to host processor interconnect

[0306] Figure 35A An exemplary architecture is shown in which multiple GPUs 3510 to 3513 are communicatively coupled to multiple multi-core processors 3505 to 3506 via high-speed links 3540 to 3543 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 3540 to 3543 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0307] Furthermore, in one embodiment, two or more of the GPUs 3510-3513 are interconnected via high-speed links 3544-3545, which may be implemented using the same or different protocols / links as used for high-speed links 3540-3543. Similarly, two or more of the multi-core processors 3505-3506 may be connected via high-speed link 3533, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 35AAll communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0308] In one embodiment, each multi-core processor 3505-3506 is communicatively coupled to processor memory 3501-3502 via memory interconnects 3530-3531, respectively, and each GPU 3510-3513 is communicatively coupled to GPU memory 3520-3523 via GPU memory interconnects 3550-3553, respectively. Memory interconnects 3530-3531 and 3550-3553 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 3501-3502 and GPU memory 3520-3523 can be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memory may be volatile memory while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0309] As described below, although the various processors 3505-3506 and GPUs 3510-3513 may each be physically coupled to a specific memory 3501-3502, 3520-3523, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 3501-3502 may each include 64GB of system memory address space, and the GPU memories 3520-3523 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory space in the described example).

[0310] Figure 35B 35 shows additional details of the interconnection between the multi-core processor 3507 and the graphics acceleration module 3546 according to one embodiment. The graphics acceleration module 3546 may include one or more GPU chips integrated on a line card coupled to the processor 3507 via the high-speed link 3540. Alternatively, the graphics acceleration module 3546 may be integrated on the same package or chip as the processor 3507.

[0311] The processor 3507 shown includes multiple cores 3560A to 3560D, each of which has a translation lookaside buffer 3561A to 3561D and one or more caches 3562A to 3562D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 3562A to 3562D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 3526 may be included in the cache hierarchy and shared by each group of cores 3560A to 3560D. For example, one embodiment of the processor 3507 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 3507 and the graphics accelerator integrated module 3546 are connected to the system memory 3541 , which may include processor memories 3501 to 3502 .

[0312] Coherence is maintained for data and instructions stored in the various caches 3562A to 3562D, 3556, and system memory 3541 via inter-core communication via a coherence bus 3564. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate via the coherence bus 3564 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 3564 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art, and to avoid obscuring the underlying principles of the present invention, they are not described in detail herein.

[0313] In one embodiment, the proxy circuit 3525 communicatively couples the graphics acceleration module 3546 to the coherence bus 3564, thereby allowing the graphics acceleration module 3546 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 3535 provides connectivity to the proxy circuit 3525 via a high-speed link 3540 (e.g., a PCIe bus, NVLink, etc.), and the interface 3537 connects the graphics acceleration module 3546 to the link 3540.

[0314] In one implementation, the accelerator integrated circuit 3536 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 3531, 3532, and N of the graphics acceleration module 3546. The graphics processing engines 3531, 3532, and N can each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 3531, 3532, and N can include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer engine. In other words, the graphics acceleration module can be a GPU having multiple graphics processing engines 3531, 3532, and N, or the graphics processing engines 3531 to 3532, and N can be separate GPUs integrated on a common package, line card, or chip.

[0315] In one embodiment, the accelerator integrated circuit 3536 includes a memory management unit (MMU) 3539 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 3541. The MMU 3539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 3538 stores commands and data for efficient access by graphics processing engines 3531-3532, N. In one embodiment, data stored in cache 3538 and graphics memory 3533-3534, N is kept consistent with core caches 3562A-3562D, 3556, and system memory 3511. As mentioned, this can be accomplished via proxy circuitry 3525, which participates in cache coherence mechanisms on behalf of cache 3538 and memories 3533 to 3534, N (e.g., sending updates to cache 3538 related to modifications / accesses of cache lines on processor caches 3562A to 3562D, 3556 and receiving updates from cache 3538).

[0316] A set of registers 3545 stores context data for threads executed by graphics processing engines 3531 to 3532, N, and context management circuitry 3548 manages thread contexts. For example, context management circuitry 3548 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 3548 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer). The context management circuitry can restore register values ​​upon returning to context. In one embodiment, interrupt management circuitry 3547 receives and processes interrupts received from system devices.

[0317] In one implementation, the virtual / effective address from the graphics processing engine 3531 is translated by the MMU 3539 into a real / physical address in the system memory 3511. One embodiment of the accelerator integrated circuit 3536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 3546 and / or other accelerator devices. The graphics accelerator module 3546 can be dedicated to a single application executing on the processor 3507, or can be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented in which the resources of the graphics processing engines 3531 to 3532, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0318] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration modules 3546 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 3536 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0319] Because the hardware resources of the graphics processing engines 3531-3532, N are explicitly mapped into the actual address space seen by the host processor 3507, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 3536 is the physical separation of the graphics processing engines 3531-3532, N so that they appear on the system as independent units.

[0320] As mentioned, in the illustrated embodiment, one or more graphics memories 3533-3534, M are respectively coupled to each of the graphics processing engines 3531-3532, N. The graphics memories 3533-3534, M store instructions and data being processed by each of the graphics processing engines 3531-3532, N. The graphics memories 3533-3534, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0321] In one embodiment, to reduce data traffic on link 3540, biasing techniques are used to ensure that the data stored in graphics memory 3533-3534, M is the data most frequently used by graphics processing engines 3531-3532, N, and preferably not used (at least not frequently) by cores 3560A-3560D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not the graphics processing engines 3531-3532, N) within caches 3562A-3562D, 3556 of the cores and system memory 3511.

[0322] Figure 35C Another embodiment is shown in which the accelerator integrated circuit 3536 is integrated into the processor 3507. In this embodiment, the graphics processing engines 3531 to 3532, N communicate directly with the accelerator integrated circuit 3536 via the interface 3537 and the interface 3535 through the high-speed link 3540 (this can also use any form of bus or interface protocol). The accelerator integrated circuit 3536 can perform operations related to Figure 35B The same operations as described above may be performed at a higher throughput given their close proximity to the coherence bus 3562 and caches 3562A to 3562D, 3526. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by the accelerator integrated circuit 3536 and a programming model controlled by the graphics acceleration module 3546.

[0323] In one embodiment of a dedicated process model, graphics processing engines 3531 to 3532, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 3531 to 3532, N, thereby providing virtualization within a VM / partition.

[0324] In a dedicated process programming model, graphics processing engines 3531 to 3532, and N can be shared by multiple VM / application partitions. This shared model requires a hypervisor, which virtualizes graphics processing engines 3531 to 3532, and N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 3531 to 3532, and N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 3531 to 3532, and N to provide access to each process or application.

[0325] For the shared programming model, the graphics acceleration module 3546 or the individual graphics processing engines 3531 to 3532, N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 3511 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 3531 to 3532, N (i.e., calling system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0326] Figure 35D An exemplary accelerator integrated slice 3590 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 3536. The application effective address space 3582 within the system memory 3511 stores process elements 3583. In one embodiment, the process elements 3583 are stored in response to a GPU call 3581 from an application 3580 executing on the processor 3507. The process elements 3583 contain the processing state of the corresponding application 3580. The work descriptor (WD) 3584 contained in the process element 3583 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 3584 is a pointer to a job request queue in the application address space 3582.

[0327] The graphics acceleration module 3546 and / or the individual graphics processing engines 3531 to 3532, N may be shared by all or some of the processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 3584 to the graphics acceleration module 3546 to start a job in a virtual environment.

[0328] In one implementation, a dedicated process programming model is specific to a particular implementation. In this model, a single process owns either the graphics acceleration module 3546 or a separate graphics processing engine 3531. Because the graphics acceleration module 3546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 3536 to obtain the partition to which it belongs, and the operating system initializes the accelerator integrated circuit 3536 to obtain the process to which it belongs when the graphics acceleration module 3546 is allocated.

[0329] In operation, the WD fetch unit 3591 in the accelerator integrated slice 3590 fetches the next WD 3584, which includes an indication of work to be performed by one of the graphics processing engines of the graphics acceleration module 3546. As shown, data from WD 3584 can be stored in registers 3545 and used by the MMU 3539, interrupt management circuitry 3547, and / or context management circuitry 3546. For example, one embodiment of the MMU 3539 includes a segment / page walk circuit for accessing the segment / page table 3586 within the OS virtual address space 3585. The interrupt management circuitry 3547 can process interrupt events 3592 received from the graphics acceleration module 3546. When executing graphics operations, the effective addresses 3593 generated by the graphics processing engines 3531 to 3532, N are converted into real addresses by the MMU 3539.

[0330] In one embodiment, the same set of registers 3545 is replicated for each graphics processing engine 3531 to 3532, N, and / or graphics acceleration module 3546, and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 3590. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0331] Table 1 - Hypervisor Initialization Registers

[0332] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0333] Example registers that may be initialized by the operating system are shown in Table 2.

[0334] Table 2 - Operating System Initialization Registers

[0335]

[0336]

[0337] In one embodiment, each WD 3584 is specific to a particular graphics acceleration module 3546 and / or graphics processing engine 3531-3532, N. The WD contains all the information needed by the graphics processing engine 3531-3532, N to complete its work, or the WD may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0338] Figure 35E

[00106] Additional details of one embodiment of a sharing model are shown. The embodiment includes a hypervisor real address space 3598 in which a process element list 3599 is stored. The hypervisor real address space 3598 is accessible via a hypervisor 3596 that virtualizes the graphics acceleration module engine of an operating system 3595.

[0339] The shared programming model allows all or some processes from all or some partitions in the system to use the graphics acceleration module 3546. There are two programming models where the graphics acceleration module 3546 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0340] In this model, the hypervisor 3596 owns the graphics acceleration module 3546 and makes its functionality available to all operating systems 3595. For the graphics acceleration module 3546 to support hypervisor 3596 virtualization, it must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 3546 must provide a context save and restore mechanism. 2) The graphics acceleration module 3546 guarantees that application job requests will complete within a specified amount of time, including any translation errors, or the graphics acceleration module 3546 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness must be guaranteed for the graphics acceleration module 3546 within the process.

[0341] In one embodiment, for a shared model, application 3580 is required to make an operating system 3595 system call using a graphics acceleration module 3546 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 3546 type describes the target acceleration function of the system call. The graphics acceleration module 3546 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 3546 and can take the following forms: a graphics acceleration module 3546 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure describing the work to be performed by the graphics acceleration module 3546. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application setting the AMR. If the implementation of the accelerator integrated circuit 3536 and graphics acceleration module 3546 does not support the User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR in the process element 3583, the hypervisor 3596 may optionally apply the current authorization mask override register (AMOR) value. In one embodiment, the CSRP is one of the registers 3545 that contains the effective address of an area in the application address space 3582 for the graphics acceleration module 3546 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be plugged into system memory.

[0342] Upon receiving the system call, the operating system 3595 can verify that the application 3580 is registered and authorized to use the graphics acceleration module 3546. The operating system 3595 then calls the hypervisor 3596 using the information shown in Table 3.

[0343] Table 3 - Parameters of the operating system calling the hypervisor

[0344] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0345] Upon receiving the hypervisor call, the hypervisor 3596 can verify that the operating system 3595 has registered and is authorized to use the graphics acceleration module 3546. The hypervisor 3596 then places the process element 3583 into the process element linked list for the corresponding graphics acceleration module 3546 type. The process element can contain the information shown in Table 4.

[0346] Table 4 - Process element information

[0347]

[0348]

[0349] In one embodiment, the hypervisor initializes multiple accelerator integrated slices 3590 of registers 3545 .

[0350] like Figure 35F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 3501-3502 and GPU memories 3520-3523. In this implementation, operations executed on GPUs 3510-3513 utilize the same virtual / effective memory address space to access processor memories 3501-3502, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 3501, a second portion is allocated to second processor memory 3502, a third portion is allocated to GPU memory 3520, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 3501-3502 and GPU memories 3520-3523, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0351] In one embodiment, bias / coherency management circuitry 3594A-3594E within one or more of the MMUs 3539A-3539E ensures cache coherency between the caches of the host processor (e.g., 3505) and the GPUs 3510-3513 and implements biasing techniques that indicate physical memory where certain types of data should be stored. Figure 35F Multiple instances of bias / consistency management circuits 3594A to 3594E are shown in FIG, but bias / consistency circuits may also be implemented within an MMU of one or more host processors 3505 and / or within an accelerator integrated circuit 3536.

[0352] One embodiment allows GPU-attached memory 3520 to 3523 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the typical performance drawbacks associated with full system cache coherence. The ability to access GPU-attached memory 3520 to 3523 as system memory does not incur heavy cache coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows host processor 3505 software to set operands and access calculation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 3520 to 3523 without cache coherence overhead may be critical to the execution time of offloaded calculations. For example, in situations with a large amount of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 3510 to 3513. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play an important role in determining the effectiveness of GPU offloading.

[0353] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure consisting of 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 3520 to 3523, with or without a bias cache in GPUs 3510 to 3513 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be maintained within the GPU.

[0354] In one implementation, the bias table entry associated with each access to GPU-attached memory 3520-3523 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from GPUs 3510-3513 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 3520-3523. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 3505 (e.g., over a high-speed link as described above). In one embodiment, requests from processor 3505 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests for GPU biased pages can be forwarded to GPUs 3510-3513. If the GPU is not currently using the page, the GPU can convert the page to the host processor bias.

[0355] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0356] One mechanism for changing bias states employs an API call (e.g., OpenCL) that in turn calls the GPU device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change bias states and, for certain transitions, performs a cache flush operation in the host. The cache flush operation is required for transitions from host processor 3505 biases to GPU biases, but not for the reverse transition.

[0357] In one embodiment, cache coherency is maintained by temporarily rendering GPU offset pages uncacheable to host processor 3505. To access these pages, processor 3505 may request access from GPU 3510, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 3505 and GPU 3510, it is advantageous to ensure that GPU offset pages are pages required by the GPU but not by host processor 3505, and vice versa.

[0358] Figure 35GA multi-GPU computing system according to an embodiment is shown. The multi-GPU computing system may include a processor 3503 coupled to a plurality of GPUs 3514A-3514D via a host interface switch 3504. In one embodiment, the host interface switch 3504 is a PCI Express switch device that couples the processor 3503 to a PCI Express bus, through which the processor 3503 can communicate with the set of GPUs 3514A-3514D. The GPUs 3514A-3514D may be interconnected via a set of high-speed peer-to-peer GPU-to-GPU links 3516. The high-speed GPU-to-GPU links may be connected to each of the GPUs 3514A-3514D via dedicated GPU links. The P2P GPU links 3516 enable direct communication between each of the GPUs 3514A-3514D without requiring communication through the host interface bus to which the processor 3503 is connected. With GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or communication with other instances of the multi-GPU computing system 3500, for example, via one or more network devices. Although in the illustrated embodiment, GPUs 3514A-3514D are connected to processor 3503 via host interface switch 3504, in one embodiment, processor 3503 includes direct support for P2P GPU link 3516 and can be directly connected to GPUs 3514A-3514D.

[0359] Graphics processing pipeline

[0360] Figure 36 3600 is shown in accordance with an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 3600. The graphics processor may be included in a parallel processing subsystem such as a Figure 33A In one embodiment, the parallel processor 3300 is Figure 33B As described herein, various parallel processing systems can be implemented via parallel processing units (e.g., Figure 33A33 ) can be configured to perform the functionality of one or more of a vertex processing unit 3604, a tessellation control processing unit 3608, a tessellation evaluation processing unit 3612, a geometry processing unit 3616, and a fragment / pixel processing unit 3624. The functionality of the data assembler 3602, primitive assemblers 3606, 3614, 3618, tessellation unit 3610, rasterizer 3622, and raster operations unit 3626 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 3314 of FIG. 34 ) and corresponding partitioning units (e.g., Figure 33A The graphics processing pipeline 3600 may also be implemented using one or more dedicated processing units. In one embodiment, one or more portions of the graphics processing pipeline 3600 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 3600 may access on-chip memory (e.g., such as a CPU) via a memory interface 3628. Figure 33A The parallel processor memory 3322 shown), the memory interface can be Figure 33A An instance of memory interface 3318.

[0361] In one embodiment, data assembler 3602 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 3602 then outputs the vertex data, including vertex attributes, to vertex processing unit 3604. Vertex processing unit 3604 is a programmable execution unit that executes vertex shader programs, thereby lighting and transforming vertex data as specified by the vertex shader programs. Vertex processing unit 3604 reads data stored in cache, local, or system memory for processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0362] A first instance of primitive assembler 3606 receives vertex attributes from vertex processing unit 3600. Primitive assembler 3606 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 3608. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0363] The tessellation control processing unit 3608 treats the input vertices as control points of a geometry patch. These control points are transformed from an input representation of the patch (e.g., a basis for the patch) into a representation suitable for surface estimation by the tessellation evaluation processing unit 3612. The tessellation control processing unit 3608 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 3610 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilaterals, which are transmitted to the tessellation evaluation processing unit 3612. The tessellation evaluation processing unit 3612 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0364] A second instance of primitive assembler 3614 receives vertex attributes from tessellation evaluation processing unit 3612, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 3616. Geometry processing unit 3616 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 3614 as specified by the geometry shader programs. In one embodiment, geometry processing unit 3616 is programmed to tessellate a graphics primitive into one or more new graphics primitives and compute parameters for rasterizing the new graphics primitives.

[0365] In some embodiments, the geometry processing unit 3616 can add or delete elements from the geometry stream. The geometry processing unit 3616 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 3618. The primitive assembler 3618 receives the parameters and vertices from the geometry processing unit 3616 and constructs graphics primitives for processing by the viewport scaling, picking, and clipping unit 3620. The geometry processing unit 3616 reads data stored in parallel processor memory or system memory for processing geometry data. The viewport scaling, picking, and clipping unit 3620 performs clipping, picking, and viewport scaling and outputs the processed graphics primitives to the rasterizer 3622.

[0366] The rasterizer 3622 can perform depth sorting and other depth-based optimizations. The rasterizer 3622 also performs scan conversion on new graphics primitives to generate segments and outputs these segments and associated coverage data to the segment / pixel processing unit 3624. The fragment / pixel processing unit 3624 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 3624 transforms fragments or pixels received from the rasterizer 3622 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 3624 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operations unit 3626. The fragment / pixel processing unit 3624 can read data stored in parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity based on the sampling rate configured for the processing unit.

[0367] Raster operations unit 3626 is a processing unit that performs raster operations including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., Figure 33A The parallel processor memory 3322 in, and / or Figure 32 3204 in system memory for display on one or more display devices 3210 or for further processing by one or more processors 3202 or one of parallel processor(s) 3212. In some embodiments, raster operations unit 3626 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0368] The foregoing description and accompanying drawings should be regarded as illustrative rather than restrictive. Those skilled in the art will appreciate that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0369] Some embodiments relate to Example 1, which includes an apparatus for facilitating computational optimization, the apparatus comprising: at least one processor for performing operations to implement a neural network; and computational logic for accelerating neural network computations.

[0370] Example 2 includes the subject matter of Example 1, wherein the computation logic comprises a local memory for storing one or more graphical representations and a graphics processing unit (GrPU) for accelerating computation of the graphical representations.

[0371] Example 3 includes the subject matter of Example 1 and Example 2, wherein the GrPU supports multiple function pointers and threads to accelerate traversal of one or more graph representations.

[0372] Example 4 includes the subject matter of Examples 1-3, wherein the compute logic further comprises a compilation unit (CU) for compiling the shader kernel.

[0373] Example 5 includes the subject matter of Examples 1-4, wherein the CU and GrPU are implemented as compute-optimized shader operations.

[0374] Example 6 includes the subject matter of Examples 1-5, wherein the computation logic performs non-uniform quantization on the neural network.

[0375] Example 7 includes the subject matter of Examples 1-6, wherein performing non-uniform quantization comprises providing a lower error percentage to weight values ​​that have a significant impact on the accuracy of the neural network.

[0376] Example 8 includes the subject matter of Examples 1-7, wherein the discrete points are selected to have a lower percentage of error for large absolute value numbers and are selected to have a higher percentage of error for small absolute value numbers.

[0377] Example 9 includes the subject matter of Examples 1-8, wherein the computational logic comprises a computational language (OpenCL) for accelerating workloads on neural networks.

[0378] Example 10 includes the subject matter of Examples 1-9, wherein OpenCL shares weights between hidden layers of a neural network.

[0379] Example 11 includes the subject matter of Examples 1-10, wherein the neural network is a recurrent neural network (RNN).

[0380] Example 12 includes the subject matter of Examples 1-11, wherein the neural network is a long short-term memory network (LTSM).

[0381] Example 13 includes the subject matter of Examples 1-12, wherein the computational logic comprises a computational architecture for activating deep learning functionality in a neural network.

[0382] Example 14 includes the subject matter of Examples 1-13, wherein the computation logic comprises a fetch stage for receiving input values, an execute stage for performing computation operations on the input values, and a write-back stage for packaging and preparing results for output.

[0383] Example 15 includes the subject matter of Examples 1-14, wherein the fetch stage analyzes and identifies values ​​to be computed by the fast operation and values ​​to be computed by the complex operation.

[0384] Example 16 includes the subject matter of Examples 1-15, wherein the execution stage includes one or more simple channels to perform computational operations on fast operations, and one or more complex channels to perform computational operations on complex operations.

[0385] Example 17 includes the subject matter of Examples 1-16, wherein the writeback stage receives results from one or more simple channels and one or more complex channels and places the results in a layout format of a tensor output.

[0386] Example 18 includes the subject matter of Examples 1-17, wherein the computational logic processes the high-resolution input image via the neural network by cropping the input image into two or more image batches and processing the image batches at the at least one processor.

[0387] Example 19 includes the subject matter of Examples 1-18, wherein the at least one processor comprises a distributed architecture having a plurality of compute nodes.

[0388] Example 20 includes the subject matter of Examples 1-19, wherein two or more batches of images are processed in parallel at multiple compute nodes.

[0389] Example 21 includes the subject matter of Examples 1-20, wherein the plurality of compute nodes comprises one or more graphics processing units for processing the first batch of images, one or more central graphics processing units for processing the second batch of images, and one or more accelerators for processing the third batch.

[0390] Some embodiments relate to Example 22, which includes a method for facilitating computational optimization in a neural network, the method comprising receiving a high-resolution input image via a neural network, cropping the input image into two or more image batches, and processing the image batches at two or more computational nodes.

[0391] Example 23 includes the subject matter of Example 22, wherein two or more batches of images are processed in parallel at multiple compute nodes.

[0392] Example 24 includes the subject matter of Examples 22 and 23, wherein processing two or more image batches at the plurality of compute nodes comprises processing a first image batch at one or more graphics processing units, processing a second image batch at one or more central graphics processing units, and processing a third image batch at one or more accelerators.

[0393] The foregoing description and accompanying drawings should be regarded as illustrative rather than restrictive. Those skilled in the art will appreciate that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. An apparatus for facilitating computational optimization, the apparatus comprising: at least one processor configured to perform operations to implement the neural network; as well as A graphics processing unit (GPU) comprising a circuit system configured to accelerate neural network calculations, the circuit system comprising: local memory for storing one or more graph representations associated with a neural network, the one or more graph representations indicating node adjacencies for the neural network; and a graph processing unit GrPU comprising instruction execution circuitry configured to accelerate computation of said one or more graph representations, wherein the GrPU includes a plurality of hardware threads to simultaneously traverse a plurality of graphic representations and execute instructions associated with the plurality of graphic representations; a compilation unit CU comprising instruction execution circuitry configured to compile shader kernels locally on the GPU; and The GrPU is configured to perform computational operations implemented via dynamically compiled shaders, the dynamically compiled shaders being dynamically compiled by the CU and executed by the GrPU in response to the GPU detecting a condition, the condition being associated with input data for a neural network computation.

2. The device according to claim 1, wherein The GPU is configured to perform non-uniform quantization on the neural network, and the one or more graphical representations include an adjacency list or an adjacency matrix.

3. The device according to claim 1, wherein The GPU includes circuitry configured to accelerate application of activation functions for operations associated with neural networks.

4. The device according to claim 3, wherein The GPU includes: circuitry for providing a fetch stage for receiving an input value; circuitry for providing an execute stage for performing computational operations on the input values; and Circuitry for providing a write-back stage for packaging and preparing results for output.

5. The device according to claim 3, wherein The fetch stage is configured to analyze and identify a first operation to be implemented via the first execute stage circuitry and a second operation to be implemented via the second execute stage circuitry.

6. The device according to claim 5, wherein The execution level includes: a first execution stage circuit system for implementing a first set of activation functions; and The second execution stage circuit system is used to implement a second set of activation functions.

7. The device according to claim 6, wherein The write-back stage is configured to: receiving results from the first execution stage circuitry and the second execution stage circuitry, and Outputs the result in the format associated with the output tensor.

8. The device according to claim 1, wherein The circuitry of the GPU is configured to: detecting conditions associated with input data to neural network computations; Based on the condition, compiling a modified shader, the modified shader for configuring the GPU to perform a modified neural network computation; as well as The modified neural network computation is performed via the compiled modified shader.

9. A method for facilitating computational optimization in a neural network, the method comprising: accelerating computations on a graph representation associated with a neural network via a graph processing unit (GrPU), the GrPU comprising instruction execution circuitry having multiple hardware threads to simultaneously traverse and execute instructions associated with multiple graph representations, the multiple graph representations comprising adjacency lists or adjacency matrices; and The following steps are performed in response to a graphics processing unit (GPU) including the GrPU detecting a condition, the condition being associated with input data for neural network computation: dynamically compiling a shader kernel locally on the GPU via a compilation unit CU included in the GPU to generate a dynamically compiled shader, the CU including an instruction execution circuit system configured to dynamically compile the shader kernel locally on the GPU; as well as Instructions of the dynamically compiled shader are executed via the GrPU to perform computational operations.

10. The method of claim 9, further comprising: detecting conditions associated with input data to neural network computations; Based on the condition, compiling a modified shader, the modified shader for configuring the GPU to perform a modified neural network computation; as well as The modified neural network computation is performed via the compiled modified shader.

11. The method of claim 9, further comprising: Cropping an input image received at a heterogeneous processor comprising the GrPU, the image being cropped into a plurality of overlapping planar segments, the overlap of the planar segments being configurable according to an overlap ratio; aggregating the overlapping planar segments into two or more image batches; as well as The two or more batches of images are processed via the heterogeneous processor, wherein the heterogeneous processor is configured to process the two or more batches of images in parallel via two or more cores.

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