Semiconductor devices

Abstract

The present invention provides a semiconductor device, comprising a mesa portion arranged inside a semiconductor substrate and in contact with a gate groove portion, the mesa portion having a shoulder portion in contact with the gate groove portion at the end of the upper surface, the shoulder portion having a shape convex outward, the mesa portion having an emitter region of a first conductive type, which is in contact with the gate groove portion between the upper surface of the semiconductor substrate and a drift region, and has a higher doping concentration than the drift region, and the lower end of the emitter region at a position in contact with the gate groove portion is arranged in a deeper position in the depth direction than the lower end of the emitter region at the center of the short side direction of the mesa portion.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, a semiconductor device including a gate trench and a mesa portion is known (for example, see Patent Document 1).

[0003] Patent Document 1: International Publication No. 2017 / 006711 Summary of the invention

[0004] Technical issues

[0005] The upper surface of the mesa portion is connected to an electrode such as an emitter electrode. Therefore, it is preferable that the upper surface of the mesa portion has a large effective width that can be connected to the electrode.

[0006] Technical Solution

[0007] In order to solve the above-mentioned problems, in one embodiment of the present invention, a semiconductor device is provided, which has a semiconductor substrate provided with a drift region of a first conductivity type. The semiconductor device may have a gate groove portion, which is provided from the upper surface of the semiconductor substrate to a position reaching the drift region in the depth direction of the semiconductor substrate, and is provided to extend along a predetermined long side direction on the upper surface of the semiconductor substrate. The semiconductor device may have a mesa portion, which is provided in contact with the gate groove portion inside the semiconductor substrate. The mesa portion may have a shoulder portion in contact with the gate groove portion at the end of the upper surface. In a short side section perpendicular to the long side direction, when the mesa portion side is taken as the inner side and the gate groove portion side is taken as the outer side, the shoulder portion may have a shape convex to the outer side. The mesa portion may be provided with an emitter region of the first conductivity type, which is in contact with the gate groove portion between the upper surface of the semiconductor substrate and the drift region, and its doping concentration is higher than that of the drift region. When the direction perpendicular to both the depth direction and the long side direction is defined as the short side direction, the lower end of the emitter region at a position in contact with the gate trench portion can be arranged deeper in the depth direction than the lower end of the emitter region at the center of the mesa portion in the short side direction.

[0008] The shoulder may have a side wall connected substantially vertically to the upper surface of the semiconductor substrate. The curvature radius of the shoulder in the short side cross section may be less than 15% of the width of the mesa portion in the short side direction at the center of the gate trench portion in the depth direction.

[0009] The emitter region may include an upper region and a lower region, wherein the upper region includes the center of the mesa portion, and the lower region is provided to protrude downward from the upper region in a region where the emitter region contacts the gate groove portion. The lower region may include a short side wide portion at a position lower than a connection portion where the lower region connects the upper region, and the short side wide portion has a width in the short side direction greater than that of the connection portion.

[0010] The emitter region may include an upper region and a lower region, wherein the upper region includes the center of the mesa portion, and the lower region is provided to protrude downward from the upper region in a region where the emitter region contacts the gate trench portion. In a short side cross section, a lower surface of the upper region may be substantially perpendicularly connected to a side surface of the lower region.

[0011] In the short side cross section, an angle formed by a lower surface of the upper region and a side surface of the lower region may be smaller than an angle formed by an upper surface of the upper region and a side wall of the shoulder.

[0012] In a region where the emitter region contacts the gate trench portion, a doping concentration distribution of the emitter region in the depth direction may have a minimum value at a position corresponding to the connection portion.

[0013] In the long side cross section perpendicular to the short side direction of the mesa portion in the area where the mesa portion contacts the gate groove portion, the lower region has a long side wide portion at a position lower than a connecting portion between the lower region and the upper region, and the width of the long side wide portion in the long side direction is larger than that of the connecting portion.

[0014] The length of the long-side wide portion protruding in the long-side direction from the connecting portion may be 0.1 μm or more and 0.3 μm or less.

[0015] The mesa portion may include a base region of the second conductivity type and a contact region of the second conductivity type, wherein the base region of the second conductivity type is disposed below the emitter region, and the contact region of the second conductivity type is alternately arranged with the emitter region in the long side direction and has a higher doping concentration than the base region. The contact region may contact the connection portion of the upper region and the lower region.

[0016] In addition, the above-mentioned invention content does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 1 is a diagram showing a structure of a top surface of a semiconductor device 100 according to an embodiment of the present invention.

[0018] Figure 2 Yes Figure 1 An enlarged view of the vicinity of region 130 in FIG.

[0019] Figure 3Yes means Figure 2 FIG. 1 is a diagram showing an example of an AA cross section in FIG.

[0020] Figure 4 Yes Figure 3 An enlarged view of the vicinity of region 132 in FIG.

[0021] Figure 5 This is an enlarged view showing an example of the vicinity of the shoulder 104 .

[0022] Figure 6 This is an enlarged view showing another example of the vicinity of the shoulder 104 .

[0023] Figure 7 It is a diagram showing an example of the mesa portion 160 of the comparative example.

[0024] Figure 8 Yes means Figure 2 An example of a BB cross section in FIG.

[0025] Fig. 9 It is a diagram showing another example of the connection structure between the gate metal layer 46 and the gate conductive portion 44 .

[0026] Fig.10 It is a diagram showing another example of the shape of the lower region 112 of the emission region 12 in the YZ cross section.

[0027] Fig.11 1 is a diagram illustrating the doping concentration distribution of the emitter region 12 in the depth direction.

[0028] Fig.12 1 is a diagram illustrating the doping concentration distribution of the emitter region 12 in the depth direction.

[0029] Fig.13A Yes means Figure 2 A diagram showing an example of a DD cross section in FIG.

[0030] Fig. 13B It is a figure which shows the DD cross section in a comparative example.

[0031] Fig.14 It is a diagram for explaining a part of the manufacturing process of the gate trench portion 40 and the emitter region 12 of the semiconductor device 100 .

[0032] Description of Reference Numerals

[0033] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 26 interlayer insulating film, 30 dummy groove portion, 32 dummy insulating film, 34 dummy conductive portion, 39 extension portion, 40 gate groove portion, 41 front end portion, 42 gate insulating film, 44 gate conductive portion, 45 gate runner, 46 gate metal layer, 52 emitter electrode, 54 contact hole, 55 contact hole, 56 contact hole, 57 connection portion, 58 collector electrode, 60 terrace portion, 61 lower end, 70 transistor portion, 71 shoulder portion, 90 edge terminal structure, 100 semiconductor device, 102 upper surface, 104 shoulder, 106 lower end, 108 lower end, 109 lower surface, 110 upper region, 112 lower region, 113 connection portion, 114 side wall, 115 ion implantation region, 116 gate pad, 118 emitter pad, 119 short side width portion, 120 side wall, 121 active portion, 122 lower surface, 123 distribution, 124 long side width portion, 125 distribution, 126 recessed portion, 128 side wall, 129 position, 130 region, 132 region, 140 peripheral end, 142 gate trench, 145 upper end, 160 terrace portion DETAILED DESCRIPTION

[0034] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the present invention. In addition, not all combinations of features described in the embodiments are essential to the solution of the invention.

[0035] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the mounting direction on a substrate, etc. when assembling a semiconductor device.

[0036] In this specification, technical matters are sometimes described using orthogonal coordinate axes such as the X-axis, the Y-axis, and the Z-axis. In this specification, a plane parallel to the upper surface of the semiconductor substrate is defined as an XY plane, and a depth direction perpendicular to the upper surface of the semiconductor substrate is defined as a Z axis.

[0037] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may also be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities. In addition, in this specification, when it is recorded as P+ type (or N+ type), it means that the doping concentration is higher than that of P type (or N type), and when it is recorded as P- type (or N- type), it means that the doping concentration is lower than that of P type (or N type).

[0038] In this specification, the doping concentration refers to the concentration of the impurity after the donor or acceptor is converted. In this specification, there is a case where the net doping concentration, which is the concentration difference between the donor and the acceptor, is used as the doping concentration. In addition, there is a case where the peak value of the doping concentration distribution in the doping region is used as the doping concentration in the doping region.

[0039] Figure 1 1 is a diagram showing the structure of the upper surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. In this specification, the end of the outer periphery of the semiconductor substrate 10 when viewed from the upper surface is referred to as the outer peripheral end 140. Viewing from the upper surface refers to viewing from the upper surface side of the semiconductor substrate 10 parallel to the Z axis.

[0040] The semiconductor device 100 includes an active portion 121 and an edge termination structure portion 90. The active portion 121 is a region where the main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. That is, it is a region where the current flows inside the semiconductor substrate 10 in the depth direction from the upper surface to the lower surface of the semiconductor substrate 10, or from the lower surface to the upper surface.

[0041] exist Figure 1 In the example, the region where the gate flow channel 45 is provided is also included in the active portion 121. When viewed from the upper surface of the semiconductor substrate 10, the active portion 121 can also be set as a region where the emitter electrode is provided and a region sandwiched by the region where the emitter electrode is provided. Figure 1 In the example of FIG. 1 , an emitter electrode is provided above the transistor portion 70 .

[0042] The active portion 121 is provided with a transistor portion 70. The transistor portion 70 includes a transistor such as an insulated gate bipolar transistor (IGBT). In addition to the transistor portion 70, the active portion 121 may also be provided with a diode portion that functions as a freewheeling diode (FWD). In this case, in each diode portion, an N+ type cathode region is provided in a region that contacts the lower surface of the semiconductor substrate 10. In the semiconductor device 100 of this example, the region other than the cathode region in the region that contacts the lower surface of the semiconductor substrate 10 is a P+ type collector region.

[0043] The edge terminal structure portion 90 is provided between the active portion 121 and the outer peripheral end 140 of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10. The edge terminal structure portion 90 can be arranged in a ring shape on the upper surface of the semiconductor substrate 10 so as to surround the active portion 121. The edge terminal structure portion 90 of this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge terminal structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion 90 has, for example, a guard ring, a field plate, a surface electric field reduction, and a combination thereof.

[0044] On the upper surface of the semiconductor substrate 10, a gate metal layer 46 is provided between the edge termination structure portion 90 and the active portion 121. An interlayer insulating film is provided between the gate metal layer 46 and the semiconductor substrate 10. Figure 1 Illustration omitted.

[0045] The gate metal layer 46 may be provided so as to surround the active portion 121 when viewed from the upper surface of the semiconductor substrate 10. The gate metal layer 46 is electrically connected to a gate pad 116 provided outside the active portion 121. The gate pad 116 may be provided between the gate metal layer 46 and the active portion 121. Between the gate metal layer 46 and the active portion 121, a pad such as an emitter pad 118 electrically connected to an emitter electrode may be provided.

[0046] The gate metal layer 46 may be formed of aluminum or an aluminum-silicon alloy. The gate metal layer 46 is electrically connected to the transistor portion 70 and supplies a gate voltage to the transistor portion 70.

[0047] The gate channel 45 is electrically connected to the gate metal layer 46 and extends to a position overlapping with the active portion 121. At least one gate channel 45 can be arranged to cross the active portion 121 along the Y-axis direction. The gate channel 45 supplies a gate voltage to the transistor portion 70. The gate channel 45 can be formed of a semiconductor material such as polysilicon doped with impurities, or can be formed of a metal. The gate channel 45 is arranged above or inside the semiconductor substrate 10, and the semiconductor substrate 10 and the gate channel 45 are insulated by an insulating film.

[0048] Figure 2 Yes Figure 1 The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, an accumulation region 16, and a well region 11, which are provided inside a semiconductor substrate 10. In this specification, the gate trench portion 40 or the dummy trench portion 30 may be referred to as simply a trench portion.

[0049] The accumulation region 16 is not exposed on the upper surface of the semiconductor substrate 10. Figure 2In FIG. 1 , a region where the accumulation region 16 is provided is indicated by a dotted line in an XY plane parallel to the upper surface of the semiconductor substrate 10. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 46 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 46 are provided separately from each other.

[0050] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 46 and the upper surface of the semiconductor substrate 10. Figure 2 In the interlayer insulating film of this example, the contact hole 54, the contact hole 55, and the contact hole 56 are provided to penetrate the interlayer insulating film.

[0051] The emitter electrode 52 contacts the emitter region 12, the contact region 15 and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. The contact hole 54 of this example is provided between the groove portions. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole 56. A connecting portion 57 may be provided between the emitter electrode 52 and the dummy conductive portion, and the connecting portion 57 is formed of a conductive material such as polysilicon doped with impurities. The connecting portion 57 is provided on the upper surface of the semiconductor substrate 10. In this example, the contact hole 56 is arranged at the front end of the dummy groove portion 30 in the X-axis direction. An insulating film is provided between the connecting portion 57 and the semiconductor substrate 10.

[0052] The gate metal layer 46 contacts the gate channel 45 through the contact hole 55. The gate channel 45 is formed of polysilicon doped with impurities or the like. The gate channel 45 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface of the semiconductor substrate 10. The gate channel 45 is not connected to the dummy conductive portion in the dummy groove portion 30. The gate channel 45 of this example is arranged from the bottom of the contact hole 55 to the front end portion 41 of the gate groove portion 40. At the front end portion 41 of the gate groove portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10 and contacts the gate channel 45. An insulating film is arranged between the gate channel 45 and the semiconductor substrate 10. In other examples, the semiconductor device 100 does not have a gate channel 45, and the gate metal layer 46 may also be directly connected to the gate groove portion 40.

[0053] An insulating film such as an oxide film is provided between the gate channel 45 and the semiconductor substrate 10. At the front end 41 of the gate groove 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. The insulating film above the gate conductive portion is provided with a contact hole connecting the gate conductive portion and the gate channel 45. Figure 2 In the plan view, there is a portion where the emitter electrode 52 and the gate channel 45 overlap, but the emitter electrode 52 and the gate channel 45 are electrically insulated from each other via an insulating film (not shown).

[0054] The emitter electrode 52 and the gate metal layer 46 are formed of a material containing a metal. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium or a titanium compound or the like under the region formed of aluminum or the like, or may have a plug formed of tungsten or the like in the contact hole.

[0055] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged on the upper surface of the semiconductor substrate 10 at predetermined intervals along a predetermined arrangement direction. Figure 2 The arrangement direction in is the Y-axis direction. In this specification, the arrangement direction may be referred to as the short-side direction. In the transistor portion 70, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately arranged along the arrangement direction.

[0056] The gate groove portion 40 of this example may have two extension portions 39 and a front end portion 41, wherein the two extension portions 39 extend in parallel along an extension direction (in this example, the X-axis direction) perpendicular to the arrangement direction, and the front end portion 41 connects the two extension portions 39 at the front end of the extension portion 39. In this specification, there is a case where the extension direction is referred to as the long side direction. Preferably, at least a portion of the front end portion 41 is formed in a curved shape on the upper surface of the semiconductor substrate 10. By connecting the front ends of the two extension portions 39 of the gate groove portion 40, the electric field concentration at the end of the extension portion 39 can be alleviated.

[0057] One or more dummy groove portions 30 are provided between the extension portions 39 of the gate groove portion 40. The dummy groove portion 30 may have a front end portion connecting the front ends of the two extension portions, similarly to the gate groove portion 40. In this example, a dummy groove portion 30 having two extension portions and a front end portion is provided between the extension portions 39 of the gate groove portion 40. The dummy groove portion 30 of other examples may also have a straight line shape without a front end portion. The dummy groove portion 30 is provided at a position that does not overlap with the gate flow channel 45.

[0058] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is provided in a predetermined range from the end of the active portion 121 on the side where the gate metal layer 46 is provided. The well region 11 is provided separately from the end of the long side direction of the contact hole 54 in the XY plane. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40. A portion of the gate trench portion 40 on the side of the gate metal layer 46 is arranged in the well region 11.

[0059] The transistor portion 70 includes one or more mesa portions 60 sandwiched between the trench portions. The mesa portion 60 is a region of the semiconductor substrate 10 sandwiched between the trench portions, which is located on the upper surface side relative to the deepest bottom of the trench portion.

[0060] A base region 14 is provided in each mesa portion 60. The base region 14 is a P-type having a lower doping concentration than the well region 11. A P+ type contact region 15 having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. In addition, an N+ type emitter region 12 having a higher doping concentration than the semiconductor substrate 10 is selectively formed on the upper surface of the base region 14.

[0061] The contact region 15 and the emitter region 12 are provided from one adjacent groove portion to the other groove portion, respectively. The contact region 15 and the emitter region 12 are provided so as to be alternately exposed on the upper surface of the semiconductor substrate 10 along the extending direction of the groove portion (X-axis direction).

[0062] In another example of the mesa portion 60 , the contact region 15 and the emitter region 12 may also be arranged in stripes along the extending direction. For example, the emitter region 12 is arranged in the region adjacent to the groove portion, and the contact region 15 is arranged in the region sandwiched by the emitter region 12 .

[0063] The contact hole 54 is provided above each region of the contact region 15 and the emitter region 12. The contact hole 54 is not provided in a region corresponding to the base region 14 and the well region 11.

[0064] On the upper surface of the semiconductor substrate 10, the well region 11 can be separated from the contact region 15 disposed closest to the end in the Y-axis direction in the direction of the gate metal layer 46. On the upper surface of the semiconductor substrate 10, the base region 14 is exposed between the well region 11 and the contact region 15.

[0065] Figure 3 Yes means Figure 2 FIG. 1 is a diagram of an example of an AA section in FIG. The AA section in this example is a YZ plane. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 58 in this section. The interlayer insulating film 26 is a silicate glass to which impurities such as boron and phosphorus are added. The interlayer insulating film 26 is selectively formed on the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52 is provided on the upper surface of the semiconductor substrate 10 and the interlayer insulating film 26. The collector electrode 58 is provided on the lower surface 23 of the semiconductor substrate 10.

[0066] The semiconductor substrate 10 is provided with an N-type drift region 18. The drift region 18 in this example is a region remaining in the semiconductor substrate 10 where the emitter region 12, the base region 14, the accumulation region 16, the buffer region 20 and the collector region 22 are not formed.

[0067] A P-type base region 14 is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. The base region 14 may be formed by implanting P-type impurities such as boron from the upper surface 21 of the semiconductor substrate 10.

[0068] An N+ type emitter region 12 is provided on the upper surface of the base region 14. The emitter region 12 can be formed by implanting N type impurities such as phosphorus from the upper surface 21 of the semiconductor substrate 10.

[0069] An N+ type accumulation region 16 is provided between the drift region 18 and the base region 14. The accumulation region 16 can be formed by implanting N type impurities such as phosphorus or protons from the upper surface 21 of the semiconductor substrate 10.

[0070] In this example, the gate groove portion 40 and the dummy groove portion 30 are provided from the upper surface 21 of the semiconductor substrate 10 to penetrate the emitter region 12, the base region 14, and the accumulation region 16. The bottoms of the gate groove portion 40 and the dummy groove portion 30 of this example are arranged in the drift region 18. In addition, the so-called groove portion penetrating each region is not limited to the case where the groove portion is formed after each region is formed by doping impurities. The so-called groove portion penetrating each region also includes the case where each region is formed between the groove portions after the groove portion is formed.

[0071] The buffer region 20 is provided on the lower surface side of the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22. A P+ type collector region 22 is provided on the lower surface side of the buffer region 20.

[0072] The gate trench portion 40 includes a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is covered by the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0073] The gate conductive portion 44 includes at least a region facing the adjacent base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered by the interlayer insulating film 26 on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in the surface layer of the interface in contact with the gate trench portion 40 in the base region 14.

[0074] The dummy groove portion 30 of this example has a dummy insulating film 32 and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove portion 30 and is covered by the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length as the gate conductive portion 44 in the depth direction. The dummy groove portion 30 on this cross section is covered by the interlayer insulating film 26 on the upper surface 21 of the semiconductor substrate 10.

[0075] Providing the dummy trench 30 can enhance the carrier accumulation effect, promote conductivity modulation, and reduce the on-voltage. In addition, by adjusting the ratio of the dummy trench 30 to the gate trench 40 , the switching speed of the semiconductor device 100 can be adjusted.

[0076] Figure 4 Yes Figure 3 FIG. 1 is an enlarged view of the vicinity of region 132 in FIG. Figure 4 The size ratios of the components shown are Figure 3 As described above, the gate trench portion 40 is provided from the upper surface 21 of the semiconductor substrate 10 to a position reaching the drift region 18 in the depth direction (Z-axis direction) of the semiconductor substrate 10 .

[0077] The mesa portion 60 is provided inside the semiconductor substrate 10 so as to be in contact with the groove portion in the Y-axis direction. Figure 4 The mesa portion 60 is shown to be sandwiched between the gate trench portion 40 and the dummy trench portion 30 , but the mesa portion 60 may be sandwiched by either two gate trench portions 40 or two dummy trench portions 30 .

[0078] The mesa portion 60 has an upper surface 102. The upper surface 102 is the uppermost surface (positive side in the Z-axis direction) of the mesa portion 60. As an example, the upper surface 102 is arranged at the same height as the upper surface 21 of the semiconductor substrate 10 (position in the Z-axis direction).

[0079] The mesa portion 60 has a shoulder portion 104 at an end portion of the upper surface 102 in the Y-axis direction. Figure 4 One shoulder 104 of the mesa portion 60 shown is in contact with the gate trench portion 40, and the other shoulder 104 is in contact with the dummy trench portion 30. In this specification, the shoulder 104 in contact with the gate trench portion 40 and its surrounding structure are described, but the shoulder 104 in contact with the dummy trench portion 30 and its surrounding structure may also have the same structure.

[0080] Shoulder 104 Figure 4 The cross section shown (YZ cross section. In this specification, it is sometimes referred to as a short side cross section) has a convex shape toward the outside. It should be noted that, with the shoulder 104 as a reference, the mesa portion 60 side (negative side in the Y-axis direction and negative side in the Z-axis direction) is set as the inner side, and the gate groove portion 40 side and the interlayer insulating film 26 side (positive side in the Y-axis direction and positive side in the Z-axis direction) are set as the outer side. The shoulder 104 is not set at a position higher than the upper surface 102.

[0081] The shape of the shoulder 104 in the YZ cross section may be composed of two or more straight lines, or may be composed of a combination of a straight line and a curved line convex outward. Figure 4 As shown, the shape of the shoulder 104 on the YZ cross section can be composed of a straight line corresponding to the upper surface 102 and a straight line corresponding to the side wall of the gate trench portion 40. In addition, the intersection of the two straight lines can be rounded with a curve convex to the outside. In addition, the shape of the shoulder 104 on the YZ cross section can also include a plurality of straight lines whose absolute values ​​of slopes gradually increase from the upper surface 102 toward the side wall of the gate trench portion 40. That is, the shoulder 104 can also have a shape approximated by a plurality of straight lines that are convex to the outside.

[0082] As described above, the N+ type emitter region 12 is provided in the mesa portion 60, the emitter region 12 is in contact with the gate trench portion 40 between the upper surface 21 of the semiconductor substrate 10 and the drift region 18, and its doping concentration is higher than that of the drift region 18. In this specification, the direction perpendicular to both the depth direction (Z-axis direction) and the long side direction (X-axis direction) is defined as the short side direction (Y-axis direction).

[0083] The emission region 12 has an upper region 110 and a lower region 112. The upper region 110 is a region including the center of the mesa portion 60 in the short side direction. In this specification, the lower end of the emission region 12 in the center of the mesa portion 60 in the short side direction is referred to as the lower end 106. The upper region 110 may be a region in the emission region 12 that is above the lower end 106.

[0084] The lower region 112 is arranged in the region in contact with the gate groove portion 40. The lower region 112 is provided to protrude downward from the upper region 110 in the region in contact with the gate groove portion 40. The lower end of the lower region 112 is set as the lower end 108. The lower end 108 is in contact with the gate groove portion 40, and is the point arranged at the lowermost side in the lower region 112. The lower end 108 of the lower region 112 is arranged at a position deeper (i.e., at the lower side) than the lower end 106 of the emitter region 12 at the center of the mesa portion 60 in the depth direction. The thickness of the lower region 112 in the short side direction may be less than 1 / 3 of the width of the mesa portion 60 in the short side direction, may be less than 1 / 4, or may be less than 1 / 5.

[0085] According to the semiconductor device 100, the shoulder portion 104 of the mesa portion 60 has a convex shape, so that the effective width of the upper surface 102 connected to the contact hole 54 can be increased. Therefore, it is easy to ensure a margin for the design position of the contact hole 54 provided in the interlayer insulating film 26, and the miniaturization of the mesa portion 60 becomes easy.

[0086] In addition, the emitter region 12 is set deeper in the area in contact with the gate groove portion 40. Therefore, the emitter region 12 is easy to be opposite to the gate conductive portion 44. In a structure in which the shoulder portion 104 has a shape convex to the outside, if the emitter region 12 is formed by injecting impurities from the upper surface side of the semiconductor substrate 10, it is difficult to form the emitter region 12 deeply in the area in contact with the gate groove portion 40. In this example, for example, after the gate conductive portion 44 is formed in the gate groove portion 40, impurities are injected into the mesa portion 60 in an inclined direction, thereby, even if the shoulder portion 104 has a shape convex to the outside, the emitter region 12 can be easily formed deep in the area in contact with the gate groove portion 40. Therefore, the controllability of the threshold voltage is improved. That is, according to the semiconductor device 100, the design margin of the contact hole 54 can be ensured, and the controllability of the threshold voltage can be improved.

[0087] In addition, by making the shoulder 104 have a substantially vertical shape, it is possible to reduce the shape deviation of the shoulder 104 between the plurality of terrace portions 60. Figure 7 Since the shoulder 104 is not formed by additional etching, it is not easy to produce shape deviation. The emitter region 12 and the like are formed by injecting impurities from the upper surface 21 side of the semiconductor substrate 10. Therefore, if the shape of the shoulder 104 is distorted, the depth of the emitter region 12 adjacent to the gate trench portion 40 and the threshold voltage and the like will be distorted.

[0088] Figure 5 1 is an enlarged view showing an example of the vicinity of the shoulder 104. As described above, the emitter region 12 has an upper region 110 and a lower region 112. The distance in the Z-axis direction from the upper surface 21 of the semiconductor substrate 10 (or the upper surface 102 of the mesa portion 60) to the lower end 106 of the upper region 110 at the center of the mesa portion 60 is set to L2, and the distance in the Z-axis direction from the upper surface 21 of the semiconductor substrate 10 (or the upper surface 102 of the mesa portion 60) to the lower end 108 of the lower region 112 is set to L1. Distance L1 is greater than distance L2. Distance L1 may be 1.2 times or more of distance L2, 1.5 times or more, or 2 times or more.

[0089] The outer shape of the shoulder 104 in this example is defined by two straight lines (the upper surface 102 and the side wall 114 of the shoulder 104) on the YZ cross section. The side wall 114 of the shoulder 104 may have the same slope as the side wall of the gate trench portion 40. The side wall 114 is connected approximately perpendicularly to the upper surface 102. In this example, the angle formed by the side wall 114 of the shoulder 104 and the upper surface 102 on the YZ cross section is set to θ1. θ1 may be in the range of 88 degrees to 92 degrees, or in the range of 89 degrees to 91 degrees. In addition, it may be greater than 90 degrees and less than 95 degrees, or in the range of 91 degrees to 93 degrees. According to Figure 4 The structure shown can easily ensure the effective width of the upper surface 102 of the mesa portion 60 .

[0090] In addition, the angle formed by the lower surface 122 of the upper region 110 and the side wall 120 of the lower region 112 is set to θ2. θ2 can be approximately 90 degrees (i.e., approximately vertical). Angle θ2 can be smaller than 90 degrees. That is, the angle formed by the lower surface 122 and the side wall 120 can be an acute angle. In other examples, angle θ2 can also be greater than 90 degrees. In addition, in this specification, the plane or curved surface extending the lower surface 122 to the gate groove portion 40 is referred to as the connecting portion 113 between the upper region 110 and the lower region 112. In addition, angle θ2 can be smaller than angle θ1. As a result, the threshold controllability can be improved, the effective width of the upper surface 102 can be increased, and the shape deviation of the shoulder 104 can be reduced.

[0091] Figure 6 1 is an enlarged view showing another example of the vicinity of the shoulder 104. The outer shape of the shoulder 104 in this example is defined by a curve that is convex to the outside in the YZ section. Figure 4 As shown, the distance in the Z-axis direction from the upper surface of the semiconductor substrate 10 to the lower end 61 of the gate groove portion 40 is set to D, and the depth position D / 2 from the upper surface of the semiconductor substrate 10 is set to the central position. In addition, the width in the short side direction of the mesa portion 60 at the central position is set to W1. The radius of curvature of the shoulder 104 can be less than 15% of the width W1, less than 10% of the width W1, less than 5% of the width W1, or less than 1% of the width W1. The radius of curvature of the shoulder 104 can be smaller than the radius of curvature of the lower end 61 of the gate groove portion 40. The radius of curvature of the shoulder 104 can be smaller than the thickness of the gate insulating film 42. The radius of curvature of the shoulder 104 can be the same as that of the gate insulating film 42 to be formed. Figure 5 The substantially vertical shoulder 104 shown has the same radius of curvature as the curved surface inevitably formed by etching or the like.

[0092] In addition, when the tangent line of the side wall of the gate trench portion 40 at the central position on the YZ cross section is extended to the height position of the upper surface 21 of the semiconductor substrate 10, the position where it intersects with the upper surface 21 of the semiconductor substrate 10 is set to position 129. In the portion from the contact hole 54 to position 129, the length of the region in the Y-axis direction where the upper end of the mesa portion 60 is arranged at the same height as the upper surface 21 of the semiconductor substrate 10 is set to L3. In addition, the length of the region in the Y-axis direction where the upper end of the mesa portion 60 is arranged below the upper surface 21 of the semiconductor substrate 10 is set to L4. The length L3 can be greater than the length L4. The length L3 can be more than twice the length L4, more than 10 times, or more than 100 times. According to Figure 5 The structure shown can also easily ensure the effective width of the upper surface 102 of the mesa portion 60 .

[0093] Figure 7 1 is a diagram showing an example of a table portion 160 of a comparative example. The shoulder portion 104 of the table portion 160 has a shape that is convex inward. In this case, Figure 7 As shown, the effective area of ​​the upper surface 102 of the mesa portion 60 connected to the contact hole 54 becomes smaller. In addition, there is a case where an ion implantation region 115 reflecting the shoulder 104 with a shape convex inward is formed between the lower region 112 and the upper region 110. In this case, if, for example, the lower region 112 is formed too deep, there is a possibility that the gate threshold value is reduced.

[0094] Figure 8 Yes means Figure 2 FIG. BB is an example of a cross section taken along the line BB in FIG. The cross section BB is an XZ plane passing through the vicinity of the dummy groove portion 30. In the range where the contact hole 54 is provided in the X-axis direction, the contact region 15 and the emitter region 12 are alternately arranged on the upper surface of the semiconductor substrate 10. In the range where the contact hole 54 is not provided, the base region 14 and the well region 11 are arranged on the upper surface of the semiconductor substrate 10.

[0095] The gate trench portion 40 is arranged to be surrounded by the well region 11. The gate trench portion 40 is connected to the gate metal layer 46 via a gate flow channel 45 arranged above the upper surface of the semiconductor substrate 10. An insulating film is provided between the gate flow channel 45 and the upper surface of the semiconductor substrate 10.

[0096] In this case, the moving direction of carriers moving between the gate conductive portion 44 and the gate metal layer 46 changes by nearly 90 degrees at the connection portion between the gate conductive portion 44 and the gate flow channel 45. Figure 5 The shoulder 104 shown is also formed to be substantially vertical, so when the gate voltage is applied, the electric field will be concentrated on the shoulder 71.

[0097] Therefore, preferably, the shoulder 71 is Figure 8 For example, after the trench of the gate trench portion 40 is formed, a shallow trench is further formed by etching by enlarging the opening of the mask, thereby forming the shoulder portion 71 having an inwardly convex shape.

[0098] However, if the shoulder 104 of the gate trench 40 of the active portion 121 is also formed to be convex inwardly similar to the shoulder 71, then Figure 7 As in the comparative example shown in FIG. 1 , the area of ​​the upper surface 102 connected to the contact hole 54 is reduced. In this example, the shoulder 104 of the mesa portion 60 adjacent to the gate trench portion 40 in the active portion 121 has Figures 1 to 6 The shoulder portion 71 adjacent to the gate trench portion 40 connected to the gate runner 45 and the shoulder portion 104 adjacent to the gate trench portion 40 of the active portion 121 may have different shapes.

[0099] Fig. 9 1 is a diagram showing another example of the connection structure between the gate metal layer 46 and the gate conductive portion 44. The semiconductor device 100 of this example does not include the gate runner 45 connecting the gate metal layer 46 and the gate conductive portion 44, and the gate metal layer 46 is directly connected to the gate conductive portion 44. Specifically, the interlayer insulating film 26 covering the gate conductive portion 44 is provided with a contact hole 55 just above the gate conductive portion 44. The gate metal layer 46 is in direct contact with the gate conductive portion 44 through the contact hole 55.

[0100] According to this structure, even if the shoulder 71 adjacent to the gate trench 40 connected to the gate metal layer 46 and the shoulder 104 adjacent to the gate trench 40 of the active portion 121 are formed substantially vertically, the electric field does not concentrate on the shoulder 71. Therefore, the manufacturing process of the semiconductor device 100 can be simplified.

[0101] Fig.101 is a diagram showing another example of the shape of the lower region 112 of the emitting region 12 in the YZ cross section. In this example, the length of the lower region 112 in the Y-axis direction at the connecting portion 113 connecting the lower region 112 and the upper region 110 is set to L5. The lower region 112 has a short side wide portion 119 at a position lower than the connecting portion 113, and the width of the short side wide portion 119 in the Y-axis direction is greater than the length L5. The maximum length of the short side wide portion 119 in the Y-axis direction is set to L6. The length L6 can be more than 1.05 times the length L5, or more than 1.1 times, or more than 1.2 times. In this example, the angle θ2 formed by the lower surface 122 of the upper region 110 and the side wall 120 of the lower region 112 is an acute angle. The angle θ2 can be less than 85 degrees, or less than 80 degrees.

[0102] Fig.11 and Fig.12 1 is a diagram illustrating the doping concentration distribution in the depth direction of the emitter region 12 . Fig.12 Yes means Fig.11 FIG. 4 is a diagram showing an example of doping concentration distribution at the CC section in FIG. The CC section is a section adjacent to the side wall 114 of the gate groove portion 40, and is a section passing from the upper end of the upper region 110 to the lower end of the lower region 112. The CC section may be a boundary surface of the mesa portion 60 connected to the side wall 114 of the gate groove portion 40, or may be a section that is a small distance away from the side wall 114. As an example, the distance between the CC section and the side wall 114 is less than 0.1 μm.

[0103] like Fig.12 As shown, in the area connected to the gate groove portion 40, the doping concentration distribution in the depth direction of the emitter region 12 has a minimum value n1 at a position L8 corresponding to the connection portion 113. The position corresponding to the connection portion 113 can be the same depth position as the connection portion 113, or it can be a position within a predetermined range relative to the same depth position as the connection portion 113. The predetermined range can be less than 1 μm, less than 0.5 μm, or less than 0.2 μm. In addition, the position L8 can also be configured at a position higher than the connection portion 113.

[0104] In the portion above the position L8, a doping concentration distribution resulting from diffusion of dopants injected from the upper surface 102 of the mesa portion 60 is dominant. In this distribution 125, the doping concentration gradually decreases from the vicinity of the upper surface 102 of the mesa portion 60 toward the lower side.

[0105] In the portion below the position L8 , a doping concentration distribution resulting from diffusion of dopants implanted from the side surfaces of the mesa portion 60 is dominant. This distribution 123 has a peak at a predetermined depth from the upper surface 102 of the mesa portion 60 .

[0106] In this example, since the shoulder 104 of the mesa portion 60 has a substantially vertical shape, the position of the upper surface 102 of the mesa portion 60 is high near the gate trench portion 40. Therefore, the distance between the distribution 125 and the distribution 123 is relatively large. By combining these distributions, the doping concentration distribution of the emitter region 12 has a minimum value n1 at a predetermined position L8.

[0107] Fig.13A Yes means Figure 2 FIG. DD is an example of a DD cross section in FIG. DD is an XZ cross section (in this specification, it may be called a long side cross section) in the mesa portion 60 in the region adjacent to the gate trench portion 40. Fig.11 The CC cross section shown may be a boundary surface of the mesa portion 60 in contact with the side wall 114 of the gate trench portion 40, or may be a cross section slightly separated from the side wall 114. As an example, the distance between the DD cross section and the side wall 114 is 0.1 μm or less.

[0108] The lower region 112 has a long side wide width portion 124 at a portion below the connecting portion 113, and the width of the long side wide width portion 124 in the X-axis direction is greater than that of the connecting portion 113. In this example, the length of the lower region 112 in the X-axis direction at the connecting portion 113 is set to L9, and the maximum length in the X-axis direction at the long side wide width portion 124 is set to L10. The length L10 of this example is greater than the length L9. The length L10 may be 1.05 times or more, 1.1 times or more, or 1.2 times or more of the length L9.

[0109] The length L11 of the long-side wide portion 124 protruding from the connection portion 113 in the X-axis direction may be 0.1 μm to 0.3 μm, or less. The protruding length may be 0.15 μm to 0.25 μm.

[0110] In addition, the contact region 15 is provided adjacent to the emitter region 12 in the X-axis direction. The contact region 15 is connected to the connection portion 113, which is a connection portion where the upper region 110 is connected to the lower region 112. That is, the contact region 15 is provided as a recessed portion 126 at the connection portion 113 entering the emitter region 12.

[0111] like Fig.12As described in the above, the N-type doping concentration in the emitter region 12 is relatively low near the connection portion 113. Therefore, if a P-type dopant is injected and diffused to form a P+ type contact region 15, the N-type region near the connection portion 113 is easily inverted to a P-type. Fig.13A As shown, the shape of the recessed portion 126 where the contact region 15 enters the connection portion 113 of the emitter region 12 is formed.

[0112] Fig. 13B It is the DD cross section of the comparative example. As described above, near the connection portion 113, the P-type dopant easily diffuses into the inside of the emitter region 12 (for example, the negative side in the X-axis direction). Therefore, the diffusion of the P-type dopant in the depth direction is suppressed. If the P-type dopant diffuses too much in the depth direction, the area of ​​the contact region 15 covering the lower surface 109 of the emitter region 12 becomes larger. If the contact region 15 covers the lower surface 109 of the emitter region 12, the length of the region that functions as a channel in the X-axis direction is reduced. In addition, when shutting down, etc., holes pass through the contact region 15 from the lower surface 109 of the emitter region 12 along the boundary surface between the contact region 15 and the emitter region 12. If the dopant of the contact region 15 (acceptor in this case) diffuses in such a way that the contact region 15 covers the lower surface 109 of the emitter region 12, the doping concentration of the contact region 15 in the hole passage area is reduced, and the on-resistance of the hole is likely to become high. As a result, latch-up is likely to occur.

[0113] In contrast, according to Fig.13A The structure shown can prevent the contact region 15 from covering the lower surface 109 of the emitter region 12. Therefore, the length of the channel region can be ensured. In addition, since the doping concentration of the contact region 15 in the hole passage region is also prevented from decreasing, latch-up can also be prevented.

[0114] In addition, the angle between the lower surface 109 of the emitter region 12 and the side wall 128 of the contact region 15 is set to θ3. The angle θ3 may be greater than 45 degrees and less than 135 degrees. The angle θ3 may also be greater than 60 degrees and less than 120 degrees, or greater than 80 degrees and less than 100 degrees.

[0115] In the absence of the recessed portion 126, as Fig. 13B As described above, the dopant (acceptor in this case) of the contact region 15 is easily diffused in a manner that covers the lower surface 109 of the emitter region 12. In this case, the isoconcentration surface of the doping concentration from the contact regions 15 of the same conductivity type to the base region 14 is distributed in a manner that leaches toward the lower surface of the lower surface 109 of the emitter region 12. Fig. 13BIn FIG. 1 , the isoconcentration surfaces near the contact region 15 and the base region 14 are indicated by dotted lines. Therefore, when the isoconcentration surface of the predetermined doping concentration is used as the sidewall 128 of the contact region 15, the angle θ3′ between the sidewall 128 and the lower surface 109 of the emitter region 12 is larger than 135 degrees.

[0116] In contrast, according to Fig.13A In the structure shown, as described above, since the P-type dopant diffuses into the recessed portion 126, the P-type dopant diffused around the lower surface 109 of the emitter region 12 becomes less. As a result, the angle θ3 is relatively small. In addition, the predetermined doping concentration may be the doping concentration of the isoconcentration surface at the position where the doping concentration changes sharply from the contact region 15 to the base region 14. More specifically, the predetermined doping concentration may be the doping concentration of the isoconcentration surface that is about 3 to 30 times the maximum value (peak concentration) of the doping concentration of the base region 14 that contacts the lower surface 109 of the emitter region 12, for example, 10 times the doping concentration of the isoconcentration surface.

[0117] Fig.14 14 is a diagram for explaining a part of the manufacturing process of the gate trench portion 40 and the emitter region 12 in the semiconductor device 100. First, in the gate trench forming process S1400, a gate trench 142 is formed on the surface of the semiconductor substrate 10. The gate trench 142 has a shoulder 104 in a region in contact with the upper surface 21 of the semiconductor substrate 10. In this example, after the gate trench 142 is formed, the shoulder 104 is not additionally etched.

[0118] Then, in the gate conductive portion forming step S1402, a gate insulating film 42 and a gate conductive portion 44 are formed on the inner wall of the gate trench 142. The gate insulating film 42 can be formed by oxidizing the semiconductor substrate 10. In addition, the gate conductive portion 44 is formed in such a manner that the upper end 145 of the gate conductive portion 44 is located at a position deeper than the upper surface 21 of the semiconductor substrate 10. In this example, the upper end 145 of the gate conductive portion 44 is provided at a position lower than the shoulder 104. The gate conductive portion 44 is formed of, for example, polysilicon doped with impurities.

[0119] After polysilicon is deposited to fill the trench, the polysilicon is etched so that the upper surface of the polysilicon is located inside the trench. The uppermost portion of the upper surface of the polysilicon may have a depth of 0.1 μm to 0.7 μm from the upper surface 102 of the semiconductor substrate.

[0120] After the gate conductive portion 44 is formed, P-type impurities are injected and diffused into the surface of the semiconductor substrate 10 to form the base region 14. The P-type impurities are, for example, boron. The diffusion temperature of the base region 14 is, for example, about 1100 degrees. In addition, the gate trench portion 40 may also be formed after the base region 14 is formed.

[0121] Then, in the emitter region forming step S1404, N-type impurities are ion-implanted and diffused into the semiconductor substrate 10. The N-type impurities are, for example, arsenic. The ion implantation of the N-type impurities is performed by tilting the semiconductor substrate 10 by more than 1° and less than 10° relative to the implantation direction (tilting). In addition, the semiconductor substrate can be rotated with the positioning plane or notch of the semiconductor substrate as an indicator so that the ion implantation direction is consistent with the rotation axis. The temperature of the annealing process can be lower than the diffusion temperature of the base region 14. The temperature of the diffusion process can be, for example, less than 1000 degrees, or more than 850°C and less than 1000°C. In addition, P-type impurities such as boron are implanted into the contact region 15 and diffused. The impurities of the emitter region 12 and the contact region 15 can be diffused in the same annealing process.

[0122] Thus, the emitter region 12 is formed. In addition, in S1404, impurities are not only injected into the upper surface 21 of the semiconductor substrate 10, but also into the sidewalls of the gate trench 142 using the gate conductive portion 44 as a mask. In S1404, the injection direction of the impurities has a predetermined slope θ relative to the normal line of the upper surface 21 of the semiconductor substrate 10. The slope θ is, for example, about 5 to 10 degrees. Using this method, the emitter region 12 is formed so that the portion in contact with the gate trench 142 is the deepest.

[0123] As in Fig.12 As described in the above, in the upper region 110, a relatively large amount of impurities injected from the upper surface 21 of the semiconductor substrate 10 diffuses downward. On the other hand, in the lower region 112, a relatively small amount of impurities injected from the sidewall of the gate trench 142 diffuses. Fig.12 The doping concentration distribution is shown.

[0124] The present invention has been described above with embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be added to the above embodiments, which is obvious to those skilled in the art. These added changes or improved forms are also included in the technical scope of the present invention.

[0125] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the devices, systems, programs and methods shown in the specification and drawings can be implemented in any order as long as "before", "before" and the like are not specifically stated and the output of the previous process is not used for the subsequent process. Even if the action flow in the specification and the drawings is described using "first" or "then" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: A semiconductor substrate having a drift region of a first conductivity type provided thereon is provided, the semiconductor device comprising: a gate trench portion, which is provided from the upper surface of the semiconductor substrate to a position reaching the drift region in the depth direction of the semiconductor substrate, and is provided to extend along a predetermined long side direction on the upper surface of the semiconductor substrate; as well as a mesa portion provided inside the semiconductor substrate so as to be in contact with the gate trench portion, The mesa portion has a shoulder portion at an end of the upper surface that contacts the gate trench portion. In a short side cross section perpendicular to the long side direction, when the mesa portion side is regarded as the inner side and the gate trench portion side is regarded as the outer side, the shoulder portion has a shape convex toward the outer side, An emitter region of a first conductivity type is provided in the mesa portion, the emitter region is in contact with the gate trench portion between the upper surface of the semiconductor substrate and the drift region, and has a doping concentration higher than that of the drift region. When the direction perpendicular to both the depth direction and the long side direction is defined as the short side direction, the lower end of the emitter region at a position in contact with the gate trench portion is arranged at a position deeper in the depth direction than the lower end of the emitter region at the center of the mesa portion in the short side direction. The emission area has: an upper area including the center of the table portion; and a lower region which is provided so as to protrude downward from the upper region in a region where the emitter region contacts the gate trench portion; The lower region has a short side wide width portion below a connection portion between the lower region and the upper region, and a width of the short side wide width portion in the short side direction is greater than a width of the connection portion in the short side direction.

2. The semiconductor device according to claim 1, wherein: The shoulder has a side wall that is substantially vertically connected to the upper surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein: A curvature radius of the shoulder portion in the short-side cross section is smaller than 15% of a width of the mesa portion in the short-side direction at a center position of the gate trench portion in the depth direction.

4. The semiconductor device according to claim 2, wherein: A curvature radius of the shoulder portion in the short-side cross section is smaller than 15% of a width of the mesa portion in the short-side direction at a center position of the gate trench portion in the depth direction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that In the short side cross section, an angle formed by a lower surface of the upper region and a side surface of the lower region is smaller than an angle formed by an upper surface of the upper region and a side wall of the shoulder.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that In a region where the emitter region contacts the gate trench portion, a doping concentration distribution in the depth direction of the emitter region has a minimum value at a position corresponding to a connection portion between the lower region and the upper region.

7. The semiconductor device according to claim 5, wherein: In a region where the emitter region contacts the gate trench portion, a doping concentration distribution in the depth direction of the emitter region has a minimum value at a position corresponding to a connection portion between the lower region and the upper region.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that In a long side cross section perpendicular to the short side direction of the mesa portion in an area where the mesa portion contacts the gate groove portion, the lower region has a long side wide portion at a position lower than a connecting portion between the lower region and the upper region, and the width of the long side wide portion in the long side direction is greater than the width of the connecting portion in the long side direction.

9. The semiconductor device according to claim 5, wherein: In a long side cross section perpendicular to the short side direction of the mesa portion in an area where the mesa portion contacts the gate groove portion, the lower region has a long side wide portion at a position lower than a connecting portion between the lower region and the upper region, and the width of the long side wide portion in the long side direction is greater than the width of the connecting portion in the long side direction.

10. The semiconductor device according to claim 6, wherein: In a long side cross section perpendicular to the short side direction of the mesa portion in an area where the mesa portion contacts the gate groove portion, the lower region has a long side wide portion at a position lower than a connecting portion between the lower region and the upper region, and the width of the long side wide portion in the long side direction is greater than the width of the connecting portion in the long side direction.

11. The semiconductor device according to claim 7, wherein: In a long side cross section perpendicular to the short side direction of the mesa portion in an area where the mesa portion contacts the gate groove portion, the lower region has a long side wide portion at a position lower than a connecting portion between the lower region and the upper region, and the width of the long side wide portion in the long side direction is greater than the width of the connecting portion in the long side direction.

12. The semiconductor device according to claim 8, wherein: The length of the long-side wide portion protruding from the connecting portion in the long-side direction is 0.1 μm or more and 0.3 μm or less.

13. The semiconductor device according to claim 9, wherein: The length by which the long-side wide portion protrudes from the connecting portion in the long-side direction is 0.1 μm or more and 0.3 μm or less.

14. The semiconductor device according to claim 10, wherein: The length by which the long-side wide portion protrudes from the connecting portion in the long-side direction is 0.1 μm or more and 0.3 μm or less.

15. The semiconductor device according to claim 11, wherein: The length by which the long-side wide portion protrudes from the connecting portion in the long-side direction is 0.1 μm or more and 0.3 μm or less.

16. The semiconductor device according to any one of claims 1 to 4, characterized in that The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

17. The semiconductor device according to claim 5, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

18. The semiconductor device according to claim 6, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

19. The semiconductor device according to claim 7, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

20. The semiconductor device according to claim 8, wherein The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

21. The semiconductor device according to claim 9, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

22. The semiconductor device according to claim 10, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

23. The semiconductor device according to claim 11, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

24. The semiconductor device according to claim 12, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

25. The semiconductor device according to claim 13, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

26. The semiconductor device according to claim 14, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

27. The semiconductor device according to claim 15, wherein: The table portion has: A base region of the second conductivity type, which is disposed below the emitter region; and contact regions of the second conductivity type, which are arranged alternately with the emitter regions in the long side direction and have a doping concentration higher than that of the base region, The contact area contacts a connection portion of the lower region and the upper region.

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