Semiconductor Devices

Abstract

Embodiments of the present disclosure relate to semiconductor devices. A level shifter is provided that can maintain an operating margin and enhance an over-breakdown voltage prevention effect. The level shifter in the embodiment includes an over-breakdown voltage prevention circuit coupled between a pair of first conductive type cross-coupling transistors and a pair of second conductive type input transistors. The over-breakdown voltage prevention circuit includes a first conductive type first transistor and a second conductive type second transistor coupled in series to each other, and a first conductive type third transistor coupled in series to the first transistor and the second transistor on a higher potential side.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-027636 filed on February 20, 2018 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and is suitably used for, for example, a semiconductor device including a level shifter. Background Art

[0004] A technique is known in which a clamp MOS transistor for exceeding breakdown voltage prevention is added to a cross-coupled level shifter to prevent a voltage not less than a breakdown voltage from being applied to each of MOS (Metal Oxide Semiconductor) transistors.

[0005] For example, Japanese Unexamined Patent Application Publication No. Hei 9(1997)-172368 (Patent Document 1) Figure 1 The level shifter disclosed in the invention includes: a clamp circuit for preventing a breakdown voltage from being exceeded, the clamp circuit clamping an intermediate potential; a latch circuit operating between a high potential power supply and a clamp potential; and a latch inverter circuit operating between the clamp potential and a ground unit.

[0006] Specifically, the latch circuit includes first and second PMOS (P channel MOS) having respective sources coupled to a high potential power supply and respective drains and gates cross-coupled together.

[0007] The clamping circuit includes third and fourth PMOS transistors coupled in series to the aforementioned first and second PMOS transistors, respectively, and first and second NMOS (N-channel MOS) transistors coupled in series to the third and fourth NMOS transistors, respectively. The gate clamping circuit in which the clamping potential is applied to each of these transistors will hereinafter also be referred to as an over-breakdown voltage prevention circuit.

[0008] The latched inverting circuit includes a third fourth NMOS transistor and a fourth NMOS transistor respectively coupled between the first NMOS transistor and the second NMOS transistor and the ground potential. Complementary input signals are input to the gates of the third fourth NMOS transistor and the fourth NMOS transistor. The latched inverting circuit will also be referred to as an input circuit hereinafter.

[0009] [Related technical literature]

[0010] [Patent Document]

[0011] [Patent Document 1] Japanese Unexamined Patent Application Publication No. Hei 9(1997)-172368. Summary of the invention

[0012] When high voltage is applied to a MOS transistor, the gate oxide film is damaged due to FN (Fowler-Nordheim) degradation, etc. This can lead to a situation where the threshold voltage gradually increases and the semiconductor circuit no longer works. The inventors' experience shows that the resistance of a MOS transistor to such high voltage stress is conceivably greatly dependent on the manufacturing process.

[0013] For example, a logic circuit and a nonvolatile memory circuit are manufactured in different processes, the logic circuit has been increasingly miniaturized and operates at a low voltage, and the nonvolatile memory circuit is difficult to miniaturize due to a high voltage applied thereto. Therefore, it is often the case that in a semiconductor integrated circuit in which a nonvolatile memory circuit is embedded in a logic circuit in a hybrid relationship, the resistance of the nonvolatile memory circuit to high voltage stress is insufficient.

[0014] In the case of the level shifter having the configuration disclosed in Patent Document 1 described above, when the clamp potential supplied to the gate of each of the third and fourth PMOS transistors is increased, exceeding the breakdown voltage of the first and second PMOS transistors included in the latch circuit is more reliably prevented. However, increasing the clamp potential of the PMOS transistor included in the exceeding-breakdown-voltage prevention circuit often produces a side effect of reduction in the operating margin of the entire semiconductor circuit, although it depends on the configuration of the semiconductor circuit.

[0015] Other problems and novel features of the present invention will become apparent from the description in this specification and the accompanying drawings.

[0016] A level shifter according to an embodiment includes an over-breakdown voltage prevention circuit coupled between a pair of first conductive type cross-coupling transistors and a pair of second conductive type input transistors. The over-breakdown voltage prevention circuit includes a first conductive type first transistor and a second conductive type second transistor coupled in series to each other, and a first conductive type third transistor coupled in series to the first transistor and the second transistor on a higher potential side.

[0017] The embodiments described above can enhance the exceeding-breakdown-voltage prevention effect on the cross-coupled transistors while suppressing a reduction in the operation margin of the entire semiconductor circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram showing the configuration of a semiconductor device according to a first embodiment;

[0019] Figure 2 It is shown Figure 1A block diagram of the configuration of the flash memory module (FMDL) in FIG.

[0020] Figure 3 A to Figure 3 D is a diagram showing an example of voltages applied to a memory cell during a data write operation in the form of a table;

[0021] Figure 4 A to Figure 4 D is a diagram showing an example of voltages applied to memory cells during a data erase operation in the form of a table;

[0022] FIG. 5A to FIG. 5D It is shown Figure 2 A view showing an example of a specific configuration of a high voltage switching circuit in FIG.

[0023] Figure 6 is a circuit diagram showing the configuration of a level shifter used in the semiconductor device in the first embodiment;

[0024] Figure 7 It is shown that the application Figure 3 A and Figure 3 B is a timing diagram of an example of the voltage of the memory strobe MG;

[0025] Figure 8 is a circuit diagram showing a configuration of a level shifter in a semiconductor device in a second embodiment;

[0026] Fig. 9 is a circuit diagram showing a configuration of a level shifter in a semiconductor device in a third embodiment;

[0027] Fig.10 It shows that the generated Fig. 9 A view of an example of a circuit for controlling a control signal ctrl6 in FIG.

[0028] Fig.11 is a circuit diagram showing a configuration of a level shifter in a semiconductor device in a fourth embodiment;

[0029] Fig.12 is a circuit diagram showing a configuration of a level shifter in a semiconductor device in a fifth embodiment;

[0030] Fig.13 It shows that the generated Fig.12 A view of an example of a circuit for controlling signals ctrl7 and ctrl8 in FIG.

[0031] Fig.14 is a circuit diagram showing a configuration of a level shifter in a semiconductor device in a sixth embodiment;

[0032] Fig.15is a block diagram showing a configuration of a level shifter in a semiconductor device in a seventh embodiment; and

[0033] Fig.16 It is shown Fig.15 A circuit diagram of an example of a configuration of a VDD-VCC level shifter. DETAILED DESCRIPTION

[0034] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. A microcomputer including a flash memory module will be described below as an example of a semiconductor device including a level shifter, but the semiconductor device is not limited to the following example. For example, the semiconductor device may also be formed only of a flash memory. The technology disclosed in the present invention may be applied to any semiconductor device including a level shifter.

[0035] In the following description, like or equivalent parts are denoted by like reference numerals, and description thereof is not repeated.

[0036] <First Embodiment>

[0037] [Microcomputer]

[0038] Figure 1 is a block diagram showing the configuration of a semiconductor device according to a first embodiment. Figure 1 A configuration of a microcomputer or microcontroller unit (MCU) 31 is shown as an example of a semiconductor device.

[0039] refer to Figure 1 , the microcomputer 31 is formed in one semiconductor chip made of single crystal silicon or the like using, for example, a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit manufacturing technology or the like.

[0040] like Figure 1 As shown, the microcomputer 31 includes a central processing unit (CPU) 32, a random access memory (RAM) 35, and a flash memory module (FMDL) 36. The central processing unit 32 includes an instruction control unit and an execution unit that executes instructions. The random access memory 35 is used as a work area for the central processing unit 32, etc. The flash memory module 36 is provided as a non-volatile memory module that stores data, programs, etc.

[0041] The microcomputer 31 also includes a direct memory access controller (DMAC) 33, a bus interface circuit (BIF) 34, a flash sequencer (FSQC) 37, external input / output ports (PRT) 38 and 39, a timer (TMR) 40, a clock pulse generator (CPG) 41, a high-speed bus (HBUS) 42, and a peripheral bus (PBUS) 43.

[0042] The bus interface circuit 34 performs bus interface control or bus bridge control between the high-speed bus 42 and the peripheral bus 43. The flash sequencer 37 performs command access control to the flash memory module (FMDL) 36. The clock pulse generator 41 generates an internal clock CLK for controlling the microcomputer 31.

[0043] The bus configuration in the microcomputer 31 is not particularly limited. Figure 1 In the case of the high-speed bus (HBUS) 42 and the peripheral bus (PBUS) 43 are provided. Each of the high-speed bus 42 and the peripheral bus 43 includes a data bus, an access bus, and a control bus, but the bus included therein is not particularly limited. By providing two buses, that is, the high-speed bus 42 and the peripheral bus 43, it is possible to reduce the load on each of the buses compared to the load on a single common bus when all circuits are coupled to a single common bus and ensure high-speed access operation.

[0044] The central processing unit 32, the direct memory access controller 33, the bus interface circuit 34, the random access memory 35, and the flash memory module 36 are coupled to the high-speed bus 42. The flash sequencer 37, the external input / output ports 38 and 39, the timer 40, and the clock pulse generator 41 are coupled to the peripheral bus 43.

[0045] The microcomputer 31 also includes a clock terminal XTAL coupled to an oscillator, a clock terminal EXTAL supplied with an external clock, an external hardware standby terminal STB giving an instruction to establish a standby state, and an external reset terminal RES giving an instruction to perform a reset. The microcomputer 31 also includes respective terminals for receiving a power supply voltage VDD for a digital circuit, a power supply voltage VDD for an analog circuit, and a ground voltage VSS.

[0046] exist Figure 1 In the figure, for convenience, the flash sequencer 37 as a logic circuit and the flash memory module 36 configured as an array are shown as different circuit blocks because the flash sequencer 37 and the flash memory module 36 are designed using different CAD tools. However, the flash sequencer 37 and the flash memory module 36 are combined to form the flash memory 46.

[0047] The flash memory module 36 is coupled to the high-speed bus (HBUS) 42 via a read-only high-speed access port (HACSP) 45. The central processing unit 32 or the direct memory access controller 33 can make a read access from the high-speed bus 42 to the flash memory module 36 via the high-speed access port 45. When making a write access or initialization access to the flash memory module 36, the central processing unit 32 or the direct memory access controller 33 issues a command to the flash sequencer 37 via the bus interface circuit 34 through the peripheral bus (PBUS) 43. In response to the command, the flash sequencer 37 controls the initialization of the flash memory module or the write operation thereof from the peripheral bus PBUS through the low-speed access port (LACSP) 44.

[0048] [Flash Module]

[0049] Figure 2 It is shown Figure 1 A block diagram of the configuration of the flash memory module (FMDL) in FIG.

[0050] The flash memory module 36 includes a memory cell array 51 , a CG driver circuit 52 , an MG driver circuit 53 , a high-voltage decoding circuit 54 , a high-voltage switch circuit 55 , an enhancement circuit 56 , and a sense amplifier / write control circuit 57 .

[0051] The memory cell array 51 includes a plurality of memory cells MC arranged in rows and columns. Figure 2 Only one of the memory cells MC is shown as a representative. Figures 2 to 4 As shown, a MONOS (metal oxide nitride oxysilicon) memory cell MC will be described by way of example. However, the technology in the present disclosure can also be applied to memory cells MC of other structures, such as a floating gate memory cell MC. Figure 3 A to 3D describe the detailed structure of the MONOS memory cell MC.

[0052] The memory cell array 51 further includes a plurality of memory strobe lines MGL, a plurality of control strobe lines CGL, and a plurality of source lines SL provided as control signal lines for the memory cells MC corresponding to the respective rows of the plurality of memory cells MC and a plurality of bit lines BL provided corresponding to the respective columns of the plurality of memory cells MC. Figure 2 , a control signal line coupled to one of the memory cells MC is shown as a representative.

[0053] The CG driver circuit 52 includes a plurality of drivers 521 that generate control gate (CG) signals that drive the control signal lines CGL.

[0054] The MG driver circuit 53 includes a plurality of drivers 531 that generate memory gate (MG) signals that drive the memory gate lines MGL.

[0055] The boost circuit 56 has an embedded charge pump circuit, generates boost voltages of different magnitudes, and provides the generated boost voltages to the voltage decoding circuit 54. Specifically, the boost circuit 56 generates a write MG positive voltage VPPA, a write non-selected MG positive voltage VPPC, a write SL positive voltage VPPB, an over-breakdown voltage prevention positive voltage VPPR, and an erase MG negative voltage VEEM.

[0056] Hereinafter, the write MG positive voltage VPPA may be referred to as a high power supply voltage VPPA, the write non-selected MG positive voltage VPPC may be referred to as an intermediate voltage VPPC, and the exceeding breakdown voltage prevention positive voltage VPPR may be referred to as an intermediate voltage VPPR. The intermediate voltage VPPC and the intermediate voltage VPPR have values ​​between the corresponding values ​​of the high power supply voltage VPPA and the ground voltage VSS. In the above embodiment, the intermediate voltage VPPC is set to a value between the corresponding values ​​of the high power supply voltage VPPA and the intermediate voltage VPPC.

[0057] The high-voltage switch circuit 55 selects various boost voltages generated from the boost circuit 56 to generate a selected block higher potential MG voltage VMGPP, a selected block lower potential MG voltage VMGPN, a non-selected block higher potential MG voltage VMGNP, a non-selected block lower potential MG voltage VMGNN, a selected SL voltage VSLP, and a non-selected SL voltage VSLN. The high-voltage switch circuit 55 supplies the generated voltages to the high-voltage decoding circuit 54 as decoder power supply voltages.

[0058] The high voltage decode circuit 54 supplies a high voltage to the MG driver circuit 53 and the source line SL. More specifically, the high voltage decode circuit 54 supplies a decode signal to the MG driver circuit 53 using a decoder power supply voltage generated from the high voltage switch circuit 55 and generates a source line signal to be supplied to the source line SL.

[0059] The sense amplifier / write control circuit 57 reads information stored in a selected memory cell via the bit line BL and writes information to be stored in the selected memory cell through the bit line BL.

[0060] [Voltage supplied to memory cell]

[0061] Next, a description will be given of an example of voltages supplied to selected / non-selected memory cells in selected / non-selected blocks from the CG driver circuit 52, the MG driver circuit 53, the high voltage decoding circuit 54, and the sense amplifier / write control circuit 57 all described above. Figure 3 A to Figure 3 D. Figure 4 A to Figure 3The numerical values ​​shown in D, etc. are given by way of example for illustrative purposes, and the supplied voltages are not limited to these numerical values.

[0062] (Example of voltage applied to a memory cell during a data write operation)

[0063] Figure 3 A to Figure 3 D is a diagram showing an example of voltages applied to memory cells during a data write operation in the form of a table.

[0064] First, refer to Figure 3 A, a simple description of the configuration of the MONOS nonvolatile memory cell MC will be given. The memory cell MC includes a control strobe (CG) 61, a silicon nitride film 62, a memory strobe (MG) 63, a source 64, and a drain 65. The control strobe 61 is formed on the top surface of the P-type silicon substrate 60 via an insulating layer (not shown). The silicon nitride film 62 is formed as an ONO (oxide-nitrogen-oxide) film including a silicon oxide film (not shown), a silicon nitride film 62, and a silicon oxide film (not shown) on the sidewall of the control strobe 61. On the ONO film, a memory strobe 63 having a sidewall structure is formed. The source 64 and the drain 65 are formed by implanting N-type impurities into the P-type silicon substrate 60 located on both sides of the strobes 61 and 63. The source 64 is coupled to the corresponding source line SL, while the drain 65 is coupled to the corresponding bit line BL.

[0065] Next, a description will be given of the voltage applied to the memory cell MC during the data write operation. Since the memory gate MG is an electrode to which such a high voltage exceeding the breakdown voltage prevention is applied, the following will focus on the voltage applied to the memory gate MG.

[0066] The voltage VMGPP is applied to Figure 3 A selected memory strobe MG of a selected memory cell in a selected block is shown. During a write operation, a voltage VPPA is selected as VMGPP. For example, the voltage VPPA has a value of about 6.4 to 11 [V].

[0067] The voltage VMGPN is applied to Figure 3 The non-selected memory gate MG of the non-selected memory cells in the selected block shown in B. During the write operation, the voltage VPPC is selected as VMGPN. For example, the voltage VPPC has a value of about 3.5 [V].

[0068] The voltage VMGNP is applied to Figure 3The selected memory strobe MG of the selected memory cells in the non-selected block is shown in C. During a write operation, the voltage VPPC is selected as VMGNP. For example, the voltage VPPC has a value of about 3.5 [V].

[0069] The voltage VMGNN is applied to Figure 3 The non-selected memory gate MG of the non-selected memory cells in the non-selected block shown in D. During the write operation, the voltage VDD is selected as VMGNN. For example, the voltage VDD has a value of about 1.5 [V].

[0070] (Example of Voltage Applied to Memory Cells During Data Erase Operation)

[0071] Figure 4 A to 4D are diagrams showing examples of voltages applied to memory cells during data erase operations in the form of tables. Since the memory gate MG is an electrode to which such a negative high voltage exceeding the breakdown voltage is applied, the following will focus on the voltage applied to the memory gate MG.

[0072] The voltage VMGPN is applied to the Figure 3 A selected memory strobe MG of a selected memory cell in a selected block is shown. During an erase operation, a voltage VEEM is selected as VMGPN. For example, the voltage VEEM has a value of about -3.3 to -8 [V].

[0073] The voltage VMGPP is applied to Figure 3 The non-selected memory gate MG of the non-selected memory cells in the selected block shown in B. During the erase operation, the voltage VDD is selected as VMGPP. For example, the voltage VDD has a value of about 1.5 [V].

[0074] Does not exist Figure 4 The non-selected blocks shown in C have this state of selected memory during the erase operation. Figure 4 As shown in D, the common voltage VMGNP is applied to all memory gates MG in the non-selected block during the erase operation. During the erase operation, the voltage VDD is selected as VMGNP. For example, the voltage VDD has a value of about 1.5 [V].

[0075] [High voltage switching circuit]

[0076] FIG. 5A to FIG. 5D It is shown Figure 2 A view of an example of a specific configuration of a high-voltage switching circuit.

[0077] Figure 5AA circuit is shown that generates voltage VMGPP. To output node 86 for voltage VMGPP, voltage VPPA is provided through switch 71 and voltage VDD is provided via switch 72. Depending on the operating mode, either voltage VPPA or voltage VDD is selected.

[0078] One or more PMOS transistors are used as each of the switches 71 and 72. Figure 5A , for simpler explanation, each of the switches 71 and 72 is shown as a PMOS transistor. However, when necessary for the breakdown voltage, a plurality of PMOS transistors may also be used or a MOS transistor may also be inserted to prevent the breakdown voltage from exceeding. In the same manner as for the switches 73 to 78 described later, if necessary for the breakdown voltage, a plurality of MOS transistors may also be used or a MOS transistor may also be inserted to prevent the breakdown voltage from exceeding.

[0079] The on / off of each of the switches 71 and 72 is controlled by the VDD level selection signals selpp_a and selpp_c. For the selection signal selpp_c, a level shifter is not required. The VDD level selection signal selpp_c is directly input to the gate of the PMOS transistor included in the switch 72.

[0080] On the other hand, the VDD level selection signal selpp_a is converted into a VPPA level signal by the positive voltage level shifter 81. The VPPA level selection signal selpp_a is input to the gate of the PMOS transistor included in the switch 71. The voltage VPPA is input to the terminal up of the positive voltage level shifter 81. Since the voltage VPPA is a high voltage, the positive voltage level shifter 81 needs to be prevented from exceeding the breakdown voltage.

[0081] Figure 5B A circuit for generating voltage VMGPN is shown. For output node 87 for voltage VMGPN, voltage VPPC is provided through switch 73 and voltage VEEM is provided via switch 74. Depending on the operating mode, voltage VPPC or voltage VEEM is selected. One or more PMOS transistors are used as switch 73, while one or more NMOS transistors are used as switch 74.

[0082] The on / off of the switch 73 is controlled by the VDD level selection signal selpn_c. The VDD level selection signal selpn_c is converted into a VPPC level signal by the positive voltage level shifter 83. The VPPC level selection signal selpn_c is input to the gate of the PMOS transistor included in the switch 73. The voltage VPPC is input to the terminal of the positive voltage level shifter 83. Since the voltage VPPC is not a high voltage, the positive voltage level shifter 83 does not need to exceed the breakdown voltage to prevent.

[0083] The on / off of the switch 74 is controlled by the VDD level selection signal selpn_e. The VDD level selection signal selpn_e is converted into a VEEM level signal by the negative voltage level shifter 84. The VEEM level selection signal selpn_e is input to the gate of the NMOS transistor included in the switch 74. The voltage VEEM is input to the terminal un of the negative voltage level shifter 84.

[0084] Figure 5C A circuit for generating voltage VMGNP is shown. For output node 88 for voltage VMGNP, voltage VPPC is provided through switch 75 and voltage VDD is provided through switch 76. Depending on the operating mode, voltage VPPC or voltage VDD is selected. One or more PMOS transistors are used as each of switches 75 and 76.

[0085] The on / off of the switches 75 and 76 is controlled by the VDD level selection signals selnp_c and selpp_d. For the selection signal selpp_d, a level shifter is not required. The VDD level selection signal selpp_d is directly input to the gate of the PMOS transistor included in the switch 76.

[0086] On the other hand, the VDD level selection signal selnp_c is converted into a VPPC level signal by the positive voltage level shifter 85. The VPPC level selection signal selnp_c is input to the gate of the PMOS transistor included in the switch 75. The voltage VPPC is input to the terminal up of the positive voltage level shifter 85. Since the voltage VPPC is not a high voltage, the positive voltage level shifter 85 does not need to exceed the breakdown voltage prevention.

[0087] Figure 5D A circuit for generating voltage VMGNN is shown. For output node 89 for voltage VMGNN, voltage VDD is provided through switch 77 and voltage VSS is provided through switch 78. Depending on the operating mode, voltage VDD or voltage VSS is selected. One or more PMOS transistors are used as switch 77. One or more NMOS transistors are used as switch 78.

[0088] The on / off of switches 77 and 78 is controlled by VDD level selection signals selnn_d and selnn_s. For the selection signal selnn_d or selnn_s, a level shifter is not required. The selection signal selnn_s is directly input to the gate of the PMOS transistor included in the switch 77. The selection signal selnn_s is directly input to the gate of the NMOS transistor included in the switch 78.

[0089] Table 1 is composed of Figure 2 A collection of examples of enhancement circuits selected by the high voltage switch circuit. Table 1 Examples of enhancement circuits selected by the high voltage switch circuit

[0090] The status of writing Erased Status VMGPP VPPA VDD VMGPN VPPC VEEM VMGNP VPPC VDD VMGNN VDD VSS

[0091] As shown in Table 1, the high-voltage switch circuit 55 selects VPPA as the output voltage VMGPP in the written state and selects VDD as the output voltage VMGPP in the erased state. The high-voltage switch circuit 55 selects VPPC as the output voltage VMGPN in the written state and selects VEEM as the output voltage VMGPN in the erased state. The high-voltage switch circuit 55 selects VPPC as the output voltage VMGNP in the written state and selects VDD as the output voltage VMGNP in the erased state. The high-voltage switch circuit 55 selects VDD as the output voltage VMGNN in the written state and selects VSS as the output voltage VMGNN in the erased state.

[0092] Note that in order to correspond to a verification mode, a test mode, and the like each as an operation mode in a state other than a written state and an erased state, an additional switch may be provided in the high-voltage switch circuit 55 .

[0093] As shown in Figure 5, in order to form Figure 2 The high-voltage switch circuit 55 of the positive voltage level shifter 81 requires the level shifters 81 and 83 to 85. Among them, for the positive voltage level shifter 81, it is necessary to consider the over-breakdown voltage prevention. This is because, when the voltage VPPA is applied to the memory strobe MG during the write operation, a high voltage of about 11V, for example, is used, but even if the MOS transistor included in the positive voltage level shifter 81 is of a high breakdown voltage type, its breakdown voltage is about 10V at maximum. Therefore, it is necessary to perform over-breakdown voltage prevention control and prevent the high power supply voltage VPPA from being directly applied to each of the MOS transistors included in the positive voltage level shifter 81.

[0094] [Example of Configuration of Level Shifter]

[0095] Figure 6 is a circuit diagram showing the configuration of a level shifter used in the semiconductor device in the first embodiment. Figure 6 The level shifter 100 in the embodiment can be applied to Figure 5A Positive voltage level shifter 81 in.

[0096] refer to Figure 6, the level shifter 100 includes a high voltage node 103 to which a high power supply voltage VPPA is input, a ground node 104 to which a ground voltage VSS is input, a level shifter stage 101 that converts VDD level complementary input signals inp and inn into VPPA level signals, and a driver stage 102 provided after the level shifter stage 101. In the present disclosure, the ground voltage VSS is also referred to as a reference voltage, the high voltage node 103 is also referred to as a first power supply node, and the ground node 104 is also referred to as a second power supply node. For example, the high power supply voltage VPPA is approximately 6.4 to 11 [V] and is generated by a charge pump circuit embedded in the enhancement circuit 56 to vary according to a control signal output from the flash sequencer 37.

[0097] The level shifter stage 101 includes a latch circuit 110 , an input circuit 111 to which complementary input signals inp and inn are input, an exceeding breakdown voltage prevention circuit 112 coupled between the latch circuit 110 and the input circuit 111 , and clamp NMOS transistors MNF1P and MNF1N.

[0098] The latch circuit 110 includes a pair of cross-coupled PMOS transistors MPCCP and MPCCN having respective sources coupled to the high voltage node 103. The PMOS transistors MPCCP and MPCCN have respective gates and drains that are cross-coupled together. Specifically, the gate of the PMOS transistor MPCCP and the drain of the PMOS transistor MPCCN are coupled together, while the drain of the PMOS transistor MPCCP and the gate of the PMOS transistor MPCCN are coupled together.

[0099] The input circuit 111 includes a pair of input NMOS transistors MNINP and MNINN. Each of the sources of the input NMOS transistors MNINP and MNINN is coupled to the ground node 104. The input signal inn is input to the gate of the input NMOS transistor MNINP, while the input signal inp is input to the gate of the input NMOS transistor MNINN.

[0100] The over-breakdown voltage prevention circuit 112 includes over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N, over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N, and additional over-breakdown voltage prevention transistors MPE3P and MPE3N. Compared to the over-breakdown voltage prevention circuit in Patent Document 1 described above, the over-breakdown voltage prevention circuit 112 is different therefrom in that additional over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are provided.

[0101] More specifically, the over-breakdown voltage prevention MOS transistors MPE3P, MPE1P, and MNE1P are arranged in this order and are coupled in series between the drain of the PMOS transistor MPCCP and the drain of the input NMOS transistor MNINP. Similarly, the over-breakdown voltage prevention MOS transistors MPE3N, MPE1N, and MNE1N are arranged in this order and are coupled in series between the drain of the PMOS transistor MPCCN and the drain of the input NMOS transistor MNINN. Currently, in the over-breakdown voltage prevention circuit 112, the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are provided on the highest potential side, while the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are provided on the lowest potential side. The over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are coupled between the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N and the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N, respectively.

[0102] In the following description, the corresponding coupling nodes between the cross-coupled PMOS transistors MPCCP and MPCCN and the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are referred to as intermediate nodes hhp and hhn. The corresponding coupling nodes between the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N and the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are referred to as intermediate nodes hxp and hxn. The corresponding coupling nodes between the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N and the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are referred to as intermediate nodes mmp and mmn. The corresponding coupling nodes between the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N and the input NMOS transistors MNINP and MNINN are referred to as intermediate nodes 11p and 11n.

[0103] The intermediate voltage VPPC is input to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N. The intermediate voltage VPPR is input to each of the gates of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N. The intermediate voltages VPPR and VPPC have values ​​between the ground voltage VSS and those of the high power supply voltage VPPA. For example, the intermediate voltage VPPR is 5.5V, the intermediate voltage VPPC is 3.0V, and the intermediate voltage VPPR is set to a value between those of the high power supply voltage VPPA and the intermediate voltage VPPC.

[0104] The exceeding breakdown voltage prevention PMOS transistors MPE3P and MPE3N have respective gates and drains coupled together. In other words, each of the exceeding breakdown voltage prevention PMOS transistors MPE3P and MPE3N is a diode-coupled transistor.

[0105] The clamp NMOS transistor MNF1P is coupled between the source of the over-breakdown voltage prevention PMOS transistor MPE3P (i.e., the intermediate node hhp) and the high voltage node 103. Similarly, the clamp NMOS transistor MNF1N is coupled between the source of the over-breakdown voltage prevention PMOS transistor MPE3N (i.e., the intermediate node hhn) and the high voltage node 103. For example, the intermediate voltage VPPR is applied to each of the gates of the clamp NMOS transistors MNF1P and MNF1N. The clamp NMOS transistors MNF1P and MNF1N are intended to clamp the voltages at the intermediate nodes hhp and hhn when the corresponding PMOS transistors MPCCP and MPCCN are turned off.

[0106] The driver 102 includes driver PMOS transistors MPDRP and MPDRN, driver NMOS transistors MNDRP and MNDRN, over-breakdown voltage prevention PMOS transistors MPE2P and MPE2N, and over-breakdown voltage prevention NMOS transistors MNE2P and MNE2N.

[0107] The driver PMOS transistors MPDRP and MPDRN have respective sources coupled to the high voltage node 103 and respective gates coupled to the intermediate nodes hhp and hhn. Complementary output signals outp and outn are output from respective drains of the driver PMOS transistors MPDRP and MPDRN.

[0108] The driver PMOS transistors MPDRP and MPDRN have respective sources coupled to the ground node 104. An input signal inn is input to the gate of the driver NMOS transistor MNDRP, while an input signal inp is input to the gate of the driver NMOS transistor MNDRN.

[0109] Similarly, the over-breakdown voltage prevention PMOS transistor MPE2P and the over-breakdown voltage prevention NMOS transistor MNE2P are arranged in this order and coupled in series between the drain of the driver PMOS transistor MPDRP and the drain of the driver NMOS crystal MNDRP. Similarly, the over-breakdown voltage prevention PMOS transistor MPE2N and the over-breakdown voltage prevention NMOS transistor MNE2N are arranged in this order and coupled in series between the drain of the driver PMOS transistor MPDRN and the drain of the driver NMOS crystal MNDRN.

[0110] An intermediate voltage VPPC (eg, 3.0V) is applied to each of the gates of the over-breakdown voltage preventing PMOS transistors MPE2P and MPE2N. An intermediate voltage VPPR (eg, 5.5V) is applied to each of the gates of the over-breakdown voltage preventing NMOS transistors MNE2P and MNE2N.

[0111] The back gate (i.e., substrate) of each of the above-described MOS transistors except the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is coupled to the source of the transistor. Each of the back gates of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is coupled to the high voltage node 103 to receive the high power supply voltage VPPA.

[0112] [Level Shifter Operation]

[0113] Next, a description will be given of the prevention of exceeding the breakdown voltage, in particular. Figure 6 Note that the following numerical values ​​are exemplary for illustrative purposes and are not limiting.

[0114] [Overview of the overall operation of the level shifter]

[0115] refer to Figure 6 , in response to the VDD level complementary input signals inp and inn, one of the input NMOS transistors MNINP and MNINN is brought into a conducting state, while the other one thereof is brought into a cutting-off state.

[0116] For example, it is assumed that the voltage of the input signal inp is VDD (e.g., 1.5 V) and the voltage of the input signal inn is VSS (e.g., 0 V). In this case, the input NMOS transistor NMINN of the input circuit 111 is brought into a conducting state, while the input NMOS transistor MNINP of the input circuit 111 is brought into a cut-off state. In addition, the driver NMOS transistor MNDRN in the driver stage 102 is brought into a conducting state, while the driver NMOS transistor MNDRP in the driver stage 102 is brought into a cut-off state.

[0117] When the input NMOS transistor MNINN is brought into the on state, each of the intermediate nodes 11n and mmn has a voltage VSS (0V). As a result, the gate voltage of the PMOS transistor MPCCP included in the latch circuit 110 shifts to a low level to bring the PMOS transistor MPCCP into the on state and shifts the voltage at the intermediate node hhp to a high level, that is, a high power supply voltage VPPA (e.g., 11V). On the other hand, the PMOS transistor MPCCN is brought into the off state to shift the voltage at the intermediate node hhn to a low level.

[0118] In addition, the voltage at the intermediate node hhp shifts to a high level (VPPA) and the voltage at the intermediate node hhn shifts to a low level to bring the driver PMOS transistor MPDRP included in the driver stage 102 into a conductive state and bring the driver PMOS transistor MPDRN included in the driver stage 102 into a cut-off state. Finally, the output signal outp shifts to a high level (VPPA), and the output signal outn shifts to a low level.

[0119] In contrast to the above, it is assumed that the voltage of the input signal inp is VSS (e.g., 0V) and the voltage of the input signal inn is VDD (e.g., 1.5V). In this case, the PMOS transistor MPCCP included in the latch circuit 110 is brought into a cut-off state to shift the voltage at the intermediate node hhp to a low level, and the PMOS transistor MPCCN is brought into a conduction state to shift the voltage at the intermediate node hhn to a high level (VPPA). As a result, the driver PMOS transistor MPDRP included in the driver stage 102 is brought into a cut-off state, and the driver PMOS transistor MPDRN included in the driver stage 102 is brought into a conduction state. Finally, the output signal outp shifts to a low level, and the output signal outn shifts to a high level (VPPA).

[0120] (Function of the circuit to prevent the voltage from exceeding the breakdown voltage)

[0121] Next, a description will be given of the function of the over-breakdown voltage prevention circuit 112. First, an intermediate voltage VPPR (e.g., 5.5V) is applied to each of the gates of the over-breakdown voltage prevention NMOS transistors MNE1P, MNE1N, MNE2P, and MNE2N. This limits each of the drain voltages of the input NMOS transistors MNINP and MNINN and each of the drain-source voltages of the driver NMOS transistors MNDRP and MNDRN to the intermediate voltage VPPR (5.5V). Thus, the corresponding breakdown voltages of the NMOS transistors MNINP, MNINN, MNDRP, and MNDRN are successfully prevented from being exceeded.

[0122] The intermediate voltage VPPC (e.g., 3.0V) is applied to each of the gates of the over-breakdown voltage prevention PMOS transistors MNE1P, MNE1N, MPE2P, and MPE2N. This limits the voltage applied between the source and drain of each of the PMOS transistors MPCCP and MPCCN and the driver PMOS transistors MPDRP and MPDRN included in the latch circuit 110 to VPPA-VPPC (e.g., 11V-3V=8V).

[0123] By further causing a current of an appropriate size to flow to the over-breakdown voltage prevention PMOS transistor MPE3P through the clamp NMOS transistor MNF1P, a potential difference of not less than the threshold voltage Vth (about 1V) can be generated between the source and drain of the over-breakdown voltage prevention PMOS transistor MPE3P (i.e., between the intermediate node hhp and the intermediate node hxp). Similarly, by causing a current of an appropriate size to flow to the over-breakdown voltage prevention PMOS transistor MPE3N through the clamp NMOS transistor MNF1N, a potential difference of not less than the threshold voltage Vth (about 1V) can be generated between the source and drain of the over-breakdown voltage prevention PMOS transistor MPE3P (i.e., between the intermediate node hhp and the intermediate node hxp). Therefore, the over-breakdown voltage prevention effect on each of the PMOS transistors MPCCP and MPCN and the driver PMOS transistors MPDRP and MPDRN included in the latch circuit 110 can be further enhanced.

[0124] Regardless of the on / off state of each of the PMOS transistors MPCCP and MPCCN included in the latch circuit 110, it is important that current is continuously supplied to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. Unless there is current supplied to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, when there is leakage current in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, the potential at the intermediate nodes hhp and hhn is no longer maintained (i.e., the potential at the intermediate nodes hhp and hhn drops to the potential at the intermediate nodes hxp and hxn). As a result, it is not possible to obtain a sufficient over-breakdown voltage prevention effect on each of the PMOS transistors MPCCP and MPCN and the driver PMOS transistors MPDRP and MPDRN included in the latch circuit 110.

[0125] In order to prevent the situation described above, clamping NMOS transistors MNF1P and MNF1N are provided. When an intermediate voltage VPPR (e.g., 5.5V) is applied to each of the gates of the clamping NMOS transistors MNF1P and MNF1N to reduce the voltage at the intermediate nodes hhp and hhn to VPPR-Vthn, the current prevents the PMOS transistors MPE3P and MPE3N from being supplied thereto from exceeding the breakdown voltage. The voltage Vthn mentioned herein is the threshold voltage of each of the clamping NMOS transistors MNF1P and MNF1N, which is approximately 1V. As a result, the voltage at the intermediate nodes hhp and hhn is clamped to a value of approximately 5.5-1=4.5[V].

[0126] In practice, the voltage at the intermediate nodes hhp and hhn depends on the size ratio between the clamping NMOS transistors MNF1P and MNF1N and the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. Specifically, when the size (i.e., gate width) of the clamping NMOS transistors MNF1P and MNF1N is reduced, the current supplied to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is reduced, so that the corresponding source-drain voltage of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N approaches Vthp. As a result, the lower limit value of the voltage at the intermediate nodes hhp and hhn approaches 4V. On the contrary, when the size of the clamping NMOS transistors MNF1P and MNF1N is increased, the current supplied to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is increased to increase the corresponding source-drain voltage of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. As a result, the voltages of the voltages at the intermediate nodes hhp and hhn approach 4.5 V as a maximum voltage determined by the respective gate voltages of the clamp NMOS transistors MNF1P and MNF1N.

[0127] As a result of the foregoing, the lower limit voltage at the intermediate nodes hxp and hxn is the intermediate voltage VPPC (3.0 V), and the lower limit voltage at the intermediate nodes hhp and hhn is 4 to 4.5 V. Therefore, the additional over-breakdown voltage prevention effect achieved by the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is 1 to 1.5 V.

[0128] [Effects of the First Embodiment]

[0129] As described above, according to the first embodiment, in the current path coupling the latch circuit 110 and the input circuit 111 both included in the level shifter 100, not only the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N and the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are provided, but also the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are provided. This can reduce the maximum voltage applied between the gate and the source of each of the cross-coupled PMOS transistors MPCCP and MPCCN and the driver PMOS transistors MPDRP and MPDRN requiring over-breakdown voltage prevention.

[0130] A description will be given using an example of specific numerical values. When the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are not provided, the maximum potential difference between the high-voltage node 103 and each of the intermediate nodes hhp and hhn is VPPA (11V) -VPPC (3V) = 8V. On the other hand, by providing over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, the maximum potential difference between the high-voltage node 103 and each of the intermediate nodes hhp and hhn drops to VPPA (11V) -VPPC (3V) - (1 to 1.5V) = 6.5 to 7V. Therefore, the maximum voltage between the gate and the source of each of the cross-coupled PMOS transistors MPCCP and MPCCN and the driver PMOS transistors MPDRP and MPDRN can be reduced from 8V to 6.5 to 7V.

[0131] When a high source-gate voltage is applied to a MOS transistor in an on state for a long time, the threshold voltage Vth of the MOS transistor deteriorates (i.e., increases) due to FN degradation. Specifically, when the threshold voltage Vth of each of the cross-coupled PMOS transistors MPCCP and MPCCN included in the latch circuit 110 increases, the inversion margin of the latch circuit 100 deteriorates significantly. When the threshold voltage Vth of each of the driver PMOS transistors MPDRP and MPDRN increases, the driving capability of the driver stage 102 deteriorates significantly. In the configuration of the first embodiment, the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are provided to be able to prevent the property deterioration of the level shifter due to such FN degradation as described above.

[0132] In addition, clamping NMOS transistors MNF1P and MNF1N for clamping the potential at the intermediate nodes hhp and hhn are provided to allow the current supplied to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N to be adjusted. As a result, the lower limit voltage at the intermediate nodes hhp and hhn can be adjusted. In addition, it is possible to prevent the voltage at the intermediate nodes hhp and hhn from dropping too much due to the leakage current in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N and thus avoid the situation where the over-breakdown voltage prevention effect is not achieved.

[0133] <Second Embodiment>

[0134] In the second embodiment, a description will be given of a case in which control is performed such that in a stage in which a write pulse is applied during a data write operation, the voltage VPPA is set to a high voltage of, for example, about 11 V, and in a stage in which a write address is selected, the voltage VPPA is set to a voltage lower than 11 V. This is because when the latch circuit is inverted using a high voltage applied between the gate and the source of each of MPCCP and MPCCN included in the latch circuit 110, the PMOS transistors MPCCP and MPCCN may be broken down.

[0135] As described in the first embodiment, by providing additional over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, it is possible to apply a voltage VPPA having a higher value to the level shifter. However, when the voltage VPPA is reduced to a lower value to invert the latch circuit 110 as described above, it may be difficult to invert the latch circuit 110 due to the provision of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. As a result, it becomes difficult for the level shifter to output correct output signals outp and outn according to the input signals inp and inn.

[0136] Therefore, in the second embodiment, a description will be given of a level shifter that allows the above-described problems to be solved. Specifically, a bypass path that bypasses the over-breakdown voltage prevention circuit 112 is provided in the level shifter stage 101 .

[0137] [Control of Voltage for Memory Gate MG]

[0138] First, the following will refer to Figure 7 Control of the voltage for the memory gate MG in this second embodiment is described.

[0139] Figure 7 It is shown that the application Figure 3 A and Figure 3 B is a timing diagram of an example of the voltage of the memory gate MG.

[0140] Figure 7 The upper graph shown in shows the temporal variation of the voltage VMGPP applied to the selected memory strobe MG in the selected block during a write operation. Figure 7 The lower graph shown in FIG. 1 shows the temporal variation of the voltage VMGPN applied to the non-selected memory strobes MG in the selected block during a write operation. Figures 5A to 5D As described, the voltage applied to the selected memory gate MG is the high power supply voltage VPPA, and the voltage applied to the non-selected memory gates is the intermediate voltage VPPC. The values ​​of the high power supply voltage VPPA and the intermediate voltage VPPC are changed by controlling the charge pump that generates the high power supply voltage VPPA and the intermediate voltage VPPC.

[0141] refer to Figure 7 , before time t1, a phase in which an address is selected and switched is established. In this phase, a voltage VMGPP (VPPA) applied to a selected memory strobe MG is as low as about 5V, while a voltage applied to a non-selected memory strobe MG is 0V.

[0142] When the write operation is started, between time t1 and time t2 , the voltage VMGPP at the selected memory gate MG is increased to a high level of about 11 V. On the other hand, the voltage VMGPN is increased to about 3 V for exceeding the breakdown voltage prevention.

[0143] When voltages VMGPP and VMGPN stabilize at predetermined values ​​between time t2 and time t3, a write pulse is applied. After the write operation is completed, between time t3 and time t4, voltage VMGPP is reduced to approximately 5 V, while voltage VMGPN is reduced to 0 V. After time t4, the address switching phase is established again.

[0144] In the address switching phase, the latch circuit 110 can be inverted according to the address. However, since the high power supply voltage VPPA is a relatively low voltage of 5V, it is not necessary to prevent the breakdown voltage from exceeding. Figure 7 After Figure 8 As shown, return to Fig.10 , the switches are controlled to allow current to flow in the bypass paths 105 and 106 and thus prevent the exceeding of the breakdown voltage prevention circuit 112 from being used.

[0145] On the other hand, in each of the power-on phase (between time t1 and time t2), the write pulse application phase (between time t2 and time t3), and the power-off phase (between time t3 and time t4), the internal state of the latch circuit 110 does not need to be changed, but the over-breakdown voltage prevention is required. In this case, the switch is controlled to allow the current to flow in the over-breakdown voltage prevention circuit 112, rather than in the bypass paths 105 and 106.

[0146] [Configuration of level shifter]

[0147] Figure 8 is a circuit diagram showing the configuration of a level shifter in the semiconductor device in the second embodiment.

[0148] refer to Figure 8 , the level shifter 100A includes a level shifter stage 101A and a driver stage 102A.

[0149] The level shifter stage 101A includes Figure 6The level shifter stage 101 in FIG. 1 is a basic component and further includes bypass paths 105 and 106 for bypassing the over-breakdown voltage prevention circuit 112. The bypass path 105 bypasses the over-breakdown voltage prevention circuit 112 and couples the intermediate node hhp and the intermediate node hhn together. The bypass path 106 bypasses the over-breakdown voltage prevention circuit 112 and couples the intermediate node hhn and the intermediate node 11n together.

[0150] The level shifter stage 101A is connected to Figure 6 The level shifter stage 101 in FIG. 1 is different in that a current path of switching NMOS transistors MNC1P and MNC2P provided in a bypass path 105 and a current path of switching NMOS transistors MNC1N and MNC2N provided in a bypass path 106 are also included therein. In the following description, a node between the NMOS transistor MNC1P and the NMOS transistor MNC2P is referred to as an intermediate node nmp, and a node between the MOS transistor MNC1N and the NMOS transistor MNC2N is referred to as an intermediate node nmn.

[0151] The control signal ctrl3 is input to the gate of each of the NMOS transistors MNC1P and MNC1N described above, and the control signal ctrl1 is input to the gate of each of the NMOS transistors MNC2P and MNC2N described above. The control signals ctrl1 and ctrl3 are intended to be used to switch between a state where there is a control for preventing the over-breakdown voltage and a state where there is no control for preventing the over-breakdown voltage. The respective back gates of the NMOS transistors MNC1P and MNC1N are coupled to their respective sources. Each of the back gates of the NMOS transistors MNC2P and MNC2N is coupled to the ground node 104.

[0152] The level shifter stage 101A is connected to Figure 6 The level shifter stage 101 in FIG. 1 is different in that the input to each of the gates of the clamping NMOS transistors MNF1P and MNF1N is replaced by the control signal ctrl4, and the input to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N is replaced by the control signal ctrl2. The control signals ctrl2 and ctrl4 are intended to switch the gate voltages depending on whether there is an over-breakdown voltage prevention control. In addition, the level shifter stage 101A is modified so that the respective back gates of the clamping NMOS transistors MNF1P and MNF1N are coupled to the respective sources of the NMOS transistors MNC1P and MNC1N.

[0153] The level shifter stage 101A is connected to Figure 6The level shifter stage 101 in FIG. 1 is also different in that clamping NMOS transistors MNF4P, MNF4N, MNF3P, MNF3N, MNF2P and MNF2N are also included therein. These NMOS transistors are not intended to float, but rather to fix the potential at the intermediate nodes in the unused current path.

[0154] Specifically, the clamp NMOS transistor MNF4P is coupled between the intermediate node hxp and the bypass path 105. The clamp NMOS transistor MNF4N is coupled between the intermediate node hxn and the bypass path 106. A fixed bias voltage bias1 is applied to each of the gates of the clamp NMOS transistors MNF4P and MNF4N. An intermediate voltage VPPR (e.g., 5.5 V) is used as the bias voltage bias1. The respective back gates of the clamp NMOS transistors MNF4P and MNF4N are coupled to their respective sources.

[0155] Each of the clamp NMOS transistors MNF3P, MNF3N, MNF2P and MNF2N is diode-coupled. The respective sources of the clamp NMOS transistors MNF3P, MNF3N, MNF2P and MNF2N are individually coupled to the intermediate nodes 11p, 11n, nmp and nmn. The bias voltage bias1 is given to each of the drains of the clamp NMOS transistors MNF3P, MNF3N, MNF2P and MNF2N. Each of the back gates of the clamp NMOS transistors MNF3P, MNF3N, MNF2P and MNF2N is coupled to the ground node 104.

[0156] In order to reduce the number of components, the driver stage 102A is configured to use the over-breakdown voltage prevention voltage in the level shifter stage 101A. Specifically, the driver stage 102A includes driver PMOS transistors MPDRP and MPDRN and driver NMOS transistors MNDRP and MNDRN. Figure 6 In the driver stage 102 , the driver stage 102A does not have any of the exceeding breakdown voltage prevention PMOS transistors MPE2P and MPE2N and the exceeding breakdown voltage prevention NMOS transistors MNE2P and MNE2N.

[0157] The coupling between the driver PMOS transistors MPDRP and MPDRN is Figure 6, and therefore the description thereof is not repeated. The respective drains of the driver NMOS transistors MNDRP and MNDRN are coupled to the respective drains of the driver PMOS transistors MPDRP and MPDRN. The respective gates of the driver NMOS transistors MNDRP and MNDRN are coupled to the intermediate nodes hxn and hxp, respectively. The respective sources of the driver NMOS transistors MNDRP and MNDRN are coupled to the intermediate nodes hxp and hxn, respectively. The respective back gates of the driver NMOS transistors MNDRP and MNDRN are coupled to the intermediate nodes nmp and nmn, respectively.

[0158] [Level Shifter Operation]

[0159] Next, we will give Figure 8 Description of the operation of the level shifter 100A in the semiconductor device in the second embodiment shown in FIG.

[0160] (Set value of control signal)

[0161] Table 2 shows the setting values ​​of the control signals ctrl1 to ctrl4 with / without the over-breakdown voltage prevention control

[0162] Table 2 Control signal values

[0163]

[0164] bias1=VPPR(5.5V)bias2=VPPC(3.0V)

[0165] It is assumed herein that the bias voltage bias1 is VPPR (eg, 5.5 V) and the bias voltage bias2 is VPPC (eg, 3.0 V). Each of the bias voltages bias1 and bias2 has a fixed value.

[0166] As shown in Table 2, the level shifter 100A is also configured so that the voltage levels of the output signals outp and outn from the level shifter 100A are switched according to whether there is an over-breakdown voltage prevention control. Regardless of whether there is an over-breakdown voltage prevention control, the high (H or high) side voltage level is VPPA. However, the high power supply voltage VPPA has different sizes when there is an over-breakdown voltage prevention control (e.g., 11V) and when there is no over-breakdown voltage prevention control (e.g., 5V). On the other hand, the low (L or low) side voltage level is the intermediate voltage VPPC (e.g., 3.0V) when there is an over-breakdown voltage prevention control and is the ground voltage VSS (e.g., 0V) when there is no over-breakdown voltage prevention control.

[0167] As described above, by setting the high-side voltage level to the high power supply voltage VPPA, Figure 5A On the other hand, by setting the low-side voltage level to the ground voltage VSS when there is no over-breakdown voltage prevention control, the PMOS switch 71 in the circuit can be reliably switched to the off state. Figure 5A Therefore, in order to ensure the capability of the PMOS switch 71, the signal levels of the output signals outp and outn are switched according to whether or not there is over-breakdown voltage prevention control.

[0168] Next, a description will be given of how to set the control signals ctrl1 to ctrl4 when there is an over-breakdown voltage prevention control and when there is no over-breakdown voltage prevention control. Figure 1 The control circuit of the flash sequencer 37 in is output.

[0169] (Operation of Level Shifter with Exceeding Breakdown Voltage Prevention Control)

[0170] When there is an over-breakdown voltage prevention control, the control circuit sets the control signal ctrl4 to VPPR (e.g., 5.5 V) and sets the control signal ctrl2 to VPPC (e.g., 3.0 V). Therefore, the input voltage (VPPR) to each of the gates of the clamp NMOS transistors MNF1P and MNF1N and the input voltage (intermediate voltage VPPC) to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are the same as those in the first embodiment. Figure 6 The same situation.

[0171] When there is over-breakdown voltage prevention control, the control circuit also sets the control signal ctrl1 to the ground voltage VSS. As a result, the NMOS transistors MNC2P and MNC2N are brought into an off state to cut off the current path via the bypass paths 105 and 106. Therefore, the same over-breakdown voltage prevention effect as obtained in the first embodiment can be obtained.

[0172] When there is a control to prevent the breakdown voltage from being exceeded, the intermediate nodes nmp and nmn of the bypass paths 105 and 106 are charged to the VPPR level through the corresponding clamping NMOS transistors MNF4P and MNF4N. When the voltages at the intermediate nodes nmp and nmn are increased to a level not less than the VPPR, the charge is extracted by clamping the NMOS transistors MNF2P and MNF2N until the VPPR level is reached. Therefore, the clamping NMOS transistors MNF4P and MNF4N are fixed to the VPPR level. In addition, when there is a control to prevent the breakdown voltage from being exceeded, the control circuit also sets the control signal ctrl3 to VPPC (e.g., 3.0V). Therefore, each voltage is set so as to prevent the breakdown voltage from being exceeded in each of the NMOS transistors MNC1P, MNC1N, MNC2P, and MNC2N.

[0173] The lowest voltage value at the intermediate nodes hxp and hxn is VPPC as the voltage value of the control signal ctrl2 given to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N when there is over-breakdown voltage prevention control. Since the driver stage 102A has already taken back the voltage at the intermediate nodes hxp and hxn to the negative side power supply voltage, the lower limit value of the output signals outp and outn is also VPPC.

[0174] (Not exceeding the breakdown voltage prevents the controlled level shifter from operating)

[0175] On the other hand, when there is no excess breakdown voltage prevention control, the control circuit sets the control signal ctrl2 to the ground voltage VSS to disable the function of the excess breakdown voltage prevention PMOS transistors MPE1P and MPE1N.

[0176] The control circuit also sets the control signal ctrl1 to the intermediate voltage VPPR to reliably bring the NMOS transistors MNC2P and MNC2N into the on state. The control circuit also sets the control signal ctrl3 to the intermediate voltage VPPR to reliably bring the NMOS transistors MNC1P and MNC1N into the on state. By thus setting the control signals ctrl1 and ctrl3, the bypass paths 105 and 106 are activated. The current path in which the over-breakdown voltage prevention circuit 112 intervenes is not positively cut off, but does not substantially function when the high power supply voltage VPPA drops.

[0177] In the state described above, the level shifter stage 101A operates using the current path in which the cross-coupled PMOS transistor MPCCP, the bypass path 105, and the input NMOS transistor MNINP intervene, and using the current path in which the cross-coupled PMOS transistor MPCCN, the bypass path 106, and the input NMOS transistor MNINN intervene. Each of the NMOS transistors MNC1P, MNC1N, MNC2P, and MNC2N functions as a switch only. Therefore, the level shifter stage 101A is equivalent to a simple cross-coupled level shifter without a function of preventing the breakdown voltage from being exceeded.

[0178] The voltage at the intermediate node in the over-breakdown voltage prevention circuit 112 not used herein is not limited by the clamp MOS transistor. This is because, when brought into a floating state, the voltage at the intermediate node may present an obstacle to the operation of the level shifter stage 101A.

[0179] Specifically, the voltages at the intermediate nodes 11p and 11n are respectively limited by the clamping NMOS transistors MNF3P and MNF3N to a level not exceeding the bias voltage bias1 (ie, VPPR). The intermediate nodes mmp and mmn prevent the NMOS transistors MNE1P and MNE1N from being directly coupled to the intermediate nodes 11p and 11n via exceeding the breakdown voltage.

[0180] The intermediate nodes hxp and hxn are coupled to the intermediate nodes nmp and nmn via the clamp NMOS transistors MNF4P and MNF4N, respectively. As a result, the lower limit of the voltage at the intermediate nodes hxp and hxn is the ground voltage VSS. Since the intermediate nodes hxp and hxn give the negative side power supply voltage in the driver stage 102A, the lower limit voltage of the output signals outp and outn is also the ground voltage VSS.

[0181] When there is no over-breakdown voltage prevention control, the clamp NMOS transistors MNF1P and MNF1N are brought into a substantially off state. This is because the control signal ctrl4 supplied to each of the gates of the clamp NMOS transistors MNF1P and MNF1N is set to the ground voltage VSS, and the ground voltage VSS is the lowest voltage at the intermediate nodes hhp and hhn. As a result, the current supplied to the PMOS transistors MPE3P and MPE3N when there is an over-breakdown voltage prevention control is no longer required when there is no over-breakdown voltage prevention control and can therefore be cut off.

[0182] [Effects of the Second Embodiment]

[0183] According to the second embodiment, bypass paths 105 and 106 that bypass the over-breakdown voltage prevention circuit 112 are provided between the latch circuit 110 and the input circuit 111. The bypass paths 105 and 106 can be switched between a conductive state and a non-conductive state by switching NMOS transistors MNC1P, MNC1N, MNC2P, and MNC2N.

[0184] As a result, in the stage where a write pulse is applied to a selected memory cell, the high power supply voltage VPPA is set to a high value and the bypass paths 105 and 106 are cut off to allow the level shifter 100A to operate in a state where there is an over-breakdown voltage prevention control. On the other hand, in the stage where a write address is selected, the high power supply voltage VPPA is set to a low value and the bypass paths 105 and 106 are brought into a conductive state to allow the level shifter 100A to operate in a state where there is no over-breakdown voltage prevention control.

[0185] The aforementioned switching between the on state and the off state of the bypass paths 105 and 106 can be performed using the set voltages of the control signals ctrl1 to ctrl4 as described using Table 2. Specifically, in the above-described Figure 7 In the address switching phase (before time t1 and after time t1), the level shifter 100A operates in a state where there is no over-breakdown voltage prevention control. Thereafter, the control circuit switches the settings of the control signals ctrl1 to ctrl4 from a state where there is no over-breakdown voltage prevention control to a state where there is over-breakdown voltage prevention control at an appropriate timing during the power-on period (for example, at the first time t1 during the power-on period). Therefore, the control circuit switches the settings of the control signals ctrl1 to ctrl4 from a state where there is over-breakdown voltage prevention control to a state where there is no over-breakdown voltage prevention control at an appropriate timing during the power-off period (for example, at the last time t4 during the power-off period). Therefore, in the phase (time t2 to time t4) in which a write pulse is applied to a selected memory cell, the level shifter 100A can operate in a state where there is over-breakdown voltage prevention control.

[0186] The respective sources of the driver NMOS transistors MNDRP and MNDRN included in the driver stage 102A are coupled to the respective sources (i.e., the intermediate nodes hxp and hxn) of the PMOS transistors MPE1P and MPE1N that prevent the breakdown voltage from being exceeded. Therefore, even when the potential at the intermediate nodes hhp and hhn is increased to prevent the respective breakdown voltages of the cross-coupled PMOS transistors MPCCP and MPCCN and the driver PMOS transistors MPDRP and MPDRN from being exceeded, the low level voltages of the output signals outp and outn remain unchanged. As a result, the operating margin of the circuit that receives the output signals outp and outn input thereto from the level shifter 100A is not reduced.

[0187] In contrast, in the case of the related art level shifter in which the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are not provided, when the gate potentials of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are increased for over-breakdown voltage prevention, the potentials at the intermediate nodes hxp and hxn are increased to increase the low-level voltages of the output signals outp and outn. As a result, the operating margin of the circuit receiving the output signals outp and outn input thereto from the level shifter 100A is undesirably reduced.

[0188] Therefore, in the case of the second embodiment, by providing the over-breakdown voltage preventing PMOS transistors MPE3P and MPE3N, it is possible to suppress a reduction in the operation margin of the entire semiconductor circuit.

[0189] <Third Embodiment>

[0190] In each of the first and second embodiments, a diode-coupled PMOS transistor is used as an additional over-breakdown voltage prevention PMOS transistor MPE3P and MPE3N. It is noted herein that the over-breakdown voltage prevention circuit (also referred to as the clamping voltage) depends on the gate potential of each of the over-breakdown voltage prevention PMOS transistors. In the case of the first and second embodiments, each of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is diode-coupled so that the gate potential is equal to the drain potential. Therefore, in order to change the gate potential, the drain potential needs to be changed, and in order to change the drain potential, it is necessary to change the current caused to flow in each of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. For the reasons described above, in the case of the first and second embodiments, it is necessary to cause the current to flow continuously in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, resulting in the problem of high DC current consumption.

[0191] In addition, in each of the first and second embodiments, in order to enhance the over-breakdown voltage prevention effect on the cross-coupled PMOS transistors MPCCP and MPCCN, it is necessary to increase the drain potential of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. In order to meet the requirements, it is appropriate to reduce the current caused to flow in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. However, when the high power supply voltage VPPA is reduced, the stability of the level shifter deteriorates. Therefore, there may be a situation where it is necessary to reduce the drain potential of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N on the contrary. In this case, a larger amount of DC current is consumed so that the range of regulation of the over-breakdown voltage prevention voltage is limited.

[0192] In the third embodiment, in order to solve the above-described embodiments, the coupling of the gates of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is changed. Referring to the drawings, a detailed description will be given below.

[0193] [Configuration of level shifter]

[0194] Fig. 9 is a circuit diagram showing the configuration of a level shifter in the semiconductor device in the third embodiment.

[0195] Fig. 9 The level shifter 100B in Figure 8 The level shifter 100A in FIG. 1 is different in coupling to the gates of the PMOS transistors MPE3P and MPE3N to prevent the PMOS transistors MPE3P and MPE3N from exceeding the breakdown voltage. Specifically, Figure 8 In the level shifter 100A, each of the PMOS transistors MPE3P and MPE3N is diode-coupled, while Fig. 9 In the level shifter 100B, the control signal ctrl6 is sent from an external control circuit (eg, Figure 1 The flash sequencer 37 in the embodiment is input to each of the gates of the exceeding breakdown voltage prevention PMOS transistors MPE3P and MPE3N.

[0196] In the configuration of the level shifter 100B described above, the over-breakdown voltage prevention effect on the PMOS transistors MPCCP and MPCCN at the cross-coupling can be adjusted using the voltage level of the control signal ctrl6. Since the control signal ctrl6 is given from an external control circuit, it is not necessary to stably flow the current in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. Therefore, the third embodiment can reduce DC current consumption compared to the second embodiment.

[0197] For the reasons described above, the clamping NMOS transistors MNF1P and MNF1N provided to allow current to flow in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are basically unnecessary. However, when there is leakage current in the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, the potential difference between the intermediate nodes hhp and hhn and the intermediate nodes hxp and hxn is reduced to reduce the over-breakdown voltage prevention effect. Therefore, Fig. 9 The clamping NMOS transistors MNF1P and MNF1N in the embodiment are provided to compensate for the voltage reduction at the intermediate nodes hhp and hhn due to the leakage current mentioned above. As a result, the current sufficient to prevent the PMOS transistors MPE3P and MPE3N from being injected beyond the breakdown voltage via the clamping NMOS transistors MNF1P and MNF1N is significantly smaller than those in the case of the first and second embodiments.

[0198] because Fig. 9 In addition Figure 8 The same, so similar or equivalent parts are given similar reference numerals, and the description thereof is not repeated. Note that the above-described change in coupling of the respective gates of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is also applicable to the first embodiment. Figure 6 The situation in.

[0199] [Specific voltage value and generation circuit of control signal ctrl6]

[0200] A description will be given of specific voltage values ​​of the control signal ctrl6.

[0201] During the over-breakdown voltage prevention control, the lower limit value of the voltage at the intermediate nodes hxp and hxn is the voltage value of the control signal ctrl2 (VPPC, for example, 3.0V), and the lower limit value of the voltage at the intermediate nodes hhp and hhn is the voltage value of the control signal ctrl6. Therefore, in order to increase the over-breakdown voltage prevention effect on the cross-coupled PMOS transistors MPCCP and MPCCN, it is necessary to satisfy ctrl6>VPPC.

[0202] On the other hand, under the clamping effect of the clamping NMOS transistors MNF1P and MNF1N, the voltage at the intermediate nodes hhp and hhn cannot be set higher than the voltage value (VPPR, for example, 5.5V) of the control signal ctrl4. Therefore, it is necessary to satisfy ctrl6 <VPPR。

[0203] Therefore, the voltage value of the control signal ctrl6 during the over-breakdown voltage prevention control is between the value of the intermediate voltage VPPR and the value of the intermediate voltage VPPC. An example of a circuit that generates the control signal ctrl6 so as to satisfy this relationship is shown below.

[0204] Fig.10 It shows that the generated Fig. 9 FIG. 1 is a diagram showing an example of a circuit for controlling the signal ctrl6 in FIG. Fig.10 , the control signal generating circuit 120 receives the bias voltage bias1 (intermediate voltage VPPR) and the bias voltage bias2 (intermediate voltage VPPC) input thereto and generates and outputs the control signal ctrl6 based on these signals. Specifically, the control signal generating circuit 120 includes PMOS transistors MPSW and MPEMI and NMOS transistors MNEMI, MNCL and MNFX. The coupling between the above-mentioned transistors will be described below.

[0205] The PMOS transistor MPSW, the NMOS transistor MNEMI, the PMOS transistor MPEMI, and the NMOS transistor MNCL are arranged in this order and are coupled in series between the power supply node 121 to which the bias voltage bias1 is input and the ground node 104. The control signal ctrl1 is input to the gate of the PMOS transistor MPSW. The control signal ctrl2 is input to the gate of the PMOS transistor MPEMI. The bias voltage bias1 is applied to each of the gates of the NMOS transistors MNEMI and MNCL. Each of the back gates of the PMOS transistors MPSW and MPEMI is coupled to the power supply node 121. The respective back gates of the NMOS transistors MNEMI and MNCL are coupled to their respective sources. The NMOS transistor MNFX is coupled between the coupling node 123 between the NMOS transistor MNEMI and the PMOS transistor MPEMI and the ground node 104. The control signal ctrl6 is input to the gate of the NMOS transistor MNFX. The back gate of the NMOS transistor MNFX is coupled to its source. From the coupling node 123 mentioned above, the control signal ctrl6 is output.

[0206] In the control signal generating circuit 120 having the aforementioned configuration, the NMOS transistor MNCL is used as a clamp MOS transistor that prevents the PMOS transistor MPEMI from being directly coupled to the ground voltage VSS.

[0207] The PMOS transistor MPSW is used as a switch to switch the control signal ctrl6 between an active state and an inactive state. When there is over-breakdown voltage prevention control, the control signal ctrl1 is set to the ground voltage VSS to bring the PMOS transistor MPSW into the on state. When there is no over-breakdown voltage prevention control, the control signal ctrl1 is set to the bias voltage bias1 to bring the PMOS transistor MPSW into the off state.

[0208] The NMOS transistor MNFX is used as a pull-down NMOS transistor for fixing the coupling node 123 to the ground voltage VSS when the control signal ctrl6 is not in use (i.e., when there is over-breakdown voltage prevention control and the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are activated). Therefore, when the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N are activated, the control circuit sets the control signal ctrl5 to the ground voltage VSS to turn off the NMOS transistor MNFX.

[0209] When the control signal ctrl6 is in use, i.e., when the NMOS transistor MNFX is off, the voltage of the control signal ctrl6 is substantially determined by the magnitude ratio between the NMOS transistor MNEMI and the PMOS transistor MPEMI.

[0210] Specifically, through the NMOS transistor MNEMI, the control signal ctrl6 is limited to a voltage value not exceeding (VPPR)-Vthn of bias1, where Vthn is the threshold voltage of the NMOS transistor MNEMI. The control signal ctrl6 is further limited by the PMOS transistor MPEMI to a voltage value not less than ctrl2 (VPPC). Therefore, the voltage value of the control signal ctrl6 is within the range given by VPPC < ctrl6 < VPPR - Vthn. When the current increases by adjusting the magnitudes of the NMOS transistor MNEMI and the PMOS transistor MPEMI, the voltage value of the control signal ctrl6 approaches the lower limit of the range shown above (i.e., VPPC). Conversely, when the current is decreased, the voltage value of the control signal ctrl6 approaches the upper limit (i.e., VPPR - Vthn). Therefore, it is possible to change the voltage value of the control signal ctrl6 and adjust the over-breakdown voltage prevention effect.

[0211] Note that when there is no over-breakdown voltage prevention control, the control circuit sets the control signal ctrl1 to VPPR to turn off the PMOS transistor MPSW and sets the control signal ctrl5 to VPPC to fix the control signal ctrl6 to the ground voltage VSS.

[0212] [Summary of Set Values and Effects of Control Signals ctrl1 to ctrl6]

[0213] Table 3 shows a summary of the set values of control signals ctrl1 to ctrl6 in each operation mode.

[0214] Table 3 Values of Control Signals

[0215]

[0216] bias1 = VPPR(5.5V) bias2 = VPPC(3.0V) bias2 < bias3 < bias1

[0217] The operation modes include a mode without over-breakdown voltage prevention control, a mode with loose over-breakdown voltage prevention control, and a mode with strict over-breakdown voltage prevention control. Each of the mode with strict over-breakdown voltage prevention control and the mode with loose over-breakdown voltage prevention control corresponds to a state where the over-breakdown voltage prevention control is effective. Specifically, the mode with strict over-breakdown voltage prevention control corresponds to the case where the control signal ctrl6 is effective (i.e., when the control signal ctrl6 is within the range given by VPPC < ctrl6 < VPPR - Vthn), resulting in Fig. 9 a state where each of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N in has an over-breakdown voltage prevention effect. The mode with loose over-breakdown voltage prevention control corresponds to the case where the control signal ctrl6 is ineffective (i.e., equal to the ground voltage VSS), resulting in Fig. 9 a state where the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N in do not exist.

[0218] The switching of the control signal ctrl6 between the effective state and the ineffective state can be performed using the control signal ctrl5. The other control signals ctrl1 and ctrl1 are not shown to have differences between the mode with loose over-breakdown voltage prevention control and the mode with strict over-breakdown voltage prevention control. Therefore, the set values of the control signals ctrl1 to ctrl4 are the same as those in Table 2.

[0219] As described above, when the high power supply voltage VPPA is relatively high, the control circuit sets the control signal ctrl5 to the ground voltage VSS to activate the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. This allows for a higher over-breakdown voltage prevention effect. On the other hand, when the high power supply voltage VPPA is relatively low, the control circuit sets the control signal ctrl5 to the bias voltage bias2 (VPPC) to deactivate the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. This can enhance the operation stability of the level shifter 100B.

[0220] <Fourth Embodiment>

[0221] In the case of the third embodiment, among the PMOS transistors included in the level shifter 100B, six elements, namely, the cross-coupled PMOS transistors MPCCP and MPCCN, the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, and the driver PMOS transistors MPDRP and MPDRN, can provide a sufficient over-breakdown voltage prevention effect compared to the effect provided by the related art circuit. On the other hand, only two elements, namely, the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N, can provide an over-breakdown voltage prevention effect equivalent to the effect provided by the related art circuit.

[0222] More specifically, among the first six PMOS transistors, the maximum gate-source applied voltage is VPPA - bias3 (bias3 is the voltage value of the control signal ctrl6). On the other hand, among the subsequent over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N, the maximum gate-source applied voltage is VPPA - bias2 (bias2 = VPPC). Since the relationship given by bias2 < bias3 is established, a higher voltage is applied between the gate and the source in the subsequent over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N.

[0223] As a result, the problem that arises is that in order to obtain a higher over-breakdown voltage prevention property, the over-breakdown voltage prevention effect on the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N is insufficient. In the fourth embodiment, a description of the level shifter 100C that solves the above-described problem will be given.

[0224] [Configuration of Level Shifter]

[0225] Fig.11 is a circuit diagram showing the configuration of the level shifter in the semiconductor device in the fourth embodiment. Fig.11The level shifter 100C in FIG. 1 includes a level shifter stage 101C and a driver stage 102A. The driver stage 102A is configured similar to Figure 8 and 9 The configuration of the level shifter stage 101C is modified by partially modifying Fig. 9 is obtained by the level shifter stage 101B in.

[0226] The over-breakdown voltage prevention circuit 112 in the level shifter stage 101C is different from the case of the third embodiment (ie, Fig. 9 The over-breakdown voltage prevention circuit 112 in FIG. 1 is different in the layout of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N. Specifically, Fig.11 In the case of the over-breakdown voltage prevention NMOS transistor MNE1P being provided between the over-breakdown voltage prevention PMOS transistor MPE3P and the over-breakdown voltage prevention PMOS transistor MPE1P and being coupled in series to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE1P. Similarly, the over-breakdown voltage prevention NMOS transistor MNE1N being provided between the over-breakdown voltage prevention PMOS transistor MPE3N and the over-breakdown voltage prevention PMOS transistor and being coupled in series to the over-breakdown voltage prevention PMOS transistors MPE3N and MPE1N.

[0227] A bias voltage bias1 (VPPR) is given to each of the gates of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N. The respective back gates of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are coupled to their respective sources. The coupling between these over-breakdown voltage prevention NMOS transistors is Fig. 9 The same situation.

[0228] Note that in Fig.11 In the related description, the corresponding coupling nodes between the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N and the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are referred to as intermediate nodes hxp and hxn. The corresponding coupling nodes between the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N and the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are referred to as intermediate nodes hyp and hyn. The corresponding coupling nodes between the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N and the input NMOS transistors MNINP and MNINN are referred to as intermediate nodes 11p and 11n.

[0229] exist Fig.11In the embodiment of the present invention, the drain of the clamp NMOS transistor MNF4P is coupled to the intermediate node hyp instead of the intermediate node hxp. The drain of the clamp NMOS transistor MNF4N is coupled to the intermediate node hyn instead of the intermediate node hxn.

[0230] Fig.11 The configuration in Fig. 9 The situation is the same, and therefore the description thereof is not repeated.

[0231] [Level Shifter Operation]

[0232] Fig.11 The level shifter 100C11 in FIG. 1 has a configuration obtained by arranging the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N on the higher potential side of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N, which presents Fig. 9 A bias voltage bias1 (VPPR) is applied to each of the gates of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N.

[0233] In the above described Fig. 9 In the case of exceeding the breakdown voltage, the maximum voltage at the source (i.e., the intermediate nodes hxp and hxn) of the PMOS transistors MPE1P and MPE1N is the high power supply voltage VPPA. For example, when the PMOS transistor MPCCP is in the on state, the corresponding potentials at the intermediate nodes hhp and hxp are equal to the potential (VPPA) at the high voltage node 103. In contrast, in Fig.11 In the case of exceeding the breakdown voltage prevention PMOS transistors MPE1P and MPE1N, the maximum voltage at the source (i.e., the intermediate nodes hyp and hyn) is the bias voltage bias1 (VPPR), which is significantly lower than the high power supply voltage VPPA. Therefore, the maximum voltage applied to the exceeding the breakdown voltage prevention PMOS transistors MPE1P and MPE1N is reduced from VPPA to VPPR.

[0234] When the over-breakdown voltage prevention circuit 112 is active (i.e., when there is an over-breakdown voltage prevention control), the minimum voltage at the intermediate nodes hyp and hyn is bias2 (VPPC) as the voltage value of the control signal ctrl2. When it is assumed that VPPR=5.5V and VPPC=3.0V are satisfied by way of example, the gate-source voltage Vgs in each of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N is VPPR-VPPC (=about 2.5V). As a result, the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N can be reliably controlled to be in a conducting state, which prevents the absence of an obstacle when causing the required current to flow in the over-breakdown voltage prevention circuit 112.

[0235] [Effects of the Fourth Embodiment]

[0236] By adopting Fig.11 The configuration of the over-breakdown voltage prevention circuit 112 in the level shifter 100C shown in FIG. 1 exerts an over-breakdown voltage prevention effect on all PMOS transistors in the current path in the level shifter 100C. As a result, it is possible to suppress degradation of the threshold voltage of each of the PMOS transistors when the PMOS transistors receive FN stress and provide a level shifter with higher resistance to FN degradation.

[0237] <Fourth Embodiment>

[0238] In the first to fourth embodiments, it is assumed that the level shifter is used in the high voltage switch circuit described using Fig. 5. Therefore, in a state where there is over-breakdown voltage prevention control (i.e., when the high power supply voltage VPPA is set at a high voltage), the level shifter does not need to be inverted.

[0239] However, in a control circuit provided in a power supply circuit that generates a high power supply voltage VPPA, a need arises to invert the level shifter in a state where the high power supply voltage VPPA is relatively high and exceeds the breakdown voltage prevention control effective. The fifth embodiment will describe an example of a configuration of a level shifter that can be inverted in a state where the breakdown voltage prevention control is effective.

[0240] [Configuration of level shifter]

[0241] Fig.12 is a circuit diagram showing the configuration of a level shifter in the semiconductor device in the fifth embodiment. Fig.12 The level shifter 100D in Fig. 9 It is obtained by the level shifter 100B in.

[0242] Specifically, Fig.12 The level shifter 100D in Fig. 9The level shifter 100B in FIG. 1 is different in that the input signal to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is changed from the control signal ctrl6 to the control signal ctrl7. Contrary to the voltage value of the control signal ctrl6 being fixed when the over-breakdown voltage prevention control is effective, the voltage value of the control signal ctrl7 is characterized by being changed according to the high power supply voltage VPPA (i.e., when the high power supply voltage VPPA increases, the control signal ctrl7 increases).

[0243] in addition, Fig.12 The over-breakdown voltage prevention circuit 112 in the level shifter 100D and Fig. 9 The level shifter 100B in FIG. 1 is different in that the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N coupled in parallel to the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are further included therein. The control signal ctrl8 is input to each of the gates of the above-mentioned over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N. The respective back gates of the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N are coupled to their respective sources.

[0244] The voltage value of the control signal ctrl2 input to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N when the over-breakdown voltage prevention control is effective is fixed to the value (VPPC) of the bias voltage bias2. In contrast, the voltage value of the control signal ctrl8 input to each of the gates of the newly added over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N is characterized by a change according to the high power supply voltage VPPA (that is, when the high power supply voltage VPPA increases, the control signal ctrl8 increases). This allows the over-breakdown voltage prevention effect of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N to be reduced when the high power supply voltage VPPA decreases.

[0245] In the later described Fig.13 In the example shown in FIG. 1 , each of the control signals ctrl7 and ctrl8 described above varies in proportion to the high power supply voltage VPPA. For example, each of the control signals ctrl7 and ctrl8 is generated by dividing the high power supply voltage VPPA. In this example, the voltage value of the control signal ctrl8 is between the voltage value 7 of the control signal ctrl7 and the value of the ground voltage VSS.

[0246] Fig.12 The level shifter 100D in Fig. 9The level shifter 100B in FIG. 1 is different in that NMOS transistors MNP1P and MNP1N are further included therein. Specifically, the NMOS transistor MNP1P has a drain coupled to the middle node hxp, a gate coupled to the middle node hxn, and a control signal ctrl2 is input to the source and the back gate. The NMOS transistor MNP1N has a drain coupled to the middle node hxn, a gate coupled to the middle node hxp, and a control signal ctrl2 is input to the source and the back gate.

[0247] The NMOS transistors MNP1P and MNP1N having the aforementioned configuration can pull down the lower limit voltage at the intermediate nodes hxp and hxn to the intermediate voltage VPPC. This allows the lower limit voltage of the output signals outp and outn to be maintained at the intermediate voltage VPPC regardless of the set value of the high power supply voltage VPPA.

[0248] Note that without the NMOS transistors MNP1P and MNP1N, the lower limit voltages of the output signals outp and outn are at most about 1 V higher than VPPC. The NMOS transistors MNP1P and MNP1N may be omitted when there is no problem in their practical use.

[0249] because Fig.12 The configuration in Fig. 9 The situation is the same as in the previous embodiment, so similar or equivalent parts are given like figure marks, and their description is not repeated.

[0250] [Control signal generation circuit]

[0251] Fig.13 It shows that the generated Fig.12 FIG. 1 is a view of an example of a circuit for controlling signals ctrl7 and ctrl8.

[0252] refer to Fig.13 , the control signal generating circuit 130 is configured as a voltage dividing circuit that divides the high power supply voltage VPPA. The high power supply voltage VPPA is given to a higher potential power supply node 131 of the voltage dividing circuit, and the ground voltage VSS is given to a lower potential power supply node 132 thereof. The control signal ctrl6 is output from a voltage dividing node 133 between the higher potential power supply node 131 and the lower potential power supply node 132, and the control signal ctrl8 is output from a voltage dividing node 134 between the voltage dividing node 133 and the lower potential power supply node 132.

[0253] Specifically, in Fig.13In the example shown in , the control signal generating circuit 130 includes eight PMOS transistors MPR1 to MPR8, each of which is diode-coupled and coupled to each other in series, and an NMOS transistor MNR coupled between the drain of the PMOS transistor MPR1 and the lower potential power supply node 132. The NMOS transistor MNR is used as a switch. The source of the PMOS transistor MPR8 is coupled to the higher potential power supply node 131. The control signal ctrl2 is input to the gate of the NMOS transistor MNR. In each of the MOS transistors, the back gate and the source are coupled together.

[0254] The coupling node between the PMOS transistor MPR4 and the PMOS transistor MPR5 serves as a voltage dividing node 133 and outputs a control signal ctrl7. The coupling node between the PMOS transistor MPR3 and the PMOS transistor MPR4 serves as a voltage dividing node 134 and outputs a control signal ctrl8.

[0255] Next, a description will be given of the operation of the control signal generating circuit 130 having the aforementioned configuration. When the over-breakdown voltage prevention control is effective, the voltage value of the control signal ctrl2 is set to the bias voltage bias2 (VPPC) to bring the NMOS transistor MNR into a conducting state. At this time, the voltage value of the control signal ctrl7 is (1 / 2)×VPPA, and the voltage value of the control signal ctrl8 is (3 / 8)×VPPA.

[0256] On the other hand, when the over-breakdown voltage prevention control is invalid, the voltage value of the control signal ctrl2 is set to the ground voltage VSS to bring the NMOS transistor MNR into a cut-off state. In this case, each of the control signals ctrl7 and ctrl8 is fixed to the high power supply voltage VPPA.

[0257] [Factors that suppress the phase inversion of the level shifter]

[0258] In the description Fig.12 Before the operation of the level shifter 100D, first, the reason why it is difficult to make the voltage corresponding to Fig.12 of Fig. 9 Description of the cause of the inversion of the level shifter 100B.

[0259] refer to Fig. 9, when the logic levels of the input signals inp and inn are inverted, the on / off states of the input NMOS transistors MNINP and MNINN included in the input circuit 111 are changed. At this time, the current flowing in the input NMOS transistors MNINP and MNINN extracts charges from the intermediate nodes hhp and hhn. As a result, the on / off states of the cross-coupled PMOS transistors MPCCP and MPCCN included in the latch circuit 110 are changed. In other words, the level shifter 100B is inverted.

[0260] Therefore, in order to improve the inversion property, it is important to increase the current in the current path coupling the latch circuit 110 and the input circuit 111 together. Fig. 9 In the illustrated over-breakdown voltage prevention type level shifter, the over-breakdown voltage prevention circuit 112 (particularly, the over-breakdown voltage prevention PMOS transistors MPE1P, MPE1N, MPE3P, and MPE3N) configures a factor that suppresses an increase in current in the above-mentioned current path.

[0261] Specifically, the problem is that when the latch circuit 110 is inverted, the high power supply voltage VPPA should be reduced to prevent the cross-coupled PMOS transistors MPCCP and MPCCN from exceeding the on-state breakdown voltage. On the other hand, each of the gate voltages (ctrl2 or control signal ctrl6) of the PMOS transistors MPE1P, MPE1N, MPE3P and MPE3N that prevent the breakdown voltage from exceeding is set at a relatively high value to allow sufficient prevention effect of exceeding the breakdown voltage to be obtained when the high power supply voltage VPPA has an upper limit value. Therefore, when the high power supply voltage VPPA is reduced without changing the set value of the gate voltage of the PMOS transistors MPE1P, MPE1N, MPE3P and MPE3N that prevent the breakdown voltage from exceeding, each of the cross-coupled PMOS transistors MPCCP and MPCCN may not have a sufficient gate-source voltage. As a result, the latch circuit 110 cannot be inverted.

[0262] To avoid the problems described above, Fig.12 In the level shifter 100D shown in FIG. 1 , the gate voltage (ctrl7) of each of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N and the gate voltage (ctrl8) of each of the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N change in proportion to the high power supply voltage VPPA. Specifically, when the high power supply voltage VPPA decreases, the voltage values ​​of the control signals ctrl7 and ctrl8 also decrease.

[0263] [Level Shifter Operation]

[0264] Table 4 shows a summary of the setting values ​​of the control signals ctrl1 to ctrl4 , ctrl7 , and ctrl8 with / without the over-breakdown voltage prevention control.

[0265] Table 4 Control signal values

[0266]

[0267] bias1=VPPR(5.5V)bias2=VPPC(3.0V)

[0268] The following will be described based on Table 4 Fig.12 Note that the numerical values ​​in Table 4 and the following description are exemplary and non-limiting.

[0269] In addition, as shown in Table 4, the case (1) in which the over-breakdown voltage prevention control exists and the case (2) in which the over-breakdown voltage prevention control does not exist will be described separately below. In the case (1) in which the over-breakdown voltage prevention control exists, the control signals ctrl7 and ctrl8 are changed in proportion to the high power supply voltage VPPA, so that the description of the three cases will be given separately according to the value of the high power supply voltage VPPA. Specifically, there are three cases, namely, a case (1.1) in which the high power supply voltage VPPA is about 11V, a case (1.2) in which the high power supply voltage VPPA is reduced to about 8V, and a case (1.3) in which the high power supply voltage VPPA does not exceed 6V.

[0270] As will be described in detail below, in case (1.1), the voltage applied to the MOS transistor exceeds the on-state breakdown voltage, and thus the level shifter cannot be inverted. On the other hand, in each of case (1.2) and case (1.3), the level shifter can be inverted. However, in case (1.2), exceeding the breakdown voltage prevents the PMOS transistors MPE1P and MPE1N from forming a main current path, while in case (1.3), exceeding the breakdown voltage prevents the PMOS transistors MPE4P and MPE4N from forming a main current path.

[0271] A case (1.1) in which the over-breakdown voltage prevention control is present and the high power supply voltage VPPA is about 11V will be described.

[0272] In this case, the voltage value of the control signal ctrl7 is about 5.5V (11V×1 / 2). Fig. 9The voltage of the control signal ctrl6 of the level shifter 100B in the embodiment is supplied to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N. As a result, the over-breakdown voltage prevention effect on the cross-coupled PMOS transistors MPCCP and MPCCN is higher than Fig. 9 The situation in FIG. 1 is similar to that in FIG. 2 , and the inversion margin of the level shifter 100D is narrower.

[0273] On the other hand, the maximum value of the voltage applied to each MOS transistor included in the level shifter 100D is about VPPA (11 V) - VPPC (3 V) = 8 V. The voltage value exceeds the on-breakdown voltage (about 7 V) of the MOS transistor. Therefore, regardless of the size of the inversion margin of the level shifter 100D, the level shifter 100D cannot be inverted in terms of the on-breakdown voltage.

[0274] A case (1.2) in which the over-breakdown voltage prevention control exists and the high power supply voltage VPPA is reduced to about 8V will be described.

[0275] In this case, the maximum value of the voltage supplied to each MOS transistor included in the level shifter 100D is about VPPA (8 V) - VPPC (3 V) = 5 V. Since this voltage value is lower than the on-breakdown voltage (about 7 V) of the MOS transistor, the level shifter 100D can be inverted in terms of on-breakdown voltage.

[0276] On the other hand, the voltage value of the control signal ctrl7 supplied to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N is about 4V (8V×1 / 2). Therefore, the over-breakdown voltage prevention effect on the cross-coupled PMOS transistors MPCCP and MPCCN is less than that of Fig. 9 The effect of the case of the level shifter 100B in is reduced. However, since the current flowing in the over-breakdown voltage prevention circuit 112 can be increased, the level shifter 100B can be inverted.

[0277] A case (1.3) in which the over-breakdown voltage prevention control exists and the high power supply voltage VPPA does not exceed 6V will be described.

[0278] In this case, the voltage value of the control signal ctrl7 does not exceed 3V (6V×1 / 2). As a result, the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N, each having a gate voltage of a fixed value (ctrl2), present an obstacle to allowing current to flow in the over-breakdown voltage prevention circuit 112. In order to avoid this problem, the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N are provided in parallel with the corresponding over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N. Since the voltage of the control signal ctrl8 provided to each of the gates of the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N does not exceed 2.25V (6V×3 / 8), current is allowed to flow in the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N. Therefore, the level shifter 100B can be inverted.

[0279] A case (2) will be described in which there is no over-breakdown voltage prevention control. In this case, the control circuit sets the voltage value of the control signal ctrl7 to VPPA to bring the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N into an off state. The control circuit also sets the control signal ctrl8 to VPPA to bring the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N into an on state. The setting values ​​of the control signals ctrl1 to ctrl4 are the same as those of the second embodiment described using Table 2 and the third embodiment described using Table 3. Therefore, the operation of the level shifter 100D when there is no over-breakdown voltage prevention control is the same as those of the second and third embodiments.

[0280] [About the effects of NMOS transistors MNP1P and MNP1N]

[0281] The effects of the NMOS transistors MNP1P and MNP1N will be supplementarily described below.

[0282] If the NMOS transistors MNP1P and MNP1N do not exist, the path into which the charge extracted from the intermediate nodes hxp and hxn enters is a first path that exceeds the breakdown voltage to prevent the PMOS transistors MPE1P and MPE1N from intervening therein or a second path that exceeds the breakdown voltage to prevent the PMOS transistors MPE4P and MPE4N from intervening therein. In the case of the first path, the lower limit voltage at the intermediate nodes hxp and hxn is ctrl2+Vthp (Vthp is the threshold voltage of the PMOS transistor). In the case of the second path, the lower limit voltage at the intermediate nodes hxp and hxn is ctrl8+Vthp. Therefore, the final lower limit voltage at the intermediate nodes hxp and hxn has a value obtained by adding the value Vthp to the smaller one of the voltage values ​​of the control signals ctrl2 and ctrl8. When the high power supply voltage VPPA is set at a value of not less than 8V, the lower limit voltage at the intermediate nodes hxp and hxn is approximately ctrl2+Vthp=VPPC+Vthp=VPPC+1V.

[0283] On the other hand, by providing NMOS transistors MNP1P and MNP1N, charges are extracted from the intermediate nodes hxp and hxn via the NMOS transistors MNP1P and MNP1N. As a result, the lower limit voltage at the intermediate nodes hxp and hxn can be maintained at VPPC. Since the lower limit voltage of the output signals outp and outn is determined by the voltage at the intermediate nodes hxp and hxn, the lower limit voltage of the output signals outp and outn can therefore be maintained at VPPC.

[0284] [Effects of the Fifth Embodiment]

[0285] According to the fifth embodiment, by using control signals ctrl7 and ctrl8 proportional to the high power supply voltage VPPA, it is possible to allow the operation of inverting the level shifter to be performed within a relatively wide setting range of the high power supply voltage VPPA while maintaining a sufficient over-breakdown voltage prevention effect.

[0286] <Sixth Embodiment>

[0287] In the same manner as in the case of the third embodiment, and also in the case of the fifth embodiment, six elements, namely, the cross-coupled PMOS transistors MPCCP and MPCCN, the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N, and the driver PMOS transistors MPDRP and MPDRN among the PMOS transistors included in the level shifter 100D can provide a sufficient over-breakdown voltage prevention effect compared to the effect provided by the related art circuit. On the other hand, only two elements, namely, the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N can only provide an over-breakdown voltage prevention effect equivalent to the effect provided by the related art circuit.

[0288] The newly added over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N in the fifth embodiment have a maximum gate-source applied voltage given by VPPA-ctrl8=VPPA-(3 / 8)×VPPA=(5 / 8)×VPPA. Therefore, when the high power supply voltage VPPA is set at 11V, the maximum applied voltage is 6.857V, and an over-breakdown voltage prevention effect equal to the effect provided by the other PMOS transistors except the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N can be obtained.

[0289] The considerations given above show that, in the same manner as in the case of the third embodiment, the insufficient over-breakdown voltage prevention effect on the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N presents a problem of obtaining a higher over-breakdown voltage prevention property. In the sixth embodiment, a description will be given of a level shifter 100E that solves the above-described problems. Specifically, for Fig.12 The level shifter 100D in FIG. 1 takes the same approach as described in the fourth embodiment.

[0290] [Configuration of level shifter]

[0291] Fig.14 is a circuit diagram showing the configuration of a level shifter in the semiconductor device in the sixth embodiment. Fig.14 The level shifter 100E in FIG. 1 includes a level shifter stage 101E and a driver stage 102A. The configuration of the driver stage 102A is similar to Figure 8 , 9 , 11 and 12 are the same, and therefore their descriptions are not repeated. The configuration of the level shifter stage 101E is modified by partially Fig.12 This is obtained by the level shifter stage 101D in.

[0292] The over-breakdown voltage prevention circuit 112 in the level shifter stage 101E is different from that in the case of the fifth embodiment (ie, Fig.12The over-breakdown voltage prevention circuit 112 in FIG. 1 is different in the layout of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N. Fig.14 In the example of FIG. 1 , the over-breakdown voltage prevention NMOS transistor MNE1P is disposed between the over-breakdown voltage prevention PMOS transistor MPE3P and the over-breakdown voltage prevention PMOS transistor MPE1P and is coupled in series to the over-breakdown voltage prevention PMOS transistors MPE3P and MPE1P. Similarly, the over-breakdown voltage prevention NMOS transistor MNE1N is disposed between the over-breakdown voltage prevention PMOS transistor MPE3N and the over-breakdown voltage prevention PMOS transistor MPE1N and is coupled in series to the over-breakdown voltage prevention PMOS transistors MPE3N and MPE1N.

[0293] The over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N, bias voltage bias1 (VPPR) is given to each of the gates of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N. The corresponding back gates of the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are coupled to the intermediate nodes 11p and 11n, respectively. The corresponding back gates of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are coupled to the intermediate nodes hxp and hxn, respectively.

[0294] Note that in Fig.14 In the related description, the corresponding coupling nodes between the over-breakdown voltage prevention PMOS transistors MPE3P and MPE3N and the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N are referred to as intermediate nodes hxp and hxn. The corresponding coupling nodes between the over-breakdown voltage prevention NMOS transistors MNE1P and MNE1N and the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N are referred to as intermediate nodes hyp and hyn. The corresponding coupling nodes between the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N and the input NMOS transistors MNINP and MNINN are referred to as intermediate nodes 11p and 11n.

[0295] The over-breakdown voltage prevention circuit 112 in the level shifter stage 101E is connected to Fig.12 The difference of the over-breakdown voltage prevention circuit 112 in FIG. 1 is that over-breakdown voltage prevention NMOS transistors MNE3P and MNE3N coupled to the respective drains of the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N are further included therein. Specifically, in FIG. Fig.14In the embodiment, the series coupling body including the over-breakdown voltage prevention PMOS transistor MPE4P and the over-breakdown voltage prevention NMOS transistor MNE3P is coupled in parallel to the series coupling body including the over-breakdown voltage prevention NMOS transistor MNE1P and the over-breakdown voltage prevention PMOS transistor MPE1P. Similarly, the series coupling body including the over-breakdown voltage prevention PMOS transistor MPE4N and the over-breakdown voltage prevention NMOS transistor MNE3N is coupled in parallel to the series coupling body including the over-breakdown voltage prevention NMOS transistor MNE1N and the over-breakdown voltage prevention PMOS transistor MPE1N.

[0296] In each of the newly added over-breakdown voltage prevention NMOS transistors MNE3P and MNE3N, a bias voltage bias1 is applied to the gate, and a back gate is coupled to the source. Fig.14 In the related description, respective coupling nodes between the exceeding breakdown voltage prevention PMOS transistors MPE4P and MPE4N and the exceeding breakdown voltage prevention NMOS transistors MNE3P and MNE3N are referred to as intermediate nodes hzp and hzn.

[0297] Fig.14 The level shifter stage 101E in FIG. 1 further includes clamped NMOS transistors MNC3P and MNC3N coupled between respective intermediate nodes hyp and hyn and a bias voltage bias1. In each of the clamped NMOS transistors MNC3P and MNC3N, a drain and a gate are coupled together, and a bias voltage bias1 is applied to a source. Respective back gates of the clamped NMOS transistors MNC3P and MNC3N are coupled to respective intermediate nodes 11p and 11n. The clamped NMOS transistors MNC3P and MNC3N are provided so as to extract a high voltage from the intermediate nodes hyp and hyn.

[0298] Note that Fig.14 , the node to which the gate of the NMOS transistor MNP1P is coupled is changed from the intermediate node hxn to the intermediate node hy, and the node to which the gate of the NMOS transistor MNP1N is coupled is changed from the intermediate node hxp to the intermediate node hyp.

[0299] because Fig.14 The configuration in Fig.12 The situation is the same as in the previous embodiment, so similar or equivalent parts are given like figure marks, and their description is not repeated.

[0300] [Level Shifter Operation]

[0301] exist Fig.12In the case of the level shifter 100D in FIG. 1 , the maximum voltage at the respective sources (ie, the intermediate nodes hxp and hxn) of the PMOS transistors MPE1P and MPE1N that prevent the breakdown voltage from exceeding is VPPA. Fig.14 In the case of the level shifter 100E in FIG. 1 , the maximum voltage at the respective sources (i.e., the intermediate nodes hyp and hyn) of the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N is VPPR. Therefore, the maximum voltage applied to the over-breakdown voltage prevention PMOS transistors MPE1P and MPE1N can be significantly reduced from VPPA to VPPR. The effect is the same as in the case of the fourth embodiment.

[0302] The maximum voltage at the respective drains (i.e., the intermediate nodes hzp and hzn) of the over-breakdown voltage prevention PMOS transistors MPE4P and MPE4N is VPPA. In order to prevent voltage from being accidentally transmitted to the intermediate nodes hyp and hyn, over-breakdown voltage prevention NMOS transistors MNE3P and MNE3N are provided to isolate the intermediate node hzp from the intermediate node hyp and to isolate the intermediate node hzn from the intermediate node hyn.

[0303] When a voltage higher than VPPR is temporarily applied to each of the intermediate nodes hyp and hyn, charges are released from the intermediate nodes hyp and hyn through the corresponding clamp NMOS transistors MNC3P and MNC3N until the voltage at each of the intermediate nodes hyp and hyn is equal to VPPR (bias1).

[0304] [Effects of the Sixth Embodiment]

[0305] By adopting Fig.14 The configuration of the over-breakdown voltage prevention circuit 112 in the level shifter 100E shown in FIG. 1 can exert an over-breakdown voltage prevention effect on all PMOS transistors in the current path in the level shifter 100E. As a result, it is possible to suppress the degradation of the threshold voltage of each of the PMOS transistors when the PMOS transistors receive FN stress and provide a level shifter with a higher resistance to FN degradation.

[0306] <Seventh Embodiment>

[0307] In the first to sixth embodiments, a VDD level control signal such as a selection signal selpp_a is assumed as an input signal inp and inn to the level shifters 100A to 100E, wherein VDD is a low voltage of, for example, about 1.5 V. Therefore, in order to invert the latch circuit 110 in each of the level shifters 100A to 100E, it is necessary to increase the size of the input NMOS transistors MNINP and MNINN and thus allow sufficient current to flow. Therefore, in the seventh embodiment, a description will be given of a configuration of a level shifter that can ensure a large inversion margin.

[0308] [Configuration of level shifter]

[0309] Fig.15 is a block diagram showing the configuration of a level shifter in the semiconductor device in the seventh embodiment.

[0310] Fig.15 The level shifter 200 in the embodiment includes: a VDD-VCC level shifter 201, which converts VDD level differential input signals inp_vdd and inn_vdd into VCC level signals; and a VCC-VPPA level shifter 202, which converts Level differential input signals inp_vcc and inn_vcc are converted into VPPA level signals. Differential signals output from the level shifter 201 provided in a stage preceding the level shifter 202 are input to the level shifter 202 as input signals inp_vcc and inn_vcc.

[0311] In the seventh embodiment, VCC is, for example, a voltage of about 3 V. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are embedded in a mixed relationship, for example, VDD is externally supplied as a power supply voltage to the digital circuit, while VCC is externally supplied as a power supply voltage to the analog circuit.

[0312] Each of the level shifters 100 and 100A to 100E described in the first to sixth embodiments can be used without modification as the VCC-VPPA level shifter 202. A cross-coupled level shifter having a simple configuration not including an over-breakdown voltage prevention circuit can be used as the VDD-VCC level shifter 201.

[0313] Fig.16 It is shown Fig.15 A circuit diagram of an example of a configuration of a VDD-VCC level shifter. Fig.16, the VDD-VCC level shifter 140 includes a power supply node 141 to which the power supply voltage VCC is input, a ground node 142 to which the ground voltage VSS is input, a latch circuit 147, and an input circuit 148 to which the differential input signals inp and inn are input.

[0314] The latch circuit 110 includes a pair of cross-coupled PMOS transistors 143 and 144 having respective sources coupled to a power supply node 141. The PMOS transistors 143 and 144 have respective gates and drains that are cross-coupled together. Specifically, the gate of the PMOS transistor 143 is coupled to the drain of the PMOS transistor 144, while the drain of the PMOS transistor 143 is coupled to the gate of the PMOS transistor 144.

[0315] The input circuit 148 includes a pair of input NMOS transistors 145 and 146. Each of the sources of the input NMOS transistors 145 and 146 is coupled to the ground node 142. An input signal inp is input to the gate of the input NMOS transistor 145, while an input signal inn is input to the gate of the input NMOS transistor 146.

[0316] The drain of the input NMOS transistor 146 and the drain of the PMOS transistor 144 are coupled together to serve as an output node for the output signal outp. Similarly, the drain of the input NMOS transistor 145 and the drain of the PMOS transistor 143 are coupled together to serve as an output node for the output signal outn.

[0317] [Effects of the Seventh Embodiment]

[0318] The level shifter 200 having the configuration described above converts a VDD level input signal into a VCC level signal using the previous stage level shifter 201. The VCC level signal is input to the subsequent stage level shifter 202. This allows the subsequent stage level shifter 202 to obtain a sufficient inversion margin without increasing the size of the input NMOS transistors MNINP and MNINN.

[0319] <Edit>

[0320] Even when the conductivity type of each of the MOS transistors in the level shifters 100 and 100A to 100E described above in the first to sixth embodiments is changed from P type to N type or from N type to P type and the high power supply voltage VPPA, the intermediate voltage VPPR, the intermediate voltage VPPC, etc. are changed from positive values ​​to negative values, the same function / effect as described above is achieved.

[0321] Although the present invention achieved by the present inventors has been specifically described so far based on its embodiments, the present invention is not limited to the aforementioned embodiments. It will be appreciated that various changes and modifications can be made in the present invention within the scope not departing from its object.

Claims

1. A semiconductor device, comprising: Level shifter, The level shifter comprises: a latch circuit including a pair of first conductivity type cross-coupled transistors, each of the first conductivity type cross-coupled transistors being coupled to a first power supply node to which a high power supply voltage is input; an input circuit including a pair of second conductivity type transistors, each second conductivity type transistor being coupled to a second power supply node and having a respective gate receiving a complementary input signal to the level shifter, a reference voltage being input to the second power supply node; and an over-breakdown voltage prevention circuit coupled between the latch circuit and the input circuit, The over-breakdown voltage prevention circuit comprises: a first conductivity type first exceed breakdown voltage prevention transistor having a gate receiving a first intermediate voltage between the high power supply voltage and the reference voltage; a second conductivity type second exceed-breakdown voltage prevention transistor having a gate receiving a second intermediate voltage between the high power supply voltage and the reference voltage and coupled in series to the first exceed-breakdown voltage prevention transistor; and a first conductivity type third exceed-breakdown voltage prevention transistor coupled in series to the first exceed-breakdown voltage prevention transistor and the second exceed-breakdown voltage prevention transistor between the first exceed-breakdown voltage prevention transistor and the second exceed-breakdown voltage prevention transistor and the latch circuit, and The level shifter further includes a first conductivity type clamp transistor coupled between a coupling node and the first power supply node, the coupling node being between the third over-breakdown voltage preventing transistor and the latch circuit.

2. The semiconductor device according to claim 1, The second intermediate voltage is between the high power supply voltage and the first intermediate voltage.

3. The semiconductor device according to claim 2, in, A third intermediate voltage is applied to the gate of the third exceeding-breakdown-voltage prevention transistor, and The third intermediate voltage is between the first intermediate voltage and the second intermediate voltage.

4. The semiconductor device according to claim 3, further comprising: a first voltage generating circuit for generating the third intermediate voltage, The first voltage generating circuit comprises: a third power supply node to which the second intermediate voltage is applied; An output node, used for outputting the third intermediate voltage; a second conductivity type first transistor coupled between the third power supply node and the output node and having a gate receiving the second intermediate voltage; and A first conductive type second transistor is coupled between the output node and the second power supply node and has a gate receiving the first intermediate voltage.

5. The semiconductor device according to claim 4, The first voltage generating circuit further includes: a first switch coupled in parallel to the second transistor between the output node and the second power supply node, and Wherein, when the first switch is brought into an on state, the reference voltage is supplied to the gate of the third exceed-breakdown-voltage prevention transistor instead of the third intermediate voltage.

6. The semiconductor device according to claim 2, in, A fourth intermediate voltage is applied to the gate of the third exceeding-breakdown-voltage prevention transistor, and The fourth intermediate voltage is between the high power voltage and the reference voltage, and increases when the high power voltage increases.

7. The semiconductor device according to claim 6, The fourth intermediate voltage is generated by dividing the high power supply voltage.

8. The semiconductor device according to claim 6, wherein the first exceed-breakdown-voltage prevention transistor is coupled between the second exceed-breakdown-voltage prevention transistor and the third exceed-breakdown-voltage prevention transistor, The over-breakdown voltage prevention circuit further comprises: a first conductivity type fourth exceed-breakdown voltage prevention transistor coupled in parallel to the first exceed-breakdown voltage prevention transistor and having a gate receiving a fifth intermediate voltage, and The fifth intermediate voltage is between the fourth intermediate voltage and the reference voltage, and increases when the high power supply voltage increases.

9. The semiconductor device according to claim 8, The fifth intermediate voltage is generated by dividing the high power supply voltage.

10. The semiconductor device according to claim 6, wherein the second exceed-breakdown voltage prevention transistor is coupled between the first exceed-breakdown voltage prevention transistor and the third exceed-breakdown voltage prevention transistor, The over-breakdown voltage prevention circuit further comprises: a first conductivity type fourth exceed-breakdown voltage prevention transistor coupled in parallel to the series coupling body including the second exceed-breakdown voltage prevention transistor and the third exceed-breakdown voltage prevention transistor and having a gate receiving a fifth intermediate voltage, and The fifth intermediate voltage is between the fourth intermediate voltage and the reference voltage, and increases when the high power supply voltage increases.

11. The semiconductor device according to claim 10, The fifth intermediate voltage is generated by dividing the high power supply voltage.

12. The semiconductor device according to claim 8, The over-breakdown voltage prevention circuit further comprises: A fifth over-breakdown voltage prevention transistor of the second conductivity type is coupled in series to the fourth over-breakdown voltage prevention transistor between the fourth over-breakdown voltage prevention transistor and the input circuit, and is coupled in parallel to a series coupling body including the second over-breakdown voltage prevention transistor and the third over-breakdown voltage prevention transistor.

13. The semiconductor device according to claim 2, Wherein the third exceed-breakdown-voltage preventing transistor is diode-coupled.

14. The semiconductor device according to claim 2, The level shifter further comprises: a bypass path for bypassing the over-breakdown voltage prevention transistor to couple the latch circuit with the input circuit; as well as A second switch is provided in the bypass path to switch the bypass path between a conductive state and a non-conductive state.

15. The semiconductor device according to claim 2, wherein the second exceed-breakdown voltage prevention transistor is coupled between the first exceed-breakdown voltage prevention transistor and the third exceed-breakdown voltage prevention transistor.

16. The semiconductor device according to claim 1, The semiconductor device further comprises: a previous-stage level shifter that converts a signal at a first voltage level into a signal at a second voltage level higher than the first voltage level, and wherein the input signal to the level shifter is the signal resulting from the conversion performed by the previous stage level shifter.

17. A semiconductor device comprising: Level shifter, The level shifter comprises: a latch circuit including a pair of first conductivity type cross-coupled transistors, each of the first conductivity type cross-coupled transistors being coupled to a first power supply node to which a high power supply voltage is input; an input circuit including a pair of second conductivity type transistors, each second conductivity type transistor being coupled to a second power supply node and having a respective gate receiving a complementary input signal to the level shifter, a reference voltage being input to the second power supply node; and an over-breakdown voltage prevention circuit coupled between the latch circuit and the input circuit, The over-breakdown voltage prevention circuit comprises: a first conductivity type first exceed breakdown voltage prevention transistor having a gate receiving a first intermediate voltage between the high power supply voltage and the reference voltage; a second conductivity type second exceed-breakdown voltage prevention transistor having a gate receiving a second intermediate voltage between the high power supply voltage and the first intermediate voltage and coupled in series to the first exceed-breakdown voltage prevention transistor; and a first conductivity type third exceed-breakdown voltage prevention transistor coupled in series to the first exceed-breakdown voltage prevention transistor and the second exceed-breakdown voltage prevention transistor between the first exceed-breakdown voltage prevention transistor and the second exceed-breakdown voltage prevention transistor and the latch circuit, wherein the third exceeding-breakdown-voltage prevents the transistor from having a third intermediate voltage applied to a gate thereof, wherein the third intermediate voltage is between the first intermediate voltage and the second intermediate voltage, and The level shifter further includes a first conductivity type clamp transistor coupled between a coupling node and the first power supply node, the coupling node being between the third over-breakdown voltage preventing transistor and the latch circuit.

18. A semiconductor device comprising: Level shifter, The level shifter comprises: a latch circuit including a pair of first conductivity type cross-coupled transistors, each of the first conductivity type cross-coupled transistors being coupled to a first power supply node to which a high power supply voltage is input; an input circuit including a pair of second conductivity type transistors, each second conductivity type transistor being coupled to a second power supply node and having a respective gate receiving a complementary input signal to the level shifter, a reference voltage being input to the second power supply node; and an over-breakdown voltage prevention circuit coupled between the latch circuit and the input circuit, The over-breakdown voltage prevention circuit comprises: a first conductivity type first exceed breakdown voltage prevention transistor having a gate receiving a first intermediate voltage between the high power supply voltage and the reference voltage; a second conductivity type second exceed-breakdown voltage prevention transistor having a gate receiving a second intermediate voltage between the high power supply voltage and the first intermediate voltage and coupled in series to the first exceed-breakdown voltage prevention transistor; and a first conductivity type third exceed-breakdown voltage prevention transistor coupled in series to the first exceed-breakdown voltage prevention transistor and the second exceed-breakdown voltage prevention transistor between the first exceed-breakdown voltage prevention transistor and the second exceed-breakdown voltage prevention transistor and the latch circuit, wherein the third exceeding-breakdown-voltage prevents the transistor from having a fourth intermediate voltage applied to a gate thereof, wherein the fourth intermediate voltage is between the high power supply voltage and the reference voltage and increases when the high power supply voltage increases, and The level shifter further includes a first conductivity type clamp transistor coupled between a coupling node and the first power supply node, the coupling node being between the third over-breakdown voltage preventing transistor and the latch circuit.

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